Test method and test system for electronic devices

Abstract

A testing method and system for electronic devices are provided. The testing method for electronic devices includes receiving multiple first test data for multiple first test cases and multiple second test data for multiple second test cases; generating multiple first local scores based on the multiple first test data; generating multiple second local scores based on the multiple second test data; generating a global score for a common test case of the multiple first test cases and the multiple second test cases; replacing at least some of the multiple first local scores with the global score to generate multiple first test scores; replacing at least some of the multiple second local scores with the global score to generate multiple second test scores; and performing a first mutation operation based on a first optimal test case corresponding to the highest score among the multiple first test scores to generate a first pre-test set.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0189080, filed with the Korean Intellectual Property Office on December 17, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application generally relates to test methods and test systems for electronic devices. Background Technology

[0004] In the manufacture of electronic devices (including semiconductor devices), testing is essential to determine optimal operating conditions. Given the limitations on the number of test iterations and the variety of operating conditions, testing must rely on engineers' proprietary skills. While the proprietary operating conditions exist, genetic algorithms have been proposed to search for optimal operating conditions more accurately and quickly. Summary of the Invention

[0005] Genetic algorithms are techniques used to solve optimization problems, modeled after the evolutionary process in the natural world. However, even when using genetic algorithms to search for operating conditions suitable for a specific DUT (device under test), overfitting may occur, where the searched operating conditions are not suitable for other DUTs.

[0006] To address the overfitting problem, a genetic algorithm is used to search for operating conditions across multiple DUTs. However, because operating conditions that perform well in a specific DUT do not take into account their performance in other DUTs during the search process, it is difficult to find robust operating conditions suitable for multiple DUT environments.

[0007] Some aspects of this disclosure provide test methods and test systems for electronic devices that rapidly explore robust operating conditions of electronic devices in multiple DUT environments.

[0008] According to some implementations, a testing method for an electronic device can be provided, comprising: receiving multiple first test data of multiple first test cases and multiple second test data of multiple second test cases; generating multiple first local scores based on the multiple first test data; generating multiple second local scores based on the multiple second test data; generating a global score of a common test case of the multiple first test cases and the multiple second test cases; replacing at least some of the multiple first local scores with the global score to generate multiple first test scores; replacing at least some of the multiple second local scores with the global score to generate multiple second test scores; and performing a first mutation operation based on a first optimal test case corresponding to the highest score among the multiple first test scores to generate a first pre-test group.

[0009] According to some implementations, a testing method for an electronic device can be provided, comprising: receiving multiple first test data of multiple first test cases and multiple second test data of multiple second test cases; generating multiple first local scores based on the multiple first test data; generating multiple second local scores based on the multiple second test data; performing a first mutation operation based on at least some of the multiple first test cases to generate a first pre-test group; performing a second mutation operation based on at least some of the multiple first test cases to generate a second pre-test group; and adding a first locally optimal test case corresponding to the highest score among the multiple first local scores and a second locally optimal test case corresponding to the highest score among the multiple second local scores to the first pre-test group to generate multiple third test cases.

[0010] According to some embodiments, a testing system can be provided, including: a first electronic device, a second electronic device, and a testing device. The first electronic device includes a first memory module configured to output a plurality of first data based on a plurality of first test cases and configured to generate a plurality of first test data for the plurality of first data. The second electronic device includes a second memory module configured to output a plurality of second data based on a plurality of second test cases and configured to generate a plurality of second test data for the plurality of second data. The testing device is configured to generate a plurality of first local scores based on the plurality of first test data, generate a plurality of second local scores based on the plurality of second test data, generate a global score for a common test case of the plurality of first test cases and the plurality of second test cases, replace at least some of the plurality of first local scores with the global score to generate a plurality of first test scores, replace at least some of the plurality of second local scores with the global score to generate a plurality of second test scores, and perform a first mutation operation based on a first optimal test case corresponding to the highest score among the plurality of first test scores to generate a first pre-test set. Attached Figure Description

[0011] Figure 1 This is a block diagram illustrating an example of a test system.

[0012] Figure 2 This is a block diagram showing an example of a test device.

[0013] Figure 3 An example of a genetic algorithm tool is shown.

[0014] Figures 4 to 6 Examples of test cases and test data are shown.

[0015] Figure 7 This is a flowchart illustrating an example of a testing method for electronic devices.

[0016] Figures 8 to 12This is a diagram illustrating an example of a testing method for electronic devices.

[0017] Figure 13 This is a block diagram illustrating an example of a test system.

[0018] Figure 14 This is a block diagram illustrating an example of a test system.

[0019] Figure 15 This is a block diagram showing an example of a test device. Detailed Implementation

[0020] As those skilled in the art will recognize, the described examples can be modified in various different ways, all without departing from the spirit or scope of this disclosure.

[0021] For clarity of this disclosure, parts irrelevant to the description have been omitted, and the same or similar reference numerals are assigned to the same or similar components throughout the specification.

[0022] Furthermore, unless explicitly stated to the contrary, the word “comprise” and variations such as “comprises” and “comprising” should be understood as implying inclusion of the stated element but not excluding any other element.

[0023] Those skilled in the art will further understand that if a specific number of claim statements are intended to be introduced, such intention will be explicitly stated in the claims, and without such a statement, such intention does not exist. For example, to facilitate understanding, the appended claims may contain the introductory phrases “at least one” and “one or more” to introduce claim statements. However, the use of these phrases should not be construed as a limitation described by the unambiguous article “a” as an example.

[0024] Furthermore, in cases where a convention similar to "at least one of A, B, and C" is used, such a construction is generally intended to make the meaning of the convention understandable to those skilled in the art (e.g., "a system having at least one of A, B, and C" will include, but is not limited to, systems having only A, only B, only C, A and B together, A and C together, B and C together, and / or A, B, and C together, etc.).

[0025] Alternatively, unless the context otherwise requires, extractive terms and / or phrases presenting two or more alternative terms (whether in the specification, claims, or drawings) should be understood to include one, any, or both of the terms. For example, the phrase “A or B” should generally be understood to include the possibility of “A” or “B” or “A and B”.

[0026] In this specification, a “module,” “unit,” or “part” may be configured to perform at least one function or operation and may be implemented as hardware such as a processor or integrated circuit, software executed by a processor, or a combination thereof.

[0027] As discussed above, when using a genetic algorithm to search for operating conditions for multiple DUTs, the search direction for each DUT may not be considered together, making it difficult to find operating conditions suitable for all DUTs.

[0028] Some embodiments of this disclosure improve device testing techniques by, for example, including the following processes: i) performing local scoring of test performance for multiple test cases (combinations of operating conditions) for each of a plurality of DUTs; ii) generating a global score for common test cases shared among the plurality of DUTs based on the multiple local scores, replacing the local scores of the common test cases with the global score; iii) selecting the optimal test case for each DUT based on the score, and performing a mutation operation based on the selected optimal test case to generate a subsequent generation for each DUT; and iv) adding locally optimized test cases for each DUT to the generated subsequent generation.

[0029] By employing one or more of steps i) through iv), performance can be quantified to explore test cases suitable for multiple DUTs, thereby incorporating DUT-specific optimal test cases into subsequent generations to achieve cross-validation of test cases across different DUTs and prevent exploration in the wrong direction. This can lead to improved DUT performance by allowing the DUT to be configured with more robust operating conditions across device-to-device variations and other variables.

[0030] Figure 1 This is a block diagram illustrating an example of a test system. Figure 2 This is a block diagram showing an example of a test device.

[0031] refer to Figure 1 and Figure 2 The test system 1 may include a test device 10, multiple electronic devices 20, and a database 30. The multiple electronic devices 20 may include a first electronic device 20_1 to a third electronic device 20_3.

[0032] Test system 1 can repeatedly generate subsequent generations of multiple test groups TG1, TG2, and TG3 based on a genetic algorithm to efficiently search for robust optimal test cases across multiple electronic devices 20_1 to 20_3. In test system 1, multiple electronic devices 20_1 to 20_3 can each receive their corresponding test groups TG1, TG2, and TG3, and perform measurement operations for each test case included in the received test groups TG1, TG2, and TG3 to generate test data TD1, TD2, and TD3 as raw data. Test device 10 can perform individual optimization for each test group TG1, TG2, and TG3 by considering test data obtained from other electronic devices, and generate separate subsequent generations for each test group TG1, TG2, and TG3.

[0033] In this disclosure, a "test set" can be defined as a set of "test cases" applied to a specific electronic device among a plurality of electronic devices 20_1 to 20_3 within the test system 1, and a "test case" can be defined as a combination of operating conditions of components within an electronic device. For example, a "test case" can be a combination of operating conditions of a memory module that is a component of an electronic device, and a "test case" can be expressed as a string or bit string and include at least a portion of MRS (Mode Register Set) information for testing the memory module.

[0034] The test device 10 may include a processor 11, a memory 12, a storage device 13, and an input / output device 14. The processor 11 may include computing circuitry.

[0035] Test device 10 can be a computer-based test device. Test device 10 can use a genetic algorithm as part of test system 1. Test device 10 can use a genetic algorithm to generate subsequent generations of test sets TG1, TG2, TG3 corresponding to each of the multiple electronic devices 20_1 to 20_3 based on test data TD1, TD2, TD3 measured from multiple electronic devices 20_1 to 20_3. Test device 10 can search for robust optimal test cases across multiple electronic devices 20_1 to 20_3 by generating subsequent generations. In the operation of generating subsequent generations, test device 10 can quantify the individually generated test data TD1, TD2, TD3 in a uniform manner, generate subsequent generations by reflecting (or based on) a portion of test data measured in another electronic device, and add locally optimal test cases in each electronic device to the subsequent generations.

[0036] According to some implementations, the test device 10 may be a dedicated device for exploring test cases of multiple electronic devices 20, but it may also be a computer for running various applications. The test device 10 may be a fixed computing system such as a desktop computer, workstation, server, etc., or a portable computing system such as a laptop computer, smartphone, etc.

[0037] The processor 11, memory 12, storage device 13 and input / output device 14 can be connected to each other via a bus, and the processor 11 can control the memory 12, storage device 13 and input / output device 14.

[0038] The processor 11 can execute the genetic algorithm tool GAT. According to some implementations, the processor 11 can execute the genetic algorithm tool GAT to perform various processing operations related to genetic algorithm operations.

[0039] Processor 11 may be at least one of various types of processors such as CPU (Central Processing Unit), GPU (Graphics Processing Unit), NPU (Neural Processing Unit), DPU (Data Processing Unit), or combinations thereof. According to some embodiments, processor 11 may include a single-core processor or a multi-core processor.

[0040] The processor 11 can control the provision of a first test group TG1 to a third test group TG3 to the corresponding first electronic device 20_1 to third electronic device 20_3, respectively. For example, the processor 11 can control the test device 10 to provide the first test group TG1 to the first electronic device 20_1, the second test group TG2 to the second electronic device 20_2, and the third test group TG3 to the third electronic device 20_3.

[0041] Processor 11 can receive test data TD from database 30. According to some embodiments, processor 11 can asynchronously receive each of the first test data TD1 to the third test data TD3 measured from each of the first electronic device 20_1 to the third electronic device 20_3.

[0042] Processor 11 can perform scoring operations on test data TD in a uniform manner to generate local scores for test cases. Local scores can be performance metrics generated based on test data measured on a specific electronic device. Processor 11 can perform scoring operations on the first test data TD1 of test cases in the first test group TG1, the second test data TD2 of test cases in the second test group TG2, and the third test data TD3 of test cases in the third test group TG3 in a uniform manner, thereby generating local scores as performance metrics for the entire test case.

[0043] Processor 11 can find the locally optimal test case with the highest local score in each of the multiple test groups TG1 to TG3. For example, processor 11 can find the first locally optimal test case with the highest local score in the test cases of the first test group TG1. Similarly, processor 11 can find the second locally optimal test case with the highest local score in the test cases of the second test group TG2, and the third locally optimal test case with the highest local score in the test cases of the third test group TG3.

[0044] Processor 11 can generate a global score based on local scores of common test cases shared by multiple test groups TG1 to TG3. The global score can be a comprehensive performance metric reflecting the performance of first test data TD1 to third test data TD3 measured on first electronic device 20_1 to third electronic device 20_3.

[0045] For example, processor 11 can perform one or more operations to generate a global score based on local scores generated by applying common test cases to a first electronic device 20_1, local scores generated by applying common test cases to a second electronic device 20_2, and local scores generated by applying common test cases to a third electronic device 20_3. Operations may include, but are not limited to, arithmetic mean, geometric mean, minimum selection, weighted average, etc.

[0046] Processor 11 can select the test case with the highest global score from the public test cases.

[0047] Processor 11 can generate multiple test scores for each of multiple test groups TG1 to TG3 by replacing local scores with global scores from common test cases. The test scores can be performance metrics reflecting a sum of local scores obtained from a specific electronic device and global scores obtained from multiple electronic devices 20_1 to 20_3.

[0048] Processor 11 can generate the best test case with the highest test score among the test cases in each of multiple test groups TG1 to TG3. For example, processor 11 can find the first best test case with the highest test score among the test cases in the first test group TG1. Similarly, processor 11 can find the second best test case with the highest test score among the test cases in the second test group TG2, and the third best test case with the highest test score among the test cases in the third test group TG3.

[0049] Processor 11 can perform mutation operations on each optimal test case of multiple test groups TG1 to TG3 to generate a pre-test group for each of the multiple test groups TG1 to TG3. For example, processor 11 can perform mutation operations on the first optimal test case of the first test group TG1 to generate a first pre-test group of the first test group TG1. Similarly, processor 11 can perform mutation operations on the second optimal test case of the second test group TG2 to generate a second pre-test group of the second test group TG2, and perform mutation operations on the third optimal test case of the third test group TG3 to generate a third pre-test group of the third test group TG3.

[0050] Processor 11 can add locally optimal test cases from multiple test groups TG1 to TG3 to multiple pre-test groups for each of test groups TG1 to TG3 to generate multiple subsequent test groups. For example, processor 11 can add locally optimal test cases from each of test groups TG1 to TG3 to a first pre-test group of a first test group TG1 to generate a first subsequent test group of the first test group TG1. Similarly, processor 11 can add locally optimal test cases from multiple test groups TG1 to TG3 to a second pre-test group of a second test group TG2, and can add locally optimal test cases from multiple test groups TG1 to TG3 to a third pre-test group of a third test group TG3.

[0051] The processor 11 can provide the generated subsequent test sets to the corresponding first electronic device 20_1 to the third electronic device 20_3. For example, the processor 11 can provide the first electronic device 20_1 with a first subsequent test set of the first test set TG1. Similarly, the processor 11 can provide the second electronic device 20_2 with a second subsequent test set of the second test set TG2, and can provide the third electronic device 20_3 with a third subsequent test set of the third test set TG3.

[0052] The memory 12 can be used as the main memory or system memory of the test device 10. The genetic algorithm tool GAT running on the processor 11 can be loaded into the memory 12. The memory 12 can store various types of information used in the genetic algorithm operation, and can store the results of intermediate operations of the genetic algorithm.

[0053] The processor 11 can execute the genetic algorithm tool GAT loaded into the memory 12 to perform the various operations described herein.

[0054] According to some embodiments, memory 12 may include volatile memory devices such as DRAM (Dynamic Random Access Memory), SDRAM (Synchronous DRAM), DDR SDRAM (Double Data Rate SDRAM), LPDDR SDRAM (Low Power Double Data Rate SDRAM), GDDR SDRAM (Graphics Double Data Rate SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, etc. According to some embodiments, memory 12 may include not only DRAM devices, but also, alternatively, non-volatile memory such as PRAM (Phase Change Random Access Memory), SRAM (Static Random Access Memory), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), FRAM (Ferroelectric Random Access Memory), Hybrid RAM (Random Access Memory), or NAND flash.

[0055] Storage device 13 may store program code (e.g., computer-readable program code) for executing the genetic algorithm tool GAT.

[0056] Storage device 13 may include a non-volatile memory device and a non-volatile memory controller for the non-volatile memory device. For example, the non-volatile memory device may include a hard disk drive, optical memory, NAND flash memory, etc. According to some embodiments, storage device 13 may include non-volatile memory, volatile memory, or a combination or portion thereof, any of which may be referred to as a "storage medium".

[0057] In some implementations, non-volatile memory devices can be configured to store data in a semi-permanent or substantially permanent form.

[0058] For example, input / output device 14 may include input devices such as a keyboard, operation panel or various data reading devices, and output devices such as a monitor, printer and recording device.

[0059] The plurality of electronic devices 20 may include first electronic devices 20_1 to third electronic devices 20_3, or any other number of electronic devices. According to some embodiments, each of the first electronic devices 20_1 to third electronic devices 20_3 may be or correspond to a separate DUT (Device Under Test) or the environment of the DUT. In each of the first electronic devices 20_1 to third electronic devices 20_3, test cases of each of the first to third test groups TG1, TG2, and TG3 may be applied. For example, test cases within the first test group TG1 may include MRS information for testing memory devices and may be applied to the first memory module (220_1) of the first electronic device (20_1).

[0060] Each of the first electronic device 20_1 to the third electronic device 20_3 can be a computer-based test device. When a test case is applied to each of the first electronic device 20_1 to the third electronic device 20_3, each of the first electronic device 20_1 to the third electronic device 20_3 can perform a measurement operation based on the test case and output first test data TD1 to third test data TD3 corresponding to the test case.

[0061] The first electronic device 20_1 may include a first processor 210_1, a first memory module 220_1, a first storage device 230_1, and a first system bus 240_1.

[0062] The first processor 210_1, the first memory module 220_1, and the first storage device 230_1 can be connected to each other via the first system bus 240_1, and the first processor 210_1 can control the first memory module 220_1 and the first storage device 230_1. According to some embodiments, the first system bus 240_1 can be physically implemented via a PCB (printed circuit board) substrate disposed in the first electronic device 20_1.

[0063] The first processor 210_1 can execute a measurement program (or evaluation program) EP. According to some embodiments, the first processor 210_1 can execute the measurement program EP to apply test cases of the first test group TG1, perform measurement operations according to the application of the test cases, and perform various processing operations related to the measurement operations. For example, the first processor 210_1 can execute the measurement program EP to apply the test cases of the first test group TG1 to the first memory module 220_1, and control the input / output operation of the first data signal DT1 input / output from the first memory module 220_1. The first processor 210_1 can execute the measurement program EP to measure the signal margin of the first data signal DT1. The aforementioned signal margin may include voltage margin, timing margin, etc.

[0064] The first processor 210_1 may be at least one of a processor such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a data processing unit (DPU), or a combination thereof. According to some embodiments, the first processor 210_1 may include a single-core processor or a multi-core processor.

[0065] The first memory module 220_1 can be used as the main memory or system memory of the first electronic device 20_1. A measurement program EP running on the first processor 210_1 can be loaded into the first memory module 220_1. The first memory module 220_1 can input and output a first data signal DT1 as the measurement program EP is executed. The first processor 210_1 can perform measurement operations according to the application of test cases within the first test group TG1 by executing the measurement program EP loaded into the first memory module 220_1.

[0066] For example, the first processor 210_1 can execute a measurement program EP loaded into the first memory module 220_1, thereby applying test cases within the first test group TG1 to the first memory module 220_1. When the test cases within the first test group TG1 are applied, the signal margin of the input / output first data signal DT1 can be measured to generate first test data TD1. As another example, the first processor 210_1 can execute a measurement program EP loaded into the first memory module 220_1, thereby applying test cases within the first test group TG1 to the first memory module 220_1. When the test cases within the first test group TG1 are applied, the bandwidth of the input / output first data signal DT1 can be measured to generate first test data TD1. More will be discussed later. Figures 4 to 6 The description provides detailed explanations of examples of test cases and test data.

[0067] The generated first test data TD1 can be sent to database 30 and stored in database 30.

[0068] The first memory module 220_1 may include volatile memory devices such as DRAM, SDRAM (Synchronous DRAM), DDR SDRAM (Double Data Rate SDRAM), LPDDR SDRAM (Low Power Double Data Rate SDRAM), GDDR SDRAM (Graphics Double Data Rate SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, etc. According to some embodiments, the first memory module 220_1 may be implemented in the form of a DIMM (Dual In-line Memory Module).

[0069] The first storage device 230_1 can store program code (e.g., computer-readable program code) for executing the measurement procedure EP.

[0070] The first storage device 230_1 may include a non-volatile memory device and a non-volatile memory controller for the non-volatile memory device. For example, the non-volatile memory device may include a hard disk drive, optical memory, NAND flash memory, etc. In some embodiments, the first storage device 230_1 may include non-volatile memory, volatile memory, and combinations or portions thereof, any of which may be referred to as a "storage medium".

[0071] In some implementations, non-volatile memory devices can be configured to store data in a semi-permanent or substantially permanent form.

[0072] The second electronic device 20_2 may include a second processor 210_2, a second memory module 220_2, a second storage device 230_2, and a second system bus 240_2. Each of the second processor 210_2, the second memory module 220_2, the second storage device 230_2, and the second system bus 240_2 may correspond to each of the first processor 210_1, the first memory module 220_1, the first storage device 230_1, and the first system bus 240_1, respectively.

[0073] For ease of explanation, the following description will focus on the differences between the second processor 210_2, the second memory module 220_2, the second storage device 230_2, and the second system bus 240_2 and the first processor 210_1, the first memory module 220_1, the first storage device 230_1, and the first system bus 240_1.

[0074] The second processor 210_2 can execute a measurement program EP. According to some embodiments, the second processor 210_2 can execute the measurement program EP to apply test cases in the second test group TG2, perform measurement operations according to the application of the test cases, and perform various processing operations related to the measurement operations. For example, the second processor 210_2 can execute the measurement program EP to control the input / output operations of the second data signal DT2 for the second memory module 220_2, and measure the signal margin of the second data signal DT2.

[0075] The second memory module 220_2 can input and output the second data signal DT2 as the measurement program EP is executed. The second processor 210_2 can execute the measurement program EP loaded into the second memory module 220_2 to perform measurement operations according to the application of test cases in the second test group TG2.

[0076] The third electronic device 20_3 may include a third processor 210_3, a third memory module 220_3, a third storage device 230_3, and a third system bus 240_3. Each of the third processor 210_3, the third memory module 220_3, the third storage device 230_3, and the third system bus 240_3 may correspond to each of the first processor 210_1, the first memory module 220_1, the first storage device 230_1, and the first system bus 240_1, respectively.

[0077] For ease of explanation, the following description of the third processor 210_3, third memory module 220_3, third storage device 230_3, and third system bus 240_3 will focus on the differences from the first processor 210_1, first memory module 220_1, first storage device 230_1, and first system bus 240_1.

[0078] The third processor 210_3 can execute a measurement program EP. According to some embodiments, the third processor 210_3 can execute the measurement program EP to apply test cases of the third test group TG3, perform measurement operations according to the application of the test cases, and perform various processing operations related to the measurement operations. For example, the third processor 210_3 can execute the measurement program EP to control the input / output operations of the third data signal DT3 for the third memory module 220_3, and measure the signal margin of the third data signal DT3.

[0079] The third memory module 220_3 can input and output the third data signal DT3 as the measurement program EP is executed. The third processor 210_3 can execute the measurement program EP loaded into the third memory module 220_3 to perform measurement operations according to the application of test cases in the third test group TG3.

[0080] Each of the first electronic devices 20_1 to the third electronic devices 20_3 commonly includes a processor, a memory module, a storage device, and a system bus; however, the corresponding components of the first electronic devices 20_1 to the third electronic devices 20_3 may differ from each other in terms of product or manufacturing process. Due to this difference, even if the same test cases are applied to the first electronic devices 20_1 to the third electronic devices 20_3, the performance of the first electronic devices 20_1 to the third electronic devices 20_3 may differ from each other, and each of the first electronic devices 20_1 to the third electronic devices 20_3 may output different test data.

[0081] Test device 10 can efficiently search for optimal test cases that are robust to environmental differences across multiple electronic devices 20_1 to 20_3 using the genetic algorithm tool GAT.

[0082] In the accompanying drawings, multiple electronic devices 20_1 to 20_3 are shown as including three electronic devices; however, the number of electronic devices in the drawings is merely an example and does not limit the technical concept of this disclosure. According to some embodiments, the number of test groups can vary with the number of multiple electronic devices in the test system 1.

[0083] According to some implementation methods, when the generation of the test group moves to a subsequent generation, the number of multiple electronic devices and the number of test groups can be adjusted to suit the purpose of the test operation of the test system 1.

[0084] Figure 3 An example of a genetic algorithm tool is shown.

[0085] refer to Figures 1 to 3 The genetic algorithm tool GAT can include a test group generation module TGGM and a mutation module GAM. The test group generation module TGGM can generate the first test group TG1 to the third test group TG3.

[0086] The Test Group Generation Module (TGGM) can receive the first test data (TD1) to the third test data (TD3) corresponding to the first test group (TG1) to the third test group (TG3). The TGGM can generate the first to third optimal test cases (TCo1, TCo2, TCo3) for each of the first to third test groups (TG1 to TG3) by considering (or based on) the first to third test data (TD1 to TD3) as a whole. The generated first to third optimal test cases (TCo1, TCo2, TCo3) can be provided to the Mutation Module (GAM).

[0087] The test group generation module TGGM can generate first subsequent test groups TGs1 to third subsequent test groups TGs3 based on the first pre-test groups TGp1 to the third pre-test groups TGp3 provided by the mutation module GAM. The first to third subsequent test groups TGs1 to TGs3 can be subsequent generations of the first to third test groups TG1 to TG3. The generated first to third subsequent test groups TGs1 to TGs3 can be provided as new test groups to multiple electronic devices 20_1 to 20_3.

[0088] The mutation module GAM can receive the first to third optimal test cases TCo1, TCo2, and TCo3, and perform mutation operations on them respectively to generate the first to third pre-test groups TGp1 to TGp3. For example, the mutation module GAM can generate the first pre-test group TGp1 based on the first optimal test case TCo1.

[0089] The mutation module GAM can randomly modify at least some of the operation conditions within the first to third optimal test cases TCo1, TCo2, and TCo3 during the mutation operation. Information regarding the operation conditions can be freely modified, as long as it does not exceed the predefined range within the mutation operation.

[0090] For example, the mutation module GAM can generate a first pre-test set TGp1 by randomly modifying at least some of the operating conditions in the first optimal test case TCo1. Similarly, the mutation module GAM can generate a second pre-test set TGp2 by randomly modifying at least some of the operating conditions in the second optimal test case TCo2. The mutation module GAM can generate a third pre-test set TGp3 by randomly modifying at least some of the operating conditions in the third optimal test case TCo3.

[0091] The mutation module GAM can generate a predefined number of test cases from mutation operations. According to some implementations, as the number of test groups in test system 1 increases, the mutation module GAM can generate fewer test cases in mutation operations. Test system 1 can rapidly transition from generation to generation by reducing the number of measurement operations on a particular electronic device while maintaining the total number of test iterations for a generation.

[0092] Figures 4 to 6 Examples of test cases and test data according to some implementation methods are shown. Specifically, when Figure 1 When the first memory module 220_1 to the third memory module 220_3 are implemented as DIMMs, each of the first memory module 220_1 to the third memory module 220_3 can be configured as follows: Figure 4 The memory module 220_i shown is expressed.

[0093] refer to Figure 1 and Figures 4 to 6 The memory module 220_i may include a memory device 222, a data buffer 223 corresponding to the memory device 222, and an RCD (registered clock driver) 224.

[0094] The memory device 222, data buffer 223, and RCD 224 can be mounted on the printed circuit board 221. The data buffer 223 corresponding to the memory device 222 can be connected via signal lines inside the printed circuit board 221, and the memory device 222 and RCD 224 can be connected via signal lines inside the printed circuit board 221.

[0095] Data buffer 223 buffers the data signal DT input / output from memory module (220_i) and sends / receives the data signal DT to / from memory device 222. RCD 224 can buffer and redrive command CMD, address ADDR, clock CLK, and control signals received from the memory controller. Command CMD, address ADDR, clock CLK, and control signals output from RCD 224 can be provided to memory device 222.

[0096] like Figure 5 As shown, the memory device 222 may include a memory cell array 300, a row decoder 460, a sense amplifier unit 485, a control logic circuit 410, an address register 420, a bank control logic 430, a refresh control circuit 445, a column address (CA) latch 450, a row address multiplexer (RA MUX) 440, a column decoder 470, an input / output (I / O) gating circuit 490, and a data input / output buffer 495.

[0097] The memory cell array 300 may include a predetermined number of memory banks 310 to 380. Additionally, according to some embodiments, the sense amplifier unit 485, the row decoder 460, and the column decoder 470 may each include a plurality of volume sense amplifiers 485a to 485h, a plurality of volume row decoders 460a to 460h, and a plurality of volume column decoders 470a to 470h connected to each of the memory banks 310 to 380, but are not limited thereto.

[0098] The memory cell array 300 may include multiple word lines WL, multiple bit lines BL, and multiple memory cells MC located at the intersection of word lines WL and bit lines BL.

[0099] The control logic circuit 410 can control the operation of the memory device 222. For example, the control logic circuit 410 can generate control signals to cause the memory device 222 to perform a write operation or a read operation. The control logic circuit 410 may include a command decoder 411 for decoding the command CMD received from the RCD 224 and a mode register 412 for setting the operating mode and operating conditions of the memory device 222.

[0100] For example, the command decoder 411 can decode the light enable signal, row address strobe signal, column address strobe signal, channel selection signal, etc., to generate control signals corresponding to the command CMD.

[0101] Mode register 412 can store MRS information. The MRS information may include setting information for configuring the operating mode of memory device 222, and test MRS information corresponding to the operating conditions te1 to te4 of memory device 222 under test conditions. Based on the MRS information stored in mode register 412, the operating mode and operating conditions of memory device 222 can be configured.

[0102] Test case TC may include information about the operating conditions te1 to te4 of memory device 222, which is MRS information for testing, and mode register 412 may store test case TC, which is a combination of information about the operating conditions te1 to te4.

[0103] Operating conditions te1 to te4 can be information for operating memory device 222, and for example, operating conditions te1 to te4 can include voltage information, such as the core voltage in row decoder 460 and column decoder 470, input / output voltage in data input / output buffer 495, reference voltage, and time information, such as skew correction time in data input / output buffer 495. Figure 5 In this paper, the number of operating conditions is shown as four, but this is an example for ease of explanation, and the technical idea of ​​this disclosure is not limited to this number of operating conditions.

[0104] Memory device 222 can perform memory operations based on the application of test case TC and input / output data signal DT. Measurement program EP can measure the signal margin of data signal DT and generate test data TD. According to some embodiments, the signal margin of data signal DT can be test data TD that varies depending on the application of test case TC.

[0105] For example, with Figure 6 For example, a data signal DT can be input / output with signal margins based on the center O of the eye diagram ED, including the a-th timing margin ta, the b-th timing margin tb, the a-th voltage margin va, and the b-th voltage margin vb. According to some implementations, the a-th timing margin ta, the b-th timing margin tb, the a-th voltage margin va, and / or the b-th voltage margin vb are performance indicators representing the reliability and stability of the transmission of the data signal DT, and can be test data TD that varies depending on the application of the test case TC.

[0106] Address register 420 can receive address ADDR from RCD 224, which includes body address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR. Address register 420 can provide body address BANK_ADDR to body control logic 430 and row address ROW_ADDR to row address multiplexer 440.

[0107] The body control logic 430 can generate a body control signal in response to the body address BANK_ADDR. In response to the body control signal, the row decoder 460 and column decoder 470 can activate the corresponding body.

[0108] The row address multiplexer 440 can receive the row address ROW_ADDR from the address register 420 and the refresh row address REF_ADDR from the control logic circuit 410. The row address multiplexer 440 can selectively output either the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 440 can be provided to the row decoder 460.

[0109] Column address latch 450 can receive column address COL_ADDR from address register 420 and temporarily store the received column address COL_ADDR. Additionally, column address latch 450 can incrementally increment column address COL_ADDR in burst mode. Column address latch 450 can apply the temporarily stored or incrementally incremented column address to column decoder 470.

[0110] In relation to the volume activated by the volume control logic 430, the column decoder 470 can activate the sense amplifier corresponding to the volume address BANK_ADDR and the column address COL_ADDR via the input / output gating circuit 490.

[0111] The input / output gating circuit 490 may include circuitry for gating input / output data, as well as input data masking logic, data registers, and multiplexers.

[0112] The data input / output buffer 495 can synchronize the data signal DT input / output from the data buffer 223 with the clock CLK and adjust the voltage value of the data signal DT.

[0113] when Figure 1 When the first memory module 220_1 to the third memory module 220_3 are implemented as DIMMs like memory module 220_i, each of the first memory module 220_1 to the third memory module 220_3 may commonly include a printed circuit board, a data buffer, an RCD, and a memory device. However, each component of memory modules 220_1 to 220_3 may differ from one another due to product or manufacturing process. Due to this difference, even when the same test cases are applied to the memory devices, the performance of the first memory module 220_1 to the third memory module 220_3 may differ, and Figure 1 The first electronic device 20_1 to the third electronic device 20_3 can generate different test data.

[0114] Figure 7 This is a flowchart illustrating an example of a testing method for electronic devices. Figures 8 to 12 This is a diagram used to explain an example of a test method. Figure 11 It is a diagram. Figure 7 A flowchart of an example of step S210.

[0115] refer to Figures 1 to 3 and Figure 7 The test group generation module TGGM generates test groups TG1 to TG3 corresponding to each of the multiple electronic devices 20_1 to 20_3 (S110).

[0116] For further reference Figure 8 The generated first test group TG1 to the third test group TG3 can be defined in the search space SS used for test cases TC. The first test group TG1 can include multiple first test cases TC1, the second test group TG2 can include multiple second test cases TC2, and the third test group TG3 can include multiple third test cases TC3.

[0117] The first test group TG1 to the third test group TG3 may include at least one common test case TCc with the same test cases, and each of the multiple first test cases TC1 to the third test cases TC3 may include at least one common test case TCc.

[0118] Multiple electronic devices 20_1 to 20_3 perform measurement operations based on multiple corresponding test cases TC1 to TC3 to generate multiple test data TD1 to TD3 (S120).

[0119] The testing equipment 10 can provide each of the first test group TG1 to the third test group TG3 to each of the corresponding plurality of electronic devices 20_1 to 20_3. The testing equipment 10 can provide the first electronic device 20_1 with a plurality of first test cases TC1 corresponding to the first test group TG1, the second electronic device 20_2 with a plurality of second test cases TC2 corresponding to the second test group TG2, and the third electronic device 20_3 with a plurality of third test cases TC3 corresponding to the third test group TG3.

[0120] The first electronic device 20_1 can apply multiple first test cases TC1 from the first test group TG1 and perform measurement operations to generate multiple first test data TD1. The second electronic device 20_2 can apply multiple second test cases TC2 from the second test group TG2 and perform measurement operations to generate multiple second test data TD2. The third electronic device 20_3 can apply multiple third test cases TC3 from the third test group TG3 and perform measurement operations to generate multiple third test data TD3.

[0121] The generated first test data TD1 to the third test data TD3 can be provided to database 30 and stored in database 30.

[0122] Test equipment 10 receives multiple test data TD1 to TD3 for multiple test groups TG1 to TG3 (S130).

[0123] Test equipment 10 can receive multiple test data TD1 to TD3 for multiple test groups TG1 to TG3 from database 30.

[0124] The test group generation module TGGM generates local scores (S140) based on the test data TD.

[0125] For further reference Figure 9 The Test Group Generation Module (TGGM) can perform scoring operations on multiple first test data (TD1) to third test data (TD3) in a unified manner to generate the local score (LS) of the test case (TC).

[0126] The Test Group Generation (TGGM) module can generate local scores (LS) for test cases (TC) by setting the weights of each performance factor in the test data (TD). Figure 6 For example, the Test Group Generation (TGGM) module can set and calculate individual weights for each of the a-th timing margin ta, the b-th timing margin tb, the a-th voltage margin va, and the b-th voltage margin vb in the test data TD to generate a local score LS. For instance, the local score LS can be generated as the sum of weighted performance factors or other combined values.

[0127] The Test Group Generation Module (TGGM) can generate multiple first local scores (LS1) for multiple first test cases (TC1) based on multiple first test data (TD1). The TGGM can also generate multiple second local scores (LS2) for multiple second test cases (TC2) based on multiple second test data (TD2). Finally, the TGGM can generate multiple third local scores (LS3) for multiple third test cases (TC3) based on multiple third test data (TD3).

[0128] A common test case TCc among multiple first test cases TC1, multiple second test cases TC2, and multiple third test cases TC3 can have a first local score LS1 generated based on first test data TD1, a second local score LS2 generated based on second test data TD2, and a third local score LS3 generated based on third test data TD3. Figure 9For example, each of the first public test case TCc1, the second public test case TCc2, and the third public test case TCc3 included in the public test case TCc can have three local scores corresponding to the application of the public test case to each of the electronic devices 20_1, 20_2, and 20_3.

[0129] The test group generation module TGGM finds the locally optimal test cases TClo1 to TClo3 for each test group TG1 to TG3 (S150).

[0130] The Test Group Generation Module (TGGM) can find the first to third locally optimal test cases (TClo1 to TClo3) with the highest local scores for each of the multiple first to third test cases (TC1 to TC3) in test groups (TG1 to TG3).

[0131] by Figure 9 For example, the test group generation module TGGM can find the first locally optimal test case TClo1 with the highest local score among multiple first test cases TC1 in the first test group TG1. The first locally optimal test case TClo1 can be the first common test case TCc1 or another test case in the first test group TG1. The test group generation module TGGM can find the second locally optimal test case TClo2 with the highest local score among multiple second test cases TC2 in the second test group TG2. The second locally optimal test case TClo2 can be the second common test case TCc2 or another test case in the second test group TG2. The test group generation module TGGM can find the third locally optimal test case TClo3 with the highest local score among multiple third test cases TC3 in the third test group TG3. The third locally optimal test case TClo3 can be the third common test case TCc3 or another test case in the third test group TG3. The locally optimal test case is not limited to common test cases, but can include test cases that are only included in a subset of the test group TG (e.g., in a single test group TG).

[0132] The Test Group Generation Module (TGGM) generates multiple global scores (GS) (S160) based on the local scores (LS) of the common test case (TCc).

[0133] by Figure 9For example, the Test Group Generation Module (TGGM) can calculate the first local score LS1 to the third local score LS3 of the first common test case TCc1. Based on the first local score LS1 to the third local score LS3 of the first common test case TCc1, one or more operations are used to generate the global score GS of the first common test case TCc1. The operations may include, but are not limited to, arithmetic mean, geometric mean, minimum selection, and / or weighted operations. Similarly, the Test Group Generation Module (TGGM) can calculate the first local score LS1 to the third local score LS3 of the second common test case TCc2 to generate the global score GS of the second common test case TCc2, and calculate the first local score LS1 to the third local score LS3 of the third common test case TCc3 to generate the global score GS of the third common test case TCc3.

[0134] The global score GS can be a performance indicator that reflects the performance of the first test data TD1 to the third test data TD3 measured across the first electronic device 20_1 to the third electronic device 20_3.

[0135] The test group generation module TGGM replaces the local score LS with the global score GS of the common test case TCc to generate the test score TS (S170) for each test group TG1 to TG3.

[0136] For further reference Figure 10 The Test Group Generation Module (TGGM) can generate multiple first test scores (TS1) for multiple first test cases (TC1) by replacing the first local scores (LS1) of the first common test cases (TCc1 to TCc3) in multiple first local scores (LS1) of multiple first test cases (TC1) with the global score (GS). Similarly, the TGGM can generate second test scores for multiple second test cases (TC2) by replacing the second local scores (LS2) of the first common test cases (TCc1 to TCc3) in multiple second local scores (LS2) of multiple second test cases (TC2) with the global score (GS). The TGGM can also generate third test scores for multiple third test cases (TC3) by replacing the third local scores (LS3) of the first common test cases (TCc1 to TCc3) in multiple third local scores (LS3) of multiple third test cases (TC3) with the global score (GS). Local scores of non-common test cases can be retained, for example, they can be left unreplaced.

[0137] The test score TS can be a performance metric that reflects both the local score LS obtained from a specific electronic device and the global score GS obtained from multiple electronic devices 20_1 to 20_3.

[0138] The first test score TS1 of the first common test cases TCc1 to the third common test cases TCc3 can be the global score GS, and the first test score TS1 of each first test case TC1 excluding the first common test cases TCc1 to the third common test cases TCc3 can be the first local score LS1. Similarly, the second test score of the first common test cases TCc1 to the third common test cases TCc3 can be the global score GS, and the second test score of each second test case TC2 excluding the first common test cases TCc1 to the third common test cases TCc3 can be the second local score LS2. Similarly, the third test score of the first common test cases TCc1 to the third common test cases TCc3 can be the global score GS, and the third test score of each third test case TC3 excluding the first common test cases TCc1 to the third common test cases TCc3 can be the third local score LS3. Thus, for each electronic device 20_1 to 20_3, the test group generation module TGGM can obtain (i) one or more local scores LS corresponding to one or more non-public test cases applied by the electronic device (e.g., by only the electronic device, or by only a subset of the electronic devices), and (ii) one or more global scores GS corresponding to one or more public test cases applied by each electronic device.

[0139] The test group generation module TGGM, for example, finds the optimal test cases TCo1 to TCo3 for each test group TG1 to TG3 from the score set obtained by operation S170 (S180).

[0140] The test group generation module TGGM can find the first optimal test case TCo1 to the third optimal test case TCo3 with the highest test score among the multiple first test cases TC1 to third test cases TC3 in test groups TG1 to TG3.

[0141] by Figure 10 For example, the test group generation module TGGM can find the first optimal test case TCo1 with the highest test score among multiple first test cases TC1 in the first test group TG1. In this example, the first optimal test case TCo1 is the second common test case TCc2. Similarly, the test group generation module TGGM can find the second optimal test case TCo2 (not individually labeled) with the highest test score among multiple second test cases TC2 in the second test group TG2. The test group generation module TGGM can find the third optimal test case TCo3 (not individually labeled) with the highest test score among multiple third test cases TC3 in the third test group TG3.

[0142] The genetic algorithm tool GAT has completed the check test (S190).

[0143] The genetic algorithm tool GAT can check the completion of genetic algorithm operations in test system 1 based on predetermined completion conditions. Predetermined completion conditions may include, but are not limited to, information about the generation targeted by the test operation or the total number of measurement operations in test system 1.

[0144] In response to the completion of the test, the genetic algorithm tool GAT selects the test case with the highest global score GS (S200).

[0145] The genetic algorithm tool GAT can select the test case with the highest global score GS from the public test cases TCc, and the selected test cases can include a combination of robust operating conditions across multiple electronic devices 20_1 to 20_3.

[0146] If the test is not completed, the genetic algorithm tool GAT generates subsequent test groups TGs1 to TGs3 based on the locally optimal test cases TClo1 to TClo3 and the optimal test cases TCo1 to TCo3 for each test group TG1 to TG3 (S210).

[0147] The genetic algorithm tool GAT can generate subsequent test groups TGs1 to TGs3 based on the optimal test cases TCo1 to TCo3 and multiple locally optimal test cases TClo1 to TClo3. These are the successor generations of test groups TG1 to TG3.

[0148] For further reference Figure 11 The mutation module GAM performs mutation operations based on the optimal test cases TCo1 to TCo3 for each test group TG1 to TG3 to generate pre-test groups TGp1 to TGp3 for test groups TG1 to TG3 (S211).

[0149] The mutation module GAM can receive the optimal test cases TCo1 to TCo3 for each test group TG1 to TG3 from the test group generation module TGGM.

[0150] The mutation module GAM can perform mutation operations based on each optimal test case TCo1 to TCo3 to generate pre-test groups TGp1 to TGp3 for each test group TG1 to TG3.

[0151] The mutation module GAM can randomly modify at least some of the operation conditions within the first to third optimal test cases TCo1, TCo2, and TCo3 during mutation operations. These operation conditions can be freely modified, as long as they do not exceed the predefined range within the mutation operation. Information regarding the operation conditions can also be freely modified during mutation operations, provided it does not exceed the predefined mutation rate.

[0152] The mutation module GAM can perform mutation operations based on the first optimal test case TCo1 to generate the first pre-test group TGp1, perform mutation operations based on the second optimal test case TCo2 to generate the second pre-test group TGp2, and perform mutation operations based on the third optimal test case TCo3 to generate the third pre-test group TGp3.

[0153] by Figure 12 For example, the mutation module GAM can randomly modify at least a portion of the first optimal operating conditions te_o11 to te_o14 of the first optimal test case TCo1 to generate pre-test cases TCp11 to TCp1y of the first pre-test group TGp1. For instance, the mutation module GAM can generate pre-operating conditions te_p11 to te_p14 of the 1_1 pre-test case TCp11 by modifying at least a portion of the first optimal operating conditions te_o11 to te_o14. Similarly, the mutation module GAM can generate pre-operating conditions te_py1 to te_py4 of the 1_y pre-test case TCp1y by modifying at least some of the first optimal operating conditions te_o11 to te_o14. Here, y is a predetermined natural number and can be determined, for example, inversely proportional to the number of multiple electronic devices 20_1 to 20_3.

[0154] The genetic algorithm tool GAT can perform mutation operations based on the optimal test cases with the highest test scores for each electronic device 20_1 to 20_3 to generate the first pretest group TGp1 to the third pretest group TGp3 that reflect all the multiple electronic devices 20_1 to 20_3.

[0155] The test group generation module TGGM adds the locally optimal test cases TClo1 to TClo3 of multiple test groups TG1 to TG3 to each of the first pre-test groups TGp1 to the third pre-test group TGp3 to generate subsequent test groups TGs1 to TGs3 of test groups TG1 to TG3 (S212).

[0156] The test group generation module TGGM can receive each of the pre-test groups TGp1 to TGp3 from each of the first test group TG1 to the third test group TG3 from the mutation module GAM.

[0157] The Test Group Generation Module (TGGM) can add multiple locally optimal test cases (TClo1 to TClo3) to each of the first pre-test groups (TGp1 to the third pre-test groups (TGp3)) and generate multiple subsequent test cases in the subsequent test groups (TGs1 to TGs3).

[0158] by Figure 12For example, the test group generation module TGGM can add multiple locally optimal test cases TClo1 to TClo3 to the first pre-test group TGp1 to generate the first subsequent test group TGs1 of the first test group TG1. Similarly, the test group generation module TGGM can add multiple locally optimal test cases TClo1 to TClo3 to the second pre-test group TGp2 to generate the second subsequent test group TGs2 of the second test group TG2. The test group generation module TGGM can add multiple locally optimal test cases TClo1 to TClo3 to the third pre-test group TGp3 to generate the third subsequent test group TGs3 of the third test group TG3.

[0159] The genetic algorithm tool GAT can cross-validate locally optimal test cases for a specific electronic device across multiple electronic devices 20_1 to 20_3 by adding multiple locally optimal test cases TClo1 to TClo3 to each pre-test group TGp1 to TGp3. Furthermore, GAT can ensure a common test case TCc shared by multiple test groups TG1 to TG3 by adding multiple locally optimal test cases TClo1 to TClo3 to each pre-test group TGp1 to TGp3.

[0160] If the test is not completed, the genetic algorithm tool GAT can perform the genetic algorithm operation by repeatedly executing steps S200 and S120 to S180.

[0161] The genetic algorithm tool GAT can efficiently search the search space SS in robust directions across multiple electronic devices 20_1 to 20_3 by repeatedly executing steps S200 and S120 to S180.

[0162] Figure 13 This is a block diagram illustrating an example of a test system. Figure 13 Each of the test equipment 10, electronic equipment 20', and database 30 can correspond to (e.g., substantially similar to) other devices. Figure 1 Each of the test equipment 10, multiple electronic devices 20, and database 30. For ease of explanation, the following will focus on [the following text is incomplete and requires further context]. Figure 1 Description of differences between test equipment 10, multiple electronic devices 20, and database 30 Figure 13 The test equipment 10, electronic equipment 20' and database 30.

[0163] refer to Figure 13 The test system 1' may include test equipment 10, electronic equipment 20' and database 30.

[0164] The test equipment 10 can be controlled to provide the first test group TG1 to the third test group TG3 to an electronic device 20'.

[0165] Electronic device 20' may include device processor 210, first memory modules 220_1 to third memory modules 220_3, device storage device 230, and system bus 240. Electronic device 20' may be a computer-based test device, which is also the environment of the DUT. Each of device processor 210, first memory modules 220_1 to third memory modules 220_3, device storage device 230, and system bus 240 may be respectively connected to... Figure 1 The first processor 210_1 to the third processor 210_3, the first memory module 220_1 to the third memory module 220_3, the first storage device 230_1 to the third storage device 230_3, and the first system bus 240_1 to the third system bus 240_3 correspond to each other.

[0166] For ease of explanation, the following description will focus on the differences between the device processor 210, the first processor 210_1 to the third processor 210_3, the first memory module 220_1 to the third memory module 220_3, the first storage device 230_1 to the third storage device 230_3, and the first system bus 240_1 to the third system bus 240_3.

[0167] The device processor 210 can execute a measurement program EP to apply test cases of the first test group TG1 to the first memory module 220_1, perform measurement operations according to the application of the test cases, and perform various processing operations related to the measurement operations. Furthermore, the device processor 210 can execute a measurement program EP to apply test cases of the second test group TG2 to the second memory module 220_2, perform measurement operations according to the application of the test cases, and perform various processing operations related to the measurement operations. The device processor 210 can also execute a measurement program EP to apply test cases of the third test group TG3 to the third memory module 220_3, perform measurement operations according to the application of the test cases, and perform various processing operations related to the measurement operations.

[0168] For example, device processor 210 can execute measurement program EP to apply test cases of the first test group TG1 to the first memory module 220_1, and control the input / output operation of the first data signal DT1 input / output from the first memory module 220_1. Device processor 210 can execute measurement program EP to measure the signal margin of the first data signal DT1 and generate first test data TD1. Similarly, device processor 210 can execute measurement program EP to apply test cases of the second test group TG2 to the second memory module 220_2, and control the input / output operation of the second data signal DT2 input / output from the second memory module 220_2. Device processor 210 can execute measurement program EP to measure the signal margin of the second data signal DT2 and generate second test data TD2. Similarly, device processor 210 can execute measurement program EP to apply test cases of the third test group TG3 to the third memory module 220_3, and control the input / output operation of the third data signal DT3 input / output from the third memory module 220_3. The device processor 210 can execute the measurement program EP to measure the signal margin of the third data signal DT3 and generate the third test data TD3.

[0169] Each of the first memory modules 220_1 to the third memory modules 220_3 can be a separate DUT. Each of the first memory modules 220_1 to the third memory modules 220_3 can be used as the main memory or system memory of the electronic device 20'. The measurement program EP running on the device processor 210 can be loaded into the first memory modules 220_1 to the third memory modules 220_3.

[0170] The first memory module 220_1 inputs and outputs a first data signal DT1 during the execution of the measurement program EP. The device processor 210 performs measurement operations according to the application of test cases within the first test group TG1, and generates first test data TD1 by executing the measurement program EP loaded into the first memory module 220_1. The second memory module 220_2 inputs and outputs a second data signal DT2 during the execution of the measurement program EP. The device processor 210 performs measurement operations according to the application of test cases within the second test group TG2, and generates second test data TD2 by executing the measurement program EP loaded into the second memory module 220_2. The third memory module 220_3 inputs and outputs a third data signal DT3 during the execution of the measurement program EP. The device processor 210 performs measurement operations according to the application of test cases within the third test group TG3, and generates third test data TD3 by executing the measurement program EP loaded into the third memory module 220_3.

[0171] The first test data TD1 to the third test data TD3 generated in the electronic device 20' can be sent to the database 30 and stored in the database 30.

[0172] Figure 14 This is a block diagram illustrating an example of a test system. Figure 15 This is a block diagram showing an example of a test device. Figure 14 and Figure 15 Each of the test device 10 and the plurality of electronic devices 20 may correspond to (e.g., substantially similar to) other devices. Figure 1 Each of the test equipment 10 and the plurality of electronic devices 20. For ease of explanation, the following will focus on the relationship with... Figure 1 Description of differences between test equipment 10 and multiple electronic devices 20 Figure 14 and Figure 15 The test equipment 10 and multiple electronic devices 20.

[0173] The test system 1'' may include test equipment 10 and multiple electronic devices 20.

[0174] The test device 10 may include a processor 11, a memory 12, a storage device 13, and an input / output device 14. Figure 15 Each of the processor 11, memory 12, storage device 13, and input / output device 14 can be respectively connected to... Figure 2 Each of the processor 11, memory 12, storage device 13, and input / output device 14 corresponds to this. For ease of explanation, the following will focus on... Figure 2 Description of the differences between processor 11, memory 12, storage device 13 and input / output device 14 Figure 15 The processor 11, memory 12, storage device 13, and input / output device 14.

[0175] Storage device 13 may store program code (e.g., computer-readable program code) for executing the genetic algorithm tool GAT and first test data TD1 to third test data TD3 generated from the first electronic device 20_1 to the third electronic device 20_3.

[0176] The first test data TD1 to the third test data TD3 generated from the first electronic device 20_1 to the third electronic device 20_3 can be sent to the test device 10 and stored in the storage device 13 of the test device 10.

[0177] While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of any claims that may be made. Certain features described in this disclosure in the context of individual implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of individual implementations may also be implemented individually or in any suitable sub-combination in multiple implementations. Furthermore, although features may be described above as functioning in certain combinations, in some cases, one or more features from a combination may be removed from the combination, and the combination may be for sub-combinations or variations thereof.

[0178] Although examples have been described in detail above, the scope of this disclosure is not limited thereto, and various modifications and improvements made by those skilled in the art also fall within the scope of this disclosure.

Claims

1. A testing method for an electronic device, the testing method comprising: Receive multiple first test data sets from multiple first test cases and multiple second test data sets from multiple second test cases, wherein... The plurality of first test data and the plurality of second test data indicate the result of one or more electronic devices performing an operation by applying the plurality of first test cases and the plurality of second test cases; Multiple first local scores are generated based on the multiple first test data; Multiple second local scores are generated based on the multiple second test data; A global score is generated based on common test data from the plurality of first test data and the plurality of second test data, wherein the common test data corresponds to common test cases included in the plurality of first test cases and the plurality of second test cases; Replace the first local score in the plurality of first local scores with the global score to generate a plurality of first test scores; Replace the second local scores in the plurality of second local scores with the global score to generate a plurality of second test scores; and A first mutation operation is performed based on the first optimal test case corresponding to the highest score among the plurality of first test scores to generate test cases for the first pre-test group. The test cases of the first pre-test group are configured to be provided to at least one of the one or more electronic devices so that the at least one electronic device applies the test cases of the first pre-test group to perform the operation.

2. The test method as described in claim 1, wherein: Based on the operation of a first electronic device using multiple operating conditions of the plurality of first test cases, the plurality of first test data are measured in the first electronic device, and Based on the operation of a second electronic device that differs from that of the first electronic device using multiple operating conditions of the multiple second test cases, the multiple second test data are measured in the second electronic device.

3. The test method as described in claim 2, wherein: The plurality of first test data includes first signal characteristics of a plurality of first data signals output from a first memory module in the first electronic device based on the operation of the first electronic device under the plurality of operating conditions using the plurality of first test cases, and The plurality of second test data includes second signal characteristics of a plurality of second data signals output from a second memory module in the second electronic device based on the operation of the second electronic device under the plurality of operating conditions using the plurality of second test cases.

4. The test method as described in claim 3, wherein, The generation of the plurality of first local scores includes generating the plurality of first local scores based on a first timing margin and a first voltage margin of the first signal characteristics.

5. The test method as described in claim 3, wherein, The multiple operating conditions of the multiple first test cases include the Mode Register Group (MRS) information of the first memory module.

6. The test method as described in claim 1, wherein: The plurality of first test data are measured in a first memory module within a first electronic device based on the operation of the first memory module under multiple operating conditions using the plurality of first test cases, and The plurality of second test data are measured in a second memory module, which is different from the first memory module in the first electronic device, based on the operation of the second memory module using a plurality of operating conditions of the plurality of second test cases.

7. The test method as described in claim 1, comprising: A second mutation operation is performed based on the second optimal test case corresponding to the highest score among the plurality of second test scores to generate test cases for a second pre-test group. in, The test cases of the second pre-test group are configured to be provided to at least one of the one or more electronic devices, so that the at least one electronic device receiving the test cases of the second pre-test group applies the test cases of the second pre-test group to perform the operation.

8. The test method as described in claim 1, wherein, Generating the global score involves generating the global score based on the following: The third local score among the plurality of first local scores, wherein the third local score corresponds to the common test case, and The fourth local score among the plurality of second local scores, wherein the fourth local score corresponds to the common test case.

9. The test method as described in claim 8, wherein, Generating the global score involves determining the arithmetic mean of the third local score and the fourth local score.

10. The test method as described in claim 1, further comprising: The first locally optimal test case corresponding to the highest score among the plurality of first local scores and the second locally optimal test case corresponding to the highest score among the plurality of second local scores are added to the first pre-test group to generate a plurality of third test cases.

11. The test method as described in claim 1, wherein, The plurality of first test cases include at least one of the following: the core voltage of the row decoder or column decoder of the at least one electronic device, the input / output voltage in the data input / output buffer of the at least one electronic device, the reference voltage of the at least one electronic device, or the time information in the data input / output buffer.

12. A testing method for an electronic device, the testing method comprising: Receive multiple first test data sets from multiple first test cases and multiple second test data sets from multiple second test cases, wherein... The plurality of first test data and the plurality of second test data indicate the result of one or more electronic devices performing an operation by applying the plurality of first test cases and the plurality of second test cases; Multiple first local scores are generated based on the multiple first test data; Multiple second local scores are generated based on the multiple second test data; A first mutation operation is performed based on at least one of the plurality of first test cases to generate test cases for a first pre-test group; A second mutation operation is performed based on at least one of the plurality of first test cases to generate test cases for a second pre-test group; as well as The first locally optimal test case corresponding to the highest score among the plurality of first local scores and the second locally optimal test case corresponding to the highest score among the plurality of second local scores are added to the first pre-test group to generate a subsequent test group including the test cases of the first pre-test group, the first locally optimal test case, and the second locally optimal test case. The subsequent test group is configured to be provided to at least one of the one or more electronic devices so that the at least one electronic device applies the subsequent test group to perform the operation.

13. The test method as described in claim 12, comprising: A global score is generated based on common test data from the plurality of first test data and the plurality of second test data, wherein, The common test data corresponds to the common test cases included in the plurality of first test cases and the plurality of second test cases; Replace at least one of the plurality of first local scores with the global score to generate a plurality of first test scores; as well as Replace at least one of the plurality of second local scores with the global score to generate a plurality of second test scores, wherein: Generating the test cases for the first pre-test group includes performing the first mutation operation based on a first optimal test case corresponding to the highest score among the plurality of first test scores. The test cases for generating the second pre-test group include performing the second mutation operation based on the second optimal test case corresponding to the highest score among the plurality of second test scores.

14. The test method as described in claim 13, wherein, Generating the global score involves generating the global score based on the following: The third local score among the plurality of first local scores, wherein the third local score corresponds to the common test case, and The fourth local score among the plurality of second local scores, wherein the fourth local score corresponds to the common test case.

15. The test method as described in claim 12, wherein, The plurality of first test cases include at least one of the following: the core voltage of the row decoder or column decoder of the at least one electronic device, the input / output voltage in the data input / output buffer of the at least one electronic device, the reference voltage of the at least one electronic device, or the time information in the data input / output buffer.

16. The test method as described in claim 12, wherein: Based on the operation of a first electronic device using multiple operating conditions of the plurality of first test cases, the plurality of first test data are measured in the first electronic device, and Based on the operation of a second electronic device that differs from that of the first electronic device using multiple operating conditions of the multiple second test cases, the multiple second test data are measured in the second electronic device.

17. A testing system, comprising: A first electronic device includes a first memory module, which is configured to output multiple first data by operating under the conditions of multiple first test cases. The first electronic device is configured to generate a plurality of first test data based on the plurality of first data; A second electronic device includes a second memory module configured to output a plurality of second data by operating under the conditions of a plurality of second test cases, wherein the second electronic device is configured to generate a plurality of second test data based on the plurality of second data; and The test equipment is configured as follows: Multiple first local scores are generated based on the multiple first test data. Multiple second local scores are generated based on the multiple second test data. A global score is generated based on common test data from the plurality of first test data and the plurality of second test data, wherein the common test data corresponds to common test cases included in the plurality of first test cases and the plurality of second test cases. Replace at least one of the plurality of first local scores with the global score to generate a plurality of first test scores. Replace at least one of the plurality of second local scores with the global score to generate a plurality of second test scores; and A first mutation operation is performed based on the first optimal test case corresponding to the highest score among the plurality of first test scores to generate test cases for the first pre-test group. The test cases of the first pre-test group are configured to be provided to the first electronic device so that the first memory module operates using the test cases of the first pre-test group.

18. The test system of claim 17, wherein: The testing equipment is configured to add a first locally optimal test case corresponding to the highest score among the plurality of first local scores and a second locally optimal test case corresponding to the highest score among the plurality of second local scores to the first pre-test group to generate a plurality of third test cases.

19. The testing system of claim 17, further comprising: The database is configured to store the plurality of first test data and the plurality of second test data. in, The testing equipment is configured to receive the plurality of first test data and the plurality of second test data from the database.

20. The testing system as described in claim 18, wherein, The testing equipment includes a storage device configured to store the plurality of first test data and the plurality of second test data.

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