Data processing method and device, electronic equipment, chip and storage medium

Abstract

This disclosure provides a data processing method and apparatus, electronic device, chip, and storage medium. The method includes: storing data received on multiple channels into at least one first storage space, wherein the number of at least one first storage spaces is less than or equal to the number of multiple channels; and processing the data stored in the at least one first storage space. This can reduce storage space overhead and improve the utilization efficiency of storage resources in multi-channel scenarios.

Description

Technical Field

[0001] This disclosure relates to the field of data processing, and more particularly to a data processing method, apparatus, electronic device, chip, and storage medium. Background Technology

[0002] Currently, communication technologies place extremely high demands on high bandwidth and low latency. For baseband chips, this requires processing large amounts of data from various services simultaneously, necessitating the use of a significant amount of on-chip static memory (SRAM). The area and power consumption of SRAM have become major bottlenecks in chip design. Efficiently and flexibly managing multi-channel data buffers has become a core challenge for improving chip performance and reducing cost and power consumption. Summary of the Invention

[0003] This disclosure provides a data processing method, apparatus, electronic device, chip, and storage medium that can improve the detail and overall visual appeal of images.

[0004] A first aspect of this disclosure provides a data processing method, the method comprising: storing data received on multiple channels into at least one first storage space, wherein the number of the at least one first storage space is less than or equal to the number of multiple channels; and processing the data stored in the at least one first storage space.

[0005] In some embodiments of this disclosure, storing the received data of multiple channels into at least one first storage space includes: determining the address range occupied by each channel in the at least one first storage space; and storing the data of the multiple channels into the at least one first storage space according to the address range occupied by each channel in the at least one first storage space.

[0006] In some embodiments of this disclosure, determining the address range occupied by each channel in at least one first storage space includes: determining the address range occupied by each channel in at least one first storage space based on at least one of the bandwidth of each channel and the number of multiple channels.

[0007] In some embodiments of this disclosure, determining the address segment occupied by each channel in at least one first storage space based on at least one of the bandwidth of each channel and the number of multiple channels includes: determining a first parameter and a second parameter corresponding to each channel based on at least one of the bandwidth of each channel and the number of multiple channels, wherein the first parameter is used to indicate the starting position of the address segment occupied by each channel in each first storage space, and the second parameter is used to indicate the length of the address segment occupied by each channel in each first storage space; and determining the address segment occupied by each channel in at least one first storage space based on the first parameter and the second parameter.

[0008] In some embodiments of this disclosure, storing data from multiple channels received into at least one first storage space includes: in response to the number of at least one first storage space being multiple, storing two adjacent data received on the same channel into different first storage spaces.

[0009] In some embodiments of this disclosure, storing data received on multiple channels into at least one first storage space includes: serializing the data received on multiple channels to obtain serial data, wherein each data in the serial data corresponds to a channel index; and storing the serial data into at least one first storage space.

[0010] In some embodiments of this disclosure, serializing data received on multiple channels to obtain serial data includes: storing the data received on multiple channels into multiple second storage spaces corresponding to the multiple channels respectively; retrieving data from the multiple second storage spaces in a polling order, and merging the retrieved data into serial data in a polling order.

[0011] In some embodiments of this disclosure, the product of the clock frequency of at least one first storage space, the data bit width of at least one first storage space, and the number of at least one first storage spaces is greater than or equal to the sum of the total bandwidth of the data written and read from the multiple channels.

[0012] In some embodiments of this disclosure, the number of at least one first storage space is equal to the number of multiple channels, wherein each first storage space is used to store data of one channel, and the method further includes: determining the backpressure time, data routing time, data reading duration, and data bit width corresponding to each first storage space; and determining the size of each first storage space based on the backpressure time, data routing time, data reading duration, and data bit width corresponding to each first storage space.

[0013] In some embodiments of this disclosure, calculations are performed using data stored in at least one first storage space to obtain calculation results, including: writing data stored in at least one first storage space into a third storage space through a direct memory access module, wherein the capacity of the third storage space is greater than the capacity of the first storage space; obtaining data in the third storage space through a calculation module, and performing calculation processing on the data.

[0014] A second aspect of this disclosure provides a data processing apparatus, comprising: a storage module for storing data received on a plurality of channels into at least one first storage space, the number of the at least one first storage space being less than or equal to the number of the plurality of channels; and a processing module for processing the data stored in the at least one first storage space.

[0015] In some embodiments of this disclosure, the storage module is further configured to: determine the address range occupied by each channel in at least one first storage space; and store the data of multiple channels into at least one first storage space according to the address range occupied by each channel in at least one first storage space.

[0016] In some embodiments of this disclosure, the storage module is further configured to: determine the address range occupied by each channel in at least one first storage space based on at least one of the bandwidth of each channel and the number of multiple channels.

[0017] In some embodiments of this disclosure, the storage module is further configured to: determine a first parameter and a second parameter corresponding to each channel based on at least one of the bandwidth of each channel and the number of multiple channels, wherein the first parameter is used to indicate the starting position of the address segment occupied by each channel in each first storage space, and the second parameter is used to indicate the length of the address segment occupied by each channel in each first storage space; and determine the address segment occupied by each channel in at least one first storage space based on the first parameter and the second parameter.

[0018] A third aspect of this disclosure provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the methods described in the first aspect of this disclosure.

[0019] A fourth aspect of this disclosure provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to perform the methods described in the first aspect of this disclosure.

[0020] A fifth aspect of this disclosure provides a chip including at least one processor and a communication interface; the communication interface is used to receive signals input to the chip or signals output from the chip, and the processor communicates with the communication interface and implements the method described in the first aspect of this disclosure through logic circuits or executing code instructions.

[0021] In summary, the data processing method proposed in this disclosure can store data received on multiple channels into at least one first storage space, wherein the number of at least one first storage space is less than or equal to the number of multiple channels. This can reduce the area overhead of storage space in multi-channel scenarios, and processing the data stored in at least one first storage space can improve the utilization efficiency of storage resources.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0024] Figure 1 A flowchart illustrating a data processing method provided in this embodiment of the disclosure. Figure 1 ;

[0025] Figure 2 A flowchart illustrating a data processing method provided in this embodiment of the disclosure. Figure 2 ; Figure 3 A flowchart illustrating a data processing method provided in this embodiment of the disclosure. Figure 3 ; Figure 4A An architecture diagram for storing and merging data in a multi-channel data cache is provided in this embodiment of the disclosure; Figure 4B A schematic flowchart illustrating a data storage method provided in an embodiment of this disclosure; Figure 4C A flowchart illustrating another data storage method provided in this embodiment of the disclosure; Figure 4D A schematic diagram of logical partitioning of a storage space provided for an embodiment of this disclosure; Figure 5 This is a schematic diagram of the structure of a data processing apparatus provided in an embodiment of the present disclosure; Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure; Figure 7 This is a schematic diagram of the chip structure provided in an embodiment of this disclosure. Detailed Implementation

[0026] Embodiments of this disclosure are described in detail below. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.

[0027] Current 5G mobile communication technology places extremely high demands on bandwidth and low latency. For 5G baseband chips, this requires processing large amounts of data from various services simultaneously. Therefore, the chip utilizes a significant amount of on-chip static random access memory (SRAM). However, the cost per bit of on-chip SRAM is at least an order of magnitude greater than that of dynamic random access memory (DRAM), often becoming a bottleneck in chip design. Furthermore, in multi-channel scenarios, on-chip SRAM presents the following problems.

[0028] Significant area overhead: The area cost per bit in smaller SRAMs is much higher than that in larger SRAMs. Without merging them, the area cost would increase by approximately 2 to 3 times. Higher power consumption: The larger area leads to a significant increase in static power consumption, especially for baseband chips, which are in a deep sleep state in most scenarios, and static power consumption accounts for a high proportion of the overall power consumption. Isolated storage resources: The storage of multiple channels cannot be shared, and the distribution of busy and idle resources is uneven. To meet the maximum usage scenario, the storage of all channels must be maximized, further increasing costs. High control complexity: A large amount of SRAM involves a large amount of read and write control logic. Given that 5G baseband chips are already very complex, this further increases the risk of overlooking problems. Poor general adaptability: The data caching logic of multiple subsystems is independent, without a unified IP, which increases the time cost of chip development and affects tape-out progress.

[0029] In traditional solutions, multi-channel data caching typically employs two methods: one is to allocate independent SRAM to each channel, resulting in fragmented storage resources, high cost per bit area, and the inability to share resources between channels, forming resource silos with poor resilience to bandwidth fluctuations; the other is to stream data directly to the subsequent computing unit, which saves on caching but requires real-time response from the computing unit, leading to high power consumption and a lack of flexibility. Both methods have significant drawbacks: SRAM has a large area and power consumption; even with smaller SRAMs, the cost per bit area is high, and the fragmented SRAMs cannot share storage, resulting in low data utilization and making them unsuitable for the high-bandwidth scenarios in 5G basebands; the caching logic development cycle is long; in 5G basebands, many subsystems require caching large amounts of data for subsequent use, resulting in a large workload for individual development and wasted manpower; multi-channel control logic is complex; multiple channels mean that each channel needs its own set of control logic, consuming excessive wiring resources, and its low gating rate often becomes a power bottleneck.

[0030] Therefore, in order to solve the above problems, this disclosure proposes a data processing method that can save chip area through merging, unified management, and hardware scheduling of caches.

[0031] The solution disclosed herein can be executed by an electronic device or a chip. The electronic device may be, for example, a terminal. The specific content of the method is as follows.

[0032] Figure 1 A flowchart illustrating a data processing method provided in this embodiment of the disclosure. Figure 1 .like Figure 1 As shown, the method may include the following steps.

[0033] Step 101 involves storing the data received on multiple channels into at least one first storage space.

[0034] In some embodiments, multiple channels can be multiple independent data sources or parallel data transmission paths. These channels exist simultaneously within the system, each carrying an independent data stream, and are the data input sources that the system needs to process in parallel. In the application scenarios of 5G baseband chips, multiple channels can take the following forms: physical receiving channels, such as signal streams received by different antenna elements in a large-scale antenna array, with each antenna corresponding to an independent channel; logical or service channels, such as data streams serving different users, different service types, or different protocol layers within the same frequency band, with each data stream considered as an independent channel; and subsystem data channels, which are data output streams generated by different processing units within the chip (such as modems, codecs, digital front-ends, etc.) that need to be buffered and subsequently processed.

[0035] In some embodiments, data is generated or arrives simultaneously on multiple channels; the data content, timing, and control of each channel are independent of each other; different channels may have different data rates (determined by the sampling rate). and bit width (Decision), meaning that bandwidth demand may be uneven.

[0036] In some embodiments, the first storage space may be an SRAM, or it may be a single-ported random access memory (SPRAM). The number of at least one first storage space is less than or equal to the number of multiple channels. In other words, in the scheme disclosed herein, multiple channels may correspond to one SRAM, and the data of multiple channels may be stored in one SRAM. At least one first storage space may form an SRAM matrix.

[0037] In some embodiments, storing data received on multiple channels into at least one first storage space includes: serializing the data received on multiple channels to obtain serial data, wherein each data in the serial data corresponds to a channel index; and storing the serial data into at least one first storage space.

[0038] In other words, before storing data received from multiple channels into at least one first storage space, the data received from multiple channels can be serialized, converting multi-channel data into single-channel data with an appended channel index to obtain serial data. Then, the serial data can be stored sequentially into the first storage space according to the order in which the data is arranged. The channel index can be used to indicate the original channel corresponding to the data, i.e., the index of the channel that originally transmitted the data.

[0039] In some embodiments, serializing data received on multiple channels to obtain serial data includes: storing the data received on multiple channels into multiple second storage spaces corresponding to the multiple channels respectively; retrieving data from the multiple second storage spaces in a polling order, and merging the retrieved data into serial data in a polling order. The second storage spaces may be First-In-First-Out (FIFO) storage spaces.

[0040] In some embodiments, data from each channel is first written into a small FIFO. The subsequent module (e.g., the serialization module) reads the data from each FIFO sequentially through a polling arbitration method and merges the arbitrated channel index into the data stream, making it easier for the subsequent module to distinguish the source of the data. The polling arbitration can be implemented using a simple counter.

[0041] In some embodiments, the product of the clock frequency of at least one first storage space, the data bit width of at least one first storage space, and the number of at least one first storage spaces is greater than or equal to the sum of the total bandwidth of the data written and read from the multiple channels. This can be expressed as:

[0042] in, The clock frequency of at least one first memory space, in GHz. The data width of at least one first storage space is expressed in bits. The number of at least one first storage space. This represents the sum of the total bandwidth for all channels' data writes and reads.

[0043] In some embodiments, total write bandwidth ( The sampling rate (in Gbps) is determined by the sum of the data rates of all channels, i.e., the sampling rate for each channel. ) and data bit width ( Summing the products of ), the total write bandwidth can be determined using the following formula. .

[0044]

[0045] in, Write bandwidth, measured in Gbps. For channel indexing, This represents the total number of channels. The sampling rate corresponding to channel n. Let be the bit width of each data item in channel n, in bits. Since data needs to be completely buffered without being discarded, the read bandwidth is equal to the write bandwidth, therefore the total bandwidth required by the system is ( This is twice the write bandwidth. Therefore, the total bandwidth formula is as follows:

[0046] In other words, the product of the clock frequency of the first storage space, the data bit width per block, and the number of storage blocks must be greater than or equal to the total data bandwidth required by the system to ensure that the transmission capacity of the first storage space can meet the data throughput requirements during peak periods. For example, in a scenario where a 5G baseband chip processes multi-antenna data streams, the system must simultaneously receive and buffer high-speed data from dozens of channels. In this case, the clock frequency of the memory determines the number of read / write operations it can perform per second; the data bit width determines how many bits can be transferred simultaneously in each operation; and the number of storage blocks represents the number of independent storage units that can work in parallel. The product of these three factors, i.e., the maximum bandwidth that the hardware can provide, must be greater than the sum of the data rates of all channels. If this condition is not met, when all channels are running at full capacity, some data will be lost because it cannot be stored in time, causing the system to malfunction.

[0047] In some embodiments, the number of at least one first storage space is equal to the number of multiple channels, wherein each first storage space is used to store data of one channel, and the method further includes: determining the backpressure time, data routing time, data reading duration, and data bit width corresponding to each first storage space; and determining the size of each first storage space based on the backpressure time, data routing time, data reading duration, and data bit width corresponding to each first storage space.

[0048] In some embodiments, the number of at least one first storage space can be configured to be equal to the number of multiple channels, i.e., each channel exclusively uses an independent first storage space (such as an independent SRAM). Under this configuration, the size of each first storage space can be determined. Further, the size of each first storage space can be determined based on parameters such as backpressure time, data routing time, data read duration, and data bit width corresponding to each first storage space.

[0049] In some embodiments, backpressure time can refer to the duration of write operations that the channel cache must withstand when the third storage space (such as Double Data Rate Synchronous Dynamic Random-Access Memory, DDR) cannot receive data; data routing time can refer to the time it takes for data to be read from the first storage space and transmitted through an internal path to the interface connected to Direct Memory Access (DMA); and data read time can refer to the operation time corresponding to the subsequent module (such as DMA) continuously reading a batch of data from the storage space.

[0050] In some embodiments, the minimum storage capacity required for each independent storage space can be calculated based on the backpressure time, data routing time, data read duration, and data bit width corresponding to each first storage space, combined with the data rate of the channel, thereby achieving precise hardware resource allocation. Furthermore, the total number of cached points required by the SRAM can be used to reflect the size of the first storage space, and the total number of cached points required by the SRAM can be expressed as... ,in The bit width for each data item, The maximum storage time, T1 is the DDR backpressure time, T2 is the data routing time, and T3 is the duration of each data read.

[0051] Step 102: Process the data stored in at least one first storage space.

[0052] In some embodiments, processing the data stored in at least one first storage space may involve performing computational processing on the data stored in at least one first storage space, that is, retrieving data from the first storage space and transferring it to the computation module so that the computation module can perform computation on the data.

[0053] In some embodiments, performing calculations using data stored in at least one first storage space to obtain calculation results includes: writing data stored in at least one first storage space into a third storage space via a direct memory access module, wherein the capacity of the third storage space is greater than the capacity of the first storage space; and retrieving data from the third storage space via a calculation module and performing calculations on the data. The direct memory access module may be a DMA module, which can retrieve data from the first storage space and move the data to the third storage space to facilitate calculations by the calculation module on the data in the third storage space.

[0054] In some embodiments, the capacity of the third storage space is greater than that of the first storage space. That is, by using a large-capacity DDR as a buffer pool, high-speed data streams can be stored smoothly first, and the computing module can read data in batches at appropriate times according to its own rhythm for processing. This reduces the system's stringent requirements for real-time performance and significantly optimizes the overall power consumption. The computing module can enter a low-power state when there are no data tasks.

[0055] In summary, the above embodiments of this disclosure can store data received on multiple channels into at least one first storage space, wherein the number of at least one first storage space is less than or equal to the number of multiple channels. This can reduce the area overhead of storage space in multi-channel scenarios, and improve the utilization efficiency of storage resources by processing the data stored in at least one first storage space.

[0056] Figure 2 A flowchart illustrating a data processing method provided in this embodiment of the disclosure. Figure 2 .like Figure 2 As shown, based on Figure 1 The illustrated embodiment shows that the method includes the following steps.

[0057] Step 201: Determine the address range occupied by each channel in at least one first storage space.

[0058] In some embodiments, determining the address range occupied by each channel in at least one first storage space can be done by determining the logical partition (part) occupied by each channel in at least one first storage space. In other words, each storage space can be divided into multiple logical partitions, each logical partition can correspond to one channel, each channel can have a dedicated logical partition in each first storage space, and the data of each channel can be stored in the corresponding logical partition, which facilitates independent processing of the data of each channel.

[0059] In some embodiments, determining the address range occupied by each channel in at least one first storage space includes: determining the address range occupied by each channel in at least one first storage space based on at least one of the bandwidth of each channel and the number of multiple channels.

[0060] In other words, multiple channels can occupy different address segments, and the size of the address segments occupied by multiple channels can be different. Based on at least one of the bandwidth of each channel and the number of multiple channels, the size of the address segment occupied by each channel in at least one first storage space is determined. In order to allocate resources to channels with larger bandwidth, and to adapt to the variability of channel bandwidth, the address segment occupied by each channel can be dynamically configured. That is, the position and size of the address segment occupied by each channel can be dynamically adjusted to meet the bandwidth requirements of different channels.

[0061] In some embodiments, determining the address segment occupied by each channel in at least one first storage space based on at least one of the bandwidth of each channel and the number of multiple channels includes: determining a first parameter and a second parameter corresponding to each channel based on at least one of the bandwidth of each channel and the number of multiple channels, wherein the first parameter is used to indicate the starting position of the address segment occupied by each channel in each first storage space, and the second parameter is used to indicate the length of the address segment occupied by each channel in each first storage space; and determining the address segment occupied by each channel in at least one first storage space based on the first parameter and the second parameter.

[0062] In some embodiments, the first parameter can be Cfg_ch_buf_idx[N], which can be used to indicate the starting position of the address segment occupied by each of the N channels, such as the index of the starting part occupied by each channel. The second parameter can be Cfg_ch_buf_len[N], which can be used to indicate the length of the address segment occupied by each of the N channels, such as the number of parts occupied.

[0063] Step 202: Storing the data of multiple channels into at least one first storage space according to the address range occupied by each channel in at least one first storage space.

[0064] In some embodiments, the controller can dynamically allocate the address range occupied by each channel. That is, the controller can determine the first parameter and the second parameter, and then store the data of different channels according to the first parameter and the second parameter.

[0065] In summary, the above embodiments of this application, by dividing and managing the dedicated address range of each channel in the shared first storage space, realize unified scheduling and efficient reuse of storage resources, improve the overall storage utilization rate, support dynamic adjustment of the address range size according to the actual bandwidth requirements of each channel, thereby flexibly tilting resources to high-bandwidth channels and adapting to the variability of channel bandwidth.

[0066] Figure 3 A flowchart illustrating a data processing method provided in this embodiment of the disclosure. Figure 3 .like Figure 3 As shown, based on Figure 1 The illustrated embodiment shows that the method includes the following steps.

[0067] Step 301: In response to the fact that there are multiple first storage spaces, two adjacent data received on the same channel are stored in different first storage spaces.

[0068] In some embodiments, when there are multiple first storage spaces, the multiple first storage spaces can be written alternately when writing data. For example, taking two first storage spaces as an example, the two first storage spaces include SRAM0 and SRAM1, then the first data of channel 1 can be written to SRAM0, and the second data of channel 1 can be written to SRAM1.

[0069] In some embodiments, under an architecture with multiple first storage spaces, a strategy of alternately writing data from the same channel to different storage spaces can balance the load of each storage space and parallelize its access bandwidth, thereby effectively improving the system's aggregate bandwidth and ensuring that the data throughput requirements of high-bandwidth channels can be met. Simultaneously, the regular alternating access pattern reduces the risk of conflicts that may arise from consecutive accesses to the same storage block, simplifying the design of timing and control logic. Furthermore, this parallel access capability enhances the system's resilience against backend backpressure; when one storage block is temporarily unavailable due to external latency, other blocks can still maintain continuous data flow processing.

[0070] In summary, the embodiments disclosed above, by distributing continuous data units of the same data channel across multiple physical storage spaces, fully exploit hardware parallelism and significantly optimize system performance. This improves the overall bandwidth and data throughput of the storage system, effectively meets the real-time data access requirements of high-bandwidth channels by utilizing the read / write ports of multiple storage blocks in parallel, optimizes the load balancing and utilization efficiency of storage resources, and allows each storage block to work evenly, thereby improving the overall performance of hardware resources.

[0071] The technical solutions of this disclosure will be further described in detail below with reference to specific application embodiments.

[0072] The following is a method for storing and merging data in a multi-channel data cache, provided by an embodiment of this disclosure. Figure 4A The diagram shows an architecture for storing and merging data in a multi-channel data cache. The overall structure is divided into three parts: the first part is the data from the front-end multi-channel; the second part is the data serialization and SRAM matrix; the data serialization is mainly responsible for serializing the multi-channel data into a single-channel form with an added channel index; and the third part is DMA, which is mainly responsible for writing the cached data into DDR.

[0073] First, the allocation of SRAM resources is guided by calculating the total system bandwidth requirements. Total write bandwidth ( The sampling rate (in Gbps) is determined by the sum of the data rates of all channels, i.e., the sampling rate for each channel. ) and data bit width ( Summing the products of ), the total write bandwidth can be determined using the following formula. .

[0074]

[0075] in, Write bandwidth, measured in Gbps. For channel indexing, This represents the total number of channels. The sampling rate corresponding to channel n. Let be the bit width of each data item in channel n, in bits. Since data needs to be completely buffered without being discarded, the read bandwidth is equal to the write bandwidth, therefore the total bandwidth required by the system is ( This is twice the write bandwidth. Therefore, the total bandwidth formula is as follows:

[0076] in, This represents the theoretical bandwidth of static storage, measured in Gbps. If a single-port SRAM (SPRAM) is used to implement the cache, its configuration must meet the following conditions: operating clock frequency ( (in GHz) multiplied by the data port width of a single SRAM block ( (unit: bits) multiplied by the number of SRAM blocks ( The total throughput obtained must be no less than the total bandwidth requirement. In other words, if static storage is implemented using SPRAM, its theoretical allocation must satisfy the following formula:

[0077] in, Clock frequency, in GHz. This refers to the data width of the SRAM, measured in bits. This represents the number of SRAM blocks.

[0078] For single-channel cache design, such as Figure 4B As shown, SRAM data storage uses a FIFO-like approach, first-in, first-out, and continues storing data from the beginning after the buffer is full. The SRAM size depends on the longest data accumulation time window T that needs to be covered. This window consists of three parts: DDR backpressure time T1, data routing time T2, and the duration of each data read T3 (i.e., ... In other words, the SRAM size mainly depends on several times and the input rate of that channel; that is, the total number of points that the SRAM needs to cache can be expressed as... ,in The bit width for each data item, The maximum storage time, T1 is the DDR backpressure time, T2 is the data routing time, and T3 is the duration of each data read.

[0079] In some embodiments, such as Figure 4C As shown, data from each channel is first written into a small FIFO. Subsequent modules then read the data from each FIFO sequentially using a polling arbitration method, merging the arbitrated channel index into the data stream to facilitate differentiation of data sources. The polling arbitration can be implemented using a simple counter.

[0080] In some embodiments, based on the SRAM allocation method calculated above, and to maximize the number of bits per SRAM block to achieve area gains, the minimum number of SRAM blocks is used. Taking two SRAM blocks as an example, the matrix form is as follows: Figure 4D As shown. The two SRAMs are in odd and even configurations, with data being written and read alternately. Since the total number of channels is N, the number of logical partitions (Parts) in each SRAM also needs to be N. Because each RAM contains data from all channels, it is necessary to calculate the address range occupied by each channel within that RAM. To allocate resources to channels with higher bandwidth and to accommodate the variability of channel bandwidth, the address range occupied by each channel can be dynamically configured. The starting partition index of each channel is set using the parameter Cfg_ch_buf_idx[N] (which can be used to configure the index corresponding to the starting Part occupied by each of the N channels), and the number of partitions occupied by each channel is set using Cfg_ch_buf_len[N] (which can be used to configure how many Parts each of the N channels occupies). This allows for on-demand allocation of storage resources, improving overall utilization.

[0081] In summary, the above examples of this application can save chip area. Taking a 16KB cache as an example, in an 8-channel scenario, the area of ​​the SRAM portion in this solution can be reduced by about 50% compared to distributed SRAM. This solution has strong resistance to fluctuations. When writing to DDR in the later stage, it may be subject to back pressure. The circular SRAM method can withstand a longer back pressure time compared to the alternating odd and even burst level method.

[0082] Figure 5 This is a schematic diagram of the structure of a data processing apparatus 500 provided in an embodiment of this disclosure. Figure 5 As shown, the device includes: a storage module 510 for storing data received on multiple channels into at least one first storage space, wherein the number of the at least one first storage space is less than or equal to the number of multiple channels; and a processing module 520 for processing the data stored in the at least one first storage space.

[0083] In some embodiments, the storage module is further configured to determine the address range occupied by each channel in at least one first storage space; and to store the data of multiple channels into at least one first storage space according to the address range occupied by each channel in at least one first storage space.

[0084] In some embodiments, the storage module is further configured to determine the address range occupied by each channel in at least one first storage space based on at least one of the bandwidth of each channel and the number of multiple channels.

[0085] In some embodiments, the storage module is further configured to determine a first parameter and a second parameter corresponding to each channel based on at least one of the bandwidth of each channel and the number of multiple channels, wherein the first parameter is used to indicate the starting position of the address segment occupied by each channel in each first storage space, and the second parameter is used to indicate the length of the address segment occupied by each channel in each first storage space; and to determine the address segment occupied by each channel in at least one first storage space based on the first parameter and the second parameter.

[0086] In some embodiments, the storage module is further configured to, in response to the presence of at least one first storage space being multiple, store two adjacent data received on the same channel to different first storage spaces.

[0087] In some embodiments, the storage module is further configured to serialize the data received on multiple channels to obtain serial data, each data in the serial data corresponding to a channel index; and to store the serial data in at least one first storage space.

[0088] In some embodiments, the storage module is further configured to store data received on multiple channels into multiple second storage spaces corresponding to multiple channels respectively; retrieve data from multiple second storage spaces in a polling order, and merge the retrieved data into serial data in a polling order.

[0089] In some embodiments, the storage module is further configured such that the product of the clock frequency of at least one first storage space, the data bit width of at least one first storage space, and the number of at least one first storage space is greater than or equal to the sum of the total bandwidth of the data written and read from the multiple channels.

[0090] In some embodiments, the processing module is further configured to determine the backpressure time, data routing time, data reading duration, and data bit width corresponding to each first storage space; and to determine the size of each first storage space based on the backpressure time, data routing time, data reading duration, and data bit width corresponding to each first storage space.

[0091] In some embodiments, the processing module is further configured to write at least one piece of data stored in a first storage space into a third storage space via a direct memory access module, wherein the capacity of the third storage space is greater than the capacity of the first storage space; and to obtain the data in the third storage space via a calculation module and perform calculation processing on the data.

[0092] In summary, the data processing device 500 can store data received on multiple channels into at least one first storage space, wherein the number of at least one first storage spaces is less than or equal to the number of multiple channels. This can reduce the area overhead of storage space in multi-channel scenarios, and improve the utilization efficiency of storage resources by processing the data stored in at least one first storage space.

[0093] The methods and apparatus provided in the embodiments of this application have been described above. To implement the functions of the methods provided in the embodiments of this application, the electronic device may include a hardware structure and software modules, and may implement the above functions in the form of a hardware structure, software modules, or a hardware structure plus software modules. One of the above functions may be executed in the form of a hardware structure, software modules, or a hardware structure plus software modules.

[0094] Figure 6 This is a block diagram illustrating an electronic device 600 for implementing the above-described method according to an exemplary embodiment. For example, the electronic device 600 may be a mobile phone, computer, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0095] Reference Figure 6The electronic device 600 may include one or more of the following components: a processing component 602, a memory 604, a power supply component 606, a multimedia component 608, an audio component 610, an input / output (I / O) interface 612, a sensor component 614, and a communication component 616.

[0096] Processing component 602 typically controls the overall operation of electronic device 600, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 602 may include one or more processors 620 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 602 may include one or more modules to facilitate interaction between processing component 602 and other components. For example, processing component 602 may include a multimedia module to facilitate interaction between multimedia component 608 and processing component 602.

[0097] Memory 604 is configured to store various types of data to support the operation of electronic device 600. Examples of such data include instructions for any application or method operating on electronic device 600, contact data, phonebook data, messages, pictures, videos, etc. Memory 604 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0098] Power supply component 606 provides power to various components of electronic device 600. Power supply component 606 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 600.

[0099] Multimedia component 608 includes a screen that provides an output interface between electronic device 600 and user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 608 includes a front-facing camera and / or a rear-facing camera. When electronic device 600 is in an operating mode, such as a shooting mode or video mode, the front-facing camera and / or rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0100] Audio component 610 is configured to output and / or input audio signals. For example, audio component 610 includes a microphone (MIC) configured to receive external audio signals when electronic device 600 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 604 or transmitted via communication component 616. In some embodiments, audio component 610 also includes a speaker for outputting audio signals.

[0101] I / O interface 612 provides an interface between processing component 602 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0102] Sensor assembly 614 includes one or more sensors for providing state assessments of various aspects of electronic device 600. For example, sensor assembly 614 may detect the on / off state of electronic device 600, the relative positioning of components such as the display and keypad of electronic device 600, changes in position of electronic device 600 or a component of electronic device 600, the presence or absence of user contact with electronic device 600, orientation or acceleration / deceleration of electronic device 600, and temperature changes of electronic device 600. Sensor assembly 614 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 614 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 614 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0103] Communication component 616 is configured to facilitate wired or wireless communication between electronic device 600 and other devices. Electronic device 600 can access wireless networks based on communication standards, such as WiFi, 2G or 3G, 4G LTE, 5G NR (NewRadio), or combinations thereof. In one exemplary embodiment, communication component 616 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 616 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0104] In an exemplary embodiment, the electronic device 600 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0105] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 604 including instructions, which can be executed by a processor 620 of an electronic device 600 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0106] Embodiments of this disclosure also provide a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to perform the methods described in the above embodiments of this disclosure.

[0107] Figure 7 This is a schematic diagram illustrating the structure of a chip 700 for implementing the above method according to an exemplary embodiment. (Refer to...) Figure 7 The chip 700 includes a communication interface 701 and at least one processor 702. The communication interface 701 is used to receive signals input to the chip 700 or signals output from the chip 700. The processor 702 communicates with the communication interface 701 and implements the methods described in the above embodiments of this disclosure through logic circuits or executing code instructions.

[0108] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0109] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in at least one embodiment or example.

[0110] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.

[0111] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processing module, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having at least one wiring (control method), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0112] It should be understood that various parts of the embodiments of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0113] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0114] Furthermore, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc.

[0115] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A data processing method, characterized in that, The method includes: Data received on multiple channels is stored in at least one first storage space, the number of which is less than or equal to the number of channels; The data stored in the at least one first storage space is processed.

2. The method according to claim 1, characterized in that, The step of storing the received data from multiple channels into at least one first storage space includes: Determine the address range occupied by each channel in the at least one first storage space; The data of the plurality of channels are stored in the at least one first storage space according to the address range occupied by each channel in the at least one first storage space.

3. The method according to claim 2, characterized in that, Determining the address range occupied by each channel in the at least one first storage space includes: The address range occupied by each channel in the at least one first storage space is determined based on at least one of the bandwidth of each channel and the number of the plurality of channels.

4. The method according to claim 3, characterized in that, Determining the address range occupied by each channel in the at least one first storage space based on at least one of the bandwidth of each channel and the number of the plurality of channels includes: Based on at least one of the bandwidth of each channel and the number of the plurality of channels, a first parameter and a second parameter corresponding to each channel are determined, wherein the first parameter is used to indicate the starting position of the address segment occupied by each channel in each first storage space, and the second parameter is used to indicate the length of the address segment occupied by each channel in each first storage space; Based on the first parameter and the second parameter, determine the address segment occupied by each channel in the at least one first storage space.

5. The method according to any one of claims 1 to 4, characterized in that, The step of storing the received data from multiple channels into at least one first storage space includes: In response to the fact that there are multiple first storage spaces, two adjacent data received on the same channel are stored in different first storage spaces.

6. The method according to any one of claims 1 to 4, characterized in that, The process of storing data received on multiple channels into at least one first storage space includes: The data received on multiple channels is serialized to obtain serial data, and each piece of data in the serial data corresponds to a channel index; The serial data is stored in the at least one first storage space.

7. The method according to claim 6, characterized in that, The step of serializing the data received on multiple channels to obtain serial data includes: The data received on the multiple channels are stored in the multiple second storage spaces corresponding to the multiple channels respectively; Data is retrieved sequentially from the plurality of second storage spaces in polling order, and the retrieved data is merged into the serial data in polling order.

8. The method according to any one of claims 1 to 4, characterized in that, The product of the clock frequency of the at least one first storage space, the data bit width of the at least one first storage space, and the number of the at least one first storage space is greater than or equal to the sum of the total bandwidth of the data written and read from the plurality of channels.

9. The method according to any one of claims 1 to 4, characterized in that, The number of the at least one first storage space is equal to the number of the plurality of channels, wherein each first storage space is used to store data for one channel. The method further includes: Determine the backpressure time, data routing time, data reading duration, and data bit width for each of the first storage spaces; The size of each first storage space is determined based on the backpressure time, the data routing time, the data reading duration, and the data bit width corresponding to each first storage space.

10. The method according to any one of claims 1 to 4, characterized in that, The step of using data stored in at least one first storage space to perform calculations and obtain calculation results includes: Data stored in at least one first storage space is written to a third storage space via a direct memory access module, wherein the capacity of the third storage space is greater than the capacity of the first storage space. The calculation module obtains data from the third storage space and performs calculations on the data.

11. A data processing apparatus, characterized in that, include: A storage module is configured to store data received on multiple channels into at least one first storage space, wherein the number of the at least one first storage space is less than or equal to the number of multiple channels; The processing module processes the data stored in the at least one first storage space.

12. The apparatus according to claim 11, characterized in that, The storage module is also used for: Determine the address range occupied by each channel in the at least one first storage space; The data of the plurality of channels are stored in the at least one first storage space according to the address range occupied by each channel in the at least one first storage space.

13. The apparatus according to claim 12, characterized in that, The storage module is also used for: The address range occupied by each channel in the at least one first storage space is determined based on at least one of the bandwidth of each channel and the number of the plurality of channels.

14. The apparatus according to claim 13, characterized in that, The storage module is also used for: Based on at least one of the bandwidth of each channel and the number of the plurality of channels, a first parameter and a second parameter corresponding to each channel are determined, wherein the first parameter is used to indicate the starting position of the address segment occupied by each channel in each first storage space, and the second parameter is used to indicate the length of the address segment occupied by each channel in each first storage space; Based on the first parameter and the second parameter, determine the address segment occupied by each channel in the at least one first storage space.

15. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the method of any one of claims 1-10.

16. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-10.

17. A chip, characterized in that, It includes at least one processor and a communication interface; the communication interface is used to receive signals input to the chip or signals output from the chip, and the processor communicates with the communication interface and implements the method as described in any one of claims 1 to 10 through logic circuits or executing code instructions.

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