Flash control system based on address remapping

Abstract

This invention discloses a Flash control system based on address remapping, relating to the field of embedded system storage management technology. It addresses the technical problems of high latency and excessive CPU load in existing technologies, which slow down debugging processes and fail to meet the debugging requirements of large programs. The Flash control system based on address remapping includes an arbitrator, an address remapping table module, a space detection module, and an external bus interface. The arbitrator determines the right to use non-Flash memory areas in the Flash control system. The address remapping table module stores the mapping relationship between Flash memory areas and non-Flash memory areas in the Flash control system in real time during debug mode. The space detection module detects the amount of unused space in non-Flash memory in real time during debug mode. The external bus interface selects different interfaces to access the memory based on the address mapping relationship.

Description

Technical Field

[0001] This invention relates to the field of embedded system storage management technology, and more specifically, to a Flash control system based on address remapping. Background Technology

[0002] In embedded system development, firmware debugging and hardware testing involve frequent program modifications and burning operations. NOR flash memory, a commonly used storage medium, has inherent limitations in its write / erase cycle lifespan, typically only 10-100,000 cycles. However, during debugging, write / erase operations can reach thousands per day, significantly shortening the flash memory's lifespan and even increasing the risk of premature failure, severely impacting development efficiency and system stability.

[0003] Existing software remapping methods achieve address translation through software algorithms, but suffer from high latency and excessive CPU (Central Processing Unit) load, slowing down the debugging process; while hardware caching methods are limited by cache capacity and cannot meet the debugging needs of large programs. Summary of the Invention

[0004] The purpose of this invention is to provide a Flash control system based on address remapping, which solves the technical problems of high latency and excessive CPU load in existing technologies, slowing down the debugging process and failing to meet the debugging requirements of large programs. In view of this, this invention is achieved through the following solution.

[0005] This invention provides a Flash control system based on address remapping, including an arbitrator, an address remapping table module, a space detection module, and an external bus interface; wherein: The arbitrator is used to determine the right to use the non-Flash storage area in the Flash control system; The address remapping table module is used to save the mapping relationship between the Flash storage area and the non-Flash storage area in the Flash control system in real time in debug mode, and the Flash accesses the mapped storage area according to the address remapping table in debug mode. The space detection module is used to detect the size of unused space in non-Flash memory in real time in debug mode; when the unused space is greater than the Flash capacity, the Flash address space is fully mapped; otherwise, the Flash address space is mapped in segments, and the memory type of the mapped space is recorded in the address mapping table. The external bus interface serves as an interaction interface, used to select different interfaces to access the memory based on the address mapping relationship in the address mapping table.

[0006] Compared with existing technologies, the Flash control system based on address remapping of the present invention can be composed of an arbitrator, an address remapping table module, a space detection module, and an external bus interface. Specifically, the arbitrator is used to determine the right to use the non-Flash memory area in the Flash control system; the address remapping table module is used to save the mapping relationship between the Flash memory area and the non-Flash memory area in the Flash control system in real time in debug mode, and the Flash accesses the mapped memory area according to the address mapping table in debug mode; furthermore, the space detection module is used to detect the size of the unused space of the non-Flash memory in real time in debug mode; when the unused space is greater than the Flash capacity, the Flash address space is fully mapped; otherwise, the Flash address space is remapped. The address space is segmented and mapped, and the memory type of the mapped space is recorded in the address mapping table. An external bus interface serves as the interaction interface, used to select different interfaces to access memory based on the address mapping relationship in the address mapping table. Based on the above technical solution, in debug mode, the address space of the Flash memory is mapped to non-Flash memory for program debugging based on the amount of unused space in each memory in the system. After debugging, the program is burned into the Flash memory in programming mode, reducing the number of Flash erase / write cycles. The external bus is connected to the Flash control circuit through the external bus interface. The space detection module monitors the status of non-Flash memory in real time and transmits the information to the address mapping table module. After the address mapping table establishes the mapping relationship, address translation is achieved through the external bus interface. Using the above technical solution, the address remapping-based Flash control system of this invention can meet the debugging needs of large programs, solving the technical problems of high latency and excessive CPU load in existing technologies, which slow down the debugging process and cannot meet the debugging needs of large programs.

[0007] Furthermore, in the address remapping-based Flash control system of the present invention, the space detection module includes an address scanning unit, a space calculation unit, a memory type identification unit, and a data interaction interface; wherein: The address scanning unit is used to determine the available space status of the non-Flash memory in debug mode, providing a basis for address mapping decisions; The spatial computing unit is used to perform address-by-address scanning of the address space of candidate non-Flash memory in the system at a preset scanning frequency via an external bus interface. The memory type identification unit is used to bind the free address region identified by the address scanning unit to a non-Flash memory; The data interaction interface is used to write to the address mapping table; The non-Flash memory includes static random access memory and synchronous dynamic random access memory; The non-Flash storage area includes a static random access memory (SRAM) storage area and a synchronous dynamic random access memory (DRAM) storage area.

[0008] Furthermore, in the address remapping-based Flash control system of the present invention, the address remapping table module includes a mapping relationship storage unit, an address translation logic unit, and an update interface; The mapping relationship storage unit uses static random access memory as the storage medium to store the correspondence between Flash address segments and target non-Flash memory address segments; The address translation logic unit is used to receive the Flash access address transmitted by the system, determine the Flash address segment to which the Flash access address belongs by searching the mapping relationship storage unit, and determine the access address of the target non-Flash memory based on the Flash address segment. The update interface is used to detect update signals from the space detection module and the arbitrator.

[0009] Furthermore, in the address remapping-based Flash control system of the present invention, the mapping relationship storage unit has mapping entries; The mapping entry includes fields such as a 32-bit Flash start address, a 32-bit Flash end address, an 8-bit target memory type, a 32-bit target start address, and a valid flag bit; for the valid flag bit, 1 indicates valid and 0 indicates invalid. In a segmented mapping scenario, the mapping relationship storage unit dynamically allocates multiple mapping entries to record the mapping information of each segment.

[0010] Furthermore, in the address remapping-based Flash control system of the present invention, for unaligned addresses, the address conversion logic unit has built-in offset calculation logic to calculate the offset value according to the preset alignment requirements and correct the converted address.

[0011] Furthermore, in the address remapping-based Flash control system of the present invention, when the space detection module detects a change in the available space status of the non-Flash memory, or when the arbitrator detects a change in the memory type, the update interface triggers the update process of the mapping relationship storage unit. The update process includes: first marking the old mapping entry as invalid, and then writing the new mapping entry. The entire update process is completed within one bus clock cycle.

[0012] Furthermore, in the address remapping-based Flash control system of the present invention, the arbitrator includes a request receiving unit, a priority arbitration logic unit, a conflict detection unit, and an authorization signal generation unit; The request receiving unit is used to receive various access request signals through the request line connected to the system bus and the debug request line for address remapping, parse the memory address and operation type in the request, and temporarily store the memory address and operation type in the request buffer. The priority arbitration logic unit has a built-in priority rule register for storing priority configuration information in debug mode and non-debug mode; The conflict detection unit is used to monitor the number of requests for the same non-Flash memory in the request buffer in real time. When the number of requests is greater than 1, it is determined that there is an access conflict and the conflict information is sent to the priority arbitration logic unit to trigger the priority judgment process. The authorization signal generation unit is used to generate an authorization signal for the target non-Flash memory based on the priority judgment result of the priority arbitration logic unit, and send it to the winning requester; the authorization signal includes a chip select signal and an access enable signal.

[0013] Furthermore, in the address remapping-based Flash control system of the present invention, in debug mode, the external bus interface converts the Flash access address issued by the system into the physical address of the target non-Flash memory according to the address mapping relationship in the address mapping table, and generates control signals.

[0014] Furthermore, in the address remapping-based Flash control system of the present invention, in the programming mode, the external bus interface transmits the programming address and data issued by the system to the Flash to realize program programming.

[0015] Furthermore, in the address remapping-based Flash control system of the present invention, the data bus width of the external bus interface supports 8-bit, 16-bit, and 32-bit adaptive bandwidth. Attached Figure Description

[0016] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of the structure of a Flash control system based on address remapping according to the present invention; Figure 2 This is a schematic diagram of the working process of the Flash control system of the present invention; Figure 3This is a schematic diagram of an initialization process for the Flash control system of the present invention; Figure 4 This is a storage diagram illustrating how unused space is marked using custom codewords in this invention. Figure 5 This is a schematic diagram illustrating the calculation of unused space size using hardware bitmaps in this invention. Detailed Implementation

[0017] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0018] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0019] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0020] Existing software remapping methods achieve address translation through software algorithms, but suffer from high latency and excessive CPU load, slowing down the debugging process; while hardware caching methods are limited by cache capacity and cannot meet the debugging needs of large programs.

[0021] To address the aforementioned technical problems, this invention provides a Flash control system based on address remapping, comprising an arbitrator, an address remapping table module, a space detection module, and an external bus interface; wherein: The arbitrator is used to determine the right to use the non-Flash storage area in the Flash control system; The address remapping table module is used to save the mapping relationship between the Flash storage area and the non-Flash storage area in the Flash control system in real time in debug mode, and the Flash accesses the mapped storage area according to the address remapping table in debug mode. The space detection module is used to detect the size of unused space in non-Flash memory in real time in debug mode; when the unused space is greater than the Flash capacity, the Flash address space is fully mapped; otherwise, the Flash address space is mapped in segments, and the memory type of the mapped space is recorded in the address mapping table. The external bus interface serves as an interaction interface, used to select different interfaces to access the memory based on the address mapping relationship in the address mapping table.

[0022] With the above technical solution, the Flash control system based on address remapping of the present invention can be composed of an arbitrator, an address remapping table module, a space detection module, and an external bus interface. Specifically, the arbitrator is used to determine the right to use the non-Flash memory area in the Flash control system; the address remapping table module is used to save the mapping relationship between the Flash memory area and the non-Flash memory area in the Flash control system in real time in debug mode, and the Flash accesses the mapped memory area according to the address mapping table in debug mode; furthermore, the space detection module is used to detect the size of the unused space of the non-Flash memory in real time in debug mode; when the unused space is greater than the Flash capacity, the Flash address space is fully mapped; otherwise, the Flash address space is remapped. The flash address space is segmented and mapped, and the memory type of the mapped space is recorded in the address mapping table. An external bus interface serves as the interaction interface, used to select different interfaces to access memory based on the address mapping relationship in the address mapping table. Based on the above technical solution, in debug mode, the Flash address space is mapped to non-Flash memory for program debugging based on the amount of unused space in each memory in the system. After debugging, the program is burned into the Flash in programming mode, reducing the number of Flash erase / write cycles. The external bus is connected to the control circuit through the external bus interface. The space detection module monitors the status of non-Flash memory in real time and transmits the information to the address mapping table module. After the address mapping table establishes the mapping relationship, address translation is achieved through the external bus interface. Using the above technical solution, the Flash control system based on address remapping of this invention can meet the debugging needs of large programs, solving the technical problems of high latency and excessive CPU load in existing technologies, which slow down the debugging process and cannot meet the debugging needs of large programs.

[0023] To better understand the present invention, the following specific embodiments further illustrate the content of the present invention, but the content of the present invention is not limited to the following embodiments.

[0024] Example 1 Please see Figure 1This embodiment provides a Flash control system based on address remapping, including an arbitrator, an address remapping table module, a space detection module, and an external bus interface; wherein: The arbitrator is used to determine the right to use non-Flash storage areas in the Flash control system; Furthermore, in this embodiment, the arbitrator includes a request receiving unit, a priority arbitration logic unit, a conflict detection unit, and an authorization signal generation unit; wherein: The request receiving unit is used to receive various access request signals through the request line connected to the system bus and the debug request line for address remapping, parse the memory address and operation type in the request, and temporarily store the memory address and operation type in the request buffer. The priority arbitration logic unit has a built-in priority rule register for storing priority configuration information in debug mode and non-debug mode; The conflict detection unit is used to monitor the number of requests for the same non-Flash memory in the request buffer in real time. When the number of requests is greater than 1, it is determined that there is an access conflict and the conflict information is sent to the priority arbitration logic unit to trigger the priority judgment process. The authorization signal generation unit is used to generate an authorization signal for the target non-Flash memory based on the priority judgment result of the priority arbitration logic unit, and send it to the winning requester; the authorization signal includes a chip select signal and an access enable signal.

[0025] The address remapping table module is used to save the mapping relationship between the Flash storage area and the non-Flash storage area in the Flash control system in real time in debug mode, and the Flash accesses the mapped storage area according to the address remapping table in debug mode. Furthermore, in this embodiment, the address remapping table module includes a mapping relationship storage unit, an address translation logic unit, and an update interface; wherein: The mapping relationship storage unit uses SRAM (Static Random Access Memory) as the storage medium to store the correspondence between Flash address segments and target non-Flash memory address segments; The address translation logic unit is used to receive the Flash access address from the system, determine the Flash address segment to which the Flash access address belongs by looking up the mapping relationship storage unit, and determine the access address of the target non-Flash memory based on the Flash address segment. The update interface is used to detect update signals from the space detection module and the arbitrator.

[0026] Furthermore, the mapping relationship storage unit has mapping entries; the mapping entries contain fields including a 32-bit Flash start address, a 32-bit Flash end address, an 8-bit target memory type, a 32-bit target start address, and a valid flag bit; for the valid flag bit, 1 indicates valid and 0 indicates invalid; in the segmented mapping scenario, the mapping relationship storage unit dynamically allocates multiple mapping entries to record the mapping information of each segment; for unaligned addresses, the address translation logic unit has built-in offset calculation logic to calculate the offset value according to the preset alignment requirements and correct the converted address; when the space detection module detects a change in the available space status of the non-Flash memory, or the arbitrator detects a change in the memory type, the update interface triggers the update process of the mapping relationship storage unit. The update process is as follows: first mark the old mapping entry as invalid, then write the new mapping entry. The entire update process is completed within one bus clock cycle.

[0027] The space detection module is used to detect the size of unused space in non-Flash memory in real time in debug mode; if the unused space is greater than the Flash capacity, the Flash address space is fully mapped; otherwise, the Flash address space is mapped in segments, and the memory type of the mapped space is recorded in the address mapping table. Furthermore, in this embodiment, the space detection module includes an address scanning unit, a space calculation unit, a memory type identification unit, and a data interaction interface; wherein: The address scanning unit is used to determine the available space status of non-Flash memory in debug mode, providing a basis for address mapping decisions; The spatial computing unit is used to scan the address space of candidate non-Flash memory in the system address by address through an external bus interface at a preset scanning frequency; The memory type identification unit is used to bind the free address region identified by the address scanning unit to non-Flash memory; The data interaction interface is used to write to the address mapping table; In this embodiment, the non-Flash memory includes SRAM and SDRAM; the non-Flash storage area includes SRAM storage area and SDRAM storage area; wherein, SRAM stands for Static Random Access Memory; SDRAM stands for Synchronous Dynamic Random Access Memory.

[0028] The external bus interface serves as an interaction interface, used to select different interfaces to access memory based on the address mapping relationship in the address mapping table; Furthermore, in this embodiment, in debug mode, the external bus interface converts the Flash access address issued by the system into the physical address of the target non-Flash memory according to the address mapping relationship in the address mapping table, and generates control signals; in programming mode, the external bus interface transmits the programming address and data issued by the system to the Flash to realize program programming. The data bus width of the external bus interface supports 8-bit, 16-bit and 32-bit adaptive.

[0029] Example 2 This embodiment provides a Flash control system based on address remapping, including an arbitrator, an address remapping table module, a space detection module, and an External Bus Interface (EBI); wherein: The space detection module mainly consists of an address scanning unit, a space calculation unit, a memory type identification unit, and a data interaction interface. In this embodiment, the space detection module is the foundation for address remapping. Its core function is to accurately and in real time grasp the available space status of non-Flash memory in debug mode, providing a basis for address mapping decisions. The space detection module scans the address range of all candidate non-Flash memory in the system. By traversing the address space of each memory and combining the used address marking information fed back by the memory controller, it determines the used and unused space of each memory. It compares the size of the unused space of each non-Flash memory with the capacity of the Flash memory region to be mapped. If the unused space of a certain non-Flash memory is greater than or equal to the Flash capacity, then the non-Flash memory can be used as a candidate region for complete mapping. If the unused space of all non-Flash memory is less than the Flash capacity, then the segmented mapping mechanism is activated, and the Flash memory region is segmented according to the available space size of the non-Flash memory, so that each segment of the Flash region corresponds to the available space of one or more non-Flash memory regions.

[0030] The address scanning unit scans the address space of all candidate non-Flash memories in the system address by address through the external bus interface at a preset scanning frequency (adjustable via the configuration register, default 100ms / time). Through continuous scanning, the address scanning unit can determine the boundaries of used and unused addresses for each memory. The space calculation unit receives the used and unused address boundary information from the address scanning unit and calculates the size of the unused space of each non-Flash memory by difference. The calculation formula is: unused space size = unused address end boundary - unused address start boundary + 1. After calculation, the unit compares the size of the unused space of each non-Flash memory with the capacity parameter of the Flash region to be mapped. If the unused space of a certain non-Flash memory is greater than or equal to the Flash capacity, it is marked as a complete mapping candidate region. If the unused space of all non-Flash memories is less than the Flash capacity, the segmented mapping mechanism is triggered.

[0031] The core function of the aforementioned memory type identification unit is to bind the free address region identified by the address scanning unit to a specific non-Flash storage device. The memory type identification unit determines the memory type by reading the device identifier register of the non-Flash storage device (the identifier register address and value differ for different types of memory; for example, SRAM is typically 0x0001, and SDRAM is 0x0002). After associating the start / end address of the free address region with the memory type information, it writes the information to the address mapping table through a data interaction interface. This embodiment uses synchronous communication to transmit the detection results (including memory type, address range, and unused space size) from the space detection module to the address mapping table in real time. The transmission rate is consistent with the internal bus clock frequency, ensuring that the address mapping table can obtain the latest memory status information in a timely manner.

[0032] Furthermore, the address remapping table module in this embodiment consists of a mapping relationship storage unit, an address translation logic unit, and an update interface. In this embodiment, the mapping relationship storage unit uses high-speed SRAM as the storage medium, and its capacity can be configured according to system requirements, supporting a minimum of 1KB and a maximum of 64KB. It is used to store the correspondence between Flash address segments and target non-Flash memory address segments. Each mapping entry contains 5 fields: 32-bit Flash start address, 32-bit Flash end address, 8-bit target memory type, 32-bit target start address, and a valid flag bit, where 1 indicates valid and 0 indicates invalid. For segmented mapping scenarios, the mapping relationship storage unit can dynamically allocate multiple mapping entries to record the mapping information of each segment. For example, the 0x0000-0x1FFF segment of Flash can be mapped to the 0x8000-0x9FFF segment of SRAM, and the 0x2000-0x3FFF segment can be mapped to the 0x20000-0x21FFF segment of SDRAM.

[0033] Specifically, when debug mode is started, the address remapping table module receives candidate region information (including memory type, address range, available space, etc.) from the space detection module. Based on either a complete mapping or segmented mapping scheme, it establishes a one-to-one correspondence between Flash addresses and target memory addresses. For complete mapping, the starting address of the Flash is mapped to the starting address of the target memory, with consistent address offsets. For segmented mapping, different address segments of the Flash are mapped to address segments of different non-Flash memories, and the starting address and length of each segment are recorded. When the system issues an access address to the Flash, the address remapping table module queries the internal mapping relationship to convert the Flash address to the corresponding non-Flash memory address. For unaligned addresses, the address translation logic calculates the address offset and adds the offset value to the converted address to achieve correct mapping of the unaligned address. When the available space status of the non-Flash memory changes, the address remapping table module receives relevant update signals and updates the internal mapping relationship in real time to ensure the accuracy of address translation.

[0034] Furthermore, in this embodiment, the address translation logic unit receives the Flash access address from the system, determines the Flash address segment to which the Flash access address belongs by searching the mapping relationship storage unit, and then calculates the access address of the target non-Flash memory based on the corresponding target address segment information. For unaligned addresses, the unit has built-in offset calculation logic to calculate the offset value according to the preset alignment requirements and correct the converted address. The update interface detects update signals from the space detection module and the arbitrator in real time. When the space detection module detects a change in the available space status of the non-Flash memory (such as the addition of unused space or the expansion of used space), or the arbitrator detects a change in the memory type, the update interface triggers the update process of the mapping relationship storage unit. The update process is as follows: first, mark the old mapping entry as invalid, and then write the new mapping entry. The entire update process is completed within one bus clock cycle to ensure the real-time performance of address translation.

[0035] Furthermore, in this embodiment, the arbitrator mainly consists of a request receiving unit, a priority arbitration logic unit, a conflict detection unit, and an authorization signal generation unit. The core function of the arbitrator is to resolve the contention for access rights to the non-Flash memory area. That is, when the system bus and the address remapping circuit (in debug mode) simultaneously request access to the same non-Flash memory, the arbitrator determines which requester will gain access rights, thus ensuring the orderliness of memory access and the priority of the debugging process. Specifically, the arbitrator receives access requests from the system bus and debug access requests from the address remapping module in real time, and distinguishes the source of the request by the characteristics of the request signal. When the system is in debug mode, the debug access request from the address remapping circuit has higher priority; when the system is in non-debug mode, the access request from the system bus has higher priority. Meanwhile, the arbitrator also considers the urgency of the request and the current state of the memory, dynamically adjusting the priority. When a bus access request and a debug access request are received simultaneously for the same non-Flash memory, a conflict handling mechanism is activated. If the debug access request has a higher priority, a "wait" signal is sent to the bus to suspend bus access and allow the debug access to execute first. If the bus access request has a higher priority, a "delay" signal is sent to the address remapping circuit, allowing the debug access to execute only after the bus access is completed. In the case of segmented mapping involving multiple non-Flash memories, the arbitrator will arbitrate the access requests of each memory separately, without interference between them.

[0036] Furthermore, the request receiving unit in the arbitrator receives various access request signals via the request line connected to the system bus and the debug request line connected to the address remapping circuit. It parses information such as the memory address and operation type in the request and temporarily stores it in the request buffer. The priority arbitration logic unit has a built-in priority rule register to store priority configuration information in debug and non-debug modes. It receives request information from the request receiving unit and, combined with the current system operating mode and memory state, prioritizes multiple requests for the same target memory to determine the winning requester. The conflict detection unit monitors the number of requests for the same non-Flash memory in the request buffer in real time. When the number is greater than one, it determines that an access conflict exists and sends the conflict information to the priority arbitration logic unit, triggering the priority judgment process. The authorization signal generation unit generates an authorization signal for the target non-Flash memory based on the priority judgment result of the priority arbitration logic unit and sends it to the winning requester. The authorization signal includes a chip select signal and an access enable signal. Simultaneously, it generates a "wait" or "delay" signal and sends it to the losing requester, achieving orderly allocation of memory access rights.

[0037] Furthermore, in this embodiment, an external bus interface is used to connect storage devices such as Flash and SRAM to realize the conversion and transmission of address, data, and control signals. In debug mode, the external bus interface converts the Flash access address issued by the system into the physical address of the target non-Flash memory according to the address mapping relationship in the address mapping table, and generates corresponding control signals. In programming mode, the external bus interface directly transmits the programming address and data issued by the system to the Flash to realize program programming. The data bus width of the external bus interface supports 8-bit, 16-bit, and 32-bit adaptive switching, which can be automatically adjusted according to the type of connected memory to ensure data transmission efficiency.

[0038] Furthermore, in this embodiment, in order for the address scanning unit to calculate the size of the unused space, firstly, the size of the unused space can be marked by a custom codeword; secondly, the size of the unused space can also be calculated by a hardware bitmap. Specifically, for the first aspect, please refer to... Figure 4 This primarily involves writing custom codewords into unused address segments of SRAM. The address scanning unit then queries these codewords to obtain the start and end addresses of the unused space, thereby calculating the available space. To reduce the probability of failure, the codewords can be encoded to decrease their appearance in program code, stack data, heap data, and pointer values. Figure 4In this method, "x" indicates that data has been written to that address, "0" indicates that it is unused, "#" represents the starting address of the unused space, and "!" represents the ending address of the unused space. The size of the free space is calculated by detecting "#" and "!". The advantages of this method are low hardware resource consumption and low cost. The disadvantages are that the probability of failure is directly related to the custom codewords used; the codewords used must have an extremely low probability of appearing in normal program code, stack data, heap data, and pointer values. Furthermore, this method is relatively slow. For further details, please refer to [link to relevant documentation]. Figure 5 Regarding the second aspect, a hardware bitmap is needed to indicate the usage status of the SRAM. The bitmap is 1 bit wide and has the same depth as the SRAM. The address scan unit can calculate the amount of unused space using the bitmap. When the CPU or Direct Memory Access (DMA) controller performs a write operation on the main SRAM, the hardware memory controller synchronously and automatically updates the corresponding bit in the hardware bitmap: 1 indicates used, and 0 indicates unused. This process is transparent to the software and requires no CPU intervention. Figure 5 As shown, "x" indicates that data has been written to that address, and "0" indicates that it is unused. The address scanning unit can calculate the size of the unused space in the SRAM by reading the number of "0"s in the bitmap. The advantages of this method are high speed and high accuracy, but the disadvantages are that it consumes certain hardware resources and is complex to design. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0039] Further, please refer to Figure 2 and Figure 3 , combined Figure 2 and Figure 3 The workflow and initialization process shown below further illustrate the address remapping-based Flash control system of the present invention. Debug means debugging.

[0040] exist Figure 2 In the process of system operation, if program debugging is required, it should be done according to... Figure 2 The middle-left branch operates by initializing the control circuit; see detailed description below. Figure 3The Flash control system obtains the address to be accessed from AXI / AHB, accesses the target non-Flash storage area according to the address mapping table, and if there is a conflict, the access is determined by the priority arbitration unit. If authorized, the target memory is accessed through the external bus interface; otherwise, it waits. If the system is in programming mode, the data is directly solidified in the Flash through the external bus interface. Here, AHB stands for Advanced High Performance Bus, and AXI stands for Advanced Extensible Interface, which is a high-performance, high-bandwidth, and low-latency interface standard.

[0041] exist Figure 3 In the initialization process, the goal of the control circuit is to complete the scan of the non-Flash memory area and perform address mapping. Specifically, if the unused space is greater than the Flash capacity, it is fully mapped; otherwise, the Flash address space is segmented and mapped to the non-Flash memory. In debug mode, once the non-Flash memory data is updated, the address mapping table needs to be updated synchronously.

[0042] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A Flash control system based on address remapping, characterized in that, It includes an arbitrator, an address remapping table module, a space detection module, and an external bus interface; among which: The arbitrator is used to determine the right to use the non-Flash storage area in the Flash control system; The address remapping table module is used to save the mapping relationship between the Flash storage area and the non-Flash storage area in the Flash control system in real time in debug mode, and the Flash accesses the mapped storage area according to the address remapping table in debug mode. The space detection module is used to detect the size of unused space in non-Flash memory in real time in debug mode; when the unused space is greater than the Flash capacity, the Flash address space is fully mapped; otherwise, the Flash address space is mapped in segments, and the memory type of the mapped space is recorded in the address mapping table. The external bus interface serves as an interaction interface, used to select different interfaces to access the memory based on the address mapping relationship in the address mapping table.

2. The Flash control system based on address remapping according to claim 1, characterized in that, The space detection module includes an address scanning unit, a space calculation unit, a memory type identification unit, and a data interaction interface; wherein: The address scanning unit is used to determine the available space status of the non-Flash memory in debug mode, providing a basis for address mapping decisions; The spatial computing unit is used to perform address-by-address scanning of the address space of candidate non-Flash memory in the system at a preset scanning frequency via an external bus interface. The memory type identification unit is used to bind the free address region identified by the address scanning unit to a non-Flash memory; The data interaction interface is used to write to the address mapping table; The non-Flash memory includes static random access memory and synchronous dynamic random access memory; The non-Flash storage area includes a static random access memory (SRAM) storage area and a synchronous dynamic random access memory (DRAM) storage area.

3. The Flash control system based on address remapping according to claim 2, characterized in that, The address remapping table module includes a mapping relationship storage unit, an address translation logic unit, and an update interface; The mapping relationship storage unit uses static random access memory as the storage medium to store the correspondence between Flash address segments and target non-Flash memory address segments; The address translation logic unit is used to receive the Flash access address transmitted by the system, determine the Flash address segment to which the Flash access address belongs by searching the mapping relationship storage unit, and determine the access address of the target non-Flash memory based on the Flash address segment. The update interface is used to detect update signals from the space detection module and the arbitrator.

4. The Flash control system based on address remapping according to claim 3, characterized in that, The mapping relationship storage unit has mapping entries; The mapping entry includes fields such as a 32-bit Flash start address, a 32-bit Flash end address, an 8-bit target memory type, a 32-bit target start address, and a valid flag bit; for the valid flag bit, 1 indicates valid and 0 indicates invalid. In a segmented mapping scenario, the mapping relationship storage unit dynamically allocates multiple mapping entries to record the mapping information of each segment.

5. The Flash control system based on address remapping according to claim 4, characterized in that, For unaligned addresses, the address conversion logic unit has built-in offset calculation logic to calculate the offset value according to the preset alignment requirements and correct the converted address.

6. The Flash control system based on address remapping according to claim 5, characterized in that, When the space detection module detects a change in the available space status of the non-Flash memory, or when the arbitrator detects a change in the memory type, the update interface triggers the update process of the mapping relationship storage unit, the update process including: First, mark the old mapping entry as invalid, then write the new mapping entry. The entire update process is completed within one bus clock cycle.

7. The Flash control system based on address remapping according to claim 1, characterized in that, The arbitrator includes a request receiving unit, a priority arbitration logic unit, a conflict detection unit, and an authorization signal generation unit; wherein: The request receiving unit is used to receive various access request signals through the request line connected to the system bus and the debug request line for address remapping, parse the memory address and operation type in the request, and temporarily store the memory address and operation type in the request buffer. The priority arbitration logic unit has a built-in priority rule register for storing priority configuration information in debug mode and non-debug mode; The conflict detection unit is used to monitor the number of requests for the same non-Flash memory in the request buffer in real time. When the number of requests is greater than 1, it is determined that there is an access conflict and the conflict information is sent to the priority arbitration logic unit to trigger the priority judgment process. The authorization signal generation unit is used to generate an authorization signal for the target non-Flash memory based on the priority judgment result of the priority arbitration logic unit, and send it to the winning requester; the authorization signal includes a chip select signal and an access enable signal.

8. The Flash control system based on address remapping according to claim 1, characterized in that, In debug mode, the external bus interface converts the Flash access address issued by the system into the physical address of the target non-Flash memory according to the address mapping relationship in the address mapping table, and generates control signals.

9. The Flash control system based on address remapping according to claim 8, characterized in that, In programming mode, the external bus interface transmits the programming address and data issued by the system to the Flash memory to enable program programming.

10. The Flash control system based on address remapping according to claim 9, characterized in that, The external bus interface supports 8-bit, 16-bit, and 32-bit adaptive data bus width.

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