A symbol simulation verification method, device and equipment of a digital circuit and a medium

Abstract

This invention discloses a method, apparatus, device, and medium for symbolic simulation verification of digital circuits, applied to a symbolic simulator. The method includes acquiring the circuit description file and symbolic simulation flow script corresponding to the circuit to be verified; parsing the circuit description file and constructing a symbolic state transition model; initializing the symbolic states corresponding to the circuit to be verified according to the symbolic state transition model; driving the symbolic states to perform simulation updates cycle by cycle according to the symbolic simulation flow script and the symbolic state transition model until the loop termination condition is met; and performing assertion verification on all symbolic states at the current moment to generate the simulation verification result corresponding to the circuit to be verified. Thus, by introducing symbolic quantities, path constraints, and path bifurcation mechanisms, a systematic exploration of the behavior space of digital circuits is achieved, effectively improving verification coverage and reducing the complexity of assertion construction and verification processes.

Description

Technical Field

[0001] This invention belongs to the field of circuit simulation technology and relates to a symbolic simulation verification method, apparatus, device, and medium for digital circuits. Background Technology

[0002] With the rapid iteration of VLSI technology, the scale, integration and logic complexity of integrated circuit design are increasing exponentially. Completing the functional correctness verification of logic design in the pre-silicon stage of chip design has become a core and critical link to ensure chip product quality, operational reliability and tape-out success rate.

[0003] In the current field of pre-silicon functional verification for digital integrated circuits, the mainstream technical solutions mainly fall into two categories: simulation-based verification methods and formal verification methods. Simulation-based verification methods apply input stimuli to the design under test (DUT) by constructing a test platform and observe the functional behavior of the circuit to determine whether it meets design expectations. This approach offers advantages such as low deployment cost, intuitive process, and ease of engineering implementation. However, simulation verification typically relies on a limited number of test vectors. For boundary scenarios involving complex control logic, large state spaces, or specific timing conditions, traditional simulation methods struggle to effectively cover them, leading to the omission of logic defects. Formal verification technology, on the other hand, has been introduced into the chip verification process to compensate for the insufficient coverage of simulation verification. This method uses mathematical proofs to exhaustively analyze the design behavior, providing a full-coverage functional correctness guarantee for the design under given assumptions.

[0004] However, formal verification techniques require writing precise assertions and environmental constraints, resulting in complex modeling processes and high engineering application costs. Furthermore, as design scale increases, they face bottlenecks in large-scale applications, such as state space explosion, low solution efficiency, and high convergence difficulty. Existing mainstream circuit verification schemes cannot simultaneously meet the dual requirements of verification efficiency and full-space coverage in the verification process of large-scale, highly complex integrated circuits. Summary of the Invention

[0005] This invention provides a symbolic simulation verification method, apparatus, device, and medium for digital circuits, which solves the technical problem that existing mainstream circuit verification schemes cannot simultaneously meet the dual requirements of verification efficiency and full spatial coverage in the verification process of large-scale, highly complex integrated circuits.

[0006] The first aspect of this invention provides a symbolic simulation verification method for digital circuits, applied to a symbolic simulator, the method comprising:

[0007] Obtain the circuit description file and symbolic simulation script corresponding to the circuit to be verified;

[0008] Parse the circuit description file and construct a symbolic state transition model;

[0009] Initialize the symbolic state corresponding to the circuit to be verified according to the symbolic state transition model;

[0010] Based on the symbolic simulation process script and the symbolic state transition model, the symbolic state is driven to be updated in simulation cycle by cycle until the cycle termination condition is met.

[0011] Assertional verification is performed on all symbol states at the current moment to generate simulation verification results for the circuit to be verified.

[0012] Optionally, the step of parsing the circuit description file and constructing a symbolic state transition model includes:

[0013] The circuit description file is converted into a system text format to obtain the file to be parsed;

[0014] The preset parser is invoked to parse the file to be parsed, extract the set of state variables, the set of input variables, the initial state conditions and the state transition relationships, and construct a symbolic state transition model.

[0015] Optionally, it also includes:

[0016] When state space constraints are extracted from the file to be parsed, the state space constraints are merged into the symbolic state transition model.

[0017] Optionally, the step of initializing the symbolic state corresponding to the circuit to be verified according to the symbolic state transition model includes:

[0018] Iterate through the set of state variables; the set of state variables includes multiple state variables;

[0019] Based on the initial state conditions, construct the state variable mapping for each of the state variables one by one;

[0020] Initialize the path constraints associated with each of the state variables according to the initial state conditions;

[0021] The symbolic state corresponding to the circuit to be verified is generated by using the state variable mapping and the path constraint.

[0022] Optionally, the step of constructing the state variable mapping for each of the state variables one by one according to the initial state conditions includes:

[0023] If the initial state condition is an open initial condition, then all state variable mappings of the state variables are initialized to symbolic quantities;

[0024] If the initial state condition is a specified initial condition, then each of the state variables is initialized to the specified quantity corresponding to the specified initial condition; the specified quantity includes a symbolic quantity or a constant value.

[0025] Optionally, the step of driving the symbolic state to perform simulation updates cycle by cycle according to the symbolic simulation process script and the symbolic state transition model until the cycle termination condition is met includes:

[0026] The flow statements within the symbol simulation flow script are analyzed line by line.

[0027] When the process statement is an assignment statement, the input mapping corresponding to the input variable is created according to the assignment statement;

[0028] When the process statement is a conditional statement, at least one set of path branches is created according to the conditional statement;

[0029] When the process statement is an assertion statement, an assertion check is performed on the symbol states corresponding to all the path branches at the current time according to the assertion statement.

[0030] According to the state transition relationship, symbolic simulation calculations are performed using all symbolic states at the current moment and the input mapping to obtain new symbolic states;

[0031] Determine if the loop termination condition is met;

[0032] If the loop termination condition is not met, the process jumps to the step of parsing the flow statements in the symbol simulation flow script line by line until the loop termination condition is met.

[0033] Optionally, the step of creating the input mapping corresponding to the input variable according to the assignment statement when the process statement is an assignment statement includes:

[0034] When the process statement is an assignment statement, an input mapping for the input variables in the input variable set is created according to the assignment corresponding to the assignment statement;

[0035] If there are unassigned input variables in the set of input variables, a new symbolic variable is created and associated with the unassigned input variable to construct a new input mapping;

[0036] If there are multiple sets of the path branches, then different symbol values ​​are configured for the input mapping of each set of the path branches.

[0037] Optionally, the step of creating at least one set of path branches based on the conditional statement when the process statement is a conditional statement includes:

[0038] When the process statement is a conditional statement, extract the conditional expression within the conditional statement;

[0039] If the symbol state involved in the conditional expression has an undetermined symbol quantity, then determine whether the value of the undetermined symbol quantity satisfies all the undetermined conditions in the conditional expression.

[0040] If so, then copy the symbolic state involved in the conditional expression, and merge the undetermined conditions satisfied by each of the values ​​into the corresponding path constraints to obtain at least two sets of parallel path branches;

[0041] If not, the undetermined conditions satisfied by the value are merged into the path constraints to obtain a single set of path branches.

[0042] Optionally, it also includes:

[0043] Periodically check whether each path branch is a redundant path;

[0044] If so, the redundant path is merged into an existing path branch.

[0045] Optionally, the step of performing assertion checks on the symbol states corresponding to all path branches at the current time based on the assertion statement when the process statement is an assertion statement includes:

[0046] When the process statement is an assertion statement, extract the first assertion condition corresponding to the assertion statement;

[0047] Construct the first logical expression using the first assertion condition and the current symbol state;

[0048] Call the preset logic solver to solve the first logic expression and determine whether there is a violation symbol state that violates the first assertion condition;

[0049] If it exists, then generate counterexample information corresponding to the violation symbol state;

[0050] If it does not exist, then the step of performing symbolic simulation calculations according to the state transition relationship, using all symbolic states at the current moment and the input mapping, to obtain a new symbolic state is executed.

[0051] Optionally, the step of performing symbolic simulation calculations using all symbolic states at the current moment and the input mapping according to the state transition relationship to obtain new symbolic states includes:

[0052] The current state variable mapping and the input mapping are merged to construct a replacement environment;

[0053] When the symbolic state transition model does not have the state space constraints, the symbolic expressions corresponding to each of the state variables are matched from the state transition relations.

[0054] The symbolic expression is symbolically replaced according to the replacement environment to obtain the target symbolic expression as a state update mapping.

[0055] By associating the state update mapping with the existing path constraints, a new symbolic state is obtained.

[0056] Optionally, it also includes:

[0057] When the symbolic state transition model has state space constraints, extract the constraint variables within the state space constraints.

[0058] The replacement environment is updated using the constraint variables;

[0059] The constraint variables are merged into the existing path constraints, and the process jumps to the step of performing symbolic substitution on the symbolic expression according to the replacement environment to obtain the target symbolic expression as the state update mapping.

[0060] Optionally, after performing the step of performing symbolic substitution on the symbolic expression according to the substitution environment to obtain the target symbolic expression as a state update mapping, the method further includes:

[0061] If the target symbolic expression satisfies the preset simplification conditions, then the symbolic representation of the target symbolic expression is simplified to obtain a new state update variable;

[0062] Jump to the step of associating the state update variable with the existing path constraints to obtain the new symbol state.

[0063] Optionally, the step of asserting and verifying all symbol states at the current time to generate the simulation verification result corresponding to the circuit to be verified includes:

[0064] Using all symbol states at the current moment, construct the second logical expression respectively;

[0065] Call the preset expression solver to determine whether each of the second logical expressions satisfies the second assertion condition;

[0066] If all of the second logic expressions satisfy the second assertion condition, the assertion is deemed to pass, and the simulation verification result corresponding to the circuit to be verified is generated as a successful verification.

[0067] If any of the second logical expressions fails to satisfy the second assertion condition, the assertion is deemed unsuccessful, and the simulation verification result corresponding to the circuit to be verified is deemed a verification failure.

[0068] Optionally, it also includes:

[0069] When the assertion fails, locate the state of the symbol to be optimized associated with the second logical expression;

[0070] The solver generates counterexample information corresponding to the symbol state to be optimized.

[0071] Optionally, the method further includes:

[0072] The symbolic simulation process script is parsed to determine the simulation clock propagation mode; the simulation clock propagation mode includes active stepping mode and asynchronous mode.

[0073] If the simulation clock advance mode is an active stepping mode, then a stepping interface, a backtracking interface, and multiple first simulation interfaces corresponding to the active stepping mode are provided for the symbolic simulation process script to call.

[0074] If the simulation clock advance mode is asynchronous, then multiple second simulation interfaces corresponding to the asynchronous mode are provided for the symbolic simulation process script to call.

[0075] Optionally, the path constraints include at least one of implicit path constraints generated by path branching and constraints explicitly added by an external validation environment.

[0076] A second aspect of the present invention provides a symbolic simulation verification device for digital circuits, applied to a symbolic simulator, the device comprising:

[0077] The file acquisition module is used to acquire the circuit description file and symbol simulation process script corresponding to the circuit to be verified.

[0078] A state transition model construction module is used to parse the circuit description file and construct a symbolic state transition model.

[0079] The symbol state initialization module is used to initialize the symbol state corresponding to the circuit to be verified according to the symbolized state transition model.

[0080] The simulation update module is used to drive the symbolic state to perform simulation updates cycle by cycle according to the symbolic simulation process script and the symbolic state transition model until the cycle termination condition is met.

[0081] The assertion verification module is used to perform assertion verification on all symbol states at the current time and generate simulation verification results corresponding to the circuit to be verified.

[0082] A third aspect of the present invention provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor performs the steps of the symbolic simulation verification method for digital circuits as described in any one of the first aspects of the present invention.

[0083] A fourth aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed, implements a symbolic simulation verification method for digital circuits as described in any of the first aspects of the present invention.

[0084] As can be seen from the above technical solutions, the present invention has the following advantages:

[0085] This invention acquires the circuit description file and symbolic simulation flow script corresponding to the circuit to be verified; parses the circuit description file to construct a symbolic state transition model; initializes the symbolic states corresponding to the circuit to be verified according to the symbolic state transition model; drives the symbolic states to perform simulation updates cycle by cycle according to the symbolic simulation flow script and the symbolic state transition model until the cycle termination condition is met; and performs assertion verification on all symbolic states at the current moment to generate the simulation verification results corresponding to the circuit to be verified. Thus, by introducing symbolic quantities, path constraints, and path bifurcation mechanisms, it achieves a systematic exploration of the behavior space of digital circuits, effectively improving verification coverage and reducing the complexity of assertion construction and verification processes. Attached Figure Description

[0086] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0087] Figure 1 A flowchart illustrating the steps of a symbolic simulation verification method for digital circuits provided in an embodiment of the present invention;

[0088] Figure 2 This is a flowchart illustrating the symbol state initialization steps in an embodiment of the present invention.

[0089] Figure 3 Flowchart of the steps for simulating and updating the state of the driving symbol in an embodiment of the present invention;

[0090] Figure 4 An example diagram of a Verilog description file for a multiplication circuit to be verified, provided for an embodiment of the present invention;

[0091] Figure 5An example diagram of the symbolic simulation flow script for the multiplication circuit to be verified provided in an embodiment of the present invention;

[0092] Figure 6 A branch example diagram illustrating the periodic changes in the symbol state during the symbol simulation process for the multiplication circuit to be verified, provided for an embodiment of the present invention;

[0093] Figure 7 A structural block diagram of a symbolic simulation verification device for digital circuits provided in an embodiment of the present invention;

[0094] Figure 8 A schematic diagram of the structure of a computer device for performing a symbolic simulation verification method for digital circuits, as provided in an embodiment of the present invention. Detailed Implementation

[0095] This invention provides a symbolic simulation verification method, apparatus, device, and medium for digital circuits, which addresses the technical problem that existing mainstream circuit verification schemes cannot simultaneously meet the dual requirements of verification efficiency and full spatial coverage in the verification process of large-scale, highly complex integrated circuits.

[0096] To make the objectives, features, and advantages of this invention more apparent and understandable, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0097] Please see Figure 1 , Figure 1 A flowchart illustrating the steps of a symbolic simulation verification method for digital circuits provided in an embodiment of the present invention.

[0098] This invention provides a symbolic simulation verification method for digital circuits, applied to a symbolic simulator. The method includes:

[0099] Step 101: Obtain the circuit description file and symbolic simulation flow script corresponding to the circuit to be verified;

[0100] A symbolic simulator is a simulation tool that receives circuit description inputs, represents circuit node signals / parameters as symbolic variables rather than specific numerical values, and generates analytical expressions (such as transfer functions) through symbolic operations, thereby covering all combinations of input behaviors at once.

[0101] Circuits to be verified refer to digital integrated circuits that have completed register transfer level (RTL) design and are ready for pre-silicon functional verification, covering various digital logic designs such as processor arithmetic units, interface control circuits, and sequential logic circuits.

[0102] A circuit description file is a text file written in a hardware description language that fully represents the port definitions, timing relationships, register configurations, combinational logic and sequential logic rules of the circuit to be verified.

[0103] Symbolic simulation process scripts refer to executable scripts written based on procedural simulation semantics. They can be written in programming languages ​​such as Python, Ruby, Scala, and JavaScript. They are used to define the core behaviors of the entire verification process, such as input stimulus application, clock progression, condition waiting, and result checking, and are fully compatible with the operating habits and verification thinking of traditional simulation engineers.

[0104] In this embodiment, the symbolic simulator reads the hardware description language circuit description file corresponding to the circuit to be verified through a standardized file interface, and loads the symbolic simulation process script written by the user based on the procedural test platform structure to complete the preparation of the basic data source before simulation verification. This step is compatible with mainstream hardware description language design files and procedural scripts through a universal interface, without the need to modify the original circuit design, while retaining the traditional simulation process framework, reducing the adaptation cost for verification personnel and the threshold for engineering implementation.

[0105] Furthermore, the acquisition of symbolic simulation process scripts can be directly connected to traditional simulation testing platforms, automatically adapting existing targeted and random simulation test scripts to symbolic simulation process scripts without manual rewriting, further reducing migration costs. Additionally, during the loading phase of the symbolic simulation process script, static syntax validation and / or semantic compliance checks can be added to identify statements in the script that are incompatible with symbolic simulation semantics in advance and output correction prompts.

[0106] Step 102: Parse the circuit description file and construct a symbolic state transition model;

[0107] Symbolic state transition model refers to abstracting the circuit to be verified into a discrete-time state transition system that can perform symbolic operations. It is the core computational model of symbolic simulation. It includes at least the set of state variables, the set of input variables, the initial state conditions and the state transition relationship of the circuit. It may also include combinational logic operation relationships, sequential logic and state space constraints.

[0108] In this embodiment, the symbolic simulator performs a full-process parsing of the read circuit description file, such as the Verilog language description file of a digital circuit, converting it into a system text format such as BTOR2. Then, it further parses the file using a BTOR2 parser to completely map the circuit into a symbolic state transition model containing a set of state variables, a set of input variables, initial state conditions, and state transition relationships. This standardized abstract modeling of the circuit design provides a unified computational carrier for subsequent symbolic computation, state updates, and path exploration, ensuring that symbolic simulation fully reproduces the hardware timing semantics of the circuit and avoiding semantic deviations and inaccurate defect localization problems caused by software model conversion.

[0109] Furthermore, for the localized model extension of circuit design, a hierarchical symbolic state transition model can be constructed based on the hierarchical structure and functional boundaries of circuit modules. This model supports enabling or disabling symbolic operations at the module level, enabling refined symbolic analysis of key verification modules and rapid behavioral-level simulation of non-key modules, thus balancing verification accuracy and simulation efficiency.

[0110] In one example of this application, step 102 may include the following sub-steps:

[0111] Convert the circuit description file into system text format to obtain the file to be parsed;

[0112] The pre-defined parser is invoked to parse the file to be parsed, extract the set of state variables, the set of input variables, the initial state conditions and the state transition relationships, and construct a symbolic state transition model.

[0113] System text format refers to a standardized text format that adapts to the parsing rules of a preset parser and can structurally represent the logic characteristics and state transition information of digital circuits, such as the BTOR2 format description.

[0114] The file to be parsed refers to the file obtained after the original circuit description file has been converted into a format that conforms to the system text format specifications and can be directly read and analyzed by the preset parser.

[0115] A parser refers to a dedicated parsing module developed for a specific system text format, capable of targeted extraction of circuit information and model building. It can perform lexical and syntactic analysis of the file to be parsed, and achieve accurate extraction and symbolic modeling of the core information of the circuit, such as the BTOR2 parser.

[0116] In this embodiment, the symbolic simulator converts the circuit description file of the circuit to be verified into a preset system text format, generating a corresponding parsing file. It then calls a pre-developed preset parser to perform lexical and syntactic analysis on this parsing file, extracting the set of state variables, the set of input variables, the initial state conditions, and the state transition relationships that characterize the core features of the circuit. Based on these four types of extracted core information, a symbolic state transition model is constructed. Standardizing the system text format decouples the circuit description file from the parser, improving the parser's adaptability to different types of circuit description files. Simultaneously, the targeted information extraction by the dedicated parser eliminates redundant descriptive information in the original file, improving the efficiency of model construction and ensuring that the symbolic state transition model completely reproduces the state transition logic of the circuit to be verified.

[0117] Specifically, a BTOR2 format description of the state transition system can be generated by parsing the Verilog language description of the digital circuit, i.e., the file to be parsed. The BTOR2 parser then parses the state transition system description to establish a symbolic model of the state transition system. After reading the BTOR2 format description, the BTOR2 parser establishes the set of state variables, the set of input variables, the initial state conditions, and the state transition relationships according to the circuit description, while maintaining the correspondence between symbol names and internal identifiers.

[0118] The state transition relationship is established based on the logical relationship between the current state and the next state in the symbolic state transition model. The update expression for the next moment is recorded for each state variable to form a state update mapping, which is used to generate the next cycle state during subsequent symbolic simulation.

[0119] Furthermore, step 102 may also include the following sub-steps:

[0120] When state-space constraints are extracted from the file to be parsed, they are merged into the symbolic state transition model.

[0121] In this embodiment, during the process of extracting core information from the file to be parsed, the parser simultaneously detects whether the file contains state space constraints. If such constraints are detected, the state space constraints are embedded into the corresponding links in the model related to the determination of state variable values ​​and the verification of state transition relationships, according to the structured constraint fusion rules of the symbolic state transition model. This completes the merging of the constraints with the symbolic state transition model, enabling the model to define the effective state space of the circuit based on the constraints. This avoids the exploration of illegal states and invalid transition paths in the subsequent symbolic simulation process, reducing meaningless symbolic operations and path bifurcations from the source and reducing the resource overhead of the simulation.

[0122] Specifically, the BTOR2 description can additionally provide state-space constraints and a set of attributes. If multiple attributes exist, they can be merged during the construction of the symbolic state transition model for unified checking.

[0123] Step 103: Initialize the symbolic state corresponding to the circuit to be verified according to the symbolic state transition model;

[0124] Symbolic states refer to the set that fully describes the operating state of a circuit at a certain simulation moment. The core consists of two parts: a mapping of state variables described by symbolic expressions and a set of path constraints. The symbolic expressions can be implemented in computable forms such as abstract syntax trees and conjunction normal forms.

[0125] In this embodiment, after constructing the symbolic state transition model, the symbolic simulator sets initial values ​​for the sequential logic state variables of the circuit based on the initial state conditions. State variables and input variables without fixed initial value constraints are automatically initialized as symbolic quantities, thereby constructing an initial state variable mapping. Simultaneously, an empty set of path constraints is constructed according to these initial state conditions, completing the initialization of the symbolic states corresponding to the circuit to be verified. Thus, through the automatic symbolization of variables without fixed constraints, the simulation initial state achieves full coverage of all legal initial scenarios, avoiding the blind spots in initial state coverage caused by fixed initial values ​​in traditional simulations. Furthermore, the standardized management of initial path constraints lays the foundation for subsequent multi-path exploration and satisfiability determination.

[0126] In addition, the granularity of symbol activation can be set according to port, signal bit width, and module level. Fixed initial values ​​can be set for non-interested ports, and symbolization can be enabled only for core verification ports, flexibly controlling the initial solution space size and avoiding unnecessary symbol computation overhead.

[0127] Please see Figure 2 In one example of this application, step 103 may include the following sub-steps S11-S14:

[0128] S11. Traverse the set of state variables; the set of state variables includes multiple state variables;

[0129] In this embodiment, the symbolic simulator retrieves the set of state variables in the symbolic state transition model, and sequentially accesses and uniquely identifies each state variable in the set according to the preset element access rules, thus completing a full-domain scan of the set of state variables.

[0130] S12. Construct state variable mappings for each state variable based on the initial state conditions;

[0131] Furthermore, S12 may include the following sub-steps:

[0132] If the initial state condition is an open initial condition, then all state variable mappings are initialized to symbolic quantities.

[0133] If the initial state condition is a specified initial condition, then each state variable will be initialized to the specified quantity corresponding to the specified initial condition; the specified quantity includes symbolic quantity or constant value.

[0134] Initialization conditions refer to the initialization rules that do not impose fixed values ​​on the initial values ​​of state variables. They are undifferentiated initialization conditions that cover all possible initial operating states of the circuit.

[0135] Specifying initial conditions refers to the initialization conditions that pre-define specific initial value rules for state variables. Initial value requirements for constant values ​​or symbolic quantities can be set for one or more state variables respectively.

[0136] A specified quantity refers to the initial value form preset for a state variable under specified initial conditions. It includes two categories: symbolic quantities that can represent all possible values ​​and fixed constant values.

[0137] In this embodiment, the symbolic simulator performs a mapping construction operation for each state variable identified in S11, based on the initial state conditions in the symbolic state transition model. Specifically, if the initial state condition is an open initial condition, the state variable mappings of all state variables are uniformly initialized as symbolic quantities to construct completely arbitrary initial states, thus covering all possible initial situations. If the initial state condition is a specified initial condition, the specified quantity is matched to each state variable according to the condition, and the mapping initialization is completed. For state variables with explicitly set initial values ​​in the state transition model, corresponding constant values ​​or symbolic quantities are assigned according to the initial state conditions. For state variables without explicitly set initial values, new symbolic quantities can be introduced for representation. Alternatively, a separate set of symbolic quantities can be established to record all introduced symbolic quantities.

[0138] In this process, by constructing mappings based on the differences in initial state conditions, we ensure that the initial value rules of state variables match the verification requirements. The variable-by-variable construction method ensures the accuracy of the mapping relationship and provides a correct initial logical association basis for the state update of subsequent symbolic simulation.

[0139] S13. Initialize the path constraints associated with each state variable according to the initial state conditions;

[0140] Path constraints refer to logical constraints that match the rules for initializing a single state variable and are used to limit the legality of the initial value of that state variable. They are the basic building blocks of a path constraint set.

[0141] In this embodiment, the symbolic simulator, based on the initial state conditions in the symbolic state transition model, configures an initial path constraint that matches the initial value (symbolic quantity / constant value) of each state variable that has been mapped and constructed in S12. This completes the global initialization of the path constraints associated with all state variables, so that the initial value of each state variable is limited by the corresponding path constraint, eliminating illegal initial values ​​from the source, and providing a compliant initial constraint basis for the accumulation of path constraints and satisfaction determination in the subsequent simulation process.

[0142] Optionally, path constraints include at least one of implicit path constraints generated by path branching and constraints explicitly added by an external validation environment.

[0143] Implicit path constraints refer to path constraints that are automatically generated by the branch selection behavior of statements such as condition judgment and loop control during the path branching process of symbolic simulation, without the need for manual intervention. They accumulate automatically as the simulation execution path extends and are a fundamental component of path constraints.

[0144] Explicitly added constraints refer to path constraints that are manually set by the external verification environment according to specific verification needs and actively imported into the symbolic simulation process. They can specifically limit the input values, state variable ranges, or state transition paths of the circuit, and are a customized supplement to implicit path constraints.

[0145] An external verification environment refers to a supporting verification system that is independent of the symbolic simulator, operated by verification personnel, and capable of editing, importing, and modifying constraints.

[0146] S14. Using state variable mapping and path constraints, generate the symbolic state corresponding to the circuit to be verified.

[0147] In this embodiment, after the initialization of the path constraints of the state variable mapping is completed, the state variable mapping that has been fully constructed in S12 and the state variable associated path constraints that have been fully initialized in S13 can be retrieved. The two types of data are structured and integrated according to the preset storage structure of the symbol state. After the data is standardized and encapsulated, the complete symbol state corresponding to the start time of the simulation of the circuit to be verified is generated. The unified management of the initial state variable mapping and path constraints is realized through structured integration.

[0148] Step 104: Based on the symbolic simulation process script and the symbolic state transition model, drive the symbolic state to perform simulation updates cycle by cycle until the cycle termination condition is met.

[0149] Cycle-by-cycle refers to the simulation cycle, which corresponds to one clock cycle of a digital circuit. It is the smallest time advance unit of symbolic simulation. Each simulation cycle completes the entire process of applying input stimulus, performing combinational logic symbolic operations, and updating the state of sequential logic.

[0150] The loop termination condition refers to the judgment condition predefined by the symbolic simulation process script to stop the simulation clock from advancing. It includes types such as reaching a preset number of simulation cycles, triggering a specified simulation event, and all execution paths completing the simulation.

[0151] In this embodiment, the symbolic simulator advances the simulation process in clock cycles according to the execution logic defined in the symbolic simulation flow script. Within each simulation cycle, based on the symbolic simulation flow script, symbolic quantities are automatically introduced as stimuli for input ports that are not explicitly assigned values. Additionally, combined with a symbolic state transition model, combinational logic operations and sequential logic state transition calculations are completed through symbolic state or symbolic expression substitution, synchronously updating the state variable mapping and path constraint set. Specifically, the flow statements within the symbolic simulation flow script are parsed line by line. When a conditional judgment statement containing symbolic quantities is encountered, the SAT (Boolean Satisfiability Problem) / SMT (Satisfiability Modulo Theories) solver is invoked to complete the satisfiability determination. Path bifurcation and constraint accumulation are executed as needed, and the above-mentioned cycle advancement process is repeated until the loop termination condition defined in the script is triggered. By using symbolic input stimuli and symbolic computation, single-cycle simulation achieves full coverage of all legal input values. At the same time, the path bifurcation mechanism enables parallel exploration of multiple execution paths, which significantly improves the state space coverage efficiency compared to traditional simulation. Furthermore, the cycle-by-cycle state update is fully compatible with the timing semantics of the hardware circuit, avoiding semantic deviations.

[0152] In addition, after a preset number of simulation cycles, the symbolic expressions of the state variables of all time-series components are automatically simplified. Redundant historical symbolic variables are eliminated through constant propagation, irrelevant variable elimination, and equivalent subexpression replacement, thereby reducing the complexity of symbolic expressions and subsequent computational overhead.

[0153] Please see Figure 3 In one example of this application, step 104 may include the following sub-steps S21-S27:

[0154] S21. Analyze the flow statements in the symbol simulation flow script line by line;

[0155] Flow statements refer to the basic execution units that constitute symbolic simulation flow scripts. They are statement forms that represent specific operation instructions in symbolic simulation and include different functional types such as assignment, condition, and assertion.

[0156] In this embodiment, the symbolic simulator performs syntax recognition and semantic parsing on each process statement in the script according to the preset statement execution order of the symbolic simulation process script. It clarifies the functional type of each statement and the corresponding execution parameters and requirements. Through orderly sentence-by-sentence parsing, it achieves full-domain and accurate identification of the script execution logic, providing a clear basis for subsequent typed execution of statement instructions, and ensuring that the symbolic simulation process strictly follows the script definition and proceeds in an orderly manner.

[0157] S22. When the flow statement is an assignment statement, create the input mapping corresponding to the input variable according to the assignment statement;

[0158] Furthermore, S22 may include the following sub-steps:

[0159] When the process statement is an assignment statement, the input mapping of the input variables in the input variable set is created according to the assignment value corresponding to the assignment statement;

[0160] If there are unassigned input variables in the input variable set, a new symbolic variable is created and associated with the unassigned input variable, thus constructing a new input mapping;

[0161] If there are multiple sets of path branches, then different symbol values ​​are configured for the input mapping of each set of path branches.

[0162] Unassigned input variables refer to input variables in the input variable set that have not been assigned any value by the assignment statements in the symbolic simulation flow script. They are the type of variables that need to be automatically supplemented with symbolic stimuli in symbolic simulation.

[0163] In this embodiment, when the symbolic simulator parses the process statement line by line, if it identifies the process statement as an assignment statement, it constructs a corresponding input mapping for the assigned input variables in the input variable set according to the assignment rules of the assignment statement. For the unassigned input variables in the set, the simulator automatically creates new symbolic quantities and binds them to the variables to construct new input mappings. The assignment statement accurately applies the stimulus to the assigned input variables, and the automatic generation of symbolic quantities completes the full coverage of the stimulus for the unassigned input variables, avoiding the blind spot of input stimulus exploration.

[0164] Meanwhile, if there are multiple path branches in the current simulation, different symbol quantities are assigned to the input mapping of each path branch to ensure that the symbol quantities of each branch are independent of each other. The independent symbol quantity configuration of multiple branches eliminates the logical interference between symbol quantities between branches, ensuring the independence and accuracy of the simulation exploration of each path branch.

[0165] In addition, you can add an input variable-specific identifier and a path branch identifier to the automatically created new symbolic quantity to form a two-layer unique identifier, which makes it easier to trace the source of the symbolic quantity and the branch to which it belongs during subsequent simulation.

[0166] S23. When the flow statement is a conditional statement, create at least one set of path branches based on the conditional statement;

[0167] Furthermore, S23 may include the following sub-steps:

[0168] When the flow statement is a conditional statement, extract the conditional expression within the conditional statement;

[0169] If the symbol states involved in the conditional expression contain undetermined symbol quantities, then determine whether the values ​​of the undetermined symbol quantities satisfy all the undetermined conditions in the conditional expression.

[0170] If so, then copy the symbolic state involved in the conditional expression, and merge the undetermined conditions satisfied by each value into the corresponding path constraints to obtain at least two sets of parallel path branches;

[0171] If not, the undetermined conditions that the values ​​satisfy will be merged into the path constraints to obtain a single set of path branches.

[0172] A conditional expression is a logical decision embedded in a conditional statement, used to determine the execution path of the simulation.

[0173] Undetermined symbolic variables refer to symbolic variables in the symbolic state associated with a conditional expression that are not uniquely locked by existing path constraints and can have multiple legal values.

[0174] Undetermined conditions refer to logical sub-conditions that are composed of undetermined symbol quantities and whose determination results are not unique under the current constraints.

[0175] Parallel path branches refer to multiple independent execution paths derived from the same symbol state, carrying independent path constraints, and capable of synchronous symbol simulation.

[0176] In this embodiment, after recognizing a conditional statement, the symbolic simulator extracts its internal conditional expression and determines whether the symbolic state associated with the expression contains undetermined symbol quantities. If it does, it verifies whether the value of the undetermined symbol quantity can satisfy all the undetermined conditions in the expression. If it does, it copies the corresponding symbolic state and merges each valid undetermined condition into the corresponding path constraint to form at least two sets of parallel path branches. If it does not satisfy, it only merges the valid undetermined conditions into the path constraint to form a single set of path branches. This allows for precise control of the number of path branches based on the satisfiability of the conditions, which both exhaustively covers all legal branch scenarios to improve verification coverage and avoids redundant calculations caused by invalid branches. At the same time, the directional merging constraint ensures that the logic of each branch is legal and independent.

[0177] For example, by regularizing the conditional judgments of hardware circuits into scripts, for conditional judgments and loop statements such as if / while / for / wait_cond in the symbolic simulation flow script, if there are undetermined symbolic quantities in their conditional expressions, it is necessary to determine whether both true and false conditions can be satisfied. If only one condition can be satisfied, execution continues along that path, and the corresponding constraint (i.e., the condition is "true" or "false") is added to that branch. If both conditions can be satisfied, the branch state is cloned. The original branch and the new branch are respectively given mutually negating conditional assumptions, realizing the branching and accumulation of path constraints, which are then retained in subsequent simulation cycles.

[0178] In addition, for the portion of the execution stack containing Python coroutines, the symbolic simulator also needs to copy the execution stack of the Python coroutines.

[0179] When the simulation process script calls the simulator's wait condition function, the same satisfiability check is performed on the condition within the function. A similar approach using conditional checks and loop statements is employed.

[0180] Furthermore, S23 may also include the following sub-steps:

[0181] Periodically check whether each path branch is a redundant path;

[0182] If so, merge the redundant path into the existing path branch.

[0183] Redundant paths refer to invalid path branches whose symbol states, path constraints, and existing path branches are logically equivalent, and whose subsequent simulation results are identical and do not add new verification coverage.

[0184] In this embodiment, the symbolic simulator performs redundancy checks on all path branches according to the simulation cycle or other manually set cycles. After identifying redundant paths, it merges the symbolic state and path constraints of the path into logically equivalent existing path branches and cancels the redundant path. This method reduces invalid simulation operations by periodically cleaning up redundant paths, lowers the resource overhead of symbolic computation and path management, and does not lose verification coverage, thus balancing verification efficiency and completeness.

[0185] In addition, for path branches that are not part of redundant paths, the corresponding path constraints are accumulated to continue advancing the symbolic simulation process of the clock.

[0186] S24. When the flow statement is an assertion statement, perform assertion checks on the symbol states corresponding to all path branches at the current time according to the assertion statement;

[0187] Furthermore, S24 may include the following sub-steps:

[0188] When the flow statement is an assertion statement, extract the first assertion condition corresponding to the assertion statement;

[0189] Construct the first logical expression using the first assertion condition and the current symbol state;

[0190] Call the preset logic solver to solve the first logic expression and determine whether there is an exception symbol state that violates the first assertion condition;

[0191] If it exists, generate counterexample information corresponding to the violation symbol state;

[0192] If it does not exist, then perform symbolic simulation calculations according to the state transition relationship, using all symbolic states and input mappings at the current moment, to obtain new symbolic states.

[0193] The first logical expression refers to the logical formula that can be determined by the logic solver after fusing the first assertion condition with the path constraints and state variable mappings of the current symbolic state.

[0194] The logic solver includes pre-configured SAT / SMT solving tools to determine whether a logic expression has a satisfying solution and to identify violation states.

[0195] A violation symbol state refers to a symbol state that makes the first assertion condition false, indicating that a certain quantity has a defect in the circuit.

[0196] Counterexample information refers to a set of symbolic data used to reproduce violation scenarios and locate the triggering conditions of defects.

[0197] In this embodiment, after recognizing an assertion statement, the symbolic simulator extracts the first assertion condition. This condition is then combined with the current symbolic state to construct a first logical expression. A preset logic solver is invoked to solve the expression to determine if a violation symbolic state exists. If a violation exists, corresponding counterexample information is generated; otherwise, symbolic simulation calculations are performed based on state transition relationships, the current symbolic state, and the input mapping to obtain a new symbolic state. This logical solving achieves accurate verification of the assertion condition. In case of a violation, a counterexample is directly output for easy defect localization; otherwise, the simulation continues, balancing verification accuracy and process continuity.

[0198] It should be noted that the assertion verification process can be executed when any assertion statement is parsed, or it can be executed after the overall symbolic simulation process is completed. This embodiment does not limit the specific execution time.

[0199] Furthermore, if the preset logic solver times out, the expression is automatically split and simplified before being re-solved, preventing a single assertion from blocking the overall simulation process. When generating counterexample information, the corresponding path branch, simulation cycle, and symbol source are bound, facilitating rapid location of defect trigger points. Logical expressions constructed from multiple assertion statements can also be grouped and solved in parallel using multi-threading, improving assertion checking efficiency.

[0200] S25. According to the state transition relationship, use all symbol states and input mappings at the current moment to perform symbol simulation calculations to obtain new symbol states;

[0201] Furthermore, S25 may include the following sub-steps:

[0202] The replacement environment is constructed by merging the current state variable mapping and input mapping.

[0203] When the symbolic state transition model does not have state space constraints, the symbolic expressions corresponding to each state variable are matched from the state transition relation.

[0204] The symbolic expression is symbolically replaced according to the replacement environment to obtain the target symbolic expression as the state update mapping;

[0205] The associated state update mapping and existing path constraints are used to obtain a new symbolic state.

[0206] The substitution context refers to the symbolic substitution context formed by merging the current state variable mapping and input mapping, which provides a unified basis for variable substitution in symbolic expressions.

[0207] Symbolic expressions refer to symbolic logical expressions in state transition relations that describe the value of a state variable at the next moment.

[0208] State update mapping refers to the updated mapping relationship where the target symbolic expression is the content and each state variable corresponds to it.

[0209] In this embodiment, the symbolic simulator merges the current state variable mapping and input mapping to construct a replacement environment. When the symbolic state transition model has no state space constraints, it matches the symbolic expressions corresponding to each state variable from the state transition relationship, completes the symbol replacement according to the replacement environment to obtain the target symbolic expression, and forms the state update mapping corresponding to the next clock cycle. After associating this mapping with existing path constraints, a new symbolic state is generated. The consistency of symbol replacement is ensured by the standardized replacement environment. The state update is completed based on the inherent state transition relationship of the circuit, the hardware timing logic is reproduced, and the associated path constraints ensure that the new symbolic state is legal and compliant, thus achieving accurate timing update of the symbolic state.

[0210] It should be noted that when the symbol simulator needs to perform multi-cycle simulations, the above symbol state update process is repeated until the number of clock cycles required by the simulation flow script is reached. Furthermore, the symbol simulator can maintain a simulation trajectory record. When backtracking is needed, the simulation clock advance can be reversed based on the simulation trajectory record, thereby restoring the symbol state to the previous cycle.

[0211] Optionally, S25 may also include the following sub-steps:

[0212] When the symbolic state transition model has state space constraints, extract the constraint variables within the state space constraints.

[0213] The environment is updated and replaced using constraint variables;

[0214] The constraint variables are merged into the existing path constraints, and the process jumps to execute the step of symbolic substitution of the symbolic expression according to the substitution environment to obtain the target symbolic expression as the state update mapping.

[0215] In this embodiment, when the symbolic simulator detects state-space constraints in the symbolic state transition model, it extracts all constraint variables within those constraints, integrates the logical relationships of the constraint variables into the constructed replacement environment to complete the replacement environment update, and simultaneously merges the constraint logic corresponding to the constraint variables into the existing path constraints. After completing the constraint fusion, it jumps to execute the step of symbolically replacing the symbolic expression according to the replacement environment to obtain the target symbolic expression as the state update mapping. Through the dual update of the replacement environment and path constraints by constraint variables, the state-space constraints are completely embedded into the entire state update process of the symbolic simulation, eliminating symbolic operations and invalid path explorations in the illegal state space from the source, while ensuring that the state update process fully conforms to the inherent constraint boundaries of the circuit design, thereby improving the logical rigor and computational efficiency of the symbolic simulation.

[0216] Furthermore, when extracting constraint variables, only valid constraint variables that match existing mapping relationships in the current replacement environment are identified, and irrelevant invalid constraint variables are automatically eliminated. Only valid constraint variables are used to update the replacement environment, reducing redundant information in the replacement environment and improving the computational efficiency of subsequent symbol replacement. Before merging constraint variables into path constraints, a logical consistency check is performed between the constraint logic and existing path constraints. If a constraint conflict is detected, the conflict location and anomaly message are output immediately to prevent invalid constraints from entering the subsequent symbol replacement process and causing simulation results distortion.

[0217] After performing the step of symbolically substituting the symbolic expression according to the substitution environment to obtain the target symbolic expression as the state update mapping, S25 may further include the following sub-steps:

[0218] If the target symbolic expression satisfies the preset simplification conditions, then the symbolic representation of the target symbolic expression is simplified to obtain a new state update variable;

[0219] Jump to execute the steps of updating the associated state variables and existing path constraints to obtain the new symbol state.

[0220] The simplification condition refers to the judgment rule used to trigger the simplification operation of the target symbolic expression, which can be set based on dimensions such as expression complexity, operation node size, and simulation cycle nodes.

[0221] The state update variable refers to the simplest symbolic expression that represents the value of the circuit state variable at the next moment, obtained after symbolic simplification.

[0222] In this embodiment, after the symbolic simulator completes the symbol replacement to obtain the target symbolic expression, it first verifies whether the expression meets the preset simplification conditions. If it does, it performs equivalent simplification processing on the symbolic representation of the target symbolic expression, removes redundant logic terms and invalid operation nodes to obtain the simplest state update variable, and after simplification, it jumps to the step of associating the state update variable with the existing path constraints to generate a new symbolic state. Thus, through the equivalent simplification triggered by preset conditions, the complexity of the state update expression is effectively reduced, and the resource overhead of subsequent symbolic simulation calculation and path constraint solving is reduced.

[0223] The process of symbol simplification includes, but is not limited to, constant propagation, elimination of irrelevant variables, elimination of unreachable branches, substitution of equivalent subexpressions, and expression rewriting.

[0224] S26. Determine whether the loop termination condition is met;

[0225] In this embodiment, the symbolic simulator extracts the preset loop termination condition from the symbolic simulation process script, matches the current actual execution state of the symbolic simulation with the condition, and determines whether the current simulation has met the requirement to stop progressing.

[0226] S27. If the loop termination condition is not met, then jump to execute the steps of the flow statements in the line-by-line parsing symbol simulation flow script until the loop termination condition is met.

[0227] In this embodiment, after determining that the loop termination condition is not currently met, the symbolic simulator triggers a flow jump instruction and executes steps S21-S26 again, continuing to advance the symbolic simulation to the next cycle according to the script definition until the simulation execution state matches the loop termination condition. This jump execution enables multi-cycle cyclic advancement of the symbolic simulation, completing a continuous and systematic exploration of the circuit's multi-clock-cycle operating state, and ensuring complete verification of the circuit's timing behavior and complex state transition processes.

[0228] Step 105: Perform assertion verification on all symbol states at the current moment to generate simulation verification results for the circuit to be verified.

[0229] Assertion verification refers to the process of constructing a decisionable logical expression based on the assertion check conditions defined in the symbolic simulation flow script, combined with the state variable mapping and path constraint set of the current symbolic state, and calling the satisfiability solver to verify whether there is a circuit state that can trigger an assertion violation.

[0230] Simulation verification results refer to the dataset that characterizes the verification conclusions of the entire symbolic simulation process, including but not limited to global conclusions of verification success / failure, path information of assertion violations, set of counterexample inputs that trigger defects, path coverage statistics, etc.

[0231] In this embodiment, when the simulation progresses to the loop termination condition or resolves to the line containing the assertion statement, the symbolic simulator traverses the symbolic states corresponding to all surviving execution paths at the current moment. It constructs a decidable logical expression by combining the path constraint set, state variable mapping, and assertion conditions defined in the script for each path. The SAT / SMT solver is then called to perform a satisfiability check on the logical expression, verifying the existence of symbolic variable values ​​that would invalidate the assertion conditions. If a symbolic state violating an assertion is detected, a verification failure result is output, and corresponding counterexample information is generated simultaneously. If no assertion violation is detected across the entire path, a verification pass result is output. Thus, through assertion verification based on symbolic states, an exhaustive property check of all reachable circuit states is achieved. Compared to traditional simulations that can only check a limited number of input trajectories, this effectively discovers hidden defects in boundary scenarios. Furthermore, the path constraint-based solution can directly generate counterexamples that trigger defects, facilitating rapid problem location and repair by verification personnel.

[0232] In addition, multiple solver adaptation interfaces can be added to support automatic matching of the optimal solver for different types of logical expressions, or to call multiple solvers in parallel for the same set of constraints, thereby improving the success rate and efficiency of the solution.

[0233] In one example of this application, step 105 may include the following sub-steps:

[0234] Using all symbol states at the current moment, construct the second logical expression respectively;

[0235] Call the preset expression solver to determine whether each second logical expression satisfies the second assertion condition;

[0236] If all second logic expressions satisfy the second assertion condition, the assertion is deemed successful, and the simulation verification result corresponding to the circuit to be verified is generated as successful verification.

[0237] If any second logic expression fails to meet the second assertion condition, the assertion is deemed unsuccessful, and the simulation verification result corresponding to the circuit to be verified is deemed a verification failure.

[0238] The second logical expression refers to the solvable logical formula used for the final determination of the global functional correctness of the circuit, which is constructed by combining the final symbolic state of a single path branch (including the path constraints and final state variable mapping accumulated throughout the cycle) with the second assertion condition after the simulation loop meets the termination condition.

[0239] The second assertion condition refers to the global judgment rule set for the final functional compliance of the circuit to be verified after the full simulation cycle. It is different from the single-step temporary assertion in the simulation process and is the final acceptance standard for this symbolic simulation verification.

[0240] An expression solver refers to a Boolean satisfiability (SAT) / satisfiability modular theory (SMT) solver that supports batch processing of multiple logic formulas.

[0241] After the symbolic simulator meets the termination condition in the simulation loop, it retrieves all symbolic states corresponding to all path branches at the current moment. Combining this with a preset second assertion condition, it constructs a corresponding second logical expression for each group of symbolic states. A preset expression solver is then called to perform satisfiability calculations on all second logical expressions, determining whether all second logical expressions satisfy the second assertion condition. If all second logical expressions satisfy the second assertion condition, the global assertion is considered successful, and the simulation verification result for the circuit to be verified is considered successful. If any second logical expression fails to satisfy the second assertion condition, the global assertion is considered unsuccessful, and the simulation verification result for the circuit to be verified is considered unsuccessful. This method performs exhaustive assertion verification on the final symbolic states of all path branches after simulation termination, fully covering all reachable operating scenarios of the circuit. This effectively compensates for the shortcomings of traditional simulation boundary scenario coverage. Simultaneously, the unified determination across all paths ensures the integrity and logical rigor of the verification results, providing a reliable basis for correctness judgment for pre-silicon verification of circuits.

[0242] In addition, if a single second logical expression times out, the expression will be automatically decomposed and its complexity reduced before being re-solved. If it still times out, the path will be marked as a path to be verified and a special prompt will be output to avoid blocking the output of the global verification results by solving a single path.

[0243] In another example of this application, step 105 may also include the following sub-steps:

[0244] When the assertion fails, locate the state of the symbol to be optimized associated with the second logical expression;

[0245] The solver generates counterexample information corresponding to the symbolic state to be optimized.

[0246] In this embodiment, after determining that the global assertion fails, the second logical expression that does not meet the second assertion condition is first matched and filtered out. The unique symbolic state to be optimized, which contains the full-cycle path constraint and state variable mapping, is accurately located. Then, a preset expression solver is called. Based on the contradiction relationship between the violation logic, path constraint and second assertion condition of the symbolic state to be optimized, the counterexample information of the defect scenario corresponding to the symbolic state to be optimized and can be stably reproduced is generated. The unbiased and accurate location of the violation scenario is achieved through the unique binding relationship between the second logical expression and the symbolic state, avoiding the invalid investigation of the entire path and greatly improving the efficiency of defect location.

[0247] In another example of this application, to adapt to the use of different circuit simulation clocks, the method further includes the following steps:

[0248] Analyze the symbolic simulation process script to determine the simulation clock propagation mode; the simulation clock propagation modes include active stepping mode and asynchronous mode.

[0249] If the simulation clock advance mode is active stepping mode, then the stepping interface, backtracking interface and multiple first simulation interfaces corresponding to the active stepping mode are provided for the symbolic simulation process script to call.

[0250] If the simulation clock advance mode is asynchronous, multiple second simulation interfaces corresponding to the asynchronous mode are provided for the symbolic simulation process script to call.

[0251] The simulation clock advance mode refers to the core operating mode in the symbol simulation process that controls the timing, triggering rules, and timing control logic of the simulation clock. It is a clock control mechanism that adapts to the timing characteristics of different circuit designs and the needs of verification scenarios. It is divided into two categories: active stepping mode and asynchronous mode.

[0252] Active stepping mode refers to a synchronous clock control mode in which the clock advance step size and timing are actively controlled by the symbolic simulation process script. The clock's stepping, pausing, and backtracking are entirely driven by the script execution instructions.

[0253] Asynchronous mode refers to an asynchronous clock control mode in which clock advance and simulation execution are driven by circuit signal events and preset trigger conditions. Clock advance does not depend on a fixed step size and is triggered by asynchronous events and signal changes defined by the script. It is suitable for asynchronous sequential circuits and event-driven verification scenarios.

[0254] The stepping interface refers to the standardized calling interface that is open to scripts in active stepping mode, used to actively control the simulation clock to advance forward according to a preset step size.

[0255] The backtracking interface refers to a standardized calling interface that is open to scripts in active stepping mode, used to roll back the simulation clock to a specified historical period and restore the state of the corresponding historical symbol.

[0256] In this embodiment, the symbolic simulator performs a full parsing of the symbolic simulation process script, identifies the timing control logic, clock triggering rules, and circuit timing characteristics within the script, and determines whether the corresponding simulation clock advancement mode is active stepping mode or asynchronous mode. If it is determined to be active stepping mode, the corresponding stepping interface, backtracking interface, and multiple first simulation interfaces are exposed and mounted to the script for the script to call to achieve active clock control, state backtracking, and related simulation operations. Among them, the first simulation interfaces may include, but are not limited to, functional interfaces adapted to active stepping timing logic, such as symbol state reading and writing, input stimulus configuration, path constraint addition, and single-step assertion checking.

[0257] If the mode is determined to be asynchronous, the symbolic simulator does not provide a stepping or backtracking interface. The script utilizes Python coroutines to implement concurrent execution of multiple execution flows. When one execution flow enters a waiting state, the symbolic simulator switches to another execution flow that can continue. When all execution flows enter a waiting state, the simulator automatically advances the simulation clock, so there is no need to explicitly call the stepping interface in the simulation flow script. Simultaneously, multiple corresponding second simulation interfaces are exposed and mounted to the script for the script to call to implement event-driven asynchronous clock advancement and simulation execution. These second simulation interfaces can include, but are not limited to, functional interfaces adapted to asynchronous event-driven logic, such as event listening, conditional trigger callbacks, asynchronous signal capture, and event-triggered assertion checks.

[0258] The following example uses the symbolic simulation process of a multi-cycle multiplier circuit in asynchronous mode.

[0259] This multiplier circuit takes a multiplicand *a*, a multiplier *b*, and a start signal as inputs, and outputs a result (*result*) and a completion indicator (*valid*). The circuit latches the input multiplicand and multiplier when the start signal is true, then calculates the product of *a* and *b* through cyclic accumulation over multiple clock cycles. After the calculation is complete, the valid signal is set to true, and the result is output through the result signal. Its Verilog description is as follows: Figure 4As shown, the corresponding multiplier module is named multiplier. It includes a clock clk, a 1-bit start signal, an 8-bit multiplier a, a 3-bit multiplicand b, a 1-bit valid output signal, and an 11-bit output signal result. The module defines two 7-bit registers rega and regb to store the multiplier a and multiplicand b respectively. The result register result is initialized to 0, and the valid signal is also initialized to 0. The initialization block first clears all registers. The combinational logic assign valid=(regb==0) indicates that the multiplication is completed when regb is 0. The sequential logic is triggered on the rising edge of the clock. If start is 1 and valid is 0, a shift-add operation is performed: rega is added to result and result is updated, while regb is decremented by 1. If valid is 1, result remains unchanged. Finally, the multiplication of a and b is achieved through loop accumulation and the result is output.

[0260] Specifically, the verification process for this multiplier is as follows:

[0261] 1. Prepare the circuit model to be verified. Convert the Verilog description of the multiplier circuit to BTOR2 format, and establish a symbolic model of the state transition system. The input variable set includes the a, b, and start signals, and the state variable set includes the internal register variables of the multiplier. The initial state conditions and state transition relationships are consistent with the Verilog description.

[0262] 2. Construct an asynchronous symbolic simulation flow script. Based on the Python interface of the symbolic simulator, create an instance of the design under test and write the simulation flow: In one implementation, the test flow is encapsulated as a registered coroutine task `run1`, which assigns symbolic values ​​("x" and "y") to input ports a and b respectively and sets the input `start` to "true"; then it calls the conditional wait function of the symbolic simulator, waiting for `valid` to become "true" to indicate that the circuit has completed the calculation; when the condition is met, it checks the assertion: the product of x and y with equal bit widths should equal the symbolic value on the output port `result`, thus verifying that the result satisfies the multiplication relationship under symbolic input. This simulation flow script is as follows: Figure 5As shown, in this script, the verification task is registered with the @register_task decorator, the run1 function is defined as a coroutine task, and the symbolic simulator sim and the object under test dut are passed in; the script first assigns symbolic variables x and y to the input ports a and b of dut respectively, sets the start signal start to 1, then blocks and waits for the valid output signal of the multiplier to be 1 to ensure that the operation is completed, and finally calls sim.check_assertion to check the assertion and verify that the output value of result is always equal to the product of symbolic variables x and y. The symbolic operation achieves the effect of traversing all input scenarios and completes the full path verification of the multiplier function.

[0263] 3. Start the symbolic simulator and execute the symbolic simulation according to the steps in the simulation flow script. The symbolic simulator first initializes the symbolic state, applies symbolic input stimuli, and performs symbolic simulation calculations cycle by cycle to obtain new symbolic states. During execution, the conditional wait function will branch when waiting for valid to be "true". The symbolic simulator will determine the satisfiability and maintain path constraints at the waiting condition and assertion check points, and perform path branching when necessary; when all branches satisfy the assertions in the script, the simulator determines that the multiplier circuit has passed the verification. Figure 6 The diagram illustrates the symbol states obtained by performing a three-cycle symbol simulation on one of the branches. Figure 6 (a) shows the branching situation when the third cycle is reached after two condition checks. At the end of cycle 1, a "valid condition" check node is set. The branching condition here corresponds to the aforementioned... Figure 5 In the simulation process script, the condition specified by the conditional statement sim.wait_cond is divided into two branches: true and false. Period 2 is the next level judgment node extended from the false branch of Period 1, which is also divided into true and false branches. Period 3 is the end node corresponding to the false branch of Period 2. Figure 6 (b) shows the symbol state table for three simulation cycles along the path of the two consecutive false branches. The table records the symbol values ​​of registers rega and regb, the symbol value of result, and the corresponding path constraints for cycles 1, 2, and 3, respectively. In cycle 1, rega is x, regb is y, result is 0, and there are no constraints. In cycle 2, rega is x, regb is y-1, result is x, and the constraint condition is y≠0. In cycle 3, rega is x, regb is y-2, result is 2*x, and the constraints condition is y≠0 and y-1≠0. This completely corresponds to the symbol state and constraint logic of each cycle under this branch path.

[0264] In this embodiment of the invention, by executing steps 101-105, symbolic quantities, path constraints, and path bifurcation mechanisms can be introduced while maintaining the operational semantics, execution model, and engineering usage habits of traditional simulation. This enables a systematic exploration of the digital circuit behavior space, effectively improving verification coverage and reducing the complexity of assertion construction and verification processes. It allows verification personnel to introduce symbolic analysis capabilities without changing their existing verification mindset. Through the symbolic simulation interface, verification personnel can achieve semi-formal circuit design checks in verification with a low learning cost, realizing the integration of the advantages of simulation and formal methods. Taking the comparative experimental results in Table 1 as an example, the runtime of the formal method is used as a reference time:

[0265] Table 1

[0266]

[0267] Therefore, the symbolic simulation method proposed in this invention, while maintaining 100% branch coverage consistent with the formal method, significantly reduces the runtime when the number of circuit branches and Verilog lines exceeds a certain threshold. Compared with existing methods, this method avoids the dependence on enumeration of specific test vectors in simulation and circumvents the high complexity and high solution difficulty of formal verification modeling based entirely on axiomatic assertions, providing a new approach for digital chip verification.

[0268] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0269] The symbolic simulation verification device for digital circuits provided in the embodiments of this application will be described below. The symbolic simulation verification device for digital circuits described below can be referred to in correspondence with the symbolic simulation verification method for digital circuits described above.

[0270] Please see Figure 7 This invention provides a symbolic simulation verification device for digital circuits, applied to a symbolic simulator. The device includes:

[0271] The file acquisition module 701 is used to acquire the circuit description file and symbol simulation process script corresponding to the circuit to be verified.

[0272] The state transition model construction module 702 is used to parse the circuit description file and construct a symbolic state transition model.

[0273] Symbol state initialization module 703 is used to initialize the symbol state corresponding to the circuit to be verified according to the symbolized state transition model.

[0274] The simulation update module 704 is used to drive the symbolic state to perform simulation updates cycle by cycle according to the symbolic simulation process script and the symbolic state transition model until the cycle termination condition is met.

[0275] The assertion verification module 705 is used to perform assertion verification on all symbol states at the current time and generate simulation verification results for the circuit to be verified.

[0276] Optionally, the state transition model building module 702 is specifically used for:

[0277] Convert the circuit description file into system text format to obtain the file to be parsed;

[0278] The pre-defined parser is invoked to parse the file to be parsed, extract the set of state variables, the set of input variables, the initial state conditions and the state transition relationships, and construct a symbolic state transition model.

[0279] Optionally, the state transition model construction module 702 is also specifically used for:

[0280] When state-space constraints are extracted from the file to be parsed, they are merged into the symbolic state transition model.

[0281] Optionally, the symbol state initialization module 703 includes:

[0282] The state variable traversal submodule is used to traverse a set of state variables; the set of state variables includes multiple state variables.

[0283] The State Variable Mapping Construction Submodule is used to construct the state variable mapping for each state variable based on the initial state conditions.

[0284] The path constraint initialization submodule is used to initialize the path constraints associated with each state variable based on the initial state conditions.

[0285] The symbol state generation submodule is used to generate the symbol state corresponding to the circuit to be verified by using state variable mapping and path constraints.

[0286] Optionally, the state variable mapping construction submodule is specifically used for:

[0287] If the initial state condition is an open initial condition, then all state variable mappings are initialized to symbolic quantities.

[0288] If the initial state condition is a specified initial condition, then each state variable will be initialized to the specified quantity corresponding to the specified initial condition; the specified quantity includes symbolic quantity or constant value.

[0289] Optionally, the simulation update module 704 includes:

[0290] The statement parsing submodule is used to parse the flow statements in the symbol simulation flow script line by line.

[0291] The input mapping creation submodule is used to create input mappings corresponding to input variables according to assignment statements when the process statement is an assignment statement;

[0292] The path branch creation submodule is used to create at least one set of path branches based on the conditional statement when the flow statement is a conditional statement.

[0293] The assertion check submodule is used to perform assertion checks on the symbol status of all path branches at the current time when the flow statement is an assertion statement.

[0294] The symbol state update submodule is used to perform symbol simulation calculations based on the state transition relationship, using all symbol states and input mappings at the current moment, to obtain the new symbol state.

[0295] The loop termination judgment submodule is used to determine whether the loop termination condition is met.

[0296] The loop jump and termination submodule is used to jump to the execution of the steps of the flow statements in the symbolic simulation flow script if the loop termination condition is not met, until the loop termination condition is met.

[0297] Optionally, the input mapping creation submodule is specifically used for:

[0298] When the process statement is an assignment statement, the input mapping of the input variables in the input variable set is created according to the assignment value corresponding to the assignment statement;

[0299] If there are unassigned input variables in the input variable set, a new symbolic variable is created and associated with the unassigned input variable, thus constructing a new input mapping;

[0300] If there are multiple sets of path branches, then different symbol values ​​are configured for the input mapping of each set of path branches.

[0301] Optionally, path branches create submodules specifically for:

[0302] When the flow statement is a conditional statement, extract the conditional expression within the conditional statement;

[0303] If the symbol states involved in the conditional expression contain undetermined symbol quantities, then determine whether the values ​​of the undetermined symbol quantities satisfy all the undetermined conditions in the conditional expression.

[0304] If so, then copy the symbolic state involved in the conditional expression, and merge the undetermined conditions satisfied by each value into the corresponding path constraints to obtain at least two sets of parallel path branches;

[0305] If not, the undetermined conditions that the values ​​satisfy will be merged into the path constraints to obtain a single set of path branches.

[0306] Optionally, the creation of submodules through path branches is also specifically used for:

[0307] Periodically check whether each path branch is a redundant path;

[0308] If so, merge the redundant path into the existing path branch.

[0309] Optionally, the assertion checking submodule is specifically used for:

[0310] When the flow statement is an assertion statement, extract the first assertion condition corresponding to the assertion statement;

[0311] Construct the first logical expression using the first assertion condition and the current symbol state;

[0312] Call the preset logic solver to solve the first logic expression and determine whether there is an exception symbol state that violates the first assertion condition;

[0313] If it exists, generate counterexample information corresponding to the violation symbol state;

[0314] If it does not exist, then perform symbolic simulation calculations according to the state transition relationship, using all symbolic states and input mappings at the current moment, to obtain new symbolic states.

[0315] Optionally, the symbol state update submodule is specifically used for:

[0316] The replacement environment is constructed by merging the current state variable mapping and input mapping.

[0317] When the symbolic state transition model does not have state space constraints, the symbolic expressions corresponding to each state variable are matched from the state transition relation.

[0318] The symbolic expression is symbolically replaced according to the replacement environment to obtain the target symbolic expression as the state update mapping;

[0319] The associated state update mapping and existing path constraints are used to obtain a new symbolic state.

[0320] Optionally, the symbol state update submodule is also specifically used for:

[0321] When the symbolic state transition model has state space constraints, extract the constraint variables within the state space constraints.

[0322] The environment is updated and replaced using constraint variables;

[0323] The constraint variables are merged into the existing path constraints, and the process jumps to execute the step of symbolic substitution of the symbolic expression according to the substitution environment to obtain the target symbolic expression as the state update mapping.

[0324] Optionally, after performing the step of symbolic substitution of the symbolic expression according to the substitution environment to obtain the target symbolic expression as the state update mapping, the symbolic state update submodule is further used for:

[0325] If the target symbolic expression satisfies the preset simplification conditions, then the symbolic representation of the target symbolic expression is simplified to obtain a new state update variable;

[0326] Jump to execute the steps of updating the associated state variables and existing path constraints to obtain the new symbol state.

[0327] Optionally, the assertion verification module 705 is specifically used for:

[0328] Using all symbol states at the current moment, construct the second logical expression respectively;

[0329] Call the preset expression solver to determine whether each second logical expression satisfies the second assertion condition;

[0330] If all second logic expressions satisfy the second assertion condition, the assertion is deemed successful, and the simulation verification result corresponding to the circuit to be verified is generated as successful verification.

[0331] If any second logic expression fails to meet the second assertion condition, the assertion is deemed unsuccessful, and the simulation verification result corresponding to the circuit to be verified is deemed a verification failure.

[0332] Optionally, the assertion verification module 705 is also specifically used for:

[0333] When the assertion fails, locate the state of the symbol to be optimized associated with the second logical expression;

[0334] The solver generates counterexample information corresponding to the symbolic state to be optimized.

[0335] Optionally, the clock mode setting module is specifically used for:

[0336] Analyze the symbolic simulation process script to determine the simulation clock propagation mode; the simulation clock propagation modes include active stepping mode and asynchronous mode.

[0337] If the simulation clock advance mode is active stepping mode, then the stepping interface, backtracking interface and multiple first simulation interfaces corresponding to the active stepping mode are provided for the symbolic simulation process script to call.

[0338] If the simulation clock advance mode is asynchronous, multiple second simulation interfaces corresponding to the asynchronous mode are provided for the symbolic simulation process script to call.

[0339] Optionally, path constraints include at least one of implicit path constraints generated by path branching and constraints explicitly added by an external validation environment.

[0340] This invention provides a computer device, including a memory and a processor. The memory stores a computer program, and when the computer program is executed by the processor, the processor performs the steps of the symbolic simulation verification method for digital circuits as described in any embodiment of this invention.

[0341] This invention provides a computer-readable storage medium storing a computer program thereon, which, when executed, implements a symbolic simulation verification method for digital circuits as described in any embodiment of this invention.

[0342] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the above-described device and module can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0343] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or modules may be electrical, mechanical, or other forms.

[0344] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0345] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0346] If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause an electronic device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0347] Indicatively, such as Figure 8 As shown, Figure 8 This is a schematic diagram of the internal structure of a computer device 800 provided in an embodiment of this application. The computer device 800 can be provided as a server. (Refer to...) Figure 5 The computer device 800 includes a processing component 802, which further includes one or more processors, and memory resources represented by memory 801 for storing instructions, such as application programs, that can be executed by the processing component 802. The application programs stored in memory 801 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 802 is configured to execute instructions to perform the text recognition method of any of the above embodiments.

[0348] The computer device 800 may also include a power supply component 803 configured to perform power management of the computer device 800, a wired or wireless network interface 804 configured to connect the computer device 800 to a network, and an input / output interface 805. The computer device 800 may operate based on storage.

[0349] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A symbolic simulation verification method for digital circuits, characterized in that, Applied to a symbolic simulator, the method includes: Obtain the circuit description file and symbolic simulation script corresponding to the circuit to be verified; Parse the circuit description file and construct a symbolic state transition model; Initialize the symbolic state corresponding to the circuit to be verified according to the symbolic state transition model; Based on the symbolic simulation process script and the symbolic state transition model, the symbolic state is driven to be updated in simulation cycle by cycle until the cycle termination condition is met. Assertional verification is performed on all symbol states at the current moment to generate simulation verification results for the circuit to be verified.

2. The symbolic simulation verification method for digital circuits according to claim 1, characterized in that, The step of parsing the circuit description file and constructing a symbolic state transition model includes: The circuit description file is converted into a system text format to obtain the file to be parsed; The preset parser is invoked to parse the file to be parsed, extract the set of state variables, the set of input variables, the initial state conditions and the state transition relationships, and construct a symbolic state transition model.

3. The symbolic simulation verification method for digital circuits according to claim 2, characterized in that, Also includes: When state space constraints are extracted from the file to be parsed, the state space constraints are merged into the symbolic state transition model.

4. The symbolic simulation verification method for digital circuits according to claim 2 or 3, characterized in that, The step of initializing the symbolic state corresponding to the circuit to be verified according to the symbolic state transition model includes: Iterate through the set of state variables; the set of state variables includes multiple state variables; Based on the initial state conditions, construct the state variable mapping for each of the state variables one by one; Initialize the path constraints associated with each of the state variables according to the initial state conditions; The symbolic state corresponding to the circuit to be verified is generated by using the state variable mapping and the path constraint.

5. The symbolic simulation verification method for digital circuits according to claim 4, characterized in that, The step of constructing the state variable mapping for each of the state variables one by one based on the initial state conditions includes: If the initial state condition is an open initial condition, then all state variable mappings of the state variables are initialized to symbolic quantities; If the initial state condition is a specified initial condition, then each of the state variables is initialized to the specified quantity corresponding to the specified initial condition; the specified quantity includes a symbolic quantity or a constant value.

6. The symbolic simulation verification method for digital circuits according to claim 2 or 3, characterized in that, The step of driving the symbolic state to perform simulation updates cycle by cycle according to the symbolic simulation process script and the symbolic state transition model until the cycle termination condition is met includes: The flow statements within the symbol simulation flow script are analyzed line by line. When the process statement is an assignment statement, the input mapping corresponding to the input variable is created according to the assignment statement; When the process statement is a conditional statement, at least one set of path branches is created according to the conditional statement; When the process statement is an assertion statement, an assertion check is performed on the symbol states corresponding to all the path branches at the current time according to the assertion statement. According to the state transition relationship, symbolic simulation calculations are performed using all symbolic states at the current moment and the input mapping to obtain new symbolic states; Determine if the loop termination condition is met; If the loop termination condition is not met, the process jumps to the step of parsing the flow statements in the symbol simulation flow script line by line until the loop termination condition is met.

7. The symbolic simulation verification method for digital circuits according to claim 6, characterized in that, When the process statement is an assignment statement, the step of creating the input mapping corresponding to the input variable according to the assignment statement includes: When the process statement is an assignment statement, an input mapping for the input variables in the input variable set is created according to the assignment corresponding to the assignment statement; If there are unassigned input variables in the set of input variables, a new symbolic variable is created and associated with the unassigned input variable to construct a new input mapping; If there are multiple sets of the path branches, then different symbol values ​​are configured for the input mapping of each set of the path branches.

8. The symbolic simulation verification method for digital circuits according to claim 6, characterized in that, The step of creating at least one set of path branches based on the conditional statement when the process statement is a conditional statement includes: When the process statement is a conditional statement, extract the conditional expression within the conditional statement; If the symbol state involved in the conditional expression has an undetermined symbol quantity, then determine whether the value of the undetermined symbol quantity satisfies all the undetermined conditions in the conditional expression. If so, then copy the symbolic state involved in the conditional expression, and merge the undetermined conditions satisfied by each of the values ​​into the corresponding path constraints to obtain at least two sets of parallel path branches; If not, the undetermined conditions satisfied by the value are merged into the path constraints to obtain a single set of path branches.

9. The symbolic simulation verification method for digital circuits according to claim 8, characterized in that, Also includes: Periodically check whether each path branch is a redundant path; If so, the redundant path is merged into an existing path branch.

10. The symbolic simulation verification method for digital circuits according to claim 6, characterized in that, When the process statement is an assertion statement, the step of performing assertion checks on the symbol states corresponding to all path branches at the current time based on the assertion statement includes: When the process statement is an assertion statement, extract the first assertion condition corresponding to the assertion statement; Construct the first logical expression using the first assertion condition and the current symbol state; Call the preset logic solver to solve the first logic expression and determine whether there is a violation symbol state that violates the first assertion condition; If it exists, then generate counterexample information corresponding to the violation symbol state; If it does not exist, then the step of performing symbolic simulation calculations according to the state transition relationship, using all symbolic states at the current moment and the input mapping, to obtain a new symbolic state is executed.

11. The symbolic simulation verification method for digital circuits according to claim 6, characterized in that, The step of performing symbol simulation calculations using all symbol states at the current moment and the input mapping according to the state transition relationship to obtain new symbol states includes: The current state variable mapping and the input mapping are merged to construct a replacement environment; When the symbolic state transition model does not have the state space constraints, the symbolic expressions corresponding to each of the state variables are matched from the state transition relations. The symbolic expression is symbolically replaced according to the replacement environment to obtain the target symbolic expression as a state update mapping. By associating the state update mapping with the existing path constraints, a new symbolic state is obtained.

12. The symbolic simulation verification method for digital circuits according to claim 11, characterized in that, Also includes: When the symbolic state transition model has state space constraints, extract the constraint variables within the state space constraints. The replacement environment is updated using the constraint variables; The constraint variables are merged into the existing path constraints, and the process jumps to the step of performing symbolic substitution on the symbolic expression according to the replacement environment to obtain the target symbolic expression as the state update mapping.

13. The symbolic simulation verification method for digital circuits according to claim 11, characterized in that, After performing the step of performing symbolic substitution on the symbolic expression according to the substitution environment to obtain the target symbolic expression as a state update mapping, the method further includes: If the target symbolic expression satisfies the preset simplification conditions, then the symbolic representation of the target symbolic expression is simplified to obtain a new state update variable; Jump to the step of associating the state update variable with the existing path constraints to obtain the new symbol state.

14. The symbolic simulation verification method for digital circuits according to claim 1, characterized in that, The step of asserting and verifying all symbol states at the current moment to generate the simulation verification result corresponding to the circuit to be verified includes: Using all symbol states at the current moment, construct the second logical expression respectively; Call the preset expression solver to determine whether each of the second logical expressions satisfies the second assertion condition; If all of the second logic expressions satisfy the second assertion condition, the assertion is deemed to pass, and the simulation verification result corresponding to the circuit to be verified is generated as a successful verification. If any of the second logical expressions fails to satisfy the second assertion condition, the assertion is deemed unsuccessful, and the simulation verification result corresponding to the circuit to be verified is deemed a verification failure.

15. The symbolic simulation verification method for digital circuits according to claim 14, characterized in that, Also includes: When the assertion fails, locate the state of the symbol to be optimized associated with the second logical expression; The solver generates counterexample information corresponding to the symbol state to be optimized.

16. The symbolic simulation verification method for digital circuits according to claim 1, characterized in that, The method further includes: The symbolic simulation process script is parsed to determine the simulation clock propagation mode; the simulation clock propagation mode includes active stepping mode and asynchronous mode. If the simulation clock advance mode is an active stepping mode, then a stepping interface, a backtracking interface, and multiple first simulation interfaces corresponding to the active stepping mode are provided for the symbolic simulation process script to call. If the simulation clock advance mode is asynchronous, then multiple second simulation interfaces corresponding to the asynchronous mode are provided for the symbolic simulation process script to call.

17. The symbolic simulation verification method for digital circuits according to claim 4, characterized in that, The path constraints include at least one of the implicit path constraints generated by the path branches and the constraints explicitly added by the external validation environment.

18. A symbolic simulation verification device for digital circuits, characterized in that, Applied to a symbol simulator, the device includes: The file acquisition module is used to acquire the circuit description file and symbol simulation process script corresponding to the circuit to be verified. A state transition model construction module is used to parse the circuit description file and construct a symbolic state transition model. The symbol state initialization module is used to initialize the symbol state corresponding to the circuit to be verified according to the symbolized state transition model. The simulation update module is used to drive the symbolic state to perform simulation updates cycle by cycle according to the symbolic simulation process script and the symbolic state transition model until the cycle termination condition is met. The assertion verification module is used to perform assertion verification on all symbol states at the current time and generate simulation verification results corresponding to the circuit to be verified.

19. A computer device, characterized in that, The system includes a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor causes the processor to perform the steps of the symbolic simulation verification method for digital circuits as described in any one of claims 1-17.

20. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed, it implements the symbolic simulation verification method for digital circuits as described in any one of claims 1-17.

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