Method for optimizing load modulation behavior of an asymmetrically load-modulated balanced power amplifier

Abstract

This invention discloses a method for optimizing the load modulation behavior of an asymmetric load-modulated balanced power amplifier. The implementation steps are as follows: Select the maximum transistor size based on the manufacturing process; evaluate the maximum fundamental current achievable by the transistor process through load-pull and source-pull simulations to determine the saturated output power design target and the required power back-off index; based on the theoretical model, plot the back-off efficiency distribution and saturated efficiency distribution under the power back-off index to identify the optimal current ratio design space; build an ideal simulation setup for the asymmetric load-modulated balanced power amplifier; compare the circuit performance under various current ratio combinations, select the optimal current ratio combination, and determine the optimal load modulation trajectory. This invention, starting from theory and combining it with ideal simulation, proposes a method for optimizing the load modulation behavior of an asymmetric load-modulated balanced power amplifier, thereby guiding the design of high-efficiency asymmetric load-modulated balanced power amplifiers.

Description

Technical Field

[0001] This invention relates to the field of power amplifier technology, and more specifically to a method for optimizing the load modulation behavior of an asymmetric load-modulated balanced power amplifier. Background Technology

[0002] In recent years, emerging applications such as the Internet of Things (IoT) and wireless backhaul have placed stringent demands on communication systems, requiring higher throughput, higher data transmission rates, and lower transmission latency. To achieve high communication rates and high-throughput data transmission within limited spectrum resources, signal modulation methods have become increasingly complex to maximize spectrum utilization. For example, orthogonal amplitude modulation (OAM) and orthogonal frequency division multiplexing (OFDM) technologies have been widely adopted. These higher-order signal modulation methods significantly increase the peak-to-average power ratio (PAPR) of the transmitted signal. Therefore, power amplifiers must operate under a certain output power back-off state, inevitably leading to a significant decrease in amplifier efficiency. As a key component in RF systems, the power amplifier accounts for almost the largest proportion of system power consumption, and the overall system efficiency is largely affected by its efficiency. Therefore, finding methods to improve the efficiency of power amplifiers under back-off state is urgently needed to enhance the performance of the entire communication system.

[0003] As an emerging active load modulation architecture, load-modulated balanced power amplifiers (DPPAs) have proven to be a solution that balances improved backoff efficiency with broadband applications. To date, the original DPPAs have evolved into several architectures, most notably the sequential load-modulated balanced power amplifier and the pseudo-Dougherty load-modulated balanced power amplifier. This architecture consists of a Class AB biased control amplifier and two Class C biased balanced amplifiers. In the low-power region, the balanced amplifier branches remain off, and the entire system's output power is provided solely by the control amplifier branches. When entering the load-modulated region, the balanced amplifier branches turn on and are load-modulated by the control amplifier branches. However, this architecture often suffers from overdrive in the control amplifier branches, leading to severe nonlinear distortion and device reliability issues.

[0004] To address the aforementioned overdrive problem and improve the overall reliability and linearity of the system, an asymmetric load-modulated balanced power amplifier architecture has been proposed. This architecture employs an asymmetric bias voltage supply strategy for the balanced amplifier branch, effectively mitigating overdrive in the control amplifier branch. However, the introduction of the asymmetric bias voltage also increases the complexity of the load modulation behavior between the control amplifier and the balanced amplifier, undoubtedly increasing the design difficulty of broadband asymmetric load-modulated balanced power amplifiers. In numerous studies, a systematic and comprehensive theoretical analysis of the impact of current ratio on load modulation behavior and overall system architecture performance is still lacking. Furthermore, due to the technological bottlenecks of millimeter-wave semiconductor processes, implementing asymmetric load-modulated balanced power amplifiers in the V-band (50-75 GHz) presents a more severe challenge than in the low-frequency band. Given these application backgrounds and technical challenges, a comprehensive and in-depth understanding of the complex load modulation behavior in V-band asymmetric load-modulated balanced power amplifier design is crucial. Summary of the Invention

[0005] Purpose of the invention: The purpose of this invention is to provide a method for optimizing the load modulation behavior of an asymmetric load-modulated balanced power amplifier, so as to optimize the performance of the asymmetric load-modulated balanced power amplifier and guide the design of a high-efficiency asymmetric load-modulated balanced power amplifier.

[0006] Technical Solution: To achieve the above-mentioned objectives, this invention provides a method for optimizing the load modulation behavior of an asymmetric load-modulated balanced power amplifier. This method analyzes the impact of the current ratio on the load modulation behavior and overall system architecture performance of the asymmetric load-modulated balanced power amplifier, visualizes the efficiency distribution as a function of the current ratio, and determines the optimal current ratio combination through ideal simulation. The method specifically includes the following steps:

[0007] S1. Select the largest size transistor according to the process technology used, and evaluate the maximum fundamental current that the transistor process can achieve through load-pull and source-pull simulations.

[0008] S2. Based on the simulation results of load pulling and source pulling of the largest size transistor, determine the saturated output power target and the required power back-off index of the asymmetric load modulated balanced power amplifier.

[0009] S3. Based on the theoretical efficiency model of the asymmetric load modulated balanced power amplifier, draw the efficiency distribution diagrams of the back-off state and the saturation state under the power back-off index. By identifying the overlapping part of the high efficiency region in the two efficiency distribution diagrams, determine the optimal current ratio design space.

[0010] S4. Build an ideal simulation setup that includes a control power amplifier module, a first balanced power amplifier module, a second balanced power amplifier module, and an output coupler module, and select multiple different current ratio combinations within the optimal current ratio design space for simulation.

[0011] S5. Compare the circuit performance under various current ratio combinations, select the optimal current ratio combination, and determine the optimal load modulation trajectory.

[0012] Preferably, in step S3, the current ratio parameters used when plotting the efficiency distribution diagram include: a first parameter σ used to describe the degree of current imbalance between the first balanced amplifier module and the second balanced amplifier module, and a second parameter γ used to describe the current ratio of the control power amplifier module between the back-off state and the saturation state.

[0013] Preferably, in step S3, the overall architecture output power and theoretical efficiency models are obtained through the Z-impedance matrix of the coupled-line coupler and the operating state of the asymmetric load modulated balanced power amplifier, respectively:

[0014]

[0015]

[0016] in Output power for the overall architecture of the load modulation region. The characteristic impedance of the coupled-line coupler. To control the drain fundamental current of the power amplifier module in the load modulation region, To control the drain fundamental current of the power amplifier module in saturation state, and These represent the normalized drive level and the backoff point drive level, respectively.

[0017] Preferably, in step S3, the efficiency variation curves of the first parameter σ and the second parameter γ under various combinations are obtained according to the output power model and the theoretical efficiency model. The efficiency of the target saturated output power and the backoff power point is visualized as an efficiency distribution map, and the overlapping part is extracted as the optimal current ratio design space.

[0018] Preferably, in step S4, the ideal simulation setting adopts an asymmetric drain voltage bias scheme, wherein the drain voltage bias of the second balanced power amplifier module is greater than that of the first balanced power amplifier module; the currents of the first balanced power amplifier module and the second balanced power amplifier module are unbalanced, and the current difference enters the control power amplifier module through the isolation terminal of the output coupler module; the load impedance of the control power amplifier module is modulated by the current difference between the second balanced power amplifier module and the first balanced power amplifier module.

[0019] Preferably, in step S4, the output current of the control power amplifier module is injected into the first balanced power amplifier module and the second balanced power amplifier module through the output coupler module, thereby generating load modulation on the first balanced power amplifier module and the second balanced power amplifier module.

[0020] Preferably, in step S4, the output coupler module uses a Lange coupler based on the coupling line.

[0021] Furthermore, the method also includes: S6, designing an actual impedance matching network based on the load modulation trajectory corresponding to the optimal current ratio combination, and completing the design of the power amplifier.

[0022] The present invention also provides a computer system, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the method for optimizing the load modulation behavior of the asymmetric load modulation balanced power amplifier.

[0023] Beneficial Effects: Compared with existing technologies, this invention employs an optimization method for the load modulation behavior of an asymmetric load-modulated balanced power amplifier. Based on the theoretical efficiency model of the asymmetric load-modulated balanced power amplifier, it plots the efficiency distribution diagrams under the power back-off index and the efficiency distribution diagrams under the saturation state. By identifying the overlapping parts of the high-efficiency regions in the two efficiency distribution diagrams, the optimal current ratio design space is determined. Finally, the optimal branch current ratio is determined through ideal simulation comparison, providing design guidance for asymmetric load-modulated balanced power amplifiers. The completed design effectively verifies the effectiveness of this method, achieving high saturation output power within the operating frequency band while maintaining high efficiency over a large back-off output power range. Attached Figure Description

[0024] Figure 1 This is a flowchart of a method according to an embodiment of the present invention;

[0025] Figure 2 This is a schematic diagram of an ideal simulation setup for an example in an embodiment of the present invention;

[0026] Figure 3 This is a diagram showing the efficiency distribution of an asymmetric load-modulated balanced power amplifier. Figure 3 In the diagram, (a) represents the distribution of the amplifier's power point efficiency with respect to the current ratio when it goes back 10 dB. Figure 3 (b) in the diagram represents the distribution of the amplifier's efficiency in saturation state with respect to the change in current ratio;

[0027] Figure 4 To Figure 3The load modulation trajectory is obtained by ideal simulation of three current ratio combinations in the optimal load modulation region. Figure 4 (a) in the figure is the current surface load modulation trajectory of the three transistors under the Case-A combination. Figure 4 (b) in the figure is the current surface load modulation trajectory of the three transistors under the Case-B combination. Figure 4 (c) in the figure represents the current surface load modulation trajectory of the three transistors under the Case-C combination.

[0028] Figure 5 To Figure 3 The curves of fundamental current versus output power obtained from ideal simulations of three current ratio combinations in the optimal load modulation region are shown. Figure 5 In the diagram, (a) represents the fundamental current controlling the power amplifier module 3 (CA). Figure 5 In the diagram, (b) represents the fundamental current of BA1 balanced power amplifier module 1 and BA2 balanced power amplifier module 2.

[0029] Figure 6 To Figure 3 The curves of power-added efficiency and gain versus output power obtained by ideal simulation of three current ratio combinations in the optimal load modulation region.

[0030] Figure 7 This is a schematic diagram of an asymmetric load modulation balanced power amplifier designed under the guidance of the method of this invention.

[0031] Figure 8 In this embodiment of the invention, the simulated power-added efficiency and gain curves of the asymmetric load modulation balanced power amplifier at frequencies of 62.5-72.5 GHz are shown as a function of output power.

[0032] Figure 9 This is a current diagram of the amplifier designed in this embodiment of the invention at 70 GHz.

[0033] Figure 10 In this embodiment of the invention, the measured power-added efficiency and gain of the asymmetric load modulated balanced power amplifier at frequencies of 62.5-72.5 GHz are curves showing the changes in output power. Detailed Implementation

[0034] The technical solution of the present invention will be further described below with reference to specific embodiments and accompanying drawings.

[0035] This invention provides a method for optimizing the load modulation behavior of an asymmetric load-modulated balanced power amplifier. After determining the maximum current achievable by the adopted transistor process, the overall architecture target performance is determined. An efficiency distribution diagram is plotted as a function of the current ratio to determine the optimal current ratio design space. Then, ideal simulation settings are used to further confirm the optimal current ratio combination. For example... Figure 1 As shown, the method includes the following steps:

[0036] S1. Select the largest size transistor according to the process technology used, and evaluate the maximum fundamental current that the transistor process can achieve through load-pull and source-pull simulations.

[0037] S2. Based on the simulation results of load pulling and source pulling of the largest size transistor, determine the saturated output power target and the required power back-off index of the asymmetric load modulated balanced power amplifier.

[0038] S3. Based on the theoretical efficiency model of the asymmetric load modulated balanced power amplifier, draw the efficiency distribution diagrams of the back-off state and the saturation state under the power back-off index. By identifying the overlapping part of the high efficiency region in the two efficiency distribution diagrams, determine the optimal current ratio design space.

[0039] S4. Build an ideal simulation setup that includes a control power amplifier module, a first balanced power amplifier module, a second balanced power amplifier module, and an output coupler module, and select multiple different current ratio combinations within the optimal current ratio design space for simulation.

[0040] S5. Compare the circuit performance under various current ratio combinations, select the optimal current ratio combination, and determine the optimal load modulation trajectory.

[0041] Specifically, in some possible implementations, in step S1, the largest-size transistor is selected based on the chosen millimeter-wave transistor process, and the maximum fundamental current achievable by this millimeter-wave transistor process is evaluated through load-pull and source-pull simulations. For example, if the transistor process used is determined to be 100-nm GaAs pHEMT, the largest-size transistor is 4×50um, and the simulation tool is Advanced Design System (ADS). In step S3, the current ratio parameters used when plotting the efficiency distribution diagram include: a first parameter σ used to describe the degree of current imbalance between the first and second balanced amplifier modules, and a second parameter γ used to describe the current ratio of the control power amplifier module between the back-off state and the saturation state. In step S4, the largest-size transistor is selected as the transistor for the first and second balanced power amplifier modules, and the control power amplifier module transistor is selected according to the back-off range. Combined with the output parasitic de-embedding network, an ideal simulation setting for the asymmetric load modulation balanced power amplifier is built.

[0042] Preferably, after obtaining the optimal current ratio combination in step S5, the method further includes: S6, designing an actual impedance matching network based on the load modulation trajectory corresponding to the optimal current ratio combination, and completing the design of the power amplifier.

[0043] The following is combined Figure 2 The ideal simulation settings shown will be used to further illustrate this embodiment in detail. For example... Figure 2 As shown, the simulation setup includes a first balanced power amplifier module 1 (BA1), a second balanced power amplifier module 2 (BA2), a control power amplifier module 3 (CA), and an output coupler module 4. The control power amplifier module 3 (CA) serves as the main circuit, while the first balanced power amplifier module 1 (BA1) and the second balanced power amplifier module 2 (BA2) serve as auxiliary circuits. The output terminal of the control power amplifier module 3 (CA) is connected to the isolation terminal of the output coupler module 4. The output terminals of the first balanced power amplifier module 1 (BA1) and the second balanced power amplifier module 2 (BA2) are respectively connected to the through port and coupling port of the output coupler module 4. The output terminal of the output coupler module 4 serves as the output terminal of the overall asymmetric load modulation balanced power amplifier, connected to the load.

[0044] The control power amplifier module 3 (CA) includes a power input port 31, a grid voltage power supply circuit 32, a third transistor 33, an output parasitic de-embedding network 34, a drain voltage power supply circuit 35, and an ideal transformer 36 connected in sequence. The input terminal of the power input port 31 is the input terminal of the control power amplifier module 3 (CA), and the output terminal of the ideal transformer 36 is the output terminal of the control power amplifier module 3 (CA).

[0045] The first balanced power amplifier module 1 (BA1) and the second balanced power amplifier module 2 (BA2) are auxiliary circuits. The first balanced power amplifier module 1 (BA1) includes a power input port 11, a grid voltage supply circuit 12, a first transistor 13, an output parasitic de-embedding network 14, a drain voltage supply circuit 15, and an ideal transformer 16, connected in sequence. The input terminal of the power input port 11 is the input terminal of the first balanced power amplifier module 1 (BA1), and the output terminal of the ideal transformer 16 is the output terminal of the first balanced power amplifier module 1 (BA1). The second balanced power amplifier module 2 (BA2) includes a power input port 21, a grid voltage supply circuit 22, a second transistor 23, an output parasitic de-embedding network 24, a drain voltage supply circuit 25, and an ideal transformer 26, connected in sequence. The input terminal of the power input port 21 is the input terminal of the second balanced power amplifier module 2 (BA2), and the output terminal of the ideal transformer 26 is the output terminal of the second balanced power amplifier module 2 (BA2).

[0046] The first balanced power amplifier module 1 (BA1) and the second balanced power amplifier module 2 (BA2) adopt an asymmetrical drain voltage bias scheme. The drain voltage bias of the second balanced power amplifier module 2 (BA2) is greater than that of the first balanced power amplifier module 1 (BA1). The current of the second balanced power amplifier module 2 (BA2) and the first balanced power amplifier module 1 (BA1) is unbalanced, and the current difference enters the control power amplifier module 3 (CA) through the isolation terminal of the output coupler module 4.

[0047] The load impedance of the control power amplifier module 3 (CA) is modulated by the current difference between the second balanced power amplifier module 2 (BA2) and the first balanced power amplifier module 1 (BA1). The output current of the control power amplifier module 3 (CA) is injected into the first balanced power amplifier module 1 (BA1) and the second balanced power amplifier module 2 (BA2) through the output coupler module 4, thus modulating the load of the first balanced power amplifier module 1 (BA1) and the second balanced power amplifier module 2 (BA2). The output coupler module 4 uses a Lange coupler based on a coupling line.

[0048] The theoretical efficiency model of an asymmetric load modulated balanced power amplifier is explained below.

[0049] The ratio of the saturation current to the back-off current of the control power amplifier module is defined as parameter γ, and the current ratio of the first balanced power amplifier module 1 (BA1) to the second balanced power amplifier module 2 (BA2) is defined as parameter σ. Based on the operating state of the asymmetric load-modulated balanced power amplifier and the Z-impedance matrix of the Lange coupler, the overall architecture output power and theoretical efficiency models under the optimal load modulation conditions are derived as follows:

[0050]

[0051]

[0052] in Output power for the overall architecture of the load modulation region. The characteristic impedance of the coupled-line coupler. To control the drain fundamental current of the power amplifier module in the load modulation region, To control the drain fundamental current of the power amplifier module in saturation state, and These represent the normalized drive level and the backoff point drive level, respectively. In this embodiment, the overall architecture output power and theoretical efficiency model are obtained through the Z-impedance matrix of the coupled-line coupler and the operating state of the asymmetric load modulated balanced power amplifier. Based on the output power model and the theoretical efficiency model, the efficiency versus output curves under various combinations of the first parameter σ and the second parameter γ are obtained. The efficiency at the target saturated output power and the backoff power point is visualized as an efficiency distribution map, and the overlapping part is extracted as the optimal current ratio design space.

[0053] The specific steps and effects of the embodiments of the present invention will be described below with reference to application examples.

[0054] Based on step S1, the achievable fundamental current using the maximum transistor must first be determined. Through single-transistor source-pull and load-pull simulations at 70 GHz, the second balanced power amplifier module 2 (BA2) can provide a saturated output power of 21.5 dBm, corresponding to a maximum drain fundamental current of 78 mA. Based on this, the target saturated output power of the asymmetric load-modulated balanced power amplifier is set to 25 dBm, and the power back-off range is set to 10 dB. Furthermore, according to the theoretical efficiency model formula derived in step S3, the relationship between drain efficiency and the current ratio parameters σ and γ can be calculated. Figure 3 As shown, the corresponding relationships are visualized and plotted to obtain the efficiency distribution diagram of the asymmetric load-modulated balanced power amplifier. Figure 3 In the diagram, (a) represents the distribution of the amplifier's power point efficiency with respect to the current ratio when it goes back 10 dB. Figure 3 (b) in the diagram represents the efficiency distribution of the amplifier in saturation state as a function of the current ratio. The contour line indicating drain efficiency exceeding 60% in the 10 dB power back-off state is marked by a dashed line. This high-efficiency region in the back-off state is depicted... Figure 3In the high-efficiency contour plot of saturation state in (b), the overlapping area of ​​the two contour lines can be used as the optimal design space for optimizing load modulation behavior. As long as appropriate values ​​of σ and γ are selected within this design space, the designed asymmetric load modulation balanced power amplifier can achieve both saturation efficiency and back-off efficiency.

[0055] Based on step S4, to illustrate concretely and intuitively how to further optimize the load modulation behavior to obtain high-efficiency performance, a simulation of an ideal architecture for an asymmetric load-modulated balanced power amplifier was performed at a frequency of 70 GHz, as follows: Figure 2 As shown. The optimal source impedance is... , , The optimal source impedances for the control power amplifier module 3 (CA), the first balanced power amplifier module 1 (BA1), and the second balanced power amplifier module 2 (BA2) are obtained based on the source-pull simulation in step S1. To control the input power of power amplifier module 3 (CA) and the phase difference between the input signal and the first balanced power amplifier module 1 (BA1) is... ; The input power is the first balanced power amplifier module 1 (BA1) and the second balanced power amplifier module 2 (BA2), wherein the phase difference between the second balanced power amplifier module 2 (BA2) and the first balanced power amplifier module 1 (BA1) is -90°. , , These are the current-surface impedances of the control power amplifier module 3 (CA), the first balanced power amplifier module 1 (BA1), and the second balanced power amplifier module 2 (BA2), respectively. Figure 3For the markings on (b), we selected three representative combinations of σ and γ for comparative simulation analysis: Case-A: σ = 0.81, γ = 0.67; Case-B: σ = 0.91, γ = 0.82; Case-C: σ = 0.67, γ = 0.6. In the ideal simulation settings, the bias voltage of each transistor is determined based on the preliminary simulation of the transistor's DC IV and AC transconductance characteristics. To achieve optimal performance, the optimal source impedance needs to be selected in advance through single-transistor source-pull simulation. Furthermore, the transistors are excited by setting three continuous wave signals with appropriate phase offsets to ensure that each transistor receives accurate load modulation. Different drain voltage bias strategies are used for the first balanced power amplifier module 1 (BA1) and the second balanced power amplifier module 2 (BA2). When the control power amplifier module 3 (CA) reaches voltage saturation, the current difference between the second balanced power amplifier module 2 (BA2) and the first balanced power amplifier module 1 (BA1) will modulate the load impedance of the control power amplifier module 3 (CA). Simultaneously, the control power amplifier module 3 (CA) will modulate the load impedances of the other two paths. According to step S5, the simulated load modulation trajectory is as follows... Figure 4 As shown. Specifically, in each example: for Case-A, as... Figure 4 As shown in (a), the modulation of the control power amplifier module 3 (CA) is more pronounced, shifting from a high-impedance region to a low-impedance region, and the saturation resistance of the first balanced power amplifier module 1 (BA1) is greater than that of the second balanced power amplifier module 2 (BA2); in Case-B, as... Figure 4 As shown in (b), due to the cancellation of symmetrical currents at the isolation port of the output coupler, the control power amplifier module 3 (CA) is almost not modulated, and the first balanced power amplifier module 1 (BA1) and the second balanced power amplifier module 2 (BA2) exhibit extremely similar load modulation trajectories; while in Case-C, as Figure 4 As shown in (c), the architecture is most asymmetric, so the control power amplifier module 3 (CA) is modulated to a lower impedance region, and the impedance difference between the first balanced power amplifier module 1 (BA1) and the second balanced power amplifier module 2 (BA2) becomes more significant.

[0056] Figure 5Further comparison of the fundamental drain current simulation results under these three conditions revealed significant differences in the current trends in the load modulation region. In Case-A, as the current difference between the second balanced power amplifier module 2 (BA2) and the first balanced power amplifier module 1 (BA1) increases, the current in the control power amplifier module 3 (CA) shows an upward trend, and the current in the second balanced power amplifier module 2 (BA2) is higher than that in the first balanced power amplifier module 1 (BA1) in the load modulation region. In contrast, in Case-C, the current increase in the control power amplifier module 3 (CA) is faster, due to the larger current difference between the other two paths. In Case-B, since the currents in the other two paths are almost identical, the control power amplifier module 3 (CA) experiences almost no overdrive due to load modulation, and its drain current decreases slightly. This indicates that the overall behavior of Case-B is extremely close to the operating state of a balanced power amplifier with symmetrical load modulation.

[0057] Figure 6 The simulation curves of power-added efficiency and gain as a function of output power are shown. In the low-power region, the curves for the three cases almost overlap, and the gain and power-added efficiency performance are almost identical. This indicates that in the stage without load modulation, the overall performance is not affected by the current ratio. After entering the load modulation region, as the asymmetry of the other two bias voltages increases, the load modulation effect on the control power amplifier module 3 (CA) becomes more significant. Thanks to this, its overdrive problem is alleviated, and its performance is maintained to a certain extent, thereby improving the overall power-added efficiency. However, since the bias voltage of the first balanced power amplifier module 1 (BA1) in the asymmetric architecture becomes lower with the increase of asymmetry, its gain compression at saturation will also intensify. Therefore, with the increase of asymmetry, gain compression and rapid decline in power-added efficiency will occur earlier. After weighing the options, Case-A achieves the optimal balance in the selection of current ratios σ and γ, effectively alleviating the overdrive problem of the control power amplifier module 3 (CA) while maintaining high efficiency and high gain, successfully optimizing the load modulation behavior and maximizing the overall performance of the asymmetric load-modulated balanced power amplifier.

[0058] Based on step S6, and using the aforementioned theoretical analysis and ideal simulation verification, and employing the optimal current ratio determined by Case-A, a 62.5-72.5 GHz asymmetric load modulation balanced power amplifier was designed. The schematic diagram is shown below. Figure 7 As shown. The proposed theoretical method can effectively extract the optimal load modulation trajectory of each transistor within the frequency band, which serves as the design target for the actual circuit and is realized through an output matching network. The power amplifier designed in this paper is fabricated using a 100-nm GaAs pHEMT process.

[0059] Figure 8 The electromagnetic simulation curves depict power-added efficiency and gain as a function of output power. Within the 62.5–72.5 GHz band, the saturated output power is greater than 22.6 dBm, and the peak power-added efficiency is greater than 23.1%. Furthermore, the amplifier achieves a power-added efficiency greater than 15.4% for 6-dB power back-off, greater than 13.1% for 8-dB power back-off, and greater than 9.6% for 10-dB power back-off within the band. Compared to the ideal simulation results given earlier, the output power and efficiency in the actual circuit simulation are slightly lower. Considering the high insertion loss of passive networks in the V-band, this result is within reasonable expectations.

[0060] like Figure 9 As shown, the current ratio achieved by this asymmetric load modulated balanced power amplifier at 70 GHz is σ = 0.82 and γ = 0.67, which is very close to the design target current ratio.

[0061] Figure 10 The large-signal continuous wave test results of the designed asymmetric load-modulated balanced power amplifier are presented. The design achieves a saturated output power greater than 21.1 dBm across the entire frequency band, with an in-band peak power-added efficiency (PPE) greater than 21.1%, a PPE greater than 15.1% at 6-dB power backoff, and a PPE greater than 11.5% at 8-dB power backoff. At a center frequency of 67.5 GHz, the asymmetric load-modulated balanced power amplifier achieves a saturated output power of 22.4 dBm and a PPE of 22.8%, with PPEs of 19%, 15.4%, and 10.2% at 6-dB, 8-dB, and 10-dB power backoff conditions, respectively. The actual measurement results agree well with the electromagnetic simulation curves. Simulation and experimental results demonstrate that the designed asymmetric load-modulated balanced power amplifier balances saturation and backoff efficiency, maintaining high efficiency under large backoff conditions.

[0062] This invention also provides a computer system, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, it implements the steps of the method for optimizing the load modulation behavior of an asymmetric load modulation balanced power amplifier in any of the foregoing method embodiments.

[0063] The program code used to implement the method of the present invention can be written in any combination of one or more programming languages. This program code can be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that when executed by the processor or controller, the program code causes the steps of the method of the present invention to be performed. The program code can be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a standalone software package, or entirely on a remote machine or server. All aspects not detailed in this invention are well-known to those skilled in the art.

[0064] Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples, without contradiction. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of this invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of this invention through logical analysis, reasoning, or limited experimentation on the basis of the prior art should be within the scope of protection defined by the claims.

Claims

1. A method for optimizing the load modulation behavior of an asymmetric load-modulated balanced power amplifier, characterized in that, Includes the following steps: S1. Select the largest size transistor according to the process technology used, and evaluate the maximum fundamental current that the transistor process can achieve through load-pull and source-pull simulations. S2. Based on the simulation results of load pulling and source pulling of the largest size transistor, determine the saturated output power target and the required power back-off index of the asymmetric load modulated balanced power amplifier. S3. Based on the theoretical efficiency model of the asymmetric load modulated balanced power amplifier, draw the efficiency distribution diagrams of the back-off state and the saturation state under the power back-off index. By identifying the overlapping part of the high efficiency region in the two efficiency distribution diagrams, determine the optimal current ratio design space. S4. Build an ideal simulation setup that includes a control power amplifier module, a first balanced power amplifier module, a second balanced power amplifier module, and an output coupler module, and select multiple different current ratio combinations within the optimal current ratio design space for simulation. S5. Compare the circuit performance under various current ratio combinations, select the optimal current ratio combination, and determine the optimal load modulation trajectory.

2. The method for optimizing the load modulation behavior of an asymmetric load-modulated balanced power amplifier according to claim 1, characterized in that, In step S3, the current ratio parameters used when plotting the efficiency distribution diagram include: a first parameter σ used to describe the degree of current imbalance between the first balanced amplifier module and the second balanced amplifier module, and a second parameter γ used to describe the current ratio of the control power amplifier module between the back-off state and the saturation state.

3. The method for optimizing the load modulation behavior of an asymmetric load-modulated balanced power amplifier according to claim 2, characterized in that, In step S3, the overall architecture output power and theoretical efficiency models are obtained through the Z-impedance matrix of the coupled-line coupler and the operating state of the asymmetric load modulated balanced power amplifier, respectively: ； ； in Output power for the overall architecture of the load modulation region. The characteristic impedance of the coupled-line coupler. To control the drain fundamental current of the power amplifier module in the load modulation region, To control the drain fundamental current of the power amplifier module in saturation state, and These represent the normalized drive level and the backoff point drive level, respectively.

4. The method for optimizing the load modulation behavior of an asymmetric load-modulated balanced power amplifier according to claim 2, characterized in that, In step S3, the efficiency variation curves of the first parameter σ and the second parameter γ under various combinations are obtained according to the output power model and the theoretical efficiency model. The efficiency of the target saturated output power and the backoff power point is visualized as an efficiency distribution map, and the overlapping part is extracted as the optimal current ratio design space.

5. The method for optimizing the load modulation behavior of an asymmetric load-modulated balanced power amplifier according to claim 1, characterized in that, In step S4, the ideal simulation setting adopts an asymmetric drain voltage bias scheme, wherein the drain voltage bias of the second balanced power amplifier module is greater than that of the first balanced power amplifier module; the currents of the second balanced power amplifier module and the first balanced power amplifier module are unbalanced, and the current difference enters the control power amplifier module through the isolation terminal of the output coupler module; the load impedance of the control power amplifier module is modulated by the current difference between the second balanced power amplifier module and the first balanced power amplifier module.

6. The method for optimizing the load modulation behavior of an asymmetric load-modulated balanced power amplifier according to claim 1, characterized in that, In step S4, the output current of the control power amplifier module is injected into the first balanced power amplifier module and the second balanced power amplifier module through the output coupler module, thereby generating load modulation on the first balanced power amplifier module and the second balanced power amplifier module.

7. The method for optimizing the load modulation behavior of an asymmetric load-modulated balanced power amplifier according to claim 1, characterized in that, In step S4, the output coupler module adopts a Lange coupler based on coupling lines.

8. The method for optimizing the load modulation behavior of an asymmetric load-modulated balanced power amplifier according to claim 1, characterized in that, Also includes: S6. Based on the load modulation trajectory corresponding to the optimal current ratio combination, design the actual impedance matching network to complete the design of the power amplifier.

9. A computer system comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the computer program is executed by the processor, it implements the steps of the method for optimizing the load modulation behavior of an asymmetric load modulation balanced power amplifier according to any one of claims 1-7.

10. An asymmetric load-modulated balanced power amplifier, characterized in that, This is obtained through the method for optimizing the load modulation behavior of an asymmetric load-modulated balanced power amplifier according to any one of claims 1-7.

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