A high-reliability camera main control unit core board based on PolarFire SOC

Abstract

This invention relates to a high-reliability camera main control core board based on the PolarFire SoC, encompassing the hardware design technology of camera main control core boards. The core board uses the PolarFire SoC as its control and processing core, which integrates a five-core 64-bit RISC-V processor and a non-volatile FPGA Fabric, possessing single-event upset resistance and hardware-level safety mechanisms. To enhance data storage reliability, the system is configured with external memory with ECC functionality: including two DDR3 chips, an SPI NorFlash, and a Parallel NorFlash, all with transparent ECC error correction capabilities, used for program storage and high-speed data caching, respectively. This invention significantly improves the data integrity and operational stability of the camera main control system under extreme environments such as radiation and temperature variations, and is suitable for aerospace imaging, military electronics, and other high-reliability embedded applications.

Description

Technical Field

[0001] This invention relates to the field of hardware design technology for camera master control unit core boards, specifically to a high-reliability camera master control unit core board based on PolarFire SOC. Background Technology

[0002] The main camera controller is the core control hub of the space camera, and its core functions are:

[0003] (1) Control the imaging detector's shooting duration, shooting mode, and image data transmission, etc.;

[0004] (2) Collect and control the camera's thermal control system to ensure that the camera operates in a suitable temperature range;

[0005] (3) Communicate with satellite platforms or ground systems, receive instructions and provide feedback on equipment status;

[0006] (4) Monitor key parameters such as power supply voltage, current, and equipment operating status, and have fault diagnosis and fault tolerance capabilities to ensure stable and reliable imaging of the camera in extreme aerospace environments.

[0007] During long-term on-orbit operation, the camera's main control unit is susceptible to radiation from space particles and cosmic rays, which can induce radiation effects such as single-event upset, single-event latch-up, and single-event breakdown, leading to momentary malfunctions or permanent damage to electronic components. In addition, due to factors such as dynamic adjustments to mission requirements and on-orbit program code upgrades, the camera's main control unit is required to have high reliability to ensure the continuous and reliable execution of its on-orbit mission.

[0008] The core advantage of PolarFire SoC lies in its integration of high performance, high security, and high reliability. Compared to traditional SRAM architecture FPGAs, its non-volatile technology can reduce power consumption by up to 50%, and it can achieve instant startup without external configuration devices, making it ideal for power- and heat-dissipation-constrained scenarios such as aerospace.

[0009] The PolarFire SoC integrates a 64-bit five-core RISC-V processor, supports Linux and real-time control, and features rich GPIO / HSIO and native DDR interfaces to meet sensing and storage interaction needs. It incorporates hardware-level security mechanisms, including secure boot, anti-tampering, and bitstream encryption, ensuring end-to-end system trust.

[0010] Furthermore, its single-event upset (SEU) resistant architecture remains stable under radiation conditions, supports a wide temperature range of -40°C to 125°C, and boasts a long lifespan of 20-30 years, making it suitable for high-reliability applications such as aerospace and defense. Overall, it features a streamlined design, controllable cost, and ease of deployment.

[0011] Based on the above factors, this invention proposes a design method for a high-reliability camera main control unit core board based on PolarFire SOC. Summary of the Invention

[0012] This invention addresses the problem that existing camera main control units are susceptible to radiation bombardment from space particles and cosmic rays during operation, which can induce radiation effects such as single-event upset, single-event latch-up, and single-event breakdown, leading to momentary malfunctions or permanent damage to electronic components. It provides a highly reliable camera main control unit core board based on PolarFire SOC.

[0013] A high-reliability camera main control core board based on PolarFire SOC, the core board is composed of the following components:

[0014] The core board uses PolarFire SOC as the processor, which integrates a RISC-V processor and a non-volatile FPGA, and has built-in anti-single-event upset characteristics.

[0015] The PolarFire SOC's SPI0 interface is connected to SPI NorFlash, and the PolarFire SOC's BANK7 I / O is connected to Parallel NorFlash. Both the SPI NorFlash and Parallel NorFlash have built-in ECC error correction functionality.

[0016] The PolarFire SOC has a dedicated MSS DDR interface that connects two DDR3 chips.

[0017] PolarFire SOC's I 2 The C0 interface connects to a temperature sensor, which is located on the back of the DDR3 chip used for normal data storage and is used to monitor the operating temperature of the DDR3 chip.

[0018] The beneficial effects of this invention are:

[0019] The core board described in this invention is a high-reliability camera main control single-unit core board hardware design based on the PolarFire SoC, primarily addressing the need for long-term reliable operation of aerospace cameras in orbit. This design fully leverages the comprehensive advantages of the PolarFire SoC in terms of power consumption, reliability, and security to construct a high-reliability embedded control platform with multi-layered fault tolerance and health monitoring mechanisms, addressing issues such as single-event upsets caused by the space radiation environment.

[0020] The core board described in this invention uses the PolarFire SoC as its control and processing core. This chip integrates a five-core 64-bit RISC-V processor and a non-volatile FPGA Fabric, possessing single-event upset resistance and hardware-level security mechanisms. To enhance data storage reliability, the system is configured with external memory with ECC functionality: including two 4Gb DDR3 chips, achieving dual protection through the chip's built-in ECC and the SoC MSS DDR interface's ECC configuration; one 1Gb SPI NorFlash and one 1Gb Parallel NorFlash, both with transparent ECC error correction capabilities, used for program storage and high-speed data caching, respectively.

[0021] The core board described in this invention integrates a digital temperature sensor and a voltage monitoring chip for monitoring and protection. This allows for real-time monitoring of the DDR3 operating temperature and SoC power supply voltage, and triggers alarms or resets in case of abnormalities. The clock is provided by a 50MHz active crystal oscillator, and the power module supports a wide input voltage range and provides multiple regulated outputs for each chip. All unused I / O, JTAG, and high-speed SerDes signals are led out through two 400-pin inter-board connectors, employing a dual-point, dual-wire connection method to improve interface reliability.

[0022] The core board described in this invention significantly improves the data integrity and operational stability of the camera main control system under extreme environments such as radiation and temperature changes through multiple protections and status monitoring at the chip level, interface level, and system level. It is suitable for aerospace imaging, military electronics, and other high-reliability embedded application scenarios.

[0023] The core board described in this invention features a core board processor and its configured DDR3, SPI NorFlash, and ParallelNorFlash memory, all equipped with ECC functionality, providing strong resistance to single-event upsets. To monitor the health of the core board, voltage monitoring chips and temperature sensing chips are included. The inter-board connectors of the core board utilize a two-point, two-wire connection for input and output signals, resulting in extremely high reliability for the core board. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the structure of the high-reliability camera main control unit core board based on PolarFire SOC described in this invention. Detailed Implementation

[0026] Combination Figure 1 This embodiment describes a high-reliability camera master control core board based on the PolarFire SOC. Specifically, this core board includes the PolarFire SOC (System-on-a-Chip), which integrates five 64-bit RISC-V processors and a non-volatile FPGA with built-in single-event upset (SEU) protection. All microprocessor subsystem (MSS) memories support SECDED (1-bit error correction, 2-bit error detection). The 20Kb local static random access memory (LSRAM) in the FPGA also includes SECDED functionality.

[0027] The core board uses the PolarFire SOC as its processor core and is equipped with 4Gb of DDR3 memory, 1Gb of serial port NorFlash (SPI NorFlash), and 1Gb of parallel port NorFlash (Parallel NorFlash). All these chips have built-in ECC functionality, automatically performing 1-bit error correction and 2-bit error detection on a certain data width without PolarFire SOC intervention, significantly improving data security and reliability on the core board. Furthermore, it utilizes the ECC configuration function of the MSS DDR interface within the PolarFire SOC, using one DDR3 chip to provide ECC protection for another, further enhancing the core board's reliability. In addition, the core board only requires one relatively wide-range power supply voltage input, with its power supply components providing the corresponding operating voltage to all chips on the board, making it simple and convenient. To ensure stable processor operation, the PolarFire SOC is equipped with a 50MHz active crystal oscillator. To monitor the core board's health, a voltage monitoring device and a temperature sensor are included. In addition, to facilitate future expansion, the remaining I / O pins of the PolarFire SOC are output through two inter-board connectors, with each pin using a dual-point, dual-wire configuration for high reliability.

[0028] The core board described in this embodiment has the following specific structural composition:

[0029] The PolarFire SOC, serving as the core board's processor, connects to DDR3 memory, Parallel NorFlash, and SpinorFlash. For normal operation, the processor's clock source input interface is connected to an active crystal oscillator. To ensure the processor operates at its normal voltage, a voltage monitoring chip monitors the processor's power supply voltage; when the voltage falls below the operating threshold, the processor resets. The PolarFire SOC processor has an internal temperature sensor that can directly read its core temperature. To monitor the DDR3 operating temperature, a temperature sensor is placed on the back of one of the DDR3 chips, connected via I / O. 2 The Type-C interface connects to the processor. The onboard power supply unit converts the power input from the inter-board connectors to the various power voltages required by the core board, meeting the operational needs of all components. Additionally, the core board connects unused I / O ports from the processor to two inter-board connectors for easy future expansion.

[0030] In this embodiment, the MSS DDR dedicated interface on the PolarFire SOC connects two 256M×16bit DDR3 chips, configured in a 16-bit data + 4-bit ECC mode. After double-word combination, it can automatically achieve 1-bit error correction and 2-bit error detection for every 32 bits of data. Additionally, this DDR3 chip has built-in capability of 1-bit error correction and 2-bit error detection for every 4 bits of data, and its ECC function is transparent to the user host, requiring no additional operation. However, the DDR3's ECC-related registers can be accessed through the I / O pins on the DDR3 chip. 2 Accessing via the C interface requires I... 2 The C interface connects to the general-purpose I / O of the MSS DDR dedicated BANK area;

[0031] In this embodiment, two DDR3 chips are connected to the MSS DDR dedicated bank area on the PolarFire SOC. These DDR3 chips have a data capacity of 4Gb, a data width of 16bit, and built-in ECC (1-bit error correction, 2-bit error detection) functionality, providing independent error correction for each 4-bit half-byte. Therefore, in a 16-bit data width scenario, up to four single-bit errors can be corrected simultaneously. The MSS DDR interface on the PolarFire SOC can be configured in ECC mode, with one DDR3 chip configured as a normal DDR3 data storage area and the other as an ECC storage area. When the PolarFire SOC performs DDR3 data read / write operations, the MSSDDR interface automatically performs ECC operations, achieving 1-bit error correction and 2-bit error detection for every 32 bits of data. Thus, utilizing the built-in ECC function of the DDR3 chips and the ECC function configured in the MSS DDR, 1-bit error correction and 2-bit error detection can be achieved for every 4 bits of data. Furthermore, 1-bit error correction and 2-bit error detection are performed again for every 32 bits of data. This reduces the impact of single-event upsets and greatly improves data security and reliability.

[0032] In this embodiment, the PolarFire SOC's SPI0 interface is connected to a 1Gb SPI NorFlash chip. Besides the standard SPI interface, this SPI NorFlash chip can also be configured as an eight-channel SPI (Octal SPI) or double-transfer-rate eight-channel SPI (DTR Octal SPI) interface. Therefore, the chip's standard SPI interface is connected to the PolarFire SOC's SPI0 interface, while the other multiplexed SPI interfaces are still connected to the PolarFire SOC's I / O ports. This allows the PolarFire SOC to interact with the chip through multiple interfaces. The PolarFire SOC uses the standard SPI interface for data interaction by default. The PolarFire SOC can also switch to Octal SPI or DTR Octal SPI interfaces for data interaction. This SPI NorFlash chip is mainly used to store the PolarFire SOC's program code and on-orbit re-injection program upgrade code; the remaining memory area can also be used to store related parameters, etc. This chip has built-in ECC functionality, which can automatically perform 1-bit error correction and 2-bit error detection for every 64 bits of data. It has high reliability and is suitable for standalone camera controllers.

[0033] In this embodiment, the PolarFire SOC's BANK7 I / O is connected to a 1Gb (64M×16bit) Parallel NorFlash chip. This chip has built-in ECC functionality, automatically generating ECC checksums for every 256 bits (32 bytes) of data and storing them in a user-invisible storage area. This process is transparent to the user's host. Therefore, this parallel port flash memory chip can automatically perform 1-bit error correction and 2-bit error detection for every 256 bits (32 bytes) of data. This chip is used to store data such as elevation data, meeting the requirements of high data read / write speeds.

[0034] In this embodiment, the I of PolarFire SOC 2 The C0 interface connects to a digital temperature sensor chip. This chip is located on the back of the DDR3 chip used for normal data storage and is used to monitor the operating temperature of the DDR3 chip, with a measurement accuracy of ±0.1℃. It issues an alarm when the DDR3 chip's operating temperature exceeds a set threshold, and ensures chip safety by reducing the DDR3 chip's operating frequency or stopping its operation.

[0035] In this embodiment, a 50MHz active crystal oscillator is connected to a global clock (CCC) pin of the PolarFire SOC to serve as the clock source for the processor.

[0036] In this embodiment, the DEVRST_N (device reset) pin of the PolarFire SOC is connected to a voltage monitoring chip. This chip monitors the 3.3V supply voltage of the PolarFire SOC, and resets the processor to restart operation when the voltage falls below the operating threshold. Additionally, the processor has an internal voltage sensor for monitoring and acquiring operating voltages other than 3.3V. The processor telemetry-based upload of these voltage data is used for real-time voltage monitoring.

[0037] In this embodiment, the JTAG-related pins on BANK3 of the PolarFire SOC are brought out via dual in-line sockets for simulation debugging. Furthermore, the JTAG-related pins are connected to inter-board connector 1 for easy future expansion.

[0038] In this embodiment, the power supply component on the core board converts the 4V~14V DC power input from the inter-board connector 1 into the 0.75V, 1.0V, 1.5V, 1.8V, 2.5V, and 3.3V power supplies required by the core board, powering all other chips on the board. For convenient future expansion, the 1.8V and 3.3V power supplies are also output through the inter-board connector 2.

[0039] In this embodiment, to facilitate future expansion, the core board is equipped with two 4×100 pin inter-board connectors, mainly connecting power input and output, unused I / O pins on the PolarFire SOC processor, SerDes pins, JTAG pins, DEVRST_N pins, etc. These connectors offer a transmission rate of up to 64Gbps, fully meeting the requirements for high-speed signal transmission. To ensure reliable signal transmission, all power and signal connections use dual-point, dual-wire connections.

[0040] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0041] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A high-reliability camera main control unit core board based on PolarFire SOC, characterized by: The core board uses PolarFire SOC as the processor, which integrates a RISC-V processor and a non-volatile FPGA, and has built-in anti-single-event upset characteristics. The PolarFire SOC's SPI0 interface is connected to SPI NorFlash, and the PolarFire SOC's BANK7 I / O is connected to Parallel NorFlash. Both the SPI NorFlash and Parallel NorFlash have built-in ECC error correction functionality. The PolarFire SOC has a dedicated MSS DDR interface that connects two DDR3 chips. PolarFire SOC's I 2 The C0 interface connects to a temperature sensor, which is located on the back of the DDR3 chip used for normal data storage and is used to monitor the operating temperature of the DDR3 chip.

2. The high-reliability camera main control core board based on PolarFire SOC according to claim 1, characterized in that: The SPI NorFlash has a data capacity of 1Gb and can automatically perform 1-bit error correction and 2-bit error detection for every 64 bits of data. It also has Octal SPI and DTR Octal SPI interfaces. Connect the SPI0 interface of the PolarFire SOC to the standard SPI interface of the SPI NorFlash, and connect the other interfaces to the I / O ports of the PolarFire SOC. The PolarFire SOC uses the standard SPI interface to interact with the SPI NorFlash by default, but the PolarFire SOC can switch to Octal SPI or DTR Octal SPI interface to interact with the SPI NorFlash.

3. The high-reliability camera main control core board based on PolarFire SOC according to claim 1, characterized in that: The Parallel NorFlash has a data capacity of 1Gb and connects to the PolarFireSOC via a standard 16-bit parallel interface. The Parallel NorFlash can automatically generate ECC checksums for every 256 bits of data and store them in a user-invisible storage area of ​​the Parallel NorFlash, automatically performing 1-bit error correction and 2-bit error detection for every 256 bits of data.

4. The high-reliability camera main control core board based on PolarFire SOC according to claim 1, characterized in that: The two DDR3 chips are connected to the BANK area of ​​the MSS DDR dedicated interface on the PolarFire SOC. Each DDR3 chip has a data capacity of 4Gb and a data bit width of 16bit. The chip also has built-in ECC function, which has an automatic error correction function for each 4-bit half-byte. The MSS DDR interface on the PolarFire SOC is configured in ECC mode. One DDR3 chip is configured as a normal DDR3 data storage area, while the other DDR3 chip is configured as an ECC storage area. When the PolarFire SOC performs DDR3 data read and write operations, the dedicated MSSDDR interface automatically performs ECC operations, achieving 1-bit error correction and 2-bit error detection for every 32 bits of data. Utilizing the ECC function built into the DDR3 chip and the ECC function configured in the MSS DDR, 1-bit error correction and 2-bit error detection are achieved for every 4 bits of data. On this basis, 1-bit error correction and 2-bit error detection are performed again for every 32 bits of data.

5. The high-reliability camera main control core board based on PolarFire SOC according to claim 1, characterized in that: A 50MHz active crystal oscillator is connected to the global clock pin of the PolarFire SOC to serve as the clock source for the processor.

6. The high-reliability camera main control core board based on PolarFire SOC according to claim 1, characterized in that: The DEVRST_N pin of the PolarFire SOC is connected to a voltage monitoring chip, which monitors the 3.3V supply voltage of the PolarFire SOC. When the voltage is lower than the operating threshold, the processor is reset and restarted. At the same time, the processor has a built-in voltage sensor to monitor and collect operating voltages other than 3.3V. The processor performs telemetry and uploads the relevant voltages for real-time voltage monitoring.

7. The high-reliability camera main control core board based on PolarFire SOC according to claim 1, characterized in that: The core board is equipped with two 4×100 pin inter-board connectors for connecting power input and output, unused I / O pins on the PolarFire SOC processor, SerDes pins, JTAG pins, and DEVRST_N pins.

8. The high-reliability camera main control core board based on PolarFire SOC according to claim 7, characterized in that: The JTAG-related pins of the PolarFire SOC are brought out through dual in-line sockets for simulation debugging; and the JTAG-related pins are connected to the first inter-board connector for easy expansion in the future.

9. A high-reliability camera main control core board based on PolarFire SOC according to claim 8, characterized in that: The power supply component on the core board converts the 4V~14V DC power input from the first inter-board connector into the 0.75V, 1.0V, 1.5V, 1.8V, 2.5V and 3.3V power required by the core board, to power all other chips on the core board; for easy future expansion, the 1.8V and 3.3V power supplies are output through the second inter-board connector.

10. A high-reliability camera main control core board based on PolarFire SOC according to claim 9, characterized in that: The transmission rates of both the first and second board-to-board connectors can reach 64Gbps; all power and signal transmissions use dual-point dual-wire connections.

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