Topologically protected quantum annealing method, apparatus, storage medium, and electronic device

Abstract

This application discloses a topology-protected quantum annealing method, apparatus, storage medium, and electronic device. The topology-protected quantum annealing method includes: obtaining the optimization problem specification, annealing hardware constraints, and protection parameter configuration; constructing a problem Hamiltonian based on the optimization problem specification, where the ground state of the problem Hamiltonian corresponds to the global optimal solution of the optimization problem; generating a topology-protected symmetric annealing path from the initial Hamiltonian to the problem Hamiltonian based on the problem Hamiltonian, annealing hardware constraints, and protection parameter configuration; synthesizing the protected annealing Hamiltonian of the symmetric annealing path, where the protected annealing Hamiltonian is a function of normalized time and maintains the topology-protected properties of the symmetric annealing path throughout the annealing process; verifying the global convergence of the protected annealing Hamiltonian and outputting the verified global optimal solution. This application can fundamentally solve the sensitivity of annealing dynamics to local minima, providing a theoretical guarantee for global convergence.

Description

Technical Field

[0001] This application relates to the field of quantum annealing technology, specifically to a topology-protected quantum annealing method, apparatus, storage medium, and electronic device. Background Technology

[0002] Quantum annealing is a computational paradigm that utilizes quantum fluctuations to solve combinatorial optimization problems. Its basic principle is to encode the problem to be optimized as the target Hamiltonian of a quantum system. By slowly evolving the initial Hamiltonian to the target Hamiltonian, the system is kept in its instantaneous ground state, ultimately obtaining the optimal solution to the problem in the ground state of the target Hamiltonian. Due to its potential computational advantages, quantum annealing has attracted widespread attention for its applications in combinatorial optimization, machine learning, and financial modeling.

[0003] However, traditional quantum annealing methods face several key technical challenges in practical applications. First, during the annealing process, the system is prone to getting trapped in local minima due to potential barriers in the energy landscape, causing the final solution to deviate from the global optimum. Especially in complex optimization problems, the energy landscape often contains a large number of local minima, and traditional annealing path design cannot guarantee that the system can effectively avoid these traps, thus affecting the quality of the solution. Second, existing annealing methods lack mathematical guarantees for convergence results, and usually can only rely on repeated executions or heuristic strategies to increase the probability of finding the optimal solution, without being able to theoretically prove that the obtained solution has global optimality. In addition, non-adiabatic transition effects further exacerbate the uncertainty of the annealing process, making the system's performance in high-dimensional complex problems difficult to predict and verify.

[0004] To address the aforementioned issues, existing techniques have improved annealing performance by optimizing the annealing scheduling function or modifying the hardware topology, such as by adjusting the annealing time curve or using graph partitioning strategies to reduce problem complexity. However, these methods essentially still fall under the category of parameter optimization or problem preprocessing, failing to fundamentally address the sensitivity of annealing dynamics to local minima and providing no theoretical guarantee for global convergence. Summary of the Invention

[0005] This application provides a topology-protected quantum annealing method, apparatus, storage medium, and electronic device, which can fundamentally solve the sensitivity of annealing dynamics to local minima and provide a theoretical guarantee for global convergence.

[0006] In a first aspect, embodiments of this application provide a topologically protected quantum annealing method, comprising: Obtain the optimization problem specification, annealing hardware constraints, and protection parameter configuration; Based on the aforementioned optimization problem specification, a problem Hamiltonian is constructed, and the ground state of the problem Hamiltonian corresponds to the global optimal solution of the optimization problem. Based on the problem Hamiltonian, annealing hardware constraints, and protection parameter configuration, a symmetric annealing path with topology protection is generated from the initial Hamiltonian to the problem Hamiltonian. The protective annealing Hamiltonian of the symmetric annealing path is synthesized. The protective annealing Hamiltonian is a function of normalized time and maintains the topology protection characteristics of the symmetric annealing path throughout the annealing process. The protected annealing Hamiltonian is globally converged and verified, and the globally optimal solution that passes the verification is output.

[0007] In the topologically protected quantum annealing method provided in this application embodiment, the optimization problem is characterized as a cost function defined on binary variables; the construction of the problem Hamiltonian based on the optimization problem specification includes: The cost function is mapped to the target Hamiltonian of the quantum system, which is represented by a linear combination of Pauli operators, and its ground state energy corresponds to the minimum value of the cost function. Extract the coefficient parameters from the target Hamiltonian; Based on the annealing hardware constraints, the coefficient parameters are adjusted for compatibility to generate the problem Hamiltonian.

[0008] In the topology-protected quantum annealing method provided in this application embodiment, generating a topology-protected symmetric annealing path from the initial Hamiltonian to the problem Hamiltonian based on the problem Hamiltonian, annealing hardware constraints, and protection parameter configuration includes: Based on the problem Hamiltonian and the protection parameter configuration, the energy landscape of the problem Hamiltonian is mathematically analyzed using Morse theory or homotopy theory to determine a protection symmetry group and a topological invariant. Based on the initial Hamiltonian, the problem Hamiltonian, and the artificial protection terms that enforce the protection of the symmetry group, a family of Hamiltonians is formed according to the path function; Based on the topological invariants and the annealing hardware constraints, a set of path functions is constructed such that the trajectory of the Hamiltonian family in the parameter space surrounds the region corresponding to the local minimum of the problem Hamiltonian with the topological invariants. The symmetric annealing path is generated based on the path function.

[0009] In the topology-protected quantum annealing method provided in this application embodiment, the step of generating a symmetric annealing path based on the path function includes: Numerical simulations are performed on the path function to verify whether the bandgap along the Hamiltonian family is greater than a preset threshold. After successful verification, the symmetric annealing path is generated based on the path function.

[0010] In the topologically protected quantum annealing method provided in this application embodiment, the synthesis of the protected annealing Hamiltonian of the symmetric annealing path includes: Based on the path function constructed in the symmetric annealing path, determine the expression for the protected annealing Hamiltonian at each time step; According to the expression, the protective annealing Hamiltonian is decomposed into a combination of intrinsic gate sets or interaction terms allowed by the annealing hardware constraints. Based on the combination of the intrinsic gate set or interaction terms, the path function is converted into an analog control pulse or digital gate sequence that matches the annealing hardware constraints, thereby generating the hardware control sequence corresponding to the protected annealing Hamiltonian.

[0011] In the topologically protected quantum annealing method provided in this application embodiment, the step of performing global convergence verification on the protected annealed Hamiltonian and outputting the verified global optimal solution includes: A mathematical analysis of the symmetric annealing path yields a convergence theorem; Obtain the numerical verification report output when performing numerical simulation on the path function; Cross-validate the convergence theorem and the numerical certification report to confirm whether the hardware control sequence satisfies all the preconditions of the convergence theorem; If so, a convergence proof certificate is generated, and the hardware control sequence is packaged with the convergence proof certificate as the verified global optimal solution.

[0012] In the topologically protected quantum annealing method provided in this application embodiment, the convergence proof certificate includes at least the protected symmetry group, the topological invariant, the hash value of the problem Hamiltonian, and the lower bound of the success probability.

[0013] Secondly, embodiments of this application provide a topology-protected quantum annealing device, comprising: The acquisition unit is used to acquire the optimization problem specification, annealing hardware constraints, and protection parameter configurations. The construction unit is used to construct the problem Hamiltonian based on the specification of the optimization problem, wherein the ground state of the problem Hamiltonian corresponds to the global optimal solution of the optimization problem; The generation unit is used to generate a symmetric annealing path from the initial Hamiltonian to the problem Hamiltonian, with topology protection, based on the problem Hamiltonian, annealing hardware constraints, and protection parameter configuration. A synthesis unit is used to synthesize the protection annealing Hamiltonian of the symmetric annealing path, wherein the protection annealing Hamiltonian is a function of normalized time and maintains the topology protection characteristics of the symmetric annealing path throughout the annealing process. The verification unit is used to perform global convergence verification on the protected annealing Hamiltonian and output the globally optimal solution that has passed the verification.

[0014] Thirdly, this application provides a storage medium storing a plurality of instructions adapted for loading by a processor to execute the topology-protected quantum annealing method described in any of the preceding claims.

[0015] Fourthly, this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the topology-protected quantum annealing method described in any of the preceding claims.

[0016] In summary, the topology-protected quantum annealing method provided in this application includes: obtaining the optimization problem specification, annealing hardware constraints, and protection parameter configuration; constructing a problem Hamiltonian based on the optimization problem specification, wherein the ground state of the problem Hamiltonian corresponds to the global optimal solution of the optimization problem; generating a symmetric annealing path from the initial Hamiltonian to the problem Hamiltonian with topology protection based on the problem Hamiltonian, annealing hardware constraints, and protection parameter configuration; synthesizing the protected annealing Hamiltonian of the symmetric annealing path, wherein the protected annealing Hamiltonian is a function of normalized time and maintains the topology-protected characteristics of the symmetric annealing path throughout the annealing process; performing global convergence verification on the protected annealing Hamiltonian and outputting the verified global optimal solution. This application embodiment can fundamentally solve the sensitivity of annealing dynamics to local minima, providing a theoretical guarantee for global convergence. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram illustrating an application scenario of the topology-protected quantum annealing method provided in the embodiments of this application.

[0019] Figure 2 This is a schematic flowchart of the topology-protected quantum annealing method provided in the embodiments of this application.

[0020] Figure 3 This is a schematic diagram of the topology-protected quantum annealing device provided in the embodiments of this application.

[0021] Figure 4 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0022] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0023] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0024] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0025] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0026] In the description of this application, it should be noted that the terms "upper," "lower," "left," "right," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, terms such as "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0027] Traditional quantum annealing methods face several key technical challenges in practical applications. First, during the annealing process, the system is prone to getting trapped in local minima due to potential barriers in the energy landscape, causing the final solution to deviate from the global optimum. This is particularly true in complex optimization problems where the energy landscape often contains numerous local minima, and traditional annealing path design cannot guarantee that the system can effectively avoid these traps, thus affecting the quality of the solution. Second, existing annealing methods lack mathematical guarantees for convergence results, typically relying on repeated executions or heuristic strategies to increase the probability of finding the optimal solution, without theoretically proving that the obtained solution possesses global optimality. Furthermore, non-adiabatic transition effects further exacerbate the uncertainty of the annealing process, making the system's performance in high-dimensional complex problems difficult to predict and verify.

[0028] To address the aforementioned issues, existing techniques have improved annealing performance by optimizing the annealing scheduling function or modifying the hardware topology, such as by adjusting the annealing time curve or using graph partitioning strategies to reduce problem complexity. However, these methods essentially still fall under the category of parameter optimization or problem preprocessing, failing to fundamentally address the sensitivity of annealing dynamics to local minima and providing no theoretical guarantee for global convergence.

[0029] Based on this, embodiments of this application provide a topology-protected quantum annealing method, apparatus, storage medium, and electronic device. Specifically, the topology-protected quantum annealing apparatus can be integrated into an electronic device, which can be a server or a terminal, etc. The terminal can include mobile phones, wearable smart devices, tablets, laptops, and personal computers (PCs), etc., as well as other computer and auxiliary devices. The server can be a single server or a server cluster composed of multiple servers, and can be a physical server or a virtual server.

[0030] For example, such as Figure 1 As shown, the electronic device can acquire the optimization problem specification, annealing hardware constraints, and protection parameter configuration; construct the problem Hamiltonian based on the optimization problem specification, where the ground state of the problem Hamiltonian corresponds to the global optimal solution of the optimization problem; generate a symmetric annealing path from the initial Hamiltonian to the problem Hamiltonian with topology protection based on the problem Hamiltonian, annealing hardware constraints, and protection parameter configuration; synthesize the protected annealing Hamiltonian of the symmetric annealing path, where the protected annealing Hamiltonian is a function of normalized time and maintains the topology protection characteristics of the symmetric annealing path throughout the annealing process; perform global convergence verification on the protected annealing Hamiltonian and output the verified global optimal solution.

[0031] The technical solutions shown in this application will be described in detail below through specific embodiments. It should be noted that the order of description of the following embodiments is not intended to limit the priority of the embodiments.

[0032] Please see Figure 2 , Figure 2 This is a schematic flowchart of the topology-protected quantum annealing method provided in an embodiment of this application. The specific flow of the topology-protected quantum annealing method is as follows: 101. Obtain the optimization problem specification, annealing hardware constraints, and protection parameter configuration.

[0033] In this context, the optimization problem is defined as a cost function on binary variables. For example, in combinatorial optimization problems, the cost function is typically expressed as... ,in And each variable The goal of the solution is to find... The configuration with the smallest value .

[0034] Annealing hardware constraints refer to the physical limitations of the target quantum annealing hardware. These limitations include at least the intrinsic Hamiltonian form, i.e., the types of qubit interactions that the hardware can natively implement (e.g., based on the Pauli operator σ). x σ y σ z (interaction); control parameter range, i.e., the minimum and maximum allowable values ​​of adjustable parameters (such as magnetic flux, coupling strength, etc.) during annealing; quantum bit coherence time T coh The maximum time the system can maintain quantum coherence, which determines the upper limit of the total annealing time; and the qubit connectivity graph, which is the physical connection topology between qubits (e.g., Chimera graph, Pegasus graph, etc.).

[0035] Protection parameter configuration refers to user-defined or system-defined hyperparameters used to control the characteristics of topology protection. Topology protection hyperparameters include at least: protection strength, denoted by λ, used to scale the contribution of artificial protection terms to the total Hamiltonian; and protection symmetry group, denoted by G, used to specify the discrete or continuous symmetry that needs to be enforced during annealing, such as a binary symmetry group. or continuous symmetric group ; and the path complexity parameter, denoted by the symbol K, is used to control the topological complexity of the designed path in the parameter space, such as the number of non-shrinkable loops or the number of turns.

[0036] 102. Construct the problem Hamiltonian based on the optimization problem specification. The ground state of the problem Hamiltonian corresponds to the global optimal solution of the optimization problem.

[0037] This embodiment transforms an abstract optimization problem into a Hamiltonian form that can be handled by a quantum system. Specifically, it can be done as follows: First, the cost function is mapped to the target Hamiltonian of the quantum system. The target Hamiltonian is represented by a linear combination of Pauli operators, and its ground-state energy corresponds to the minimum of the cost function.

[0038] For example, for the Ising model, the objective Hamiltonian can be expressed as: .

[0039] in, It is the Pauli Z operator acting on the i-th qubit, with coefficient h. i and J ij From the cost function Extracted from.

[0040] Secondly, the coefficient parameters in the target Hamiltonian are extracted. These coefficient parameters are h in the above formula. i and J ij The specific value.

[0041] Finally, based on the annealing hardware constraints, the coefficient parameters are adjusted for compatibility to generate the problem Hamiltonian.

[0042] Specifically, the coefficient parameters can be adjusted according to the annealing hardware constraints to ensure that the adjusted coefficient parameters meet the range and accuracy requirements of the annealing hardware constraints, and the problem Hamiltonian H can be generated based on the adjusted coefficient parameters. P For example, if hardware constraints specify the coupling strength J ij Must be in [ If the original coefficients are within the range of 1,1, then they need to be scaled or truncated to generate physically realizable problem Hamiltonians.

[0043] 103. Based on the problem Hamiltonian, annealing hardware constraints, and protection parameter configuration, generate a symmetric annealing path from the initial Hamiltonian to the problem Hamiltonian, with topology protection.

[0044] In this embodiment, by designing paths with specific topological properties in the parameter space, the system can be prevented from getting trapped in local minima from a mechanistic perspective. Specifically, this can be done as follows: First, based on the problem Hamiltonian H P And the energy landscape of the problem Hamiltonian is mathematically analyzed using Morse theory or homotopy theory to determine a protection symmetry group and protection parameter configuration. And a topological invariant.

[0045] Morse theory is used to analyze the topological properties of critical points (such as local minima) in energy landscapes; homotopy theory can be used to study the equivalence classes of continuous deformations of paths. Using these two mathematical tools, it can be proven that any path in the protected symmetry group... And it has specific topological invariants (e.g., the number of turns in a certain parametric subspace). The adiabatic path will inevitably lead the system to the problem of Hamiltonian H. P The global ground state cannot enter the local minimum region belonging to different symmetry sectors.

[0046] Then, based on the initial Hamiltonian H I Problem: Hamiltonian H P and the enforcement of protected symmetric groups Artificial protection items These can be grouped into a family of Hamiltonians based on their path functions. The Hamiltonians of the annealing process can be parameterized as follows:

[0047] in, , , It is the path function to be designed; It is the protection strength; s=t / T (t is the actual time, T is the total annealing time), is the normalized time, and its value range is [0,1]. For example, if you want to enforce the symmetry of U(1), you can introduce, for example Items.

[0048] Then, based on topological invariants and annealing hardware constraints, a set of path functions is constructed. This makes the Hamiltonian family The trajectory in parameter space surrounds the problem Hamiltonian H with topological invariants. P The region corresponding to the local minimum point.

[0049] Specifically, the design of the path function needs to satisfy the following conditions: when s=0, A(0)=1, B(0)=0, C k (0)=0, so that H(0)=H I When s=1, A(1)=0, B(1)=1, C k (1) = 0, so that H(1) = H P ; Throughout the process, control vector The path (s) = (A(s), B(s), C1(s), ...)g always remains within the manifold defined by the protective symmetry group G, and in the parameter space, it circles the region corresponding to the known local minimum with a predetermined number of turns. This design prevents the path from continuously shrinking to a single point in a topological sense, thus preventing the system from entering the symmetry sector where the local minimum is located during its evolution.

[0050] Finally, a symmetric annealing path is generated based on the path function. Specifically, numerical simulations can be performed on the path function to verify the bandgap Δ(s) = E1(s) along the Hamiltonian family. Whether E0(s) (the difference between the energy of the first excited state and the energy of the ground state) is greater than a preset threshold; a sufficiently large bandgap is key to satisfying the adiabatic conditions and avoiding non-adiabatic transitions. After successful verification, a symmetric annealing path is generated based on the path function, and a numerical verification report is output.

[0051] 104. Synthesize the protective annealing Hamiltonian of the symmetric annealing path. The protective annealing Hamiltonian is a function of normalized time and maintains the topology protection property of the symmetric annealing path throughout the annealing process.

[0052] It is understood that this embodiment can transform the path of an abstract design into a concrete form that can be executed on physical hardware. Specifically, it can be as follows: First, based on the path function constructed in the symmetric annealing path, determine the expression for the protected annealing Hamiltonian at each time step.

[0053] That is, any normalized time s, according to the time determined in step 103 Substitute into the formula We obtain the expression for the protected annealing Hamiltonian at that moment.

[0054] Then, based on the expression, the protective annealing Hamiltonian is decomposed into a combination of eigengate sets or interaction terms allowed by the annealing hardware constraints. For example, a complex U(1) protective term H Prot It may need to be decomposed into σ that the target hardware can natively support. x σ y σ z A linear combination of interactions.

[0055] Finally, based on the combination of intrinsic gate sets or interaction terms, the path function is converted into an analog control pulse or digital gate sequence that matches the annealing hardware constraints, generating the hardware control sequence corresponding to the protected annealing Hamiltonian.

[0056] Understandably, this means incorporating time-related coefficients. This is converted into specific analog waveforms (such as magnetic flux modulation signals) or digital logic instructions to ensure that at every moment during the annealing process, the effective Hamiltonian actually generated by the hardware precisely matches the designed H(s).

[0057] 105. Perform global convergence verification on the protected annealing Hamiltonian and output the verified global optimal solution.

[0058] Specifically, a mathematical analysis of the symmetric annealing path can be performed to obtain a convergence theorem. This convergence theorem, based on Morse theory or homotopy theory applied in step 103, provides a rigorous mathematical proof that the evolution result will inevitably converge to the global ground state under certain symmetry and topological invariant conditions.

[0059] Secondly, obtain the numerical verification report output during the numerical simulation of the path function. This report records the simulation results of key indicators such as bandgap variation along the path and final ground state fidelity.

[0060] Then, the convergence theorem and numerical verification report are cross-validated to confirm whether the hardware control sequence satisfies all the preconditions of the convergence theorem. For example, it is necessary to confirm the minimum bandgap (min) of the numerical simulation. s Δ(s) is large enough to satisfy the adiabatic conditions under the selected total annealing time T.

[0061] If so, a convergence proof certificate is generated. This convergence proof certificate may at least include the protection of the symmetric group, topological invariants, hash values ​​of the problem Hamiltonian (used to uniquely identify the problem instance being solved), and a lower bound on the probability of success (e.g., greater than 99%).

[0062] Finally, the hardware control sequence and convergence proof certificate are packaged together as the verified globally optimal solution. It is understandable that this step outputs not only a candidate solution, but also a verifiable mathematical proof of its global optimality, achieving a leap from "heuristic solution" to "verifiable solution."

[0063] To more clearly illustrate the practical application of the embodiments of this application, a specific embodiment is provided below.

[0064] Application scenario: Solving the maximum cut problem.

[0065] The maximum cut problem is a classic combinatorial optimization problem. The goal is to partition an undirected graph G=(V,E) into two sets of vertices V such that the sum of the weights of the edges connecting the two sets is maximized. This problem can be mapped to the ground state search problem of the Ising model.

[0066] First, proceed to step 101. The maximum cut problem instance input by the user is defined as the optimization problem specification in the binary variable z.i =±1 (indicating which set the vertex belongs to). Simultaneously, obtain the constraint parameters of the target quantum annealing hardware, such as the quantum annealer from D-Wave, whose intrinsic Hamiltonian form is the Ising model, and whose coupling strength J... ij The range is [ [1,1], the qubit connection diagram is a Pegasus topology. The user sets the protection parameters, selects the protection symmetry group as Z2 (corresponding to global flip symmetry), and the protection strength λ=0.5.

[0067] Next, proceed to step 102. Map the cost function of the maximum cut problem to the objective Hamiltonian and extract the coefficients J. ij (The weights of the corresponding edges). Since the original weights may exceed the hardware's limits... The coefficients within the range of 1,1 are normalized and adjusted to generate a hardware-executable problem Hamiltonian H. P .

[0068] Next, proceed to step 103. Analyze H using homotopy theory. P The energy landscape, determining the topological invariants that must be preserved under Z2 symmetry (e.g., number of turns). =1). Then construct path functions A(s), B(s), and C(s) such that the family of Hamiltonians surrounds a known local minimum region in the parameter space. H Prot To enforce the protection term for Z2 symmetry, numerical simulations were used to verify that the bandgap along the path is always greater than 0.1 (a preset threshold), ensuring the adiabatic performance of the annealing process. After the simulation passed, a symmetrical annealing path was generated.

[0069] Then, proceed to step 104. Based on the path function, determine the Hamiltonian expression for each time step s. Decompose H(s) into intrinsic interaction terms supported by D-Wave hardware. Convert the path function into a specific flux bias control pulse sequence to generate the hardware control sequence.

[0070] Finally, step 105 is executed. The mathematically proven convergence theorem is cross-validated with the numerical verification report output in step 103 to confirm that the control sequence satisfies all preconditions. A convergence proof certificate is generated, including Z2 symmetry and the number of turns. =1. The hash value of the problem's Hamiltonian and a 99% success probability lower bound. Package the hardware control sequence with the certificate and output the verified globally optimal solution. After executing this control sequence on the D-Wave hardware, the measured bit configuration is the globally optimal solution to the maximum cut problem, and its optimality is mathematically proven.

[0071] In summary, the topology-protected quantum annealing method provided in this application includes obtaining the optimization problem specification, annealing hardware constraints, and protection parameter configuration; constructing a problem Hamiltonian based on the optimization problem specification, where the ground state of the problem Hamiltonian corresponds to the global optimal solution of the optimization problem; generating a symmetric annealing path from the initial Hamiltonian to the problem Hamiltonian based on the problem Hamiltonian, annealing hardware constraints, and protection parameter configuration, and possessing topology protection; synthesizing the protected annealing Hamiltonian of the symmetric annealing path, where the protected annealing Hamiltonian is a function of normalized time and maintains the topology protection characteristics of the symmetric annealing path throughout the annealing process; verifying the global convergence of the protected annealing Hamiltonian and outputting the verified global optimal solution. This application actively introduces a topology protection mechanism during the annealing process, mathematically guaranteeing global convergence and overcoming the shortcomings of traditional quantum annealing methods that easily get trapped in local minima and lack theoretical guarantees, providing a reliable and verifiable solution for quantum optimization computation. In other words, this application can fundamentally solve the sensitivity of annealing dynamics to local minima, providing a theoretical guarantee for global convergence.

[0072] To facilitate better implementation of the topology-protected quantum annealing method provided in this application, this application also provides a topology-protected quantum annealing apparatus. The meanings of the terms used are the same as in the above-described topology-protected quantum annealing method, and specific implementation details can be found in the descriptions within the method embodiments.

[0073] Please see Figure 3 , Figure 3 This is a schematic diagram of the topology-protected quantum annealing device provided in an embodiment of this application. The topology-protected quantum annealing device may include an acquisition unit 201, a construction unit 202, a generation unit 203, a synthesis unit 204, and a verification unit 205. Acquisition unit 201 is used to acquire the optimization problem specification, annealing hardware constraints, and protection parameter configuration; Construction unit 202 is used to construct the problem Hamiltonian based on the optimization problem specification. The ground state of the problem Hamiltonian corresponds to the global optimal solution of the optimization problem. The generation unit 203 is used to generate a symmetric annealing path from the initial Hamiltonian to the problem Hamiltonian, with topology protection, based on the problem Hamiltonian, annealing hardware constraints, and protection parameter configuration. Synthesis unit 204 is used to synthesize the protection annealing Hamiltonian of the symmetric annealing path. The protection annealing Hamiltonian is a function of normalized time and maintains the topology protection characteristics of the symmetric annealing path throughout the annealing process. Verification unit 205 is used to perform global convergence verification on the protected annealed Hamiltonian and output the globally optimal solution that has passed the verification.

[0074] For specific implementation methods of each of the above units, please refer to the embodiments of the topologically protected quantum annealing method described above, which will not be repeated here.

[0075] In summary, the topology-protected quantum annealing apparatus provided in this application can acquire the optimization problem specification, annealing hardware constraints, and protection parameter configuration through the acquisition unit 201; the construction unit 202 constructs the problem Hamiltonian based on the optimization problem specification, where the ground state of the problem Hamiltonian corresponds to the global optimal solution of the optimization problem; the generation unit 203 generates a symmetric annealing path from the initial Hamiltonian to the problem Hamiltonian, which has topology protection, based on the problem Hamiltonian, annealing hardware constraints, and protection parameter configuration; the synthesis unit 204 synthesizes the protected annealed Hamiltonian of the symmetric annealing path, where the protected annealed Hamiltonian is a function of normalized time and maintains the topology protection characteristics of the symmetric annealing path throughout the annealing process; and the verification unit 205 performs global convergence verification on the protected annealed Hamiltonian and outputs the verified global optimal solution. This application actively introduces a topology protection mechanism during the annealing process, mathematically guaranteeing global convergence and overcoming the shortcomings of traditional quantum annealing methods that are prone to getting trapped in local minima and lack theoretical guarantees, thus providing a reliable and verifiable solution for quantum optimization computation. In other words, the embodiments of this application can fundamentally solve the sensitivity of annealing dynamics to local minima, providing a theoretical guarantee for global convergence.

[0076] This application also provides an electronic device that may integrate the topology-protected quantum annealing device of this application, such as... Figure 4 As shown, it illustrates a structural schematic diagram of the electronic device involved in the embodiments of this application, specifically: The electronic device may include components such as a processor 301 with one or more processing cores and a memory 302 with one or more computer-readable storage media. Those skilled in the art will understand that... Figure 4 The electronic device structure shown does not constitute a limitation on the electronic device and may include more or fewer components than shown, or combine certain components, or have different component arrangements. Wherein: The processor 301 is the control center of the electronic device. It connects various parts of the electronic device via various interfaces and lines. By running or executing software programs stored in the memory 302 and / or this application, and by calling data stored in the memory 302, it performs various functions and processes data, thereby providing overall monitoring of the electronic device. Optionally, the processor 301 may include one or more processing cores; preferably, the processor 301 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operation of the storage medium, user interface, and application programs, while the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into the processor 301.

[0077] The memory 302 can be used to store software programs and this application. The processor 301 executes various functional applications and data processing by running the software programs and this application stored in the memory 302. The memory 302 may mainly include a program storage area and a data storage area. The program storage area may store applications required for operating the storage medium and at least one function; the data storage area may store data created based on the use of the electronic device. In addition, the memory 302 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device. Accordingly, the memory 302 may also include a memory controller to provide the processor 301 with access to the memory 302.

[0078] Although not shown, the electronic device may also include a display unit, an input unit, and a power supply, etc., which will not be described in detail here. Specifically, in this embodiment, the processor 301 in the electronic device loads the executable files corresponding to the processes of one or more application programs into the memory 302 according to the following instructions, and the processor 301 runs the application programs stored in the memory 302 to realize various functions, as follows: Obtain the optimization problem specification, annealing hardware constraints, and protection parameter configuration; The problem Hamiltonian is constructed based on the optimization problem specification. The ground state of the problem Hamiltonian corresponds to the global optimal solution of the optimization problem. Based on the problem Hamiltonian, annealing hardware constraints, and protection parameter configuration, a symmetric annealing path with topology protection is generated from the initial Hamiltonian to the problem Hamiltonian. The protective annealing Hamiltonian of the synthesized symmetric annealing path is a function of normalized time and maintains the topological protection property of the symmetric annealing path throughout the annealing process. Perform global convergence verification on the protected annealing Hamiltonian and output the verified global optimal solution.

[0079] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be performed by instructions, or by instructions controlling related hardware. These instructions can be stored in a computer-readable storage medium and loaded and executed by a processor.

[0080] Therefore, embodiments of this application provide a storage medium storing a plurality of instructions that can be loaded by a processor to execute steps in any of the methods provided in embodiments of this application. For example, the instructions can execute the following steps: Obtain the optimization problem specification, annealing hardware constraints, and protection parameter configuration; The problem Hamiltonian is constructed based on the optimization problem specification. The ground state of the problem Hamiltonian corresponds to the global optimal solution of the optimization problem. Based on the problem Hamiltonian, annealing hardware constraints, and protection parameter configuration, a symmetric annealing path with topology protection is generated from the initial Hamiltonian to the problem Hamiltonian. The protective annealing Hamiltonian of the synthesized symmetric annealing path is a function of normalized time and maintains the topological protection property of the symmetric annealing path throughout the annealing process. Perform global convergence verification on the protected annealing Hamiltonian and output the verified global optimal solution.

[0081] For details on the implementation of each of the above operations, please refer to the previous examples, which will not be repeated here.

[0082] The storage medium may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0083] Since the instructions stored in the storage medium can execute the steps of any method provided in the embodiments of this application, the beneficial effects that any method provided in the embodiments of this application can achieve can be realized. For details, please refer to the previous embodiments, which will not be repeated here.

[0084] The foregoing has provided a detailed description of the topology-protected quantum annealing method, apparatus, storage medium, and electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A topologically protected quantum annealing method, characterized in that, include: Obtain the optimization problem specification, annealing hardware constraints, and protection parameter configuration; Based on the aforementioned optimization problem specification, a problem Hamiltonian is constructed, and the ground state of the problem Hamiltonian corresponds to the global optimal solution of the optimization problem. Based on the problem Hamiltonian, annealing hardware constraints, and protection parameter configuration, a symmetric annealing path with topology protection is generated from the initial Hamiltonian to the problem Hamiltonian. The protective annealing Hamiltonian of the symmetric annealing path is synthesized. The protective annealing Hamiltonian is a function of normalized time and maintains the topology protection characteristics of the symmetric annealing path throughout the annealing process. The protected annealing Hamiltonian is globally converged and verified, and the globally optimal solution that passes the verification is output.

2. The topology-protected quantum annealing method as described in claim 1, characterized in that, The optimization problem specification is a cost function defined on binary variables; the construction of the problem Hamiltonian based on the optimization problem specification includes: The cost function is mapped to the target Hamiltonian of the quantum system, which is represented by a linear combination of Pauli operators, and its ground state energy corresponds to the minimum value of the cost function. Extract the coefficient parameters from the target Hamiltonian; Based on the annealing hardware constraints, the coefficient parameters are adjusted for compatibility to generate the problem Hamiltonian.

3. The topology-protected quantum annealing method as described in claim 1, characterized in that, The step of generating a symmetric annealing path with topology protection from the initial Hamiltonian to the problem Hamiltonian, based on the problem Hamiltonian, annealing hardware constraints, and protection parameter configuration, includes: Based on the problem Hamiltonian and the protection parameter configuration, the energy landscape of the problem Hamiltonian is mathematically analyzed using Morse theory or homotopy theory to determine a protection symmetry group and a topological invariant. Based on the initial Hamiltonian, the problem Hamiltonian, and the artificial protection terms that enforce the protection of the symmetry group, a family of Hamiltonians is formed according to the path function; Based on the topological invariants and the annealing hardware constraints, a set of path functions is constructed such that the trajectory of the Hamiltonian family in the parameter space surrounds the region corresponding to the local minimum of the problem Hamiltonian with the topological invariants. The symmetric annealing path is generated based on the path function.

4. The topology-protected quantum annealing method as described in claim 3, characterized in that, The step of generating a symmetric annealing path based on the path function includes: Numerical simulations are performed on the path function to verify whether the bandgap along the Hamiltonian family is greater than a preset threshold. After successful verification, the symmetric annealing path is generated based on the path function.

5. The topology-protected quantum annealing method as described in claim 4, characterized in that, The protected annealing Hamiltonian for synthesizing the symmetrical annealing path includes: Based on the path function constructed in the symmetric annealing path, determine the expression for the protected annealing Hamiltonian at each time step; According to the expression, the protective annealing Hamiltonian is decomposed into a combination of intrinsic gate sets or interaction terms allowed by the annealing hardware constraints. Based on the combination of the intrinsic gate set or interaction terms, the path function is converted into an analog control pulse or digital gate sequence that matches the annealing hardware constraints, thereby generating the hardware control sequence corresponding to the protected annealing Hamiltonian.

6. The topology-protected quantum annealing method as described in claim 5, characterized in that, The step of performing global convergence verification on the protected annealing Hamiltonian and outputting the verified global optimal solution includes: A mathematical analysis of the symmetric annealing path yields a convergence theorem; Obtain the numerical verification report output when performing numerical simulation on the path function; Cross-validate the convergence theorem and the numerical certification report to confirm whether the hardware control sequence satisfies all the preconditions of the convergence theorem; If so, a convergence proof certificate is generated, and the hardware control sequence is packaged with the convergence proof certificate as the verified global optimal solution.

7. The topology-protected quantum annealing method as described in claim 6, characterized in that, The convergence proof certificate includes at least the protected symmetric group, the topological invariant, the hash value of the problem Hamiltonian, and the lower bound of the success probability.

8. A topology-protected quantum annealing device, characterized in that, include: The acquisition unit is used to acquire the optimization problem specification, annealing hardware constraints, and protection parameter configurations. The construction unit is used to construct the problem Hamiltonian based on the specification of the optimization problem, wherein the ground state of the problem Hamiltonian corresponds to the global optimal solution of the optimization problem; The generation unit is used to generate a symmetric annealing path from the initial Hamiltonian to the problem Hamiltonian, with topology protection, based on the problem Hamiltonian, annealing hardware constraints, and protection parameter configuration. A synthesis unit is used to synthesize the protection annealing Hamiltonian of the symmetric annealing path, wherein the protection annealing Hamiltonian is a function of normalized time and maintains the topology protection characteristics of the symmetric annealing path throughout the annealing process. The verification unit is used to perform global convergence verification on the protected annealing Hamiltonian and output the globally optimal solution that has passed the verification.

9. A storage medium, characterized in that, The storage medium stores multiple instructions that are applicable to a processor for loading to execute the topology-protected quantum annealing method according to any one of claims 1-7.

10. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the topology-protected quantum annealing method as described in any one of claims 1-7.

Images