Driving circuit, driving method, and display device

Abstract

A driving circuit, driving method, and display device are disclosed, wherein the scan signal lines of a first region and the scan signal lines of a second region are spaced apart and disconnected; adjacent m-th sub-driving circuits and m+1-th sub-driving circuits are connected through a first transistor, the drain of the first transistor is connected to the m-th row scan signal line of the second region, and the first transistor transmits voltage to the m-th row first data line scan signal line of the second region when it is turned on; adjacent m-th sub-driving circuits and m+1-th sub-driving circuits are connected to a row scan signal line through an AND gate, the output of the AND gate is connected to the m-th row scan signal line of the first region, and the AND gate transmits voltage to the m-th row scan signal line of the first region when it is turned on; each pixel is connected to a row scan signal line and a column data signal line through a second transistor, and the gate of the second transistor is connected to a row scan signal line, thereby reducing the voltage difference between the far-end pixel electrode and the near-end pixel electrode.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to a driving circuit, driving method, and display device. Background Technology

[0002] Currently, in large-size display devices, the electrical signal of the data line sequentially turns on the switches of multiple transistors on the same horizontal line from the near end to the far end, so that the electrical signal of the data line is input to the pixel electrode. However, in the process of the electrical signal of the scan line turning on the transistors from near to far, there is energy loss in the transmission of the electrical signal from the near end to the far end because the electrical signal passes through multiple transistors. This results in the transistors at the near and far ends being turned on at different degrees, which makes the voltage of the far pixel electrode different from that of the near pixel electrode, resulting in a difference between the near and far end images. Summary of the Invention

[0003] The purpose of this invention is to provide a driving circuit, driving method, and display device that improves the problem of large differences between the voltage of the far-end pixel electrode and the voltage of the near-end pixel electrode.

[0004] To achieve the objectives of this invention, the following technical solution is provided: In a first aspect, the present invention provides a driving circuit, the driving circuit including x rows of scan signal lines, multiple columns of data signal lines, a gate row driving circuit, and multiple arrayed pixels. The gate row driving circuit includes x sub-driving circuits corresponding one-to-one with the multiple rows of scan signal lines. Each row of scan signal lines includes a scan signal line disposed in a first region and a scan signal line disposed in a second region. The scan signal lines in the first region and the scan signal lines in the second region are spaced apart and disconnected. The output terminals of adjacent m-th sub-driving circuits and the output terminals of m+1-th sub-driving circuits are connected through a first transistor. The output terminal of the m-th sub-driving circuit is connected to the gate of the first transistor, the output terminal of the m+1-th sub-driving circuit is connected to the source of the first transistor, and the drain of the first transistor is connected to the m-th row of scan signal lines in the second region. The first transistor is used to transmit voltage to the first data line scan signal line in the m-th row of the second region when it is turned on; the output terminals of the adjacent m-th sub-driving circuit and the (m+1)-th sub-driving circuit are connected to a row of scan signal lines through an AND gate, the output terminal of the m-th sub-driving circuit is connected to the first input terminal of the AND gate, the output terminal of the (m+1)-th sub-driving circuit is connected to the second input terminal of the AND gate, the output terminal of the AND gate is connected to the m-th row of scan signal lines in the first region, and the AND gate is used to transmit voltage to the m-th row of scan signal lines in the first region when it is turned on; each pixel is connected to a row of scan signal lines and a column of data signal lines through a second transistor, the gate of the second transistor is connected to a row of scan signal lines, the source of the second transistor is connected to a column of data signal lines, and the drain of the second transistor is connected to the pixel.

[0005] The output terminals of adjacent m-th sub-driving circuits and (m+1)-th sub-driving circuits are connected via a first transistor. The output terminal of the m-th sub-driving circuit is connected to the gate of the first transistor, and the output terminal of the (m+1)-th sub-driving circuit is connected to the source of the first transistor. The drain of the first transistor is connected to the m-th row of the second region's scanning signal line. The first transistor is used to transmit voltage to the m-th row of the second region's scanning signal line when it is turned on. The output terminals of adjacent m-th and (m+1)-th sub-driving circuits are connected to a row of scanning signal lines via an AND gate. The output of the driving circuit is connected to the first input of the AND gate, the output of the (m+1)th sub-driving circuit is connected to the second input of the AND gate, and the output of the AND gate is connected to the m-th row of the scanning signal line in the first region. The AND gate is used to transmit voltage to the m-th row of the scanning signal line in the first region when it is turned on. The AND gate ensures the accuracy of voltage transmission in the first region and is only triggered when both adjacent sub-driving circuits output high-level signals. Furthermore, the m-th sub-driving circuit can precisely control the voltage of the m-th row of data lines through the AND gate and the first transistor, and can simultaneously control the second transistors in the first and second regions. Since the second transistors in the first and second regions are controlled by two adjacent circuits, the number of second transistors passing through the electrical signal transmission of a row of scanning signal lines is reduced, voltage loss is reduced, and the difference between the voltage of the far-end pixel electrode and the near-end pixel electrode is reduced, thus reducing the difference between the far-end and near-end images.

[0006] In one embodiment, the first row of scan signal lines in the x rows is connected to the gate of the second transistor in the first row of the first region, and the first row of scan signal lines is also connected to the gate of the first transistor. The source of the first transistor is connected to the output terminal of the second sub-driving circuit, and the drain of the first transistor is connected to the gate of the second transistor in the first row of the second region. The second transistor is used to transmit voltage to the first row of scan signal lines in the second region when it is turned on.

[0007] By configuring the first row of scan signal lines in the x-row scan signal lines to be connected to the gate of the second transistor in the first row of the first region, and also to the gate of the first transistor, the source of the first transistor is connected to the output of the second sub-driving circuit, and the drain of the first transistor is connected to the gate of the second transistor in the first row of the second region, the second transistor is used to transmit voltage to the first row of scan signal lines in the second region when it is turned on. Through the multi-functional multiplexing design of the first row of scan signal lines, the linkage driving of the first row of pixels in the first and second regions can be achieved without the need for additional dedicated control circuits. The indirect control of the voltage of the first row of pixels in the second region is achieved through the first transistor, which improves the accuracy of the first row of pixel driving and effectively eliminates display defects at the edges of the screen. At the same time, the cross-region linkage control keeps the display timing of the first row of pixels in the two regions consistent, avoiding problems such as screen partition misalignment and stuttering, and improving the overall integrity of the display screen. In addition, the multiplexing circuit reduces the power consumption of the circuit and reduces signal transmission delay, further optimizing the energy efficiency and response performance of the display device.

[0008] In one embodiment, the xth row of the scan signal lines is connected to the gate of the second transistor in the xth row of the second region, and the xth row of the scan signal lines is also connected to the second input terminal of the AND gate. The xth row of the scan signal lines is used to transmit voltage to the gate of the second transistor in the xth row of the second region.

[0009] By employing a dual-function design for the x-th row scan signal line, the direct driving of the last row pixels in the second region and the logic input of the AND gate can be simultaneously achieved without the need for additional control circuits and logic components, further simplifying the circuit structure. As the final part of the display screen, the driving stability of the last row pixels is crucial to the integrity of the image. The direct connection method reduces signal transmission links, lowers the risk of signal attenuation and interference, and ensures clear and stable display of the last row pixels, avoiding problems such as blurring at the bottom of the screen and ghosting. Simultaneously, introducing the last row data line signal into the AND gate logic judgment makes the logic control of the entire driving circuit more coherent, achieving coordinated driving of the last row and adjacent regions, and improving the overall logic consistency and reliability of the circuit.

[0010] In one embodiment, x of the sub-driving circuits, the AND gate, and the first transistor are all disposed at one end of the first region away from the second region.

[0011] By setting x sub-driving circuits, AND gates, and the first transistor at the end of the first region furthest from the second region, the driving control element is physically separated from the pixel array. This effectively avoids electromagnetic interference generated by the sub-driving circuits and AND gates affecting the signal transmission of the pixel array, significantly improving the stability of pixel driving and the quality of the displayed image. The edge layout facilitates component wiring and maintenance, shortens the connection lines between control elements, reduces signal transmission delay and energy loss, and improves circuit response speed and energy efficiency. Simultaneously, the centralized arrangement makes the component arrangement more regular, facilitating automated mounting and soldering during production and improving production efficiency. Furthermore, this layout reserves more space for the pixel arrays in the first and second regions, facilitating optimized pixel density. At the same time, the concentration of the control unit at the edge also provides favorable conditions for the narrow bezel design of the display device.

[0012] In one embodiment, the number of first transistors is x-1, the number of AND gates is x-1, the m-th row of the scan signal lines in the x rows is connected to the output of the (m-1)-th AND gate, the first input of the (m-1)-th AND gate is connected to the gate of the m-th first transistor, the second input of the (m-2)-th AND gate, the output of the m-th sub-driving circuit, and the source of the (m-1)-th first transistor, the second input of the (m-1)-th AND gate is connected to the first input of the m-th AND gate, the gate of the (m+1)-th first transistor, the output of the m-th sub-driving circuit, and the source of the m-th first transistor, and the drain of the m-th first transistor is connected to the gate of the m-th row of the second transistors in the second region, the (m-1)-th AND gate is used to transmit voltage to the m-th row of the scan signal lines when it is turned on, and the m-th first transistor is used to transmit voltage to the gate of the m-th row of the second transistors when it is turned on, where 1 < m < x.

[0013] By using x-1 AND gates and x-1 first transistors, the operating state of x rows of data lines can be precisely controlled, achieving optimized component configuration, avoiding component redundancy, and reducing circuit cost and power consumption. The multi-channel signal access method allows the operating states of each AND gate and first transistor to feedback and coordinate, effectively improving the circuit's logic fault tolerance. Even if a single component experiences slight signal fluctuations, the linkage mechanism can correct them, ensuring the overall driving stability. Simultaneously, this design keeps the driving signals of corresponding rows in the first and second regions highly synchronized, avoiding timing misalignment during partitioned display and improving the continuity and consistency of the image. Furthermore, the compact signal linkage link shortens the signal transmission path, reduces signal attenuation, and improves the circuit's response speed.

[0014] Secondly, embodiments of this application provide a driving method. The driving circuit includes x rows of scan signal lines, multiple columns of data signal lines, a gate row driving circuit, and multiple arrayed pixels. The gate row driving circuit includes x sub-driving circuits corresponding one-to-one with the multiple rows of scan signal lines. Each row of scan signal lines includes a scan signal line disposed in a first region and a scan signal line disposed in a second region. The scan signal lines in the first region and the scan signal lines in the second region are spaced apart and disconnected. The output terminals of adjacent m-th sub-driving circuits and the (m+1)-th sub-driving circuits are connected through a first transistor. The output terminal of the m-th sub-driving circuit is connected to the gate of the first transistor, and the output terminal of the (m+1)-th sub-driving circuit is connected to the source of the first transistor. The method comprises the following connections: the drain of the first transistor is connected to the scan signal line of the m-th row of the second region; the outputs of the adjacent m-th sub-driving circuit and the (m+1)-th sub-driving circuit are connected to a row of scan signal lines via an AND gate; the output of the m-th sub-driving circuit is connected to the first input of the AND gate; the output of the (m+1)-th sub-driving circuit is connected to the second input of the AND gate; the output of the AND gate is connected to the scan signal line of the m-th row of the first region; each pixel is connected to a row of scan signal lines and a column of data signal lines via a second transistor; the gate of the second transistor is connected to a row of scan signal lines; the source of the second transistor is connected to a column of data signal lines; and the drain of the second transistor is connected to the pixel. When the AND gate is turned on, voltage is transmitted to the scan signal line in the m-th row of the first region, and when the first transistor is turned on, voltage is transmitted to the scan signal line in the m-th row of the second region.

[0015] By setting up a first and second region and configuring x sub-driving circuits, with x rows of scanning signal lines, multiple columns of data signal lines, and multiple arrayed pixels in each region, this architecture achieves independent voltage transmission control for the first and second regions through a dual-path control mechanism. The AND gate configuration ensures the accuracy of voltage transmission in the first region, triggering only when both adjacent sub-driving circuits output high-level signals, thus improving the stability of the displayed image. The division of labor between the first transistor and the AND gates ensures that the drive signal transmissions in the two regions do not interfere with each other, allowing adjustment of the drive timing of the two regions according to display requirements and enhancing circuit adaptability. This setup reduces the complexity of circuit wiring, decreases the number of second transistors passing through during the transmission of electrical signals in a single row of scanning signal lines, reduces voltage loss, and minimizes the voltage difference between the far-end and near-end pixel electrodes, thus reducing the difference between the near and far-end images.

[0016] In one embodiment, the first row of scan signal lines in the x rows is connected to the gate of the second transistor in the first row of the first region, and the first row of scan signal lines is also connected to the gate of the first transistor. The source of the first transistor is connected to the output terminal of the second sub-driving circuit, and the drain of the first transistor is connected to the gate of the second transistor in the first row of the second region. The method further includes: When the second transistor is turned on, it transmits voltage to the scan signal line of the first row of the second region.

[0017] By configuring the first row of scan signal lines in the x-row scan signal lines to be connected to the gate of the second transistor in the first row of the first region, and also to the gate of the first transistor, the source of the first transistor is connected to the second sub-driving circuit, and the drain of the first transistor is connected to the gate of the second transistor in the first row of the second region, the second transistor is used to transmit voltage to the first row of scan signal lines in the second region when it is turned on. Through the multi-functional multiplexing design of the first row of scan signal lines, the linkage driving of the first row of pixels in the first and second regions can be achieved without the need for additional dedicated control circuits. The indirect control of the voltage of the first row of pixels in the second region is achieved through the first transistor, which improves the accuracy of the first row of pixel driving and effectively eliminates display defects at the edges of the screen. At the same time, the cross-region linkage control keeps the display timing of the first row of pixels in the two regions consistent, avoiding problems such as screen partition misalignment and stuttering, and improving the overall integrity of the display screen. In addition, the multiplexing circuit reduces the power consumption of the circuit and reduces signal transmission delay, further optimizing the energy efficiency and response performance of the display device.

[0018] In one embodiment, the x-th row of scan signal lines is connected to the gate of the second transistor in the x-th row of the second region, and the x-th row of scan signal lines is also connected to the second input terminal of the AND gate. The method further includes: Voltage is transferred to the gate of the second transistor in the xth row of the second region via the data line in the xth row.

[0019] By employing a dual-function design for the x-th row scan signal line, the direct driving of the last row pixels in the second region and the logic input of the AND gate can be simultaneously achieved without the need for additional control circuits and logic components, further simplifying the circuit structure. As the final part of the display screen, the driving stability of the last row pixels is crucial to the integrity of the image. The direct connection method reduces signal transmission links, lowers the risk of signal attenuation and interference, and ensures clear and stable display of the last row pixels, avoiding problems such as blurring at the bottom of the screen and ghosting. Simultaneously, introducing the last row data line signal into the AND gate logic judgment makes the logic control of the entire driving circuit more coherent, achieving coordinated driving of the last row and adjacent regions, and improving the overall logic consistency and reliability of the circuit.

[0020] In one embodiment, the number of first transistors is x-1, the number of AND gates is x-1, the m-th row scan signal line of the first region is connected to the output of the (m-1)-th AND gate, the first input of the (m-1)-th AND gate is connected to the gate of the m-th first transistor, the second input of the (m-2)-th AND gate, the output of the m-th sub-driving circuit, and the source of the (m-1)-th first transistor, the second input of the (m-1)-th AND gate is connected to the first input of the m-th AND gate, the gate of the (m+1)-th first transistor, the output of the m-th sub-driving circuit, and the source of the m-th first transistor, and the drain of the m-th first transistor is connected to the gate of the second transistor in the m-th row of the second region. The method includes: When the (m-1)th AND gate is turned on, voltage is transmitted to the scan signal line in the m-th row, and when the m-th first transistor is turned on, voltage is transmitted to the gate of the second transistor in the m-th row, 1 < m < x.

[0021] By using x-1 AND gates and x-1 first transistors, the operating state of x rows of data lines can be precisely controlled, achieving optimized component configuration, avoiding component redundancy, and reducing circuit cost and power consumption. The multi-channel signal access method allows the operating states of each AND gate and first transistor to feedback and coordinate, effectively improving the circuit's logic fault tolerance. Even if a single component experiences slight signal fluctuations, the linkage mechanism can correct them, ensuring the overall driving stability. Simultaneously, this design keeps the driving signals of corresponding rows in the first and second regions highly synchronized, avoiding timing misalignment during partitioned display and improving the continuity and consistency of the image. Furthermore, the compact signal linkage link shortens the signal transmission path, reduces signal attenuation, and improves the circuit's response speed.

[0022] Thirdly, according to an embodiment of this application, a display device includes a timing controller and a driving circuit as described in any of the first aspects, wherein the timing controller is connected to the driving circuit and is used to transmit timing signals of the driving circuit to the driving circuit. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram illustrating an application scenario of a driving method according to one embodiment. Figure 2 This is a schematic diagram of the structure of a conventional driving circuit according to one embodiment; Figure 3 This is a schematic diagram of the structure of the driving circuit of this application according to one embodiment; Figure 4 This is a signal diagram of an AND gate according to one embodiment; Figure 5 This is a schematic diagram of the input signal of the driving circuit in one embodiment; Figure 6 This is a flowchart illustrating a driving method of one embodiment; Figure 7 This is a schematic diagram of the sub-driving circuit of one embodiment; Figure 8 This is a schematic diagram of the structure of a display device according to one embodiment.

[0025] Explanation of reference numerals in the attached figures: 101 - User, 102 - Display device, 103 - Server, 201 - Scan signal line, 202 - Data signal line, 203 - Pixel, 204 - Output of the m-th sub-driver circuit, 205 - Output of the (m+1)-th sub-driver circuit, 206 - First region, 207 - Second region, 208 - First transistor, 209 - Second transistor, G(n-1) - Input of the (n-1)-th stage, G(n+1) - Input of the (n+1)-th stage, VDS - First voltage terminal, T1 - First auxiliary transistor, T1A - Second auxiliary transistor, VSD - Second voltage terminal, VGL - Third voltage terminal, Reset Q - Reset terminal, CLKn+3 - (n+3)th level signal terminal, TPE - Touch signal terminal, Gn - Output signal terminal, CLKn - (n)th level signal terminal, T2 - Third auxiliary transistor, T2A - Fourth auxiliary transistor, T3 - Fifth auxiliary transistor, T4 - Sixth auxiliary transistor, T5 - Seventh auxiliary transistor, T6 - Eighth auxiliary transistor, T6A - Ninth auxiliary transistor, T7 - ​​Tenth auxiliary transistor, C1 - First capacitor, C2 - Second capacitor, C3 - Third capacitor, Q - First node, 801 - Timing controller, 802 - Driver circuit, 803 - Processor, 804 - Memory, 805 - Program. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] It should be noted that when a component is said to be "fixed" to another component, it can be directly on the other component or it can be in a middle component. When a component is said to be "connected" to another component, it can be directly connected to the other component or it may be in a middle component.

[0028] Unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used in this invention includes any and all combinations of one or more of the associated listed items.

[0029] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other. Obviously, the described embodiments are merely some, not all, of the embodiments described herein. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0030] The terms “1” and “2”, etc., in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such processes, methods, products, or apparatus.

[0031] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0032] Please see Figure 1 , Figure 1 This is a schematic diagram illustrating an application scenario of a driving method according to an embodiment of this application. For example... Figure 1 As shown in the diagram, this application scenario includes a user 101, a display device 102, and a server 103. It should be noted that the display device 102 includes a display unit that can display video data or image data. Furthermore, Figure 1 The number of devices, the form of each device, and the number of users in the system shown are for illustrative purposes only and do not constitute a limitation of this application. A user 101 can use multiple display devices 102, and a server 103 can be connected to multiple display devices 102. The server 103 transmits data to the display devices 102, and the display devices 102 can display the data on the display device.

[0033] User 101 is the user who actually operates the display device 102 to control it to perform corresponding operations. The display device 102 can be... Figure 1The laptop shown can also be a personal computer (PC), all-in-one computer, handheld computer, tablet computer, desktop computer, smartphone, smart TV playback terminal, and portable device. PC-side display devices, such as all-in-one computers, can have operating systems including, but not limited to, Linux, Unix, and Windows series systems (such as Windows XP, Windows 7, etc.). Mobile-side display devices, such as smartphones, can have operating systems including, but not limited to, Android, iOS (Apple's operating system), and Windows.

[0034] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of an existing driving circuit provided in an embodiment of this application. For example... Figure 2 As shown, the driving circuit includes x rows of scanning signal lines 201, multiple columns of data signal lines 202, a gate row driving circuit, and multiple arrayed pixels 203. The gate row driving circuit includes x sub-driving circuits that are arranged one-to-one with the multiple rows of scanning signal lines 201. Each row of scanning signal lines 201 includes a scanning signal line 201 disposed in a first region 206 and a scanning signal line 201 disposed in a second region 207. The scanning signal lines 201 in the first region 206 and the scanning signal lines 201 in the second region 207 are spaced apart and disconnected. The output terminals 204 and 205 of the adjacent m-th sub-driving circuit are connected through the first transistor 208. The output terminal 204 of the m-th sub-driving circuit is connected to the gate of the first transistor 208, and the output terminal 205 of the (m+1)-th sub-driving circuit is connected to the source of the first transistor 208. The drain of the first transistor 208 is connected to the m-th row scan signal line 201 of the second region 207. The first transistor 208 is used to transmit voltage to the m-th row first data line scan signal line 201 of the second region 207 when it is turned on. The output terminals 204 and 205 of the adjacent m-th sub-driving circuits are connected to a row scan signal line 201 via an AND gate. The output terminal 204 of the m-th sub-driving circuit is connected to the first input terminal of the AND gate, and the output terminal 205 of the (m+1)-th sub-driving circuit is connected to the second input terminal of the AND gate. The output terminal of the AND gate is connected to the m-th row scan signal line 201 of the first region 206. The AND gate is used to transmit voltage to the m-th row scan signal line 201 of the first region 206 when it is turned on. Each pixel 203 is connected to a row of scan signal lines 201 and a column of data signal lines 202 via a second transistor 209. The gate of the second transistor 209 is connected to the row of scan signal lines 201, the source of the second transistor 209 is connected to the column of data signal lines 202, and the drain of the second transistor 209 is connected to the pixel 203.

[0035] Optional, please refer to Figure 5 Each sub-drive circuit is used to input the display signal for that row.

[0036] The m-th and (m+1)-th adjacent sub-driving circuits are connected via a first transistor 208. The m-th sub-driving circuit is connected to the gate of the first transistor 208, and the (m+1)-th sub-driving circuit is connected to the source of the first transistor 208. The drain of the first transistor 208 is connected to the m-th row scan signal line 201 of the second region 207. The first transistor 208 is used to transmit voltage to the m-th row scan signal line 201 of the second region 207 when it is turned on. The m-th and (m+1)-th adjacent sub-driving circuits are connected to a row scan signal line 201 via an AND gate. The m-th sub-driving circuit is connected to the first input of the AND gate, and the (m+1)-th sub-driving circuit is connected to the second input of the AND gate. The output of the AND gate is connected to the m-th row scan signal line 201 of the first region 206. Please refer to... Figure 4 The output terminal only outputs a high level when both the first and second input terminals are high-level. This AND gate configuration ensures the accuracy of voltage transmission in the first region 206, triggering only when both adjacent sub-driver circuits output high-level signals, thus improving the stability of the display. Please refer to... Figure 3 In the prior art, a row of scan signal lines 201 connects the gates of all the second transistors 209 in that row. However, in this application, since the second transistors 209 in the first region 206 and the second region 207 are controlled by two adjacent circuits, the number of second transistors 209 passing through the electrical signal transmission of a row of scan signal lines 201 is reduced, voltage loss is reduced, and the difference between the electrode voltage of the far pixel 203 and the electrode voltage of the near pixel 203 is reduced, thereby reducing the difference between the far and near images.

[0037] In one possible example, the first row of scan signal lines 201 in the x-row scan signal lines 201 is connected to the gate of the second transistor 209 in the first row of the first region 206. The first row of scan signal lines 201 is also connected to the gate of the first transistor 208. The source of the first transistor 208 is connected to the output terminal of the second sub-driving circuit. The drain of the first transistor 208 is connected to the gate of the second transistor 209 in the first row of the second region 207. The second transistor 209 is used to transmit voltage to the first row of scan signal lines 201 in the second region 207 when it is turned on.

[0038] Optionally, a first transistor 208 and an AND gate may also be provided in row 0 before the first row. The sub-driving circuit in row 0 and the first sub-driving circuit are connected through the first transistor 208. The sub-driving circuit in row 0 is connected to the gate of the first transistor 208, and the first sub-driving circuit is connected to the source of the first transistor 208. The scan signal line 201 is not provided in row 0. The sub-driving circuit in row 0 is connected to the first input terminal of the AND gate, and the first sub-driving circuit is connected to the second input terminal of the AND gate.

[0039] By setting the first scan signal line 201 in the x scan signal lines 201 to be connected to the gates of the second transistors 209 in the first row of the first region 206, the first scan signal line 201 is also connected to the gate of the first transistor 208. The source of the first transistor 208 is connected to the output terminal of the second sub-driving circuit, and the drain of the first transistor 208 is connected to the gates of the second transistors 209 in the first row of the second region 207. The second transistor 209 is used to transmit voltage to the first scan signal line 201 in the first row of the second region 207 when it is turned on. Through the multi-functional multiplexing design of the first scan signal line 201, the linkage driving of the first pixels 203 in the first region 206 and the second region 207 can be realized without additional dedicated control lines. The indirect control of the voltage of the first row in the second region 207 is achieved through the first transistor 208, improving the accuracy of driving the first pixels 203 and effectively eliminating the display defects at the edge of the screen. At the same time, the cross-region linkage control makes the display timings of the first pixels 203 in the two regions consistent, avoiding problems such as picture partition misalignment and stuttering, and improving the integrity of the display picture. In addition, the multiplexed line reduces the power consumption of the circuit and the signal transmission delay, further optimizing the energy efficiency and response performance of the display device.

[0040] In a possible example, the x-th scan signal line 201 in the x scan signal lines 201 is connected to the gates of the second transistors 209 in the x-th row of the second region 207, and the x-th scan signal line 201 is also connected to the second input terminal of the AND gate. The x-th scan signal line 201 is used to transmit voltage to the gate of the second transistor 209 in the x-th row of the second region 207.

[0041] By employing a dual-function design for the x-th row scan signal line 201, the direct driving of the last row pixel 203 in the second region 207 and the logic input of the AND gate can be simultaneously achieved without the need for additional control circuitry and logic components, further simplifying the circuit structure. As the final part of the display screen, the driving stability of the last row pixel 203 is crucial to the integrity of the image. The direct connection method reduces signal transmission links, lowers the risk of signal attenuation and interference, and ensures the clear and stable display of the last row pixel 203, avoiding problems such as blurring at the bottom of the screen and ghosting. Simultaneously, introducing the last row data line signal into the AND gate logic judgment makes the logic control of the entire driving circuit more coherent, achieving coordinated driving between the last row and adjacent region driving, and improving the overall logic consistency and reliability of the circuit.

[0042] In one possible example, x sub-driving circuits, AND gates, and the first transistor 208 are all located at the end of the first region 206 away from the second region 207.

[0043] By setting x sub-driving circuits, AND gates, and the first transistor 208 all at the end of the first region 206 furthest from the second region 207, the driving control element is physically separated from the pixel 203 array. This effectively avoids electromagnetic interference generated by the sub-driving circuits and AND gates affecting the signal transmission of the pixel 203 array, significantly improving the stability of the pixel 203 driving and the quality of the displayed image. The edge layout facilitates component wiring and maintenance, shortens the connection lines between control elements, reduces signal transmission delay and energy loss, and improves circuit response speed and energy efficiency. Simultaneously, the centralized arrangement makes the component arrangement more regular, facilitating automated mounting and soldering during production and improving production efficiency. Furthermore, this layout provides more ample space for the pixel 203 array in the first region 206 and the second region 207, facilitating the optimization of the pixel 203 arrangement density. At the same time, the concentration of the control unit at the edge also provides favorable conditions for the narrow bezel design of the display device.

[0044] In one possible example, the number of first transistors 208 is x-1, the number of AND gates is x-1, the m-th row of scan signal lines 201 is connected to the output of the (m-1)-th AND gate, the first input of the (m-1)-th AND gate is connected to the gate of the m-th first transistor 208, the second input of the (m-2)-th AND gate, the output 204 of the m-th sub-driving circuit, and the source of the (m-1)-th first transistor 208, and the second input of the (m-1)-th AND gate is connected to the m-th AND gate. The first input terminal, the gate of the (m+1)th first transistor 208, the output terminal 204 of the mth sub-driving circuit, and the source of the mth first transistor 208 are all connected. The drain of the mth first transistor 208 is connected to the gate of the second transistor 209 in the mth row of the second region 207. The (m-1)th AND gate is used to transmit voltage to the scan signal line 201 in the mth row when it is turned on. The mth first transistor 208 is used to transmit voltage to the gate of the second transistor 209 in the mth row when it is turned on. 1 < m < x.

[0045] The m-th sub-driving circuit can precisely control the voltage of the m-th row of data lines through AND gates and the first transistor 208, and can precisely control the working state of the x-th row of data lines through x-1 AND gates and x-1 first transistors 208. This optimizes the configuration of component quantity, avoids component redundancy, and reduces circuit cost and power consumption. The multi-channel signal access method allows the working states of each AND gate and the first transistor 208 to feedback to each other and coordinate control, effectively improving the circuit's logic fault tolerance. Even if a single component experiences slight signal fluctuations, the linkage mechanism can correct them, ensuring the overall driving stability. Simultaneously, this design keeps the driving signals of corresponding rows in the first area 206 and the second area 207 highly synchronized, avoiding timing misalignment during partitioned display and improving the continuity and consistency of the image. Furthermore, the compact signal linkage link shortens the signal transmission path, reduces signal attenuation, and improves the circuit's response speed.

[0046] The following describes a driving method provided in an embodiment of this application. This driving method can be executed by a display device, which can be implemented by software and / or hardware.

[0047] Please refer to Figure 6 , Figure 6 This is a flowchart illustrating a driving method provided in an embodiment of this application. An example is given of the driving process of this driving method applied to a driving circuit. The method includes the following step S601, wherein... S601: When the AND gate is turned on, voltage is transmitted to the m-th row scan signal line of the first region, and when the first transistor is turned on, voltage is transmitted to the m-th row scan signal line of the second region.

[0048] Please refer to Figure 7 , Figure 7This is a schematic diagram of a sub-driving circuit provided in an embodiment of this application. For example... Figure 7 As shown, the sub-driving circuit includes the (n-1)th stage input terminal G(n-1), the (n+1)th stage input terminal G(n+1), the first voltage terminal VDS, the first auxiliary transistor T1, the second auxiliary transistor T1A, the second voltage terminal VSD, the third voltage terminal VGL, the reset terminal Reset Q, the (n+3)th stage signal terminal CLKn+3, the touch signal terminal TPE, the output signal terminal Gn, the nth stage signal terminal CLKn, the third auxiliary transistor T2, the fourth auxiliary transistor T2A, the fifth auxiliary transistor T3, the sixth auxiliary transistor T4, the seventh auxiliary transistor T5, the eighth auxiliary transistor T6, the ninth auxiliary transistor T6A, the tenth auxiliary transistor T7, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the first node Q. The third capacitor C3 can charge the first node Q to increase its voltage, thereby increasing the time it takes to reach its peak voltage. When the sub-driving circuit charges the gate of the second auxiliary transistor, it reduces the time it takes for the gate of the second auxiliary transistor to reach its peak voltage.

[0049] Please refer to Figure 8 , Figure 8 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 8 As shown, the display device 102 includes a timing controller 801, a driving circuit 802, a processor 803, a memory 804, and one or more programs 805. The one or more programs are stored in the memory and configured to be executed by the processor. The processor controls the timing controller to send signals. The timing controller is electrically connected to the driving circuit and is used to transmit timing signals from the driving circuit to the driving circuit. The program includes instructions for performing the following steps: Voltage is transmitted to the m-th row of the scan signal line in the first region by means of an AND gate when it is turned on, and voltage is transmitted to the m-th row of the scan signal line in the second region by means of a first transistor when it is turned on.

[0050] In one possible example, the program specifically executes the following instructions: When the second transistor is turned on, voltage is transmitted to the first row of the scan signal line in the second region.

[0051] In one possible example, the program specifically executes the following instructions: Voltage is transferred to the gate of the second transistor in the xth row of the second region via the xth row data line.

[0052] In one possible example, the program specifically executes the following instructions: When the (m-1)th AND gate is turned on, voltage is transmitted to the scan signal line of the m-th row, and when the m-th first transistor is turned on, voltage is transmitted to the gate of the second transistor in the m-th row, 1 < m < x.

[0053] Those skilled in the art will understand that, for ease of explanation, Figure 5 Only one memory and processor are shown in the illustration. In a real terminal or server, multiple processors and memories may exist. Memory can also be called storage medium or storage device, etc., and this application does not limit this.

[0054] It should be understood that in this application, the processor can be a central processing unit, or it can be other general-purpose processors, digital signal processors, application-specific integrated circuits, off-the-shelf programmable gate arrays or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor can also be a general-purpose microprocessor, graphics processor or one or more integrated circuits, used to execute relevant programs to achieve the functions required by the embodiments of this application.

[0055] The processor can also be an integrated circuit chip with signal processing capabilities. In implementation, each step of this application can be completed through integrated logic circuits in the processor hardware or instructions in software form. The aforementioned processor can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The steps of the methods disclosed in the embodiments of this application can be directly manifested as execution by a hardware decoding processor, or execution by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the functions required by the units included in the methods, apparatus, and storage media of the embodiments of this application.

[0056] It should also be understood that the memory mentioned in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory can be read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, or flash memory. Volatile memory can be random access memory used as an external cache. By way of example, but not limitation, many forms of RA second angles are available, such as static random access memory, dynamic random access memory, synchronous dynamic random access memory, double data rate synchronous dynamic random access memory, enhanced synchronous dynamic random access memory, synchronous linked dynamic random access memory, and direct memory bus random access memory. The memory can also be read-only optical disc or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but is not limited thereto. The memory can exist independently and be connected to the processor via a bus. Alternatively, the memory can be integrated with the processor. The memory can store programs, and when the program stored in the memory is executed by the processor, the processor performs the various steps of the method determined in the above embodiments of this application.

[0057] It should be noted that when the processor is a general-purpose processor or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory (storage module) is integrated into the processor. It should be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0058] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0059] In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware processor, or by a combination of hardware and software modules within the processor. The software modules can reside in mature storage media in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. Since this storage medium is located in memory, the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method; to avoid repetition, these will not be described in detail here.

[0060] Those skilled in the art will recognize that the various illustrative logical blocks (ILBs) and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0061] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented, in whole or in part, as a computer-programmed program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a processor, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic) or wireless (e.g., infrared, wireless, microwave, etc.) means, or from one website, computer, server, or data center to a mobile phone processor via a wired means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive), etc.

[0062] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A driving circuit, characterized in that, The driving circuit includes x rows of scan signal lines, multiple columns of data signal lines, a gate row driving circuit, and multiple arrayed pixels. The gate row driving circuit includes x sub-driving circuits that correspond one-to-one with the multiple rows of scan signal lines. Each row of scan signal lines includes a scan signal line disposed in a first region and a scan signal line disposed in a second region. The scan signal lines in the first region and the scan signal lines in the second region are spaced apart and disconnected. The output terminals of the adjacent m-th sub-driving circuit and the (m+1)-th sub-driving circuit are connected through a first transistor. The output terminal of the m-th sub-driving circuit is connected to the gate of the first transistor, and the output terminal of the (m+1)-th sub-driving circuit is connected to the source of the first transistor. The drain of the first transistor is connected to the scan signal line in the m-th row of the second region. The first transistor is used to transmit voltage to the first data line scan signal line in the m-th row of the second region when it is turned on. The output terminals of the mth and (m+1)th adjacent sub-driving circuits are connected to a row of scan signal lines via an AND gate. The output terminal of the mth sub-driving circuit is connected to the first input terminal of the AND gate, and the output terminal of the (m+1)th sub-driving circuit is connected to the second input terminal of the AND gate. The output terminal of the AND gate is connected to the mth row of scan signal lines in the first region. The AND gate is used to transmit voltage to the mth row of scan signal lines in the first region when it is turned on. Each pixel is connected to a row of scan signal lines and a column of data signal lines via a second transistor. The gate of the second transistor is connected to a row of scan signal lines, the source of the second transistor is connected to a column of data signal lines, and the drain of the second transistor is connected to the pixel.

2. The driving circuit according to claim 1, characterized in that, The first row of scan signal lines in the x-row is connected to the gate of the second transistor in the first row of the first region. The first row of scan signal lines is also connected to the gate of the first transistor. The source of the first transistor is connected to the output terminal of the second sub-driving circuit. The drain of the first transistor is connected to the gate of the second transistor in the first row of the second region. The second transistor is used to transmit voltage to the first row of scan signal lines in the second region when it is turned on.

3. The driving circuit according to claim 1, characterized in that, The x-th row of the scan signal lines is connected to the gate of the second transistor in the x-th row of the second region. The x-th row of the scan signal lines is also connected to the second input terminal of the AND gate. The x-th row of the scan signal lines is used to transmit voltage to the gate of the second transistor in the x-th row of the second region.

4. The driving circuit according to claim 1, characterized in that, The x sub-driving circuits, the AND gate, and the first transistor are all located at the end of the first region that is away from the second region.

5. The driving circuit according to claim 1, characterized in that, The number of first transistors is x-1, the number of AND gates is x-1, the m-th row of the scan signal lines in the x rows is connected to the output of the (m-1)-th AND gate, the first input of the (m-1)-th AND gate is connected to the gate of the m-th first transistor, the second input of the (m-2)-th AND gate, the output of the m-th sub-driving circuit, and the source of the (m-1)-th first transistor, the second input of the (m-1)-th AND gate is connected to the first input of the m-th AND gate, the gate of the (m+1)-th first transistor, the output of the m-th sub-driving circuit, and the source of the m-th first transistor, the drain of the m-th first transistor is connected to the gate of the m-th row of the second transistors in the second region, the (m-1)-th AND gate is used to transmit voltage to the m-th row of the scan signal lines when it is turned on, and the m-th first transistor is used to transmit voltage to the gate of the m-th row of the second transistors when it is turned on, 1 < m < x.

6. A driving method, characterized in that, The driving circuit includes x rows of scan signal lines, multiple columns of data signal lines, a gate row driving circuit, and multiple arrayed pixels. The gate row driving circuit includes x sub-driving circuits, each corresponding one-to-one with one of the rows of scan signal lines. Each row of scan signal lines includes a scan signal line located in a first region and a scan signal line located in a second region. The scan signal lines in the first region and the scan signal lines in the second region are spaced apart and disconnected. The output terminals of adjacent m-th sub-driving circuits and (m+1)-th sub-driving circuits are connected via a first transistor. The output terminal of the m-th sub-driving circuit is connected to the gate of the first transistor, and the output terminal of the (m+1)-th sub-driving circuit is connected to the source of the first transistor. The drain of the pixel is connected to the scan signal line in the m-th row of the second region. The outputs of the adjacent m-th sub-driving circuit and the (m+1)-th sub-driving circuit are connected to a row of scan signal lines via an AND gate. The output of the m-th sub-driving circuit is connected to the first input of the AND gate. The output of the (m+1)-th sub-driving circuit is connected to the second input of the AND gate. The output of the AND gate is connected to the scan signal line in the m-th row of the first region. Each pixel is connected to a row of scan signal lines and a column of data signal lines via a second transistor. The gate of the second transistor is connected to a row of scan signal lines, the source of the second transistor is connected to a column of data signal lines, and the drain of the second transistor is connected to the pixel. The method includes: When the AND gate is turned on, voltage is transmitted to the scan signal line in the m-th row of the first region, and when the first transistor is turned on, voltage is transmitted to the scan signal line in the m-th row of the second region.

7. The driving method according to claim 6, characterized in that, The first row of scan signal lines in the x-row is connected to the gate of the second transistor in the first row of the first region. The first row of scan signal lines is also connected to the gate of the first transistor. The source of the first transistor is connected to the output terminal of the second sub-driving circuit. The drain of the first transistor is connected to the gate of the second transistor in the first row of the second region. The method further includes: When the second transistor is turned on, it transmits voltage to the scan signal line of the first row of the second region.

8. The driving method according to claim 6, characterized in that, The x-th row of scan signal lines is connected to the gate of the second transistor in the x-th row of the second region, and the x-th row of scan signal lines is also connected to the second input terminal of the AND gate. The method further includes: Voltage is transferred to the gate of the second transistor in the xth row of the second region via the data line in the xth row.

9. The driving method according to claim 6, characterized in that, The number of first transistors is x-1, the number of AND gates is x-1, the m-th row scan signal line of the first region is connected to the output of the (m-1)-th AND gate, the first input of the (m-1)-th AND gate is connected to the gate of the m-th first transistor, the second input of the (m-2)-th AND gate, the output of the m-th sub-driving circuit, and the source of the (m-1)-th first transistor, the second input of the (m-1)-th AND gate is connected to the first input of the m-th AND gate, the gate of the (m+1)-th first transistor, the output of the m-th sub-driving circuit, and the source of the m-th first transistor, and the drain of the m-th first transistor is connected to the gate of the second transistor in the m-th row of the second region. The method includes: When the (m-1)th AND gate is turned on, voltage is transmitted to the scan signal line in the m-th row, and when the m-th first transistor is turned on, voltage is transmitted to the gate of the second transistor in the m-th row, 1 < m < x.

10. A display device, characterized in that, It includes a timing controller and a driving circuit as described in any one of claims 1 to 5, wherein the timing controller is connected to the driving circuit and is used to transmit timing signals of the driving circuit to the driving circuit.

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