An electrically controlled drive output short circuit delay protection circuit

Abstract

This invention discloses an electronically controlled drive output short-circuit delay protection circuit, comprising an oscillation circuit, a comparator circuit, a short-circuit self-locking output circuit, and a delay protection circuit. The oscillation circuit adjusts the oscillation frequency to generate an oscillation signal and stably output it to the comparator circuit. The comparator circuit continuously generates a PWM pulse width modulation signal to drive the short-circuit self-locking output circuit. The delay protection circuit uses negative feedback to cut off the input of the comparator circuit during a short circuit to delay the output of the PWM pulse width modulation signal. This invention features a simple circuit principle, low cost, and ease of implementation. It utilizes a delay circuit to extract the protection signal from the subsequent power drive circuit and feed it back to the preceding stage with a certain delay time, avoiding rapid and frequent start-stop processes of the output power transistor that could cause overload damage and effectively improving the service life of circuit components.

Description

Technical Field

[0001] This invention relates to an electronically controlled drive output short-circuit delay protection circuit, belonging to the technical field of power drive protection circuits. Background Technology

[0002] Traditional power drive protection circuits typically lock out the output quickly after a short circuit or overcurrent is detected in the drive stage after the drive input signal is activated, thus preventing damage to the power output stage due to short circuit or overcurrent. They can also release the protection lockout after the drive input signal leaves the active state, ensuring that the drive action can be executed again with the next drive input signal without interrupting power.

[0003] This type of protection circuit works fine for slow-speed control such as switching lights on and off or starting and stopping motors, but in fast-switching states, such as PWM dimming or speed control circuits, if the load is still in a short-circuit or overload state, the power output stage will eventually be damaged due to losses from frequent switching on and off. Summary of the Invention

[0004] Therefore, the purpose of this invention is to provide an electronically controlled drive output short-circuit delay protection circuit to at least solve the problems mentioned in the background art.

[0005] The objective of this invention is achieved through the following technical solution: An electronically controlled drive output short-circuit delay protection circuit includes an oscillation circuit, a comparator circuit, a short-circuit self-locking output circuit, and a delay protection circuit. The oscillation circuit is used to adjust the oscillation frequency to generate an oscillation signal and output it stably to the comparator circuit. The comparator circuit is used to continuously generate a PWM pulse width modulation signal to drive the short-circuit self-locking output circuit. The delay protection circuit is used to delay the output of the PWM pulse width modulation signal by cutting off the input of the comparator circuit with negative feedback when a short circuit occurs.

[0006] Furthermore, the oscillation circuit includes U1B, R1, R2, R3, R5, and C1. R1 and R2 are connected in series and their two ends are connected to power-related pins. Their connection node is connected to one end of resistor R3. The other end of R3 is connected to the non-inverting input pin 5 of U1B. The inverting input pin 6 of U1B is directly connected to the output pin 7. The output pin 7 of U1B is connected to one end of resistor R5. The other end of resistor R5 is connected to one end of capacitor C1. The other end of capacitor C1 is grounded. At the same time, capacitor C1 is connected to the inverting input pin 6 of U1B.

[0007] Furthermore, R5 is an adjustable resistor and C1 is an adjustable capacitor. The oscillation frequency of the oscillation circuit can be adjusted by adjusting the value of R5 or C1.

[0008] Furthermore, the comparison circuit includes U1A, R4, and R7. R4 and R7 are connected in series in the power supply loop. Their connection node is connected to the non-inverting input pin 3 of U1A. The output of the oscillation circuit is connected to the inverting input pin 2 of U1A. The output pin 1 of U1A is connected to the short-circuit self-locking output circuit. Pins 4 and 8 of U1A are connected to power supply related pins.

[0009] Furthermore, R4 and R7 are adjustable resistors or multi-position variable resistance switches, and the duty cycle of the output is adjusted by adjusting the resistance values ​​of R4 and R7.

[0010] Furthermore, the short-circuit self-locking output circuit includes C2, R8, R9, R10, R11, Q1, D1, and D2. The capacitor C2 is connected between the power supply and ground. R8 and R9 are connected in series, with one end connected to pin 1 of the output terminal of the comparator circuit U1A and the other end connected to the base of transistor Q1. R10 is connected between the power supply and the collector of Q1. The anode of D1 is connected to the relevant circuit of Q1, and the cathode is connected to the load. R11 is connected to the control electrode of D2 and Q3. The other end of D2 is grounded, and the two main electrodes of Q3 are connected to the two ends of the load.

[0011] Furthermore, the delay protection circuit includes Q2, R12, R13, C3, R12, and R13 connected in series, with one end of C3 connected to the base of transistor Q2 and the other end connected to the control terminal of D2 in the short-circuit self-locking output circuit. The base of Q2 is connected to pin 2 of the inverting input terminal of U1A in the comparator circuit, and the emitter is connected to one end of C3. The other end of C3 is connected to the series node of R12 and R13.

[0012] Furthermore, R13 is an adjustable resistor and C3 is an adjustable capacitor. Adjusting the value of R13 or C3 adjusts the delay time.

[0013] Compared with the prior art, the beneficial effects of the present invention are: The circuit principle of this invention is simple, low-cost, and easy to implement. It uses a delay circuit to extract the protection signal of the power drive circuit of the subsequent stage and feed it back to the previous stage with a certain delay time. This avoids the output power tube from having a rapid and frequent start-stop process, which would cause overload damage and effectively improve the service life of the circuit components.

[0014] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0015] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will now be described in further detail with reference to the accompanying drawings, wherein: Figure 1 The circuit diagram shows the short-circuit delay protection circuit for the electronically controlled drive output provided in an embodiment of the present invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] This embodiment is illustrated using an in-vehicle headlight dimming circuit, with the load being an automotive instrument panel backlight bulb. Figure 1 This is the circuit schematic diagram of the present invention, wherein: R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, and R13 are resistors; U1A and U1B are voltage comparators; C1, C2, and C3 are capacitors; D1 and D2 are diodes; Q1, Q2, and Q3 are transistors. Q1 and Q2 are BJT transistors, which control the conduction / turn-off between the collector and emitter through the base current. Q3 is an output power transistor, which controls the conduction / turn-off between the drain and source through the gate voltage.

[0018] like Figure 1 As shown, the first embodiment of the present invention provides an electronically controlled drive output short-circuit delay protection circuit, including an oscillation circuit, a comparator circuit, a short-circuit self-locking output circuit, and a delay protection circuit. The oscillation circuit is used to adjust the oscillation frequency to generate an oscillation signal and output it stably to the comparator circuit. The comparator circuit is used to continuously generate a PWM pulse width modulation signal to drive the short-circuit self-locking output circuit. The delay protection circuit is used to delay the output of the PWM pulse width modulation signal by cutting off the input of the comparator circuit with negative feedback when a short circuit occurs.

[0019] The oscillation circuit includes U1B, R1, R2, R3, R5, and C1. R1 and R2 are connected in series and their two ends are connected to power-related pins. Their connection point is connected to one end of resistor R3. The other end of R3 is connected to the non-inverting input pin 5 of U1B. The inverting input pin 6 of U1B is directly connected to the output pin 7. The output pin 7 of U1B is connected to one end of resistor R5. The other end of resistor R5 is connected to one end of capacitor C1. The other end of capacitor C1 is grounded. At the same time, capacitor C1 is connected to the inverting input pin 6 of U1B. R1 and R2 are connected in series in the power supply circuit, providing a reference voltage to the input terminal of U1B through voltage division, while limiting current and protecting the circuit. R3 connects the non-inverting input pin 5 of U1B to the voltage divider node of R1 and R2, participating in the voltage division or biasing of the input signal, affecting the circuit gain and stability. R5 connects the output pin 7 of U1B and capacitor C1, forming an RC feedback network together with C1 to adjust the frequency response of the circuit. U1B is the core operational unit of the circuit, using a positive feedback mechanism to generate a continuous oscillation signal. The frequency and amplitude of the output signal are determined by the values ​​of R5 and C1. Through the synergistic effect of these components, the circuit achieves the generation and stable output of the oscillation signal, while ensuring the stability and accuracy of the circuit. R5 is an adjustable resistor, and C1 is an adjustable capacitor; adjusting R5 or C1 adjusts the oscillation frequency.

[0020] The comparator circuit includes U1A, R4, and R7. R4 and R7 are connected in series in the power supply circuit, and their connection node is connected to the non-inverting input pin 3 of U1A. The output of the oscillation circuit is connected to the inverting input pin 2 of U1A. The output pin 1 of U1A is connected to a short-circuit self-locking output circuit. Pins 4 and 8 of U1A are connected to power supply-related pins. R4 and R7 function as voltage dividers in the circuit, providing different input voltage signals to the two input terminals of U1A. By changing the resistance values ​​of R4 and R7, the voltage input to the non-inverting and inverting terminals of U1A can be adjusted. U1A, as the core component of the comparator circuit, compares the voltages at the non-inverting input pin 3 and the inverting input pin 2. When the voltage at the non-inverting input is higher than the voltage at the inverting input, U1A outputs a high level; when the voltage at the non-inverting input is lower than the voltage at the inverting input, U1A outputs a low level, thus achieving the function of comparing the two input voltage signals. R4 and R7 can be an adjustable resistor or a multi-position variable resistor switch. Adjusting the resistance values ​​of R4 and R7 can adjust the duty cycle of the output.

[0021] The short-circuit self-locking output circuit includes C2, R8, R9, R10, R11, Q1, D1, and D2. Capacitor C2 is connected between the power supply and ground. R8 and R9 are connected in series, with one end connected to pin 1 of the output terminal of the comparator circuit U1A and the other end connected to the base of transistor Q1. R10 is connected between the power supply and the collector of Q1. The anode of D1 is connected to the relevant circuit of Q1, and the cathode is connected to the load. R11 is connected to the control electrode of D2 and Q3. The other end of D2 is grounded, and the two main electrodes of Q3 are connected to the two ends of the load. C2 acts as a filter, removing high-frequency interference signals from the power supply and making the power output more stable; R8, R9, and R10 limit current and divide voltage; Q1 controls the conduction or cutoff between the collector and emitter according to the base current, thereby controlling the circuit's on / off state or amplifying the signal; R11 limits the current flowing into the control electrode of Q3; D1 prevents reverse voltage from damaging other components; D2 protects the control electrode of Q3 from overvoltage damage; Q3 controls the load's on / off state and protects the load.

[0022] The delay protection circuit includes Q2, R12, R13, and C3. R12 and R13 are connected in series, with one end connected to the base of transistor Q2 and the other end connected to the control terminal of D2 in the short-circuit self-locking output circuit. The base of Q2 is connected to pin 2 of the inverting input of U1A in the comparator circuit, and its emitter is connected to one end of C3. The other end of C3 is connected to the series connection of R12 and R13. When Q2 is turned on, C3 charges through R12, making the base of Q2 high, and the inverting input of U1A is pulled low, causing U1A to stop outputting the PWM waveform. When the circuit is turned on again due to the PWM pulse, the RC delay circuit composed of C3 and R13 keeps Q2 on. R13 is an adjustable resistor, and C3 is an adjustable capacitor. Adjusting the value of R13 or C3 can adjust the delay time.

[0023] Working principle and process of the device: After the circuit is powered on, the terminals of capacitor C1 in the oscillation circuit are at a low level. Therefore, terminal 6 of voltage comparator U1B is also low. The voltage at terminal 5 of U1B is obtained by voltage division using resistors R1 and R2, so the voltage at terminal 5 of U1B is higher than that at terminal 6. Therefore, terminal 7 of U1B outputs a high level. This level charges capacitor C1 after current limiting through resistor R5. When the voltage at C1 is higher than that at terminal 5 of U1B, hysteresis is achieved by resistor R3, causing U1B to flip. Finally, a triangular-like wave is obtained and sent to the second-stage comparator circuit. Terminal 2 of U1A is compared with the voltage at terminal 3 of U1A. Under normal power-on conditions, the voltage at terminal 2 of U1A is higher than that at terminal 3, and terminal 1 of U1A outputs a low level, activating the short-circuit self-locking output circuit and enabling power drive output to the load. When the load is short-circuited or overcurrent, a delay protection circuit causes the voltage at terminal 2 of U1A to fall below that at terminal 3, and terminal 1 of U1A outputs a high level, preventing the activation of the short-circuit self-locking output circuit. When comparing the voltage at terminal 3 of U1A with that at terminal 2, adjusting R4 or R7 can obtain different comparison voltages, achieving PWM pulse width adjustment.

[0024] Specifically, under normal circumstances, when the short-circuit self-locking output circuit is activated, due to the charging effect of C2, the protection transistor Q1 will not conduct, and Q3 will conduct and output a high level. D1 feeds this high level output back to Q1 to ensure that the protection transistor Q1 does not conduct during the entire input activation process, and Q3 maintains normal output.

[0025] When the load is short-circuited or overcurrent, if the drive time of the driver input activation signal exceeds the charging time of C1, the output cannot reach a high level. D1 cannot then feed back to Q1, causing Q1 to conduct and shutting down the output of Q3. Since Q3 has short-term overload impact capability, as long as the output is turned off within the time Q3 can withstand, Q3 will only generate slight heat and will not be damaged. This time is typically in the millisecond range. However, if the driver input activation signal is a high-speed signal and the load is short-circuited or overloaded, such as a 100Hz PWM modulation signal, it means that Q3 will experience a large current surge every 10 milliseconds. Although the protection circuit can time and shut down the driver, this surge will cause Q3 to accumulate heat without sufficient time for heat dissipation and recovery, ultimately leading to damage. Therefore, the protection action is triggered by the time-delay protection circuit: D2 provides reverse isolation, connecting the protection signal of Q1 to Q2 through R12 and R13. After Q2 is turned on, it pulls terminal 2 of U1A in the preceding stage low, preventing U1A from outputting an activation signal to the subsequent stage again. The presence of C3 allows Q2 to remain on for a certain period of time, achieving the protection delay. As long as the protection delay time (e.g., 500ms) is greater than the heat dissipation recovery time of Q3's power output, Q3 will not be damaged, and the entire circuit will receive reliable protection.

[0026] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the present invention in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments without departing from the technical solution of the present invention and based on the technical essence of the present invention shall still fall within the scope of the technical solution of the present invention.

Claims

1. A short-circuit delay protection circuit for an electronically controlled drive output, characterized in that, It includes an oscillation circuit, a comparator circuit, a short-circuit self-locking output circuit, and a delay protection circuit. The oscillation circuit is used to adjust the oscillation frequency to generate an oscillation signal and output it stably to the comparator circuit. The comparator circuit is used to continuously generate a PWM pulse width modulation signal to drive the short-circuit self-locking output circuit. The delay protection circuit is used to cut off the input of the comparator circuit with negative feedback when a short circuit occurs to delay the output of the PWM pulse width modulation signal.

2. The electronically controlled drive output short-circuit delay protection circuit according to claim 1, characterized in that, The oscillation circuit includes U1B, R1, R2, R3, R5, and C1. R1 and R2 are connected in series and their two ends are connected to power-related pins. Their connection point is connected to one end of resistor R3. The other end of R3 is connected to the non-inverting input pin 5 of U1B. The inverting input pin 6 of U1B is directly connected to the output pin 7. The output pin 7 of U1B is connected to one end of resistor R5. The other end of resistor R5 is connected to one end of capacitor C1. The other end of capacitor C1 is grounded. At the same time, capacitor C1 is connected to the inverting input pin 6 of U1B.

3. The electronically controlled drive output short-circuit delay protection circuit according to claim 2, characterized in that, R5 is an adjustable resistor and C1 is an adjustable capacitor. The oscillation frequency of the oscillation circuit can be adjusted by adjusting the value of R5 or C1.

4. The electronically controlled drive output short-circuit delay protection circuit according to claim 2, characterized in that, The comparator circuit includes U1A, R4, and R7. R4 and R7 are connected in series in the power supply circuit. Their connection node is connected to the non-inverting input pin 3 of U1A. The output of the oscillation circuit is connected to the inverting input pin 2 of U1A. The output pin 1 of U1A is connected to the short-circuit self-locking output circuit. Pins 4 and 8 of U1A are connected to power supply related pins.

5. The electronically controlled drive output short-circuit delay protection circuit according to claim 4, characterized in that, R4 and R7 are adjustable resistors or multi-position variable resistance switches. Adjusting the resistance values ​​of R4 and R7 adjusts the duty cycle of the output.

6. The electronically controlled drive output short-circuit delay protection circuit according to claim 4, characterized in that, The short-circuit self-locking output circuit includes C2, R8, R9, R10, R11, Q1, D1, and D2. Capacitor C2 is connected between the power supply and ground. R8 and R9 are connected in series, with one end connected to pin 1 of the output terminal of the comparator circuit U1A and the other end connected to the base of transistor Q1. R10 is connected between the power supply and the collector of Q1. The anode of D1 is connected to the relevant circuit of Q1, and the cathode is connected to the load. R11 is connected to the control electrode of D2 and Q3. The other end of D2 is grounded, and the two main electrodes of Q3 are connected to the two ends of the load.

7. The electronically controlled drive output short-circuit delay protection circuit according to claim 6, characterized in that, The delay protection circuit includes Q2, R12, R13, and C3. R12 and R13 are connected in series, with one end connected to the base of transistor Q2 and the other end connected to the control terminal of D2 in the short-circuit self-locking output circuit. The base of Q2 is connected to the inverting input pin 2 of U1A in the comparator circuit, and the emitter is connected to one end of C3. The other end of C3 is connected to the series node of R12 and R13.

8. The electronically controlled drive output short-circuit delay protection circuit according to claim 7, characterized in that, R13 is an adjustable resistor and C3 is an adjustable capacitor. The delay time can be adjusted by adjusting the value of R13 or C3.

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