Converter controller and converter control method

Abstract

This disclosure relates to a converter controller and a converter control method. The converter controller includes a first core configured to, in each control cycle, calculate a pulse width modulation (PWM) control value for a first switch included in a first power factor correction (PFC) circuit and configure a register for a PWM signal output to the first switch. The converter controller also includes a second core configured to, in each control cycle, calculate a PWM control value for a second switch included in a second PFC circuit and store the PWM control value of the second switch in one of a plurality of second data variables selected according to a sequence number. The first core is further configured to configure the register for the PWM signal output to the second switch based on the value of the selected second data variable.

Description

[0001] Cross-citation of related applications

[0002] This application claims the benefit and priority of Korean Patent Application No. 10-2024-0189817, filed on December 18, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to control techniques for converters including PFC (Power Factor Correction) circuitry. Background Technology

[0004] The statements in this section are provided only as background information in connection with this disclosure and may not constitute prior art.

[0005] Electric vehicles may include an on-board charger (OBC). An OBC can be a device that converts alternating current (AC) supplied from an external power source into direct current (DC) usable within the vehicle. This device provides converted power with voltage and current suitable for the electric vehicle's battery pack. Furthermore, the OBC can perform functions to control current and voltage during the power conversion process, thereby preventing overcharging and damage to the battery.

[0006] An on-board charger (OBC) may include a power factor correction (PFC) circuit. The PFC circuit can be designed to maintain a consistent power factor for the alternating current (AC) supplied from an external power source. This circuit improves current flow efficiency and reduces power loss by aligning the input current and input voltage. Furthermore, the PFC circuit may include filtering functionality to reduce electromagnetic interference with the power grid. The circuit also improves the OBC's input current waveform and ensures a stable power supply during battery charging.

[0007] Power factor correction (PFC) circuits may have limitations in terms of the capacity of the power they can handle. One factor determining the maximum power a circuit can handle is the capacity of the switches included in the PFC circuit. Switch capacities can be set according to current and voltage limits, and overheating or damage may occur if the switches operate beyond their design specifications. Furthermore, the capacity of the input filters included in the PFC circuit can also affect the power capacity. Input filters are designed to reduce electromagnetic interference from the power entering the circuit, and if the filter capacity is limited, its performance may degrade under high power conditions. The capacity of the power lines also affects the circuit's power limits, and a stable power delivery may become difficult if the power lines reach overload conditions. These factors can vary depending on the design and configuration of the PFC circuit.

[0008] To increase the power capacity of the power factor correction (PFC) circuitry, multiple PFC circuits can be arranged in parallel within the on-board charger (OBC). Each PFC circuit arranged in parallel can handle power independently, allowing the entire PFC system to support a higher power capacity than a single circuit. This configuration reduces the power load on each PFC circuit, thereby reducing the likelihood of each individual circuit overheating or overloading. Furthermore, in a parallel structure, even if a particular circuit fails, the remaining circuits can continue to operate, potentially maintaining system stability.

[0009] To operate multiple power factor correction (PFC) circuits in parallel, it may be necessary to synchronize the control cycles, switching cycles, or duty cycles of the two PFC circuits. Synchronizing the control cycles means adjusting the control signals of the PFC circuits to operate at identical time intervals. Synchronizing the switching cycles refers to setting the on and off cycles of the power switches in each circuit to keep them equal. Synchronizing the duty cycles means controlling each PFC circuit to maintain the same duty cycle. This synchronization can be used as a method to minimize current and voltage imbalances between circuits connected in parallel. Without synchronization, a particular circuit may end up handling excessive power, potentially leading to overheating or performance degradation. Summary of the Invention

[0010] In this context, in one aspect, this disclosure relates to providing techniques for synchronously controlling multiple power factor correction (PFC) circuits. In another aspect, this disclosure relates to providing techniques for ensuring data consistency when multiple PFC circuits are controlled by different cores.

[0011] Embodiments of this disclosure provide a converter controller including a first core. The first core is configured to calculate, in each control cycle, a pulse width modulation (PWM) control value for a first switch included in a first power factor correction (PFC) circuit and configure a register for a PWM signal output to the first switch. The converter controller also includes a second core. The second core is configured to calculate, in each control cycle, a PWM control value for a second switch included in a second PFC circuit and store the PWM control value of the second switch in one of a plurality of second data variables selected according to a serial number. The first core is further configured to configure a register for the PWM signal output to the second switch based on the value of the selected second data variable.

[0012] The second core can store the PWM control value of the second switch in one of two second data variables. The two second data variables are selected and used alternately.

[0013] The second core can store the sequence number selected for the current control cycle or the sequence number selected for the next control cycle from among multiple second data variables in an index variable.

[0014] The first core can verify the second data variable selected by the index variable based on the sequence number.

[0015] Multiple second data variables can be configured as an array, and one of the second data variables in the array can be selected based on the sequence number.

[0016] The first core can store the PWM control value of the first switch in one of a plurality of first data variables selected according to the serial number.

[0017] Multiple first data variables and multiple second data variables can reside in a buffer shared by the first core and the second core.

[0018] The first core can configure a register for the PWM signal output to the first switch based on the value of a selected first data variable, and can configure a register for the PWM signal output to the second switch based on the value of a selected second data variable.

[0019] In the top-level interrupt service routine (ISR), the first core can configure a register for the PWM signal output to the first switch and a register for the PWM signal output to the second switch.

[0020] The top-level ISR can call a certain amount of time before the start of a new control cycle, and can complete the task before the start of the new control cycle.

[0021] The PWM control value may include at least one of a value indicating the duty cycle of the PWM signal and a value indicating the period of the PWM signal.

[0022] The first core can generate the rising edge time value or falling edge time value of the PWM signal from the value of the selected second data variable, and can store the rising edge time value or falling edge time value in a register for the PWM signal output to the second switch.

[0023] The converter controller may further include a timer output module (TOM) configured to output PWM signals to a first switch and a second switch. A first core is configured with shadow registers (SRs) corresponding to the TOM.

[0024] Each TOM may include a first CM register for setting the rising edge of the PWM signal and a second CM register for setting the falling edge of the PWM signal. At the start of the control cycle, the value stored in the shadow register is sent to the first CM register and the second CM register.

[0025] The first core can execute, in each control cycle, the process of acquiring sensed values ​​from the analog-to-digital converter (ADC) used in the first PFC circuit, the voltage control process, and the current control process, and can calculate the PWM control value of the first switch. The second core can execute, in each control cycle, the process of acquiring sensed values ​​from the ADC used in the second PFC circuit, the voltage control process, and the current control process, and can calculate the PWM control value of the second switch.

[0026] Another embodiment of this disclosure provides a converter control method, including: calculating, via a first core, a pulse width modulation (PWM) control value for a first switch included in a first power factor correction (PFC) circuit. The method further includes calculating, via a second core, a PWM control value for a second switch included in a second PFC circuit. The method also includes storing, via the first core, the PWM control value of the first switch in one of a plurality of first data variables selected according to a serial number. The method further includes storing, via the second core, the PWM control value of the second switch in one of a plurality of second data variables selected according to a serial number; and configuring, via the first core, a register for a PWM signal output to the first switch based on the values ​​of the selected first data variables and a register for a PWM signal output to the second switch based on the values ​​of the selected second data variables.

[0027] Storing the PWM control value of the first switch includes: storing the PWM control value of the first switch in one of two first data variables via a first core, wherein the two first data variables can be selected and used alternately. Storing the PWM control value of the second switch includes: storing the PWM control value of the second switch in one of two second data variables via a second core, wherein the two second data variables are selected and used alternately.

[0028] The method also includes: storing the sequence number selected for the current control cycle or the sequence number selected for the next control cycle in the index variable through the first core and the second core.

[0029] The registers configured to output PWM signals to the first and second switches can be executed in the top-level interrupt service routine (ISR) of the first core.

[0030] The top-level ISR can call a certain amount of time before the start of a new control cycle, and can complete the task before the start of the new control cycle.

[0031] As described above, according to this disclosure, multiple power factor correction (PFC) circuits can be controlled synchronously. Furthermore, according to this disclosure, data consistency can be ensured when multiple PFC circuits are controlled by different cores. Attached Figure Description

[0032] Figure 1This is a schematic diagram of a converter according to an implementation method.

[0033] Figure 2 This is a schematic diagram of a power factor correction (PFC) power stage according to one embodiment.

[0034] Figure 3 This is an exemplary waveform diagram of a first pulse width modulation (PWM) a-phase signal and a second PWM a-phase signal according to one embodiment.

[0035] Figure 4 This is a schematic diagram illustrating the elements that determine the control value of each PWM signal in one embodiment.

[0036] Figure 5 An example diagram is shown illustrating the control process executed by a single core during a control cycle.

[0037] Figure 6 This is a schematic diagram illustrating potential problems when a single core simultaneously controls two PFC (Power Factor Correction) circuits during a single control cycle.

[0038] Figure 7 This is a schematic diagram illustrating how two cores in a converter controller according to one embodiment control the corresponding PFC circuit.

[0039] Figure 8 This is a schematic diagram of a converter controller according to one embodiment.

[0040] Figure 9 This is a schematic diagram of the Timer Output Module (TOM) channel according to an implementation method.

[0041] Figure 10 This is a schematic diagram illustrating the process and waveforms for the core to execute the main signal according to one embodiment.

[0042] Figure 11 This is a flowchart illustrating a converter control method according to one embodiment.

[0043] Figure 12 yes Figure 11 The detailed flowchart of step S1104 in the flowchart is shown below.

[0044] Figure 13 yes Figure 11 The detailed flowchart of step S1106 in the flowchart is shown below.

[0045] Figure 14 yes Figure 11 The detailed flowchart of step S1108 in the flowchart.

[0046] The accompanying drawings described herein are for illustrative purposes only and are not intended to limit the scope of this disclosure in any way. Detailed Implementation

[0047] In the following description, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Furthermore, when labeling components in the drawings, the same reference numerals are used as much as possible for the same components, even in different drawings. Additionally, in describing the present disclosure, detailed descriptions of well-known components or functions may be omitted if they are considered to obscure the main points of the disclosure.

[0048] In describing the components of this disclosure, terms such as first, second, A, B, (a), (b), etc., may be used. These terms are intended only to distinguish one component from another, and the nature, order, or sequence of these components are not limited by these terms. Furthermore, when a component is described as “connected,” “coupled,” or “interfaced” to another component, it should be understood that the component may be directly connected or interfaced to the other component, or the component may also be “connected,” “coupled,” or “interfaced” to the other component via yet another component disposed therebetween. When the controllers, modules, components, devices, elements, units, parts, etc., of this disclosure are described as having a purpose or performing an operation, function, etc., the controllers, modules, components, devices, elements, units, parts, etc., shall be considered herein to be “configured” to satisfy that purpose or perform that operation or function. Each controller, module, part, device, element, unit, part, etc., may individually embody or include a processor and memory (such as a non-transitory computer-readable medium) as part of the apparatus.

[0049] Figure 1 This is a configuration diagram of the converter according to the implementation method.

[0050] See Figure 1 The converter 100 may include a power factor correction (PFC) power stage 110, a DC / DC power stage 120, and a converter controller 130, etc.

[0051] Converter 100 can be an on-board charger (OBC). When converter 100 is an OBC, the load connected to converter 100 can be a battery (BAT).

[0052] The converter 100 can be an on-board charger (OBC). The converter 100 can be a power conversion device installed in an electric vehicle, capable of converting alternating current (AC) power supplied from an external power source into direct current (DC) power to provide the power required for battery charging. The OBC can monitor the battery's state of charge and control the charging current and voltage to prevent damage caused by overcharging or overcurrent. Furthermore, the OBC can be designed to operate reliably under various input voltage conditions and can include a power factor correction (PFC) function to reduce interference with the power grid.

[0053] The load connected to converter 100 can be a battery (BAT). A battery (BAT) can be used as the primary energy storage device in an electric vehicle, and lithium-ion battery cells are commonly used. The battery (BAT) stores the electricity converted by converter 100, and the stored energy can be used to drive the motor of the electric vehicle and supply power to other electronic devices. The battery (BAT) can be designed to repeatedly charge and discharge, and a battery management system (BMS) can be used to monitor conditions such as temperature, voltage, and current.

[0054] In converter 100, PFC power stage 110 can receive AC power and convert it into DC power. DC / DC power stage 120 can regulate the voltage or current level of the DC power supplied from PFC power stage 110 and provide it to the load.

[0055] DC / DC power stage 120 may include multiple DC / DC conversion circuits 122 and 124. DC / DC conversion circuits 122 and 124 may be power conversion circuits capable of converting the voltage or current of an input DC power supply to generate a voltage or current suitable for the load. These circuits may be designed to improve power transmission efficiency and adjust the power according to the load requirements.

[0056] DC / DC conversion circuits 122 and 124 can be buck converter circuits that convert the output voltage to a level lower than the input voltage. The buck converter circuit can primarily employ a buck converter structure, converting the input voltage to a low voltage suitable for the load through controlled switching operations. This conversion minimizes power loss and provides a stable power supply within the voltage tolerance range of the load.

[0057] DC / DC conversion circuits 122 and 124 can be boost converter circuits that convert the output voltage to a level higher than the input voltage. The boost converter circuit can primarily employ a boost converter structure and can convert a low input voltage to a higher output voltage by utilizing switching operations and energy storage components. The circuit can be designed to provide the voltage required by the load even when the input voltage is low.

[0058] DC / DC converter circuits 122 and 124 can be designed not only for buck and boost conversion, but also to support bidirectional power conversion. In such cases, they can include functions for regulating voltage and current according to the direction of power flow.

[0059] The PFC power stage 110 may include multiple PFC circuits 112 and 114, and in this case, DC / DC conversion circuits 122 and 124 may operate in conjunction with PFC circuits 112 and 114, respectively.

[0060] PFC circuits 112 and 114 are circuits that receive AC power and convert it into DC power. These circuits can rectify and filter AC power input from an external source to convert it into DC power that can be used for electrical loads. PFC circuits 112 and 114 may include functions for correcting the power factor by adjusting the phase of the input current and input voltage during the power conversion process.

[0061] PFC circuits 112 and 114 can be designed to adjust the waveform of the input current so that it remains in phase with the input voltage. This enables efficient use of power supplied from the grid and helps reduce power loss and electromagnetic interference. To achieve such power factor correction, PFC circuits 112 and 114 can employ an active PFC method.

[0062] In the case of an active PFC method, PFC circuits 112 and 114 may include switches, and converter controller 130 may control these switches to dynamically adjust the input current and perform accurate power factor correction.

[0063] Multiple switches can be arranged in the PFC circuits 112 and 114 and the DC / DC conversion circuits 122 and 124. The switches may include, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), or bipolar junction transistors (BJTs).

[0064] A MOSFET is a device in which the drain-source current can be controlled by applying a voltage between the gate and source. MOSFETs can be voltage-controlled devices, and their channel conductivity can be adjusted according to the voltage applied to the gate. The drain-source current is determined by the gate voltage, and due to their excellent switching characteristics, MOSFETs are widely used in switching applications.

[0065] IGBTs are devices that combine the characteristics of MOSFETs and BJTs, and the collector-emitter current can be controlled by applying a voltage between the gate and emitter. IGBTs can handle high voltages, and their structure can have the input characteristics of a MOSFET and the output characteristics of a BJT. Due to these characteristics, IGBTs are suitable for various applications.

[0066] A BJT is a three-terminal device: base, collector, and emitter. It controls the current between the collector and emitter by applying a base current. A BJT is a current-controlled device, and the collector current can be amplified by the base current. Due to this amplification characteristic, BJTs can be used as current amplifiers and have the advantage of handling high currents in certain applications.

[0067] The converter controller 130 can use pulse width modulation (PWM) to control these switches. Through this PWM control, the converter controller 130 can control the duty cycle of each switch and the switching period or switching frequency of each switch.

[0068] PWM control can be a method of generating a desired output voltage or current by adjusting the on-time and off-time of switches. Through this PWM control, the converter controller 120 can adjust the duty cycle of each switch. The duty cycle represents the ratio of the switch's on-time and can be used to control the amplitude of the output power.

[0069] The converter controller 130 can control not only the duty cycle but also the switching cycle or switching frequency of each switch. The switching cycle refers to the time it takes for a switch to turn on and off once, and the switching frequency refers to the number of switching operations per second. Controlling the switching cycle or frequency can affect the quality of the output power and the efficiency of power conversion, and can also be related to the thermal management of the power unit.

[0070] The converter controller 130 may include circuitry or algorithms capable of monitoring input signals of voltage, current, and temperature and generating PWM signals based on the input signals in order to adjust the state of the switch in real time.

[0071] Alternating current (AC) power can be supplied to the input terminal TI of converter 100, and a load (e.g., a battery BAT) can be connected to the output terminal TO of converter 100. Furthermore, an input node Ni can be formed at the input terminal TI, and an output node No can be formed at the output terminal TO.

[0072] The first PFC circuit 112 and the second PFC circuit 114 can share an input node Ni, and the first DC / DC converter circuit 122 and the second DC / DC converter circuit 124 can share an output node No. The first PFC circuit 112 can convert the AC power generated at the input node Ni into DC power and supply it to the first DC / DC converter circuit 122. The first DC / DC converter circuit 122 can then convert the voltage or current of the DC power and supply it to the output node No. The second PFC circuit 114 can convert the AC power generated at the input node Ni into DC power and supply it to the second DC / DC converter circuit 124. The second DC / DC converter circuit 124 can then convert the voltage or current of the DC power and supply it to the output node No.

[0073] For the power conversion of each of circuits 112, 114, 122, and 124, converter controller 130 can output a first PWM signal (PWM1) to the first PFC circuit 112 and a second PWM signal (PWM2) to the second PFC circuit 114. Additionally, converter controller 130 can output a third PWM signal (PWM3) to the first DC / DC conversion circuit 122 and a fourth PWM signal (PWM4) to the second DC / DC conversion circuit 124.

[0074] Figure 2 This is a configuration diagram of a PFC power stage according to one implementation.

[0075] See Figure 2 The PFC power stage may include a first PFC circuit 112 and a second PFC circuit 114. The first PFC circuit 112 and the second PFC circuit 114 may share an input node Ni.

[0076] The power supplied to the input node Ni can be three-phase power. According to an embodiment, the power supplied to the input node Ni can be single-phase power; however, for ease of explanation, the supply of three-phase power to the input node Ni is described below.

[0077] Input filters can be configured in each PFC circuit 112 and 114. A first inductor L1 can be configured on phase A of the first PFC circuit 112, a second inductor L2 on phase B, and a third inductor L3 on phase C. A fourth inductor L4 can be configured on phase A of the second PFC circuit 114, a fifth inductor L5 on phase B, and a sixth inductor L6 on phase C.

[0078] In each PFC circuit 112 and 114, a pair of switches can be connected to each phase. In the first PFC circuit 112, the first switch Q1 and the fourth switch Q4 can be connected to phase A, the second switch Q2 and the fifth switch Q5 can be connected to phase B, and the third switch Q3 and the sixth switch Q6 can be connected to phase C. In the second PFC circuit 114, the seventh switch Q7 and the tenth switch Q10 can be connected to phase A, the eighth switch Q8 and the eleventh switch Q11 can be connected to phase B, and the ninth switch Q9 and the twelfth switch Q12 can be connected to phase C.

[0079] The converter controller can provide PWM signals to the gates of switches Q1 to Q12 to control the on / off state of switches Q1 to Q12. For example, the converter controller can provide a first PWM a-phase signal (PWM1a) to the gate of the first switch Q1 to control the on / off state of the first switch Q1. The converter controller can supply a second PWM a-phase signal (PWM2a) to the gate of the seventh switch Q7 to control the on / off state of the seventh switch Q7.

[0080] Based on the switching on / off state of switches Q1 to Q12, phase currents IA1, IB1, IC1, IA2, IB2, and IC2 can be converted into DC currents and temporarily stored in DC link capacitors Clink1 and Clink2. For example, based on the switching on / off state of switches Q1 to Q6, the phase currents IA1, IB1, and IC1 of the first PFC circuit 112 can be converted into DC currents and temporarily stored in the first DC link capacitor Clink1. Based on the switching on / off state of switches Q7 to Q12, the phase currents IA2, IB2, and IC2 of the second PFC circuit 114 can be converted into DC currents and temporarily stored in the second DC link capacitor Clink2.

[0081] In this configuration, switches Q1 to Q6 of the first PFC circuit 112 and switches Q7 to Q12 of the second PFC circuit 114 can operate in a manner that ensures consistent control values. Here, consistency can refer to updating the control values ​​within the same cycle.

[0082] Figure 3 It is a waveform diagram of the first PWM a-phase signal and the second PWM a-phase signal according to one embodiment.

[0083] See Figure 3 The first PWM a-phase signal (PWM1a) and the second PWM a-phase signal (PWM2a) can be updated within the same control period Tctr. For example, the duty cycle of the first PWM a-phase signal (PWM1a) and the second PWM a-phase signal (PWM2a) can be changed within the same control period Tctr. Figure 3In the example shown, the first PWM a-phase signal (PWM1a) and the second PWM a-phase signal (PWM2a) have a phase difference of 180 degrees, but the control period Tctr of the two signals can be basically the same.

[0084] exist Figure 3 In the example, a control cycle Tctr can include two switching cycles Tctr / 2, and the first PWMa phase signal (PWM1a) and the second PWMa phase signal (PWM2a) can both have the same switching cycle Tctr / 2.

[0085] Figure 4 This is a diagram illustrating the elements that determine the control value for each PWM signal in one embodiment.

[0086] See Figure 4 The control values ​​for the PWM signal can include the duty cycle and period. The converter controller can perform PWM control on each switch to control the output of each PFC circuit, where PWM control can refer to controlling the duty cycle and period of the PWM signal.

[0087] Meanwhile, the converter controller can use timers and registers to control the duty cycle and period of the PWM signal.

[0088] For example, the converter controller may include a timer, and the period of the PWM signal can be determined by comparing the timer value with the value of a first CN register CN0. The timer may start counting from an initial value (e.g., 0), increment at fixed intervals, and return to its initial value when its value becomes equal to the value of the first CN register CN0. In this method, the period of the PWM signal can be determined by the value of the first CN register CN0.

[0089] As another example, the converter controller can set the rising edge of the PWM signal when the timer value becomes equal to the value of the first CM register CM0, and the converter controller can set the falling edge of the PWM signal when the timer value becomes equal to the value of the second CM register CM1. In this method, the duty cycle of the PWM signal can be determined by the values ​​of the first CM register CM0 and the second CM register CM1.

[0090] The converter controller can calculate control values ​​(e.g., duty cycle and period) for each PWM signal, and then calculate register values ​​based on these control values. The controller can then update the registers with the calculated values ​​to control each PWM signal.

[0091] At this point, the converter controller can use the shadow register SR to synchronize the registers to ensure consistent timing of updates and control. After calculating the control values ​​(e.g., duty cycle and period) for each PWM signal, the converter controller can first store these values ​​in the shadow register SR. The converter controller can then be configured such that the values ​​stored in the shadow register SR are sent to registers CN0, CM0, and CM1 at the start of the next control cycle. This method prevents arbitrary updates to the registers and helps maintain register consistency.

[0092] The converter controller may include a core for computation. This core can execute a control algorithm to calculate control values ​​for each PWM signal. Based on these control values, it can derive register values ​​and then update the shadow register.

[0093] Figure 5 An example diagram is shown illustrating the control process executed by a single core during a control cycle.

[0094] See Figure 5 In each control cycle, the core can perform processes such as obtaining sensed values ​​from the analog-to-digital converter (ADC), voltage control, current control, control value setting, and register configuration.

[0095] The converter controller may include multiple ADC channels. Each ADC channel can sense the current in each phase, the voltage of the DC link capacitor, the voltage of the output node, etc., and convert them into digital values. The core can acquire sensed values ​​from individual ADC channels during the initial time period of each control cycle.

[0096] The core can perform PFC voltage control based on the acquired ADC sensed values. For example, the core can execute a PFC voltage control process to perform a control algorithm designed to compare the sensed voltage value of the DC link capacitor with a reference voltage value and minimize the difference between the two values.

[0097] The core can perform PFC current control based on the ADC sensed values ​​and the results of the PFC voltage control process. For example, the core can execute the PFC current control process to perform a control algorithm that uses the sensed current value of each phase and the results calculated during the PFC voltage control process to maintain the current value of each phase at a consistent level.

[0098] The kernel can calculate the control values ​​(e.g., duty cycle and period) of the pulse width modulation (PWM) signal for each switch based on the results of the PFC current control process, and can store the calculated values ​​in predefined data variables.

[0099] The kernel can read values ​​stored in predefined data variables, calculate register values ​​based on these values, and configure registers with the calculated values.

[0100] Figure 6 This is a simplified diagram illustrating the problems that may occur when a single core controls two PFC (Power Factor Correction) circuits simultaneously during a single control cycle.

[0101] See Figure 6 A single core can control two PFC circuits. In this case, the core needs to calculate the control value for each PFC circuit separately, which may require executing the PFC voltage control process and the PFC current control process twice.

[0102] After acquiring the sensed values ​​from the analog-to-digital converter (ADC), the core can first execute voltage and current control procedures for the first PFC circuit. Then, the core can execute voltage and current control procedures for the second PFC circuit. Once the control values ​​for each PFC circuit have been calculated, the core can execute control value setting and register configuration procedures.

[0103] However, there is a possibility that a single core may not be able to complete all these processes within a single control cycle. Specifically, if a core is optimized for controlling a single PFC circuit, attempting to control two or more PFC circuits with the same core may result in the failure to execute each process within a single control cycle.

[0104] To address this issue, one example converter controller can use two cores to independently control each PFC circuit.

[0105] Figure 7 This is a diagram illustrating how two cores in a converter controller according to one embodiment control the corresponding PFC circuit.

[0106] refer to Figure 7 The first core can perform processing to acquire sensed values ​​from the analog-to-digital converter (ADC) connected to the first PFC circuit. The first core can then perform voltage control and current control processes for the first PFC circuit. Furthermore, the first core can perform processes to set the control values ​​required by the first PFC circuit and update the registers.

[0107] The second core can execute the process of acquiring sensed values ​​from the ADC connected to the second PFC circuit. Then, the second core can execute voltage control and current control processes for the second PFC circuit. Afterward, the second core can execute the control value setting process required by the second PFC circuit.

[0108] At this point, if the second core performs the register configuration process independently, there is a possibility of problems. When the first and second cores each execute the register configuration process, one core may configure the registers properly, while the other core may not. For example, the first core may complete the register configuration properly, but the second core may not.

[0109] In such a scenario, the first and second PFC circuits can be controlled without maintaining data consistency. Therefore, control values ​​(such as switching cycles) may not be synchronized, potentially leading to excessive current flowing through a particular circuit.

[0110] To address this issue, a method can be applied where a single core (e.g., the first core) configures registers for both PFC circuits. The first core can read control values ​​calculated by the second core, calculate register values ​​based on the calculated control values, and then configure registers for the second PFC circuit.

[0111] Figure 8 This is a configuration diagram of a converter controller according to one embodiment.

[0112] See Figure 8 The converter controller 130 may include a first core 810, a second core 820, a buffer 830, and a timer module 840.

[0113] The converter controller 130 can be configured as a microcontroller unit (MCU).

[0114] An MCU is an integrated circuit used in embedded systems that may include one or more processor cores. These cores can have a structure capable of performing 8-bit, 16-bit, 32-bit, or higher-bit data processing. Depending on the requirements of a specific application, an MCU may be designed to include multiple 32-bit cores. Such a design can provide the potential for parallel processing and high-performance computing tasks.

[0115] MCUs can be configured as hardware and software platforms for use in automotive and industrial applications. MCUs can operate in environments requiring high-performance computing, communication, and data processing. Therefore, MCUs can be used to control various sensors and actuators and execute complex control algorithms. MCUs can contribute to enhanced system stability and efficiency by generating control signals or processing data.

[0116] The MCU supports functional safety at ISO 26262 Automotive Safety Integrity Level-D (ASIL-D). This standard defines the requirements necessary to ensure safe operation in automotive applications. Based on these requirements, the MCU can include fault diagnosis, error detection, and recovery functions. This allows for the fulfillment of the hardware and software design elements needed to enhance the safety of automotive systems.

[0117] MCUs can conform to the Automotive Open Systems Architecture (AUTOSAR) 4.2 standard. This standard defines the software architecture of automotive electronic control units (ECUs), and MCUs can perform integrated functions within this architecture. By complying with AUTOSAR, MCUs can provide a software platform that ensures interoperability between various suppliers and systems.

[0118] An MCU may include communication interfaces, data processing capabilities, and security features. Communication interfaces may include Controller Area Network (CAN), Local Internet (LIN), FlexRay, and Ethernet, allowing the MCU to exchange data with external devices. Data processing capabilities can vary depending on the performance of the cores included in the MCU and the size of the memory. Furthermore, the MCU may provide hardware security features such as encryption modules or security authentication.

[0119] MCUs can perform sensor data collection and processing, as well as actuator control, through various input and output interfaces. This enables MCUs to support conversion tasks between the physical world and digital signals. Furthermore, MCUs can include functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and pulse-width modulation (PWM), allowing for a wide range of control and conversion tasks.

[0120] An MCU may include built-in memory and other memory. Embedded flash memory or electrically erasable programmable read-only memory (EEPROM) can be used to store program code and data, and random access memory (RAM) may be included to handle data required during execution. This memory architecture can be designed in different ways to meet the requirements of the application.

[0121] Both the first core 810 and the second core 820 can be one of multiple cores included in the MCU.

[0122] The first core 810 can acquire ADC sensing values ​​in each control cycle and execute voltage and current control processes for the first PFC circuit to calculate PWM control values ​​for the first switch included in the first PFC circuit, such as a first duty cycle value DT1 and a first cycle value FR1. The first core 810 can then store the control values ​​DT1 and FR1 for the first switch in a first data variable included in the buffer 830. Here, multiple first data variables may exist, and the first core 810 can select one of the multiple first data variables and store the control values ​​DT1 and FR1 for the first switch in the selected first data variable.

[0123] The second core 820 can acquire ADC sensing values ​​in each control cycle and execute voltage and current control processes for the second PFC circuit to calculate PWM control values ​​(e.g., a second duty cycle value DT2 and a second cycle value FR2) for the second switch included in the second PFC circuit. The second core 820 can then store the control values ​​DT2 and FR2 of the second switch in a second data variable included in the buffer 830. Here, multiple second data variables may exist, and the second core 820 can select one of the multiple second data variables and store the control values ​​DT2 and FR2 for the second switch in the selected second data variable.

[0124] Here, buffer 830 can be shared by the first core 810 and the second core 820. Therefore, the first core 810 can access not only the first data variable, but also the second data variable.

[0125] The first core 810 can verify data variables—for example, a first data variable and a second data variable—and configure registers for the PWM signals output to the first and second switches based on the values ​​of the data variables. At this time, the first core 810 can set the value of the shadow register SR included in the timer module 840.

[0126] The timer module 840 can be in the form of a GTM (General Purpose Timer Module).

[0127] GTM can be a hardware module capable of performing complex timing and event control tasks in embedded systems. This module can include different channels and can be used in applications requiring precise time-based control. GTM can provide hardware-based timing management capabilities to support tasks such as input signal processing, output signal generation, and timing control.

[0128] GTM can include submodules. These submodules can include substructures such as the Timer Output Module (TOM), the Advanced Timer Output Module (ATOM), the Timer Input Module (TIM), and the Time Base Unit (TBU). The TOM is a module that supports pulse width modulation (PWM) signal generation and can be designed to allow independent control for each channel. The ATOM is a timing control module that offers higher accuracy and flexibility than the TOM. The TIM can process input signals to detect timing events or capture timing data. The TBU provides a time base for reference during timer operation.

[0129] GTM may include an integrated clock management mechanism. The Clock Management Unit (CMU) can provide clock signals suitable for each submodule of the module and can control the frequency and precision of the timers. In this way, GTM can support operation for different timing requirements.

[0130] GTM supports multi-channel operation. This allows the Timer Module 840 to process multiple input and output signals simultaneously, with each channel being configured and controlled independently.

[0131] The timer module 840 may include multiple TOMs (TOM1, TOM2, TOM3, ..., TOM7, TOM8, TOM9, ...). Each TOM channel (TOM1, TOM2, TOM3, ..., TOM7, TOM8, TOM9, ...) can output a single PWM signal (PWM1a, PWM1b, PWM1c, ..., PWM2a, PWM2b, PWM2c, ...) to control the on / off state of the corresponding switch. For example, the first TOM channel (TOM1) can output the first PWM a-phase signal (PWM1a), the second TOM channel (TOM2) can output the first PWM b-phase signal (PWM1b), and the third TOM channel (TOM3) can output the first PWM c-phase signal (PWM1c). The seventh TOM channel (TOM7) can output the second PWM a-phase signal (PWM2a), the eighth TOM channel (TOM8) can output the second PWM b-phase signal (PWM2b), and the ninth TOM channel (TOM9) can output the second PWM c-phase signal (PWM2c).

[0132] Figure 9 This is a configuration diagram of the TOM channel according to the implementation method.

[0133] See Figure 9 The TOM channel can include registers such as a shadow register (SR), a first CN register (CN0: compare sign register 0), a first CM register (CM0: compare match register 0), and a second CM register (CM1: compare match register 1). The TOM channel can perform timer-based signal processing through these registers. Each register can perform a specific function in the process of generating or outputting PWM (pulse width modulation) signals.

[0134] The shadow register SR can be used as space to temporarily store values ​​during operation. This helps prevent immediate effects on the timer output when the register value is changed and provides a structure that allows for the reliable application of new values. This allows for designs that help maintain signal continuity and stability during PWM signal generation.

[0135] The first CN register, CN0, can be configured to store or compare the current value of a timer. It can be used to verify the current state of the timer or determine whether the timer's value has reached a specific reference. CN0 stores values ​​related to the timer period and can be used as a reference value required to generate the PWM signal period.

[0136] The first CM register CM0 and the second CM register CM1 can be used to store reference values ​​to be compared with the timer value. CM0 can be used to switch the PWM signal high or trigger a specific operation when the timer value reaches a certain point. When the timer value reaches another specific point, CM1 can be used to switch the PWM signal low or perform another operation. The duty cycle and period of the PWM signal can be determined based on the values ​​of these two registers.

[0137] The TOM channel may include an output unit 910 that generates PWM signals based on register settings. The output unit can process timer events based on register values ​​and generate PWM signals to send to external systems. The output unit (a block designed at the hardware level) is controlled by register values ​​and can operate in a manner that ensures the accuracy and consistency of the PWM signals.

[0138] Figure 10 This is a diagram illustrating the process and waveforms for the core to execute the main signal according to one embodiment.

[0139] See Figure 10 The ADC can perform sensing during the initial time period of each control cycle. Then, based on the sensing completion interrupt signal from the ADC, the first core can execute the first control procedure (PFC1C), and the second core can execute the second control procedure (PFC2C).

[0140] In the first control procedure (PFC1C), the first core can calculate the PWM control value of the first switch included in the first PFC circuit. In the first control procedure (PFC1C), the first core can execute a process of acquiring sensed values ​​from the ADC used in the first PFC circuit, a voltage control process, and a current control process, and subsequently calculate the PWM control value of the first switch. The first control procedure (PFC1C) can be executed in each control cycle.

[0141] In the second control process (PFC2C), the second core can calculate the PWM control value of the second switch included in the second PFC circuit. In the second control process (PFC2C), the second core can execute a process of acquiring sensed values ​​from the ADC used in the second PFC circuit, a voltage control process, and a current control process, and then calculate the PWM control value of the second switch. The second control process (PFC2C) can be executed for each control cycle.

[0142] After executing the first control procedure (PFC1C), the first core can store the calculated PWM control value of the first switch in the first data variable located in the buffer (PFC1S). After executing the second control procedure (PFC2C), the second core can store the calculated PWM control value of the second switch in the second data variable located in the buffer (PFC2S).

[0143] Based on the values ​​of the data variables stored in the buffer, the first core can configure registers for the PWM signal output to the first switch and registers for the PWM signal output to the second switch (T-ISR). This process can be executed in the first core's top-level ISR (Interrupt Service Routine). In the top-level ISR, the first core can configure registers for the PWM signal output to the first switch and registers for the PWM signal output to the second switch.

[0144] The top-level interrupt service routine (ISR) can be invoked a certain time before the start of a new control cycle, and the top-level ISR can complete before the start of a new control cycle. UPWM can be generated for each switching cycle Tctr / 2, and the next switching cycle can begin at the falling edge of the UPWM. The top-level ISR can be invoked at the rising edge of the UPWM generated for the second switching cycle of a control cycle Tctr. The first core can configure the registers for the PWM signal output to the first switch and the registers for the PWM signal output to the second switch based on the values ​​of data variables stored in the buffer, until the start of the next control cycle.

[0145] Meanwhile, if the PWM control values ​​for the first switch and the second switch are not properly stored in the first data variable and the second data variable before the first core configures the register for the PWM signal output to the first switch and the register for the PWM signal output to the second switch, data consistency may not be guaranteed.

[0146] According to one implementation, the converter controller may employ a multi-buffering method or a double-buffering method to ensure data consistency.

[0147] In the double-buffered method, two first data variables and two second data variables can reside in a buffer. A first core can select one of the two first data variables and store the PWM control value in the selected first data variable. A second core can select one of the two second data variables and store the PWM control value in the selected second data variable. The first core can alternately select and use the two first data variables. The second core can alternately select and use the two second data variables.

[0148] Multiple buffering can be viewed as an extension of double buffering. If multiple buffering uses two data variables, it can be used as a double buffering method.

[0149] In a multi-buffered approach, multiple first data variables can reside in a buffer. For example, there can be two or three first data variables. Additionally, multiple second data variables can reside in a buffer. Each type of data variable can be configured as an array. For example, the first data variables can be configured as DATA1[N], and the second data variables can be configured as DATA2[N]. Here, DATA1 is the variable name of the first data variable, and DATA2 is the variable name of the second data variable. The number of arrays N can be a natural number equal to or greater than 2.

[0150] The first core can select and use one of a plurality of first data variables, and the second core can select and use one of a plurality of second data variables. Both the first and second cores can select data variables based on a serial number. An index variable can be used to manage the serial number. For example, the first core can select a first data variable with a serial number corresponding to the value of a first index variable from a plurality of first data variables, and can store the PWM control value in the selected data variable. The second core can select a second data variable with a serial number corresponding to the value of a second index variable from a plurality of second data variables, and can store the PWM control value in the selected data variable.

[0151] Once storage is complete, the value of the index variable can be incremented. The first core can store the PWM control value in the selected first data variable and then increment the value of the first index variable. The second core can store the PWM control value in the selected second data variable and then increment the value of the second index variable. If the value of the index variable reaches the number of data variables, such as N, the value of the index variable can be reset to its initial value, such as 0. For example, in the double-buffered method, the value of the index variable can be changed in the order 0→1→0. If the number of data variables N is 3, the value of the index variable can be changed in the order 0→1→2→0.

[0152] Such an index variable can also reside in a buffer shared by the first and second cores. The first core can verify a data variable selected by the index variable based on a sequence number. The first core can verify the PWM control value from the data variable corresponding to the sequence number indicated by the index variable's value, or from the data variable corresponding to a sequence number preceding the sequence number indicated by the index value. After storing the PWM control value in the data variable, the first and second cores can change the index variable. At this time, the sequence number selected in the current control cycle or the sequence number selected in the next control cycle can be stored in the index variable. Once the sequence number selected for the current control cycle is stored in the index variable, the first core can verify the PWM control value from the data variable corresponding to the sequence number indicated by the index variable's value. Then, once the sequence number to be selected for the next control cycle is stored in the index variable, the first core can verify the PWM control value from the data variable corresponding to the sequence number preceding the sequence number indicated by the index variable's value. Based on the verified PWM control value, the first core can then configure registers for the PWM signal output to the first switch and registers for the PWM signal output to the second switch.

[0153] In one implementation, the first core manages multiple data variables not only for the second core but also for itself. This is because the register configuration process is performed in the top-level ISR. When the top-level ISR is called, other processes are interrupted. In this situation, if the process of storing PWM control values ​​in data variables is interrupted, the data variables may not be fully stored in the first core. Therefore, both the first and second cores can use a multi-buffered or dual-buffered approach to manage the data variables.

[0154] Figure 11 This is a flowchart illustrating a converter control method according to one embodiment.

[0155] See Figure 11 The first core can calculate PWM control values ​​for a first switch included in the first PFC circuit (S1100). The PWM control values ​​may include at least one of a value indicating the duty cycle of the PWM signal and a value indicating the period of the PWM signal.

[0156] Then, the second core can calculate the PWM control value for the second switch included in the second PFC circuit (S1102).

[0157] Then, the first core can store the PWM control value for the first switch in one of a plurality of first data variables selected according to a sequence number (S1104). The plurality of first data variables can be configured as an array, and one of the data variables in the array can be selected according to a sequence number. For example, the sequence number can be stored in an index variable, and the first data variable corresponding to the value of the index variable can be selected from the array of first data variables. If two first data variables exist, the first core can store the PWM control value for the first switch in one of the two first data variables. These two data variables can be selected and used alternately.

[0158] Then, the second core can store the PWM control value of the second switch in one of a plurality of second data variables selected according to a sequence number (S1106). The plurality of second data variables can be configured as an array, and one of the data variables in the array can be selected according to a sequence number. For example, the sequence number can be stored in an index variable, and the second data variable corresponding to the value of the index variable can be selected from the array of second data variables. If two second data variables exist, the second core can store the PWM control value of the second switch in one of the two second data variables. These two data variables can be selected and used alternately.

[0159] Then, the first core can configure the register for the PWM signal output to the first switch based on the value of the selected first data variable, and can configure the register for the PWM signal output to the second switch based on the value of the selected second data variable (S1108).

[0160] The first and second cores can store the sequence number selected for the current control cycle or the sequence number to be selected for the next control cycle in an index variable. Using this index variable, the first core can verify the data variable storing the PWM control value in the current control cycle and configure the registers used for PWM signal output based on the value of this data variable.

[0161] This step S1108 can be executed in the top-level ISR of the first core. This top-level ISR can be invoked for a certain period of time before the start of a new control cycle, and can complete before the start of a new control cycle.

[0162] Figure 12 yes Figure 11 The detailed flowchart of step S1104 in the flowchart is shown below.

[0163] See Figure 12 The first core can verify the value of the first index variable DATA_INDEX1 (S1202). Based on the value of the first index variable, the first core can select a data variable to store the PWM control value for the first switch.

[0164] When the value of the first index variable is 0 (0 at S1202), the first core can select the first variable DATA1[0] from a plurality of first data variables. Then, the first core can store the PWM control value (e.g., duty cycle value DT1 and / or frequency value FR1) for the first switch in the first variable DATA1[0] (S1204). The first core can change the value of the first index variable to 1 (S1206).

[0165] When the value of the first index variable is 1 (1 at S1202), the first core can select the second first data variable DATA1[1] from a plurality of first data variables. Then, the first core can store the PWM control value (e.g., duty cycle value DT1 and / or frequency value FR1) for the first switch in the second first data variable DATA1[1] (S1204). The first core can change the value of the first index variable to 0 (S1210).

[0166] Figure 13 yes Figure 11 The detailed flowchart of step S1106 in the flowchart is shown below.

[0167] See Figure 13 The second core can verify the value of the second index variable DATA_INDEX2 (S1302). Based on the value of the second index variable, the second core can select the data variable that stores the PWM control value of the second switch.

[0168] When the value of the second index variable is 0 (0 at S1302), the second core can select the first second data variable DATA2[0] from a plurality of second data variables. Then, the second core can store the PWM control values ​​for the second switch - such as the duty cycle value DT2 and / or the frequency value FR2 - in the first second data variable (DATA2[0]) (S1304). The second core can change the value of the second index variable to 1 (S1306).

[0169] When the value of the second index variable is 1 (1 at S1302), the second core can select the second variable DATA2[1] from multiple second data variables. Then, the second core can store the PWM control value of the second switch - such as the duty cycle value DT2 and / or the frequency value FR2 - in the second variable (DATA2[1]) (S1308). The second core can change the value of the second index variable to 0 (S1310).

[0170] Figure 14 yes Figure 11 The detailed flowchart of step S1108 in the flowchart.

[0171] See Figure 14The first core can verify the value of the first index variable DATA_INDEX1 (S1402). Based on the value of the first index variable, the first core can verify one of the multiple first data variables.

[0172] When the value of the first index variable is 0 (0 at S1402), the first core can select the second first data variable DATA1[1] from multiple first data variables. Then, the first core can configure the register for the PWM signal output to the first switch based on the value of the second first data variable DATA1[1] (S1404).

[0173] The step S1404 of configuring the register may include steps of calculating the value of the register and setting the register to those values.

[0174] For example, the first core can calculate a first CN register value to correspond to a value indicating the period of the PWM signal included in the PWM control value. The first core can store the first CN register value in a shadow register corresponding to the first CN register. The value stored in a shadow register can be transferred to the first CN register at the start of the next control cycle.

[0175] As another example, the first core can calculate the values ​​of a first CM register and a second CM register to correspond to the duty cycle of the PWM signal included in the PWM control values. The first CM register value can be a value used to set the rising edge of the PWM signal—for example, the rising edge time value—and the second CM register value can be a value used to set the falling edge of the PWM signal—for example, the falling edge time value. Additionally, the first core can store the first CM register value in another shadow register corresponding to the first CM register, and can store the second CM register value in yet another shadow register corresponding to the second CM register. At the start of the next control cycle, the values ​​stored in the other shadow register and the values ​​stored in the other shadow register can be sent to the first CM register and the second CM register, respectively.

[0176] In step S1404 of the configuration register, the first core can basically configure shadow registers corresponding to TOM.

[0177] In step S1402, when the value of the first index variable is 1 (1 at S1402), the first core can select the first variable DATA1[0] from a plurality of first data variables. Then, based on the value of the first variable DATA1[0], the first core can configure the register for the PWM signal output to the first switch (S1406).

[0178] Then, the first core can verify the value of the second index variable DATA_INDEX2 (S1408). Based on the value of the second index variable, the first core can verify one of multiple second data variables.

[0179] When the value of the second index variable is 0 (0 at S1408), the first core can select the second variable DATA2[1] from multiple second data variables. Then, based on the value of the second variable DATA2[1], the first core can configure the register for the PWM signal output to the second switch (S1410).

[0180] When the value of the second index variable is 1 (1 at S1408), the first core can select the first second data variable DATA2[0] from multiple second data variables. Then, based on the value of the first second data variable DATA2[0], the first core can configure the register for the PWM signal output to the second switch (S1412).

[0181] As described above, according to this disclosure, multiple PFC circuits can be controlled synchronously. Furthermore, according to this disclosure, data consistency can be ensured when multiple PFC circuits are controlled by different cores.

[0182] As used herein, terms such as “include,” “comprise,” or “have” should be interpreted as indicating the possibility of inclusion unless otherwise expressly stated, and therefore should not be interpreted as excluding other components but allowing the inclusion of additional components. Unless otherwise defined, all terms (including technical and scientific terms) should be interpreted as having the meaning commonly understood by one of ordinary skill in the art to which this disclosure pertains. Common terms, such as those defined in dictionaries, should be interpreted according to their meaning in the context of the relevant technical field, and should not be interpreted in an idealized or overly formal sense unless explicitly defined in this disclosure.

[0183] The above description is merely an illustration of the technical concept of this disclosure, and those skilled in the art will understand that various modifications and changes can be made without departing from the essential characteristics of this disclosure. Therefore, the embodiments disclosed herein are intended to illustrate (not limit) the technical concept of this disclosure, and the scope of the technical concept should not be construed as being limited by these embodiments. The scope of protection of this invention should be determined by the scope of the claims, and all technical concepts falling within the equivalent scope should be determined by the scope of the claims.

Claims

1. A converter controller, comprising: The first core is configured to: Calculate the PWM control value of the first switch included in the first PFC circuit; and Configure a register for the PWM signal output to the first switch; as well as The second core is configured to: Calculate the PWM control value of the second switch included in the second PFC circuit; and The PWM control value of the second switch is stored in one of a plurality of second data variables selected according to the serial number. The first core is also configured to configure the register of the PWM signal output to the second switch based on the value of the selected second data variable.

2. The converter controller according to claim 1, wherein, The second core is also configured to store the PWM control value of the second switch in one of two second data variables. In this process, the two second data variables are selected and used alternately.

3. The converter controller according to claim 1, wherein, The second core is also configured to store the sequence number selected for the current control cycle or the sequence number selected for the next control cycle among the plurality of second data variables in an index variable.

4. The converter controller according to claim 3, wherein, The first core is also configured to validate a second data variable selected by the index variable according to the sequence number.

5. The converter controller according to claim 1, wherein, The plurality of second data variables are configured as an array, and one of the second data variables in the array is selected according to the sequence number.

6. The converter controller according to claim 1, wherein, The first core is also configured to store the PWM control value of the first switch in one of a plurality of first data variables selected according to a sequence number.

7. The converter controller according to claim 6, wherein, The first core is also configured as follows: The register for the PWM signal output to the first switch is configured based on the value of the selected first data variable; and The register for the PWM signal output to the second switch is configured based on the value of the selected second data variable.

8. The converter controller according to claim 1, wherein, In the top-level ISR, the first core is also configured as follows: Configure the register for the PWM signal output to the first switch; and Configure a register for the PWM signal output to the second switch.

9. The converter controller according to claim 1, in, The first core is also configured as follows: In each control cycle, the process of acquiring sensed values ​​from the ADC used in the first PFC circuit, the voltage control process, and the current control process are executed; and Calculate the PWM control value of the first switch, wherein the second core is further configured as follows: In each control cycle, the process of acquiring sensed values ​​from the ADC used in the second PFC circuit, the voltage control process, and the current control process are executed; and Calculate the PWM control value of the second switch.

10. A converter control method, comprising: The first core calculates the PWM control value of the first switch included in the first PFC circuit; The second core calculates the PWM control value of the second switch included in the second PFC circuit; The first core stores the PWM control value of the first switch in one of a plurality of first data variables selected according to the serial number; The second core stores the PWM control value of the second switch in one of a plurality of second data variables selected according to the serial number; and The first core configures the register for the PWM signal output to the first switch based on the value of a selected first data variable, and configures the register for the PWM signal output to the second switch based on the value of a selected second data variable.

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