Semiconductor device and electronic apparatus

Abstract

This disclosure provides a semiconductor device and electronic device in which the drift region is made of AlN, which can improve the device's breakdown voltage or reduce the drift region thickness at the same breakdown voltage, thereby reducing on-resistance and epitaxial cost and difficulty. At least one of the following is formed between the drift region and the source metal through distributed polarization doping: an N+ type AlGaN current extension layer, a P- type body region, and an N+ type source ohmic contact region. Since the Al composition content in at least one of these three layers gradually changes away from the N++ type conductive substrate, a certain concentration of electrons or holes is induced through the polarization effect, which can increase the electron or hole concentration of the corresponding layer. That is, at least one layer is a high carrier concentration layer formed by unintentional doping, which can optimize current distribution and reduce device on-resistance. Since at least one of the above three layers is formed by distributed polarization doping, the carriers have higher mobility, avoiding the diffusion of dopants in high-temperature environments that could affect device performance.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor device and electronic device. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are core devices in modern power electronic systems, widely used in switching power supplies, motor drives, and new energy conversion. MOSFETs are classified into planar MOSFETs and vertical MOSFETs based on their current path. Vertical MOSFETs are widely used because they can achieve a synergistic optimization of low on-resistance and high breakdown voltage.

[0003] Vertical MOSFETs are classified into planar gate vertical MOSFETs and trench gate vertical MOSFETs based on their gate structure. Planar gate vertical MOSFETs refer to MOSFETs where the gate structure is laid flat on the surface and the channel is parallel to the substrate surface. However, they have the following challenges: 1) The JFET effect leads to an increase in on-resistance, which is particularly noticeable in high-voltage applications; 2) The parasitic capacitance between the gate and drain is high, which affects the switching speed and increases switching losses.

[0004] Trench-gate vertical MOSFETs (VMOSFETs) achieve the following performance breakthroughs by embedding the gate within a trench etched into the semiconductor to form a vertical channel: 1) The trench gate eliminates the JFET effect, reducing the total on-resistance. 2) Smaller cell spacing and higher cell density. 3) Reduced lateral overlap between the gate and drain reduces parasitic capacitance, accelerates switching transient response, and reduces switching losses.

[0005] However, trench gate vertical MOSFETs also have the following main problems: 1) The trench etching process increases sidewall roughness, affecting the quality of the gate oxide layer and the consistency and stability of the threshold voltage. 2) Electric field concentration at the trench corners may cause premature breakdown of the device. The diffusion of N-type and P-type doped impurities at high temperatures leads to a decrease in device performance, limiting the application of the device at high temperatures and high voltages, and severely restricting the device's lifespan. 3) The device is incompatible with high frequency, high switching speed, and high voltage withstand capability.

[0006] Therefore, those skilled in the art urgently need to solve the bottlenecks encountered by trench gate vertical MOSFET devices in high-temperature, high-voltage, and high-current applications. Summary of the Invention

[0007] This disclosure provides a semiconductor device and electronic device to improve the device's voltage withstand capability, reduce its on-resistance, and lower epitaxial cost and complexity, thereby achieving high power efficiency and accelerating its application in high-temperature, high-voltage, and high-switching-frequency fields. The specific solution is as follows: On one hand, embodiments of this disclosure provide a semiconductor device, including: an N++ type conductive substrate, a drain metal located on one side of the N++ type conductive substrate, and an N-type AlN drift region, an N+ type AlGaN current spreading layer, a P-type body region, an N+ type source ohmic contact region, and a source metal sequentially stacked on the side of the N++ type conductive substrate away from the drain metal; wherein, The surfaces of the N-type AlN drift region, the N+ type AlGaN current spreading layer, the P-type body region, and the N+ type source ohmic contact region that are away from the N++ type conductive substrate are all nitrogen polar surfaces. The Al composition content of at least one of the N+ type AlGaN current spreading layer, the P-type body region, and the N+ type source ohmic contact region gradually changes along the direction away from the N++ type conductive substrate.

[0008] In one possible implementation, in the semiconductor device provided in the embodiments of this disclosure, the Al component content in the N+ type AlGaN current spreading layer gradually decreases along the direction away from the N++ type conductive substrate.

[0009] In one possible implementation, in the semiconductor device provided in the embodiments of this disclosure, with the metal atom content in the N+ type AlGaN current extension layer being 100%, the initial content of the bottom Al component in the N+ type AlGaN current extension layer near the N++ type conductive substrate is 100%~50%, and the final content of the top Al component in the N+ type AlGaN current extension layer away from the N++ type conductive substrate is 50%~0%.

[0010] In one possible implementation, in the semiconductor device provided in the embodiments of this disclosure, the material of the P-type body region is P-type ion-doped P-type GaN, and the material of the N+ type source ohmic contact region is N-type ion-doped N+ type GaN.

[0011] In one possible implementation, in the semiconductor device provided in the embodiments of this disclosure, the material of the P-type body region is unintentionally doped P-type AlGaN, and the Al component content in the unintentionally doped P-type AlGaN gradually increases in the direction away from the N++ type conductive substrate.

[0012] In one possible implementation, in the semiconductor device provided in the embodiments of this disclosure, with the metal atom content in the unintentionally doped P-type AlGaN being 100%, the initial content of the bottom Al component in the unintentionally doped P-type AlGaN near the N++ type conductive substrate is 50% to 0%, and the final content of the top Al component in the unintentionally doped P-type AlGaN away from the N++ type conductive substrate is 100% to 50%.

[0013] In one possible implementation, in the semiconductor device provided in the embodiments of this disclosure, the material of the N+ type source ohmic contact region is unintentionally doped N+ type AlGaN, and the Al component content in the unintentionally doped N+ type AlGaN gradually decreases in the direction away from the N++ type conductive substrate.

[0014] In one possible implementation, in the semiconductor device provided in the embodiments of this disclosure, with the metal atom content in the unintentionally doped N+ type AlGaN being 100%, the initial content of the bottom Al component in the unintentionally doped N+ type AlGaN near the N++ type conductive substrate is 100%~50%, and the final content of the top Al component in the unintentionally doped N+ type AlGaN away from the N++ type conductive substrate is 50%~0%.

[0015] In one possible implementation, in the semiconductor device provided in the embodiments of this disclosure, the thickness of the N-type AlN drift region is 1 µm to 20 µm, the thickness of the N+ type AlGaN current spreading layer is 10 nm to 300 nm, the thickness of the P-type body region is 200 nm to 5000 nm, and the thickness of the N+ type source ohmic contact region is 50 nm to 500 nm.

[0016] In one possible implementation, the semiconductor device provided in the embodiments of this disclosure further includes: a gate trench extending from the surface of the N+ type source ohmic contact region away from the N++ type conductive substrate to the N- type AlN drift region; a gate dielectric layer located on the inner wall of the gate trench; a gate metal covering the gate dielectric layer and filling the gate trench; and a source metal located on the side of the N+ type source ohmic contact region away from the N++ type conductive substrate and located outside the gate trench; the source metal is in contact with the P-type body region.

[0017] In one possible implementation, in the semiconductor device provided in the embodiments of this disclosure, the inner wall of the gate trench extending into the N-type AlN drift region is arc-shaped.

[0018] On the other hand, embodiments of this disclosure also provide an electronic device, including any of the semiconductor devices described above in embodiments of this disclosure.

[0019] The beneficial effects of this disclosure are as follows: This disclosure provides a semiconductor device and electronic device in which the N-type AlN drift region uses AlN material with an ultra-wide bandgap and high breakdown field strength (>15 MV / cm) instead of traditional GaN material. This can improve the device's withstand voltage capability, or reduce the thickness of the drift region under the same withstand voltage, thereby reducing the on-resistance, epitaxial cost and difficulty, achieving high power figure of merit for the device, and accelerating the application of the device in high withstand voltage and high switching frequency fields. Meanwhile, the drift region adopts nitrogen-polarized AlN. At least one of the following layers is formed between the drift region and the source metal through distributed polarization doping: an N+ type AlGaN current extension layer, a P- type body region, and an N+ type source ohmic contact region. Since the Al composition content in at least one of the N+ type AlGaN current extension layer, P- type body region, and N+ type source ohmic contact region gradually changes in the direction away from the N++ type conductive substrate, a certain concentration of electrons or holes can be induced through the polarization effect, which can increase the electron or hole concentration of the corresponding layer. Thus, at least one of the N+ type AlGaN current extension layer, P- type body region, and N+ type source ohmic contact region is a high carrier concentration layer formed by unintentional doping, which can optimize the current distribution, suppress the increase in on-resistance caused by current congestion, and further reduce the on-resistance of the device. In addition, by using unintentional distributed polarization doping to form at least one of the N+ type AlGaN current extension layer, P- type bulk region, and N+ type source ohmic contact region, the carrier mobility is higher, while the diffusion of normally doped impurities in high-temperature environments can be avoided, thus improving the high-temperature stability of the device. Attached Figure Description

[0020] Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure; Figure 2 This is another schematic diagram of the structure of a semiconductor device provided in an embodiment of this disclosure; Figure 3 for Figure 1 Al composition variation diagram of N-type AlN drift region, N+ type AlGaN current spreading layer, P-type bulk region and N+ type source ohmic contact region along the direction away from N++ type conductive substrate AA'; Figure 4 for Figure 2 Al composition variation diagram of N-type AlN drift region, N+ type AlGaN current spreading layer, P-type bulk region and N+ type source ohmic contact region along the direction away from N++ type conductive substrate BB'; Figure 5 I-transmission of semiconductor devices provided in embodiments of this disclosure ds -V gs curve; Figure 6 for Figure 5 Corresponding Log diagram; Figure 7 Turn-off breakdown curves for semiconductor devices provided in embodiments of this disclosure; Figure 8 for Figure 7 The corresponding Log diagram. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes do not represent the precise shape of the illustrated regions or reflect true proportions; they are only intended to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0022] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0023] In the following description, when a component or layer is referred to as "on" or "connected to" another component or layer, the component or layer may be directly on or directly connected to the other component or layer, or there may be intermediate components or intermediate layers. When a component or layer is referred to as "located on one side of" another component or layer, the component or layer may be directly on or directly connected to the other component or layer, or there may be intermediate components or intermediate layers. However, when a component or layer is referred to as "directly on" or "directly connected to" another component or layer, there are no intermediate components or intermediate layers. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0024] This disclosure provides a semiconductor device, such as... Figure 1 and Figure 2 As shown, Figure 1 This is a schematic cross-sectional view of a semiconductor device. Figure 2 This is another cross-sectional schematic diagram of a semiconductor device, which includes: an N++ type conductive substrate 1, a drain metal 2 located on one side of the N++ type conductive substrate 1, and N-type AlN drift region 3, N+ type AlGaN current spreading layer 4, P-type body region 5, N+ type source ohmic contact region 6, and source metal 7, which are sequentially stacked on the side of the N++ type conductive substrate 1 away from the drain metal 2; wherein... The surfaces of the N-type AlN drift region 3, the N+ type AlGaN current spreading layer 4, the P-type bulk region 5, and the N+ type source ohmic contact region 6 that are far from the N++ type conductive substrate 1 are all nitrogen polar surfaces. The Al composition content of at least one of the N+ type AlGaN current spreading layer 4, P- type bulk region 5, and N+ type source ohmic contact region 6 gradually changes along the direction away from the N++ type conductive substrate 1, such as... Figure 3 and Figure 4 As shown, Figure 3 for Figure 1 Diagram showing the Al composition variation of the N-type AlN drift region 3, N+ type AlGaN current spreading layer 4, P-type bulk region 5, and N+ type source ohmic contact region 6 along the direction away from the N++ type conductive substrate 1, AA'. Figure 4 for Figure 2 Al composition variation diagram of N-type AlN drift region 3, N+ type AlGaN current spreading layer 4, P-type bulk region 5 and N+ type source ohmic contact region 6 along the direction away from N++ type conductive substrate 1 BB'.

[0025] The semiconductor device provided in this disclosure uses AlN material with an ultra-wide bandgap and high breakdown field strength (>15 MV / cm) in the N-type AlN drift region instead of traditional GaN material. This can improve the device's withstand voltage capability, or reduce the thickness of the drift region under the same withstand voltage, thereby reducing the on-resistance, epitaxial cost and difficulty, achieving high power figure of merit for the device, and accelerating the application of the device in the field of high withstand voltage and high switching frequency. Meanwhile, the drift region adopts nitrogen-polarized AlN. At least one of the following layers is formed between the drift region and the source metal through distributed polarization doping: an N+ type AlGaN current extension layer, a P- type body region, and an N+ type source ohmic contact region. Since the Al composition content in at least one of the N+ type AlGaN current extension layer, P- type body region, and N+ type source ohmic contact region gradually changes in the direction away from the N++ type conductive substrate, a certain concentration of electrons or holes can be induced through the polarization effect, which can increase the electron or hole concentration of the corresponding layer. Thus, at least one of the N+ type AlGaN current extension layer, P- type body region, and N+ type source ohmic contact region is a high carrier concentration layer formed by unintentional doping, which can optimize the current distribution, suppress the increase in on-resistance caused by current congestion, and further reduce the on-resistance of the device. In addition, by using unintentional distributed polarization doping to form at least one of the N+ type AlGaN current extension layer, P- type bulk region, and N+ type source ohmic contact region, the carrier mobility is higher, while the diffusion of normally doped impurities in high-temperature environments can be avoided, thus improving the high-temperature stability of the device.

[0026] In some embodiments, the N++ type conductive substrate 1 can be any one of the N++ type conductive Si substrate, N++ type conductive SiC substrate, N++ type conductive GaN substrate, N++ type conductive QST substrate, and N++ type conductive AlN substrate.

[0027] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-4As shown, the Al content in the N+ type AlGaN current extension layer 4 gradually decreases along the direction away from the N++ type conductive substrate 1. Because the Al content in this N+ type AlGaN current extension layer 4 gradually decreases along the direction away from the N++ type conductive substrate 1, a certain concentration of electrons can be induced through the polarization effect, increasing the electron concentration of this layer and thus forming an unintentionally doped high-electron-concentration N+ type AlGaN current extension layer 4. When the gate metal voltage of the device increases, the P-type body region near the gate metal inverts, forming a current channel, and the device turns on. The N+ type AlGaN current extension layer 4 makes the current distribution in the drift region more uniform, optimizing the current distribution and suppressing the increase in on-resistance caused by current congestion, further reducing the device's on-resistance. Furthermore, the N+ type AlGaN current extension layer 4 formed using an unintentionally doped distributed polarization doping method exhibits higher carrier mobility and avoids the diffusion of normally doped impurities in high-temperature environments, thus improving the device's high-temperature stability.

[0028] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figures 1-4 As shown, taking the metal atom content in the N+ type AlGaN current-spreading layer 4 as 100%, Figure 3 and Figure 4 In this paper, N+AlGaN is used to represent the N+ type AlGaN current spreading layer 4. The initial content of Al component on the bottom surface of the N+ type AlGaN current spreading layer 4, which is close to the N++ type conductive substrate 1, can be 100%~50%. It is understood that the initial content of Al component on the bottom surface is not 100%, for example, 95%, 90%, 85%, 80%, 75%, 70%, 65%, 60%, 55%, 50%, etc. The final content of Al component on the top surface of the N+ type AlGaN current spreading layer 4, which is far from the N++ type conductive substrate 1, can be 50%~0%. It is understood that the final content of Al component on the top surface is not 0%, for example, 50%, 45%, 40%, 35%, 30%, 25%, 20%, 15%, 10%, 5%, etc.

[0029] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 1 and Figure 3 As shown, the material of the P-type body region 5 can be P-type GaN doped with P-type ions, where the P-type ions can be Mg, etc. Figure 1 and Figure 3 P-GaN is used to represent the P-type bulk region 5; the material of the N+ type source ohmic contact region 6 can be N+ type GaN doped with N-type ions, where N-type ions can be Si, etc. Figure 1 and Figure 3 N+GaN is used to represent the N+ type source ohmic contact region 6. That is, in this embodiment... Figure 1The P-type body region 5 is realized by ion doping, and the N+ type source ohmic contact region 6 is realized by ion doping.

[0030] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 2 and Figure 4 As shown, the material of the P-type body region 5 can be unintentionally doped P-type AlGaN. Figure 2 and Figure 4 In this embodiment, P-AlGaN is used to represent the P-type body region 5. The Al content in the unintentionally doped P-type AlGaN gradually increases in the direction away from the N++ type conductive substrate 1. That is, the P-type body region 5 in this embodiment achieves P-type doping using distributed polarization doping. Since the Al content in this layer gradually increases in the direction away from the N++ type conductive substrate 1, a certain concentration of holes can be induced through the polarization effect, thus forming the P-type body region 5. The distributed polarization doping method for P-type doping in the P-type body region 5 results in higher carrier mobility, faster switching speed and frequency, and reduced losses. Simultaneously, it avoids the diffusion of normally doped impurities in high-temperature environments, which could affect device performance, further improving the high-temperature stability of the device.

[0031] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 2 and Figure 4 As shown, taking the metal atom content in the unintentionally doped P-type AlGaN (i.e., P-type body region 5) as 100%, the initial content of the bottom Al component in the unintentionally doped P-type AlGaN near the N++ type conductive substrate 1 can be 50%~0%. It is understood that the initial content of the bottom Al component is not 0%, for example, 50%, 45%, 40%, 35%, 30%, 25%, 20%, 15%, 10%, 5%, etc. The termination content of the top Al component in the unintentionally doped P-type AlGaN away from the N++ type conductive substrate 1 can be 100%~50%. It is understood that the termination content of the top Al component is not 100%, for example, 95%, 90%, 85%, 80%, 75%, 70%, 65%, 60%, 55%, 50%, etc.

[0032] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 2 and Figure 4 As shown, the material of the N+ type source ohmic contact region 6 can be unintentionally doped N+ type AlGaN. Figure 2 and Figure 4In this embodiment, N+AlGaN is used to represent the N+ type source ohmic contact region 6. The Al content in the unintentionally doped N+ type AlGaN gradually decreases along the direction away from the N++ type conductive substrate 1. That is, the N+ type source ohmic contact region 6 in this embodiment uses distributed polarization doping to achieve a heavily doped N-type layer. The Al content in this layer gradually decreases along the direction away from the N++ type conductive substrate 1, thus allowing a certain concentration of electrons to be induced through the polarization effect, thereby forming a high-electron-concentration N+ type source ohmic contact region 6. The distributed polarization doping method for achieving heavily doped N+ type source ohmic contact region 6 results in higher carrier mobility, faster switching speed and frequency, and reduced losses. Simultaneously, it avoids the diffusion of normally doped impurities in high-temperature environments, which could affect device performance, further improving the high-temperature stability of the device.

[0033] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 2 and Figure 4 As shown, taking the metal atom content in the unintentionally doped N+ type AlGaN (i.e., N+ type source ohmic contact region 6) as 100%, the initial content of the bottom Al component in the unintentionally doped N+ type AlGaN near the N++ type conductive substrate 1 can be 100%~50%. It is understood that the initial content of the bottom Al component is not 100%, for example, 95%, 90%, 85%, 80%, 75%, 70%, 65%, 60%, 55%, 50%, etc.; the termination content of the top Al component in the unintentionally doped N+ type AlGaN away from the N++ type conductive substrate 1 can be 50%~0%. It is understood that the termination content of the top Al component is not 0%, for example, 50%, 45%, 40%, 35%, 30%, 25%, 20%, 15%, 10%, 5%, etc.

[0034] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 1 and Figure 2 As shown, the thickness of the N-type AlN drift region 3 can be 1 µm to 20 µm, the thickness of the N+ type AlGaN current spreading layer 4 can be 10 nm to 300 nm, the thickness of the P-type bulk region 5 can be 200 nm to 5000 nm, and the thickness of the N+ type source ohmic contact region 6 can be 50 nm to 500 nm.

[0035] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 1 and Figure 2 As shown, the N+ type AlGaN current extension layer 4, the P- type body region 5, and the N+ type source ohmic contact region 6 may contain a certain percentage of In composition.

[0036] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 1 and Figure 2 As shown, it also includes: a gate trench U extending from the surface of the N+ type source ohmic contact region 6 away from the N++ type conductive substrate 1 into the N- type AlN drift region 3; a gate dielectric layer 8 located on the inner wall of the gate trench U; a gate metal 9 covering the gate dielectric layer 8 and filling the gate trench U; and a source metal 7 located on the side of the N+ type source ohmic contact region 6 away from the N++ type conductive substrate 1 and located on the periphery of the gate trench U; the source metal 7 is in contact with the P- type body region 5. Specifically, the source metal 7 can contact the P- type body region 5 through a contact hole V penetrating the N+ type source ohmic contact region 6, so that the semiconductor device formed in this embodiment is a trench gate vertical MOSFET device.

[0037] In some embodiments, in the semiconductor devices provided in the present disclosure, such as Figure 1 and Figure 2 As shown, the inner wall of the gate trench U extending into the N-type AlN drift region 3 is arc-shaped, which can optimize the electric field distribution and improve the device's withstand voltage capability.

[0038] It should be noted that this disclosure Figure 1 Taking the example of the Al composition content of the N+ type AlGaN current spreading layer 4 gradually changing along the direction away from the N++ type conductive substrate 1, the following is a case study. Figure 2 Taking the gradual change of Al content in each of the N+ type AlGaN current spreading layer 4, P- type body region 5, and N+ type source ohmic contact region 6 as an example, it is possible that only the Al content in the P- type body region 5 gradually changes in the direction away from the N++ type conductive substrate 1; or only the Al content in the N+ type source ohmic contact region 6 gradually changes in the direction away from the N++ type conductive substrate 1; or the Al content in both the N+ type AlGaN current spreading layer 4 and the P- type body region 5 gradually changes in the direction away from the N++ type conductive substrate 1; or the Al content in each of the N+ type AlGaN current spreading layer 4 and the N+ type source ohmic contact region 6 gradually changes in the direction away from the N++ type conductive substrate 1; or the Al content in both the P- type body region 5 and the N+ type source ohmic contact region 6 gradually changes in the direction away from the N++ type conductive substrate 1. The specific trend of Al content change in each layer is described above.

[0039] The inventor in this case Figure 1The semiconductor device structure shown was subjected to IV characteristic simulation. The lateral lengths of the source metal 7, drain metal 2, and gate metal 9 are 3.5 μm, 11.2 μm, and 4.0 μm, respectively. The thicknesses of the N-type AlN drift region 3, N+ type AlGaN current spreading layer 4, P-type bulk region 5, and N+ type source ohmic contact region 6 are 7.0 μm, 0.1 μm, 3.5 μm, and 0.2 μm, respectively. The carrier concentration of the N-type AlN drift region 3 is 1E16 cm⁻¹. -3 ,like Figures 5-8 As shown, Figure 5 I for device transmission ds -V gs (Source-drain current - gate-source voltage) curve, Figure 6 for Figure 5 The corresponding Log diagram, Figure 7 The turn-off breakdown curve of the device (I) ds -V ds ), Figure 8 for Figure 7 The corresponding Log diagram shows that the device's threshold voltage is 6.1 V and the saturation current is 170 A / cm². 2 The withstand voltage is 2025 V, indicating that the semiconductor device provided in this disclosure can improve the device's withstand voltage capability.

[0040] In some embodiments, Figure 1 and Figure 2 The semiconductor devices shown are all based on nitrogen polar plane epitaxial layers on N++ type conductive substrate 1. In order to better understand the above-mentioned semiconductor devices provided in the embodiments of this disclosure, this disclosure uses... Figure 1 Taking the semiconductor device shown as an example, the fabrication process of this semiconductor device will be described in detail. The fabrication process of this semiconductor device specifically includes the following steps: (1) Epitaxial layer growth: The epitaxial wafer required for the preparation of semiconductor devices can be obtained by sequentially growing an N-type AlN drift region 3, an N+ type AlGaN current spreading layer 4, a P-type body region 5, and an N+ type source ohmic contact region 6 on an N++ type conductive substrate 1 using metal-organic chemical vapor deposition (MOCVD) technology. Among them, the Al content in the N+ type AlGaN current spreading layer 4 gradually decreases in the direction away from the N++ type conductive substrate 1. The ways to gradually reduce the Al content include, but are not limited to, gradually reducing the Al source, gradually increasing the reaction temperature, and gradually increasing the Ga source.

[0041] (2) Gate Trench Patterning and Etching: After cleaning the epitaxial wafer obtained in step (1), a SiO2 hard mask is deposited using PECVD. The gate trench pattern is defined by photolithography, and a photoresist mask is obtained after exposure and development. Using the photoresist as a mask, the SiO2 in the uncovered areas is removed. ICP dry etching is used to etch from the N+ type source ohmic contact region 6 downwards to the N- type AlN drift region 3 to form the gate trench U. The photoresist and SiO2 hard mask are removed, etching damage is repaired, and the sidewalls and bottom of the gate trench U are smoothed. The hard mask in this embodiment can also be metal or other hard masks.

[0042] (3) Terminal region isolation fabrication: Photolithography defines the terminal region pattern, exposing the epitaxial wafer surface of the terminal region; fluoride ion or ICP etching is used to achieve device isolation and repair damage.

[0043] (4) Etching of the contact hole of the source metal: Photolithography defines and exposes the contact hole pattern between the source metal and the P-type body region 5. Using photoresist as a mask, RIE or ICP is used to etch the N+ type source ohmic contact region 6 to expose at least the surface of the P-type body region 5. Due to the influence of the manufacturing process, it is generally etched into the interior of the P-type body region 5, and then the photoresist is removed.

[0044] (5) Source and drain metal preparation: Source metal is deposited by electron beam evaporation or magnetron sputtering, and the non-source metal layer is removed by photolithography or etching to obtain source metal 7; then drain metal is deposited on the back side of N++ type conductive substrate 1 and annealed to form ohmic contact.

[0045] (6) Gate dielectric layer deposition: Al2O3, SiNx or SiO2 are deposited on the inner wall of the gate trench U and the front side of the device to form the gate dielectric layer 8 using ALD technology.

[0046] (7) Gate metal preparation: Electron beam evaporation or magnetron sputtering is used to deposit the gate metal, and photolithography is used to remove the non-gate metal layer or etching is used to form the gate metal 9 covering the gate dielectric layer 8 and filling the gate trench U.

[0047] (8) Passivation: Deposit the final passivation layer on the front side of the device and open the source and gate metal windows through photolithography and etching.

[0048] Through the above steps (1)-(8), a process was formed. Figure 1 The semiconductor device shown.

[0049] It needs to be clarified that yes, Figure 2 The fabrication process of the semiconductor device shown is as follows: Figure 1 The preparation processes shown are basically the same, with the difference being: Figure 1 The P-type body region 5 and the N+ type source ohmic contact region 6 are formed by ion doping to create P-type and N-type regions, respectively. Figure 2The P-type body region 5 and the N+ type source ohmic contact region 6 are formed by distributed polarization doping, respectively. The Al content in the P-type body region gradually increases along the direction away from the N++ type conductive substrate 1; the Al content in the N+ type source ohmic contact region gradually decreases along the direction away from the N++ type conductive substrate 1.

[0050] It should be noted that in the above-described fabrication method provided in the embodiments of this disclosure, the patterning processes involved in forming each layer structure may include not only some or all of the processes such as deposition, photoresist coating, masking, exposure, development, etching, and photoresist stripping, but may also include other processes, depending on the pattern to be formed in the actual fabrication process, and are not limited here. For example, a post-baking process may be included after development and before etching. The deposition process may be chemical vapor deposition, plasma-enhanced chemical vapor deposition, or physical vapor deposition, and is not limited here; the mask used in the masking process may be a half-tone mask, a single-slit mask, or a gray-tone mask, and is not limited here; the etching may be dry etching or wet etching, and is not limited here.

[0051] Based on the same inventive concept, this disclosure provides an electronic device including the semiconductor device described above. Since the principle by which this electronic device solves the problem is similar to that of the semiconductor device described above, the implementation of the electronic device provided in this disclosure can refer to the implementation of the semiconductor device described above, and repeated details will not be elaborated further.

[0052] In some embodiments, the electronic devices provided in this disclosure may include, but are not limited to, radio frequency amplifiers, mixers, radar, satellites, power supplies, automotive electronics, energy-saving lamps, and home appliances. Of course, the electronic devices provided in this disclosure may include other structures besides semiconductor devices. For example, when the electronic device is a radar, it may also include structures such as transmitters, antennas, and receivers; when the electronic device is a mixer, it may also include structures such as input ports and output ports.

[0053] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0054] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A semiconductor device, characterized in that, include: An N++ type conductive substrate, a drain metal located on one side of the N++ type conductive substrate, and an N- type AlN drift region, an N+ type AlGaN current spreading layer, a P- type body region, an N+ type source ohmic contact region, and a source metal sequentially stacked on the side of the N++ type conductive substrate away from the drain metal; wherein... The surfaces of the N-type AlN drift region, the N+ type AlGaN current spreading layer, the P-type body region, and the N+ type source ohmic contact region that are away from the N++ type conductive substrate are all nitrogen polar surfaces. The Al composition content of at least one of the N+ type AlGaN current spreading layer, the P-type body region, and the N+ type source ohmic contact region gradually changes along the direction away from the N++ type conductive substrate.

2. The semiconductor device as claimed in claim 1, characterized in that, The Al component content in the N+ type AlGaN current spreading layer gradually decreases along the direction away from the N++ type conductive substrate.

3. The semiconductor device as described in claim 2, characterized in that, Assuming the metal atom content in the N+ type AlGaN current extension layer is 100%, the initial content of the bottom Al component in the N+ type AlGaN current extension layer near the N++ type conductive substrate is 100%~50%, and the final content of the top Al component in the N+ type AlGaN current extension layer away from the N++ type conductive substrate is 50%~0%.

4. The semiconductor device according to any one of claims 1-3, characterized in that, The material of the P-type body region is P-type GaN doped with P-type ions, and the material of the N+ type source ohmic contact region is N+ type GaN doped with N-type ions.

5. The semiconductor device according to any one of claims 1-3, characterized in that, The material of the P-type body region is unintentionally doped P-type AlGaN, and the Al content in the unintentionally doped P-type AlGaN gradually increases in the direction away from the N++ type conductive substrate.

6. The semiconductor device as claimed in claim 5, characterized in that, Assuming the metal atom content in the unintentionally doped P-type AlGaN is 100%, the initial content of the bottom Al component in the unintentionally doped P-type AlGaN near the N++ type conductive substrate is 50%~0%, and the final content of the top Al component in the unintentionally doped P-type AlGaN away from the N++ type conductive substrate is 100%~50%.

7. The semiconductor device according to any one of claims 1-3, characterized in that, The material of the N+ type source ohmic contact region is unintentionally doped N+ type AlGaN, and the Al content in the unintentionally doped N+ type AlGaN gradually decreases along the direction away from the N++ type conductive substrate.

8. The semiconductor device as claimed in claim 7, characterized in that, Assuming the metal atom content in the unintentionally doped N+ type AlGaN is 100%, the initial content of the bottom Al component in the unintentionally doped N+ type AlGaN near the N++ type conductive substrate is 100%~50%, and the final content of the top Al component in the unintentionally doped N+ type AlGaN away from the N++ type conductive substrate is 50%~0%.

9. The semiconductor device as claimed in claim 1, characterized in that, The thickness of the N-type AlN drift region is 1 µm to 20 µm, the thickness of the N+ type AlGaN current spreading layer is 10 nm to 300 nm, the thickness of the P-type body region is 200 nm to 5000 nm, and the thickness of the N+ type source ohmic contact region is 50 nm to 500 nm.

10. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A gate trench extending from the surface of the N+ type source ohmic contact region away from the N++ type conductive substrate into the N- type AlN drift region; a gate dielectric layer located on the inner wall of the gate trench; a gate metal covering the gate dielectric layer and filling the gate trench; and a source metal located on the side of the N+ type source ohmic contact region away from the N++ type conductive substrate and located outside the gate trench; the source metal is in contact with the P- type body region.

11. The semiconductor device as claimed in claim 10, characterized in that, The inner wall of the gate trench extending into the N-type AlN drift region is arc-shaped.

12. An electronic device, characterized in that, Includes the semiconductor device as described in any one of claims 1-11.

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