Shadow evaporation mask for fabricating tunnel junction devices

Abstract

One method includes forming a shadow evaporation mask (100) on a substrate (110) and performing a dual-angle evaporation process using the shadow evaporation mask to form a plurality of tunnel junction devices in each different region of the substrate. The shadow evaporation mask includes a plurality of patterned openings in the different regions of the substrate, wherein each of the patterned openings includes an opening of the same size and shape. Each tunnel junction device includes a first metal layer and a second metal layer having overlapping regions, wherein the overlapping regions of the tunnel junction devices remain unchanged in the different regions of the substrate.

Description

Technical Field

[0001] This disclosure relates in general to techniques for shadow evaporation fabrication of superconducting tunnel junction devices (e.g., Josephson junction devices), and more specifically to evaporation mask designs for shadow evaporation fabrication of superconducting tunnel junction devices (such as Josephson junctions for superconducting quantum components). Background Technology

[0002] Quantum computing systems can be implemented using superconducting circuits and devices that utilize superconducting qubits to generate and process quantum information. Typically, a superconducting qubit (qubit) is an electronic circuit implemented using components such as superconducting tunnel junction devices (e.g., Josephson junctions), inductors, and / or capacitors, and when cooled to low temperatures, it behaves as a quantum mechanical anharmonic (nonlinear) oscillator with quantized states.

[0003] Continued technological advancements in quantum processor design enable rapid scaling of both the physical number of superconducting qubits and the computational power of quantum processors. In fact, while current state-of-the-art quantum processors have more than 50 qubits, future quantum processors are expected to have even larger numbers, such as hundreds or thousands or more. As quantum processors scale, manufacturing techniques must be implemented to ensure the uniformity and reliability of quantum components fabricated on large wafer areas. For example, since Josephson junctions are core components of qubits and other quantum parts in superconducting quantum computers, wafer-level processes capable of precisely controlling the junction size of Josephson junctions formed on a wafer area are desired.

[0004] Currently, scanning electron beam lithography and dual-angle shadow evaporation techniques are used to fabricate superconducting tunnel junction devices, such as Josephson junctions. This technique utilizes shadow evaporation masks to fabricate overlapping electrodes for tunnel junction devices, with in-situ oxidation in the middle to form a junction barrier between the overlapping electrodes. The main variables affecting the Josephson coupling energy of a Josephson junction are the overlap region between the two junction electrodes and the thickness of the tunnel barrier layer between them.

[0005] When performing dual-angle electron beam evaporation (DBE) on a Josephson junction, a divergent evaporated metal flow with a conical shape is formed. For wafer-level fabrication of Josephson junctions on large wafer regions, the conical shape of the evaporated metal flow can lead to nanoscale misalignments in the shadowed image of the junction electrode locations formed using a shadowed evaporation mask, as well as in the linear dimensions of the junction electrodes. In effect, the conical shape of the evaporated metal flow effectively causes variations in the deposition angle of the evaporated metal on the wafer region, from the center point of the wafer to the edge. As a result, wafer-level fabrication of tunnel junction devices (such as superconducting Josephson junctions) using dual-angle DBE can lead to significant variations in the size of the tunnel junction devices and inhomogeneities (e.g., different overlapping regions) over large wafer regions, which is undesirable. Summary of the Invention

[0006] Exemplary embodiments of this disclosure include techniques for shadow evaporation fabrication of tunnel junction devices (e.g., superconducting tunnel junction devices, such as Josephson junction devices), and specifically, shadow evaporation masks for dual shadow evaporation fabrication of tunnel junction devices, which are designed to enable wafer-level fabrication of tunnel junction devices having uniform dimensions over a given wafer region.

[0007] For example, an exemplary embodiment includes a method comprising forming a shadow evaporation mask on a substrate and performing a dual-angle evaporation process using the shadow evaporation mask to form a plurality of tunnel junction devices in each different region of the substrate. The shadow evaporation mask includes a plurality of patterned openings in the different regions of the substrate, wherein each of the patterned openings includes an opening of the same size and shape. Each tunnel junction device includes a first metal layer and a second metal layer having overlapping regions, wherein the overlapping regions of the tunnel junction devices are constant in the different regions of the substrate.

[0008] Advantageously, the exemplary shadow evaporation mask is designed with patterned openings of the same size and configuration to enable the junction electrode of the tunnel junction device to be evaporated at two angles over a large substrate region, wherein the tunnel junction device is fabricated to have a uniform area over the substrate region, although the deposition angle varies depending on the different positions of the tunnel junction device over the substrate region.

[0009] For example, in another exemplary embodiment that can be combined with the foregoing paragraphs, the patterned openings of the shadow evaporation mask are configured to provide self-correction of geometric errors when forming the first and second metal layers of the tunnel junction device in different regions of the substrate, so as to ensure that the overlap area between the first and second metal layers of each tunnel junction device remains unchanged in different regions of the substrate.

[0010] In another exemplary embodiment that can be combined with the foregoing paragraphs, performing the dual-angle evaporation process includes: performing a first evaporation process at a first angle to deposit a first metal layer for each tunnel junction device, wherein the first metal layer for each tunnel junction device includes a first shadow image of a corresponding patterned opening in a patterned opening; forming an insulating layer on the first metal layer for each tunnel junction device; and performing a second evaporation process at a second angle to deposit a second metal layer for each tunnel junction device, wherein the second metal layer for each tunnel junction device includes a second shadow image of a corresponding patterned opening in a patterned opening.

[0011] In another exemplary embodiment that can be combined with the foregoing paragraphs, the patterned openings of the shadow evaporation mask each include a quadrilateral opening of the same size and having at least one non-right-angled opening.

[0012] Another exemplary embodiment includes a method comprising: forming a shadow evaporation mask on a substrate, the shadow evaporation mask including a plurality of patterned openings in different regions of the substrate, wherein each patterned opening includes a quadrilateral opening of the same size and having at least one non-right-angled quadrilateral opening; performing a first evaporation process at a first angle to deposit a first metal layer, the first metal layer including a first shadow image of the patterned openings; forming an insulating layer on each of the first metal layers; and performing a second evaporation process at a second angle to deposit a second metal layer including a second shadow image of the patterned openings. A portion of the second metal layer overlaps with a corresponding portion of the first metal layer to form a corresponding tunnel junction device in different regions of the substrate, which includes overlapping metallized regions of the same size and having at least one non-right-angled quadrilateral footprint.

[0013] Another exemplary embodiment includes a device comprising a shadow evaporation mask including a first layer and a second layer disposed above the first layer, and a plurality of uniformly patterned openings configured to fabricate a tunnel junction device of a corresponding uniform shape on a substrate by dual-angle shadow evaporation.

[0014] Another exemplary embodiment includes a device comprising: a first metal layer disposed on a substrate; an insulating layer disposed on the first metal layer; and a second metal layer disposed on the insulating layer. A portion of the second metal layer overlaps with a portion of the first metal layer to form a stacked structure including overlapping metallized regions therebetween, wherein a portion of the insulating layer is located therebetween, and wherein the stacked structure includes a tunnel junction device having at least one non-right-angled quadrilateral projection region.

[0015] In another exemplary embodiment that can be combined with the foregoing paragraphs, both the first metal layer and the second metal layer comprise a superconducting metal, and the insulating layer comprises an oxide of the superconducting metal.

[0016] In another exemplary embodiment that can be combined with the foregoing paragraphs, the quadrilateral projection region of the tunnel junction device includes a parallelogram projection region with non-right angles. The first metal layer and the second metal layer each include a parallelogram region with non-right angles.

[0017] In another exemplary embodiment that can be combined with the foregoing paragraphs, the first metal layer includes an extension providing a first contact pad for the tunnel junction device, and the second metal layer includes an extension providing a second contact pad for the tunnel junction device.

[0018] In another exemplary embodiment that can be combined with the foregoing paragraphs, the tunnel junction device includes a Josephson junction of superconducting qubits.

[0019] Another exemplary embodiment includes a device comprising a plurality of tunnel junction devices disposed on a substrate. Each tunnel junction device includes a corresponding stacked structure comprising an overlap of a first metal layer and a second metal layer, and an insulating layer disposed therebetween, wherein the corresponding stacked structure includes a quadrilateral projection region having at least one non-right-angled quadrilateral.

[0020] In another exemplary embodiment that can be combined with the foregoing paragraphs, the quadrilateral projection areas of the stacked structures have substantially the same projection area.

[0021] Other embodiments of this disclosure will be described in the following detailed description, which is taken in conjunction with the accompanying drawings. Attached Figure Description

[0022] Figure 1A , 1B Figure 1C schematically illustrates a shadow evaporation mask formed on a substrate according to an exemplary embodiment of the present disclosure, wherein... Figure 1A This is a schematic top view of the shadow evaporation mask and substrate. Figure 1B It is the shadow evaporation mask and substrate along Figure 1A A schematic cross-sectional side view of line 1B-1B in the diagram, and Figure 1C It is the shadow evaporation mask and substrate along Figure 1A A schematic cross-sectional side view of line 1C-1C in the diagram.

[0023] Figure 2A , Figure 2B and Figure 2C The diagram schematically illustrates a dual-angle shadow evaporation process for wafer-level fabrication of tunnel junction devices according to exemplary embodiments of the present disclosure.

[0024] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G and Figure 3H The diagram schematically illustrates a dual-angle shadow evaporation process for wafer-level fabrication of tunnel junction devices according to exemplary embodiments of the present disclosure.

[0025] Figure 4A and 4B The illustration schematically depicts a method for configuring a shadow evaporation mask to compensate for a first error component in the wafer-level fabrication of metal electrodes for a tunnel junction device using a dual-angle shadow evaporation process, according to exemplary embodiments of the present disclosure.

[0026] Figure 5A method for determining the lateral overlap of metal electrodes in a tunnel junction device manufactured using a dual-angle shadow evaporation process is illustrated schematically according to an exemplary embodiment of the present disclosure.

[0027] Figure 6 An exemplary configuration of a dual-angle shadow evaporation process for wafer-level fabrication of tunnel junction devices according to exemplary embodiments of the present disclosure is illustrated to achieve the same amount of lateral overlap of the metal electrodes of the respective tunnel junction devices formed in different regions of the wafer.

[0028] Figure 7A and 7B A dual-angle shadow evaporation process for wafer-level fabrication of tunnel junction devices according to another exemplary embodiment of the present disclosure is schematically illustrated. Detailed Implementation

[0029] Exemplary embodiments of this disclosure will now be discussed in further detail, relating to shadow evaporation fabrication techniques for superconducting tunnel junction devices (e.g., Josephson junction devices), particularly shadow evaporation masks for dual shadow evaporation fabrication of superconducting tunnel junction devices, designed to enable the fabrication of superconducting tunnel junction devices with uniform dimensions over large wafer regions. Specifically, the evaporation mask is designed to perform a dual-angle evaporation process to form multiple superconducting tunnel junctions in different regions of the wafer, wherein the superconducting tunnel junction devices include respective first and second metal layers, the overlapping region of which remains substantially unchanged on the wafer. As explained in further detail below, the exemplary shadow evaporation mask is designed to provide self-correction for process variations caused by changes in deposition angles on the wafer (from the center point to the edge of the wafer), which would otherwise result in different shadows of the metal flow from the edges of the dual-layer resist mask, thereby providing irregular regions (e.g., Josephson junctions) on the wafer substrate for large-scale fabrication.

[0030] It should be understood that the various layers, structures, and regions shown in the accompanying drawings are schematic diagrams not drawn to scale. Furthermore, for ease of interpretation, one or more layers, structures, and regions of types typically used to form semiconductor devices or structures may not be explicitly shown in a given drawing. This does not mean that any layers, structures, and regions not explicitly shown are omitted from an actual semiconductor structure. Moreover, it should be understood that the embodiments discussed herein are not limited to the specific materials, features, and processing steps shown and described herein. In particular, regarding semiconductor processing steps, it is emphasized that the description provided herein is not intended to cover all processing steps that may be necessary to form a functional semiconductor integrated circuit device. Rather, for the sake of economics, certain processing steps typically used to form semiconductor devices, such as wet cleaning and annealing steps, are not intentionally described herein.

[0031] Furthermore, the same or similar reference numerals are used throughout the accompanying drawings to denote the same or similar features, elements, or structures; therefore, detailed descriptions of the same or similar features, elements, or structures will not be repeated for each drawing. It should be understood that, as used herein, the terms “about” or “substantially” relating to thickness, width, percentage, range, etc., are intended to indicate approximation or approximation, but are not precise. For example, the terms “about” or “substantially” as used herein mean that a small margin of error may exist, such as 1% or less than the stated amount. The term “exemplary” as used herein means “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” should not be construed as preferred or advantageous over other embodiments or designs. The word “above” as used herein to describe forming a feature (e.g., a layer) “above” a side or surface means that the feature (e.g., a layer) may be formed “directly” on the implied side or surface (i.e., in direct contact with it), or that the feature (e.g., a layer) may be formed “indirectly” on the implied side or surface, wherein one or more additional layers are disposed between the feature (e.g., a layer) and the implied side or surface.

[0032] Furthermore, as used herein, the term "quantum chip" is intended to broadly refer to any device including qubits and possibly other quantum devices. For example, a quantum chip can be a semiconductor die comprising an array (lattice) of qubits, fabricated on a wafer comprising multiple dies, and can be diced (cut) from the wafer using a die-dicing process to provide diced dies. In some cases, a quantum chip can be a wafer with multiple quantum dies. In the context of quantum computing, a quantum chip can include one or more processors for use in a quantum computer.

[0033] To provide spatial context for the different structural orientations of the semiconductor structures shown in the accompanying figures, XYZ Cartesian coordinates are illustrated in the figures. The terms "vertical" or "vertical direction" or "vertical height" as used herein refer to the Z-direction of the Cartesian coordinates shown in the figures, and the terms "horizontal," "horizontal direction," "lateral," or "lateral direction" as used herein refer to the X-direction and / or Y-direction of the Cartesian coordinates shown in the figures.

[0034] Figure 1A , 1B Figure 1C schematically illustrates a shadow evaporation mask according to an exemplary embodiment of the present disclosure. In particular, Figure 1A , 1B Figure 1C schematically illustrates a shadow evaporation mask 100 formed on the surface of a substrate 110 (e.g., a wafer), wherein... Figure 1A This is a schematic top view of the shadow evaporation mask 100. Figure 1B It is along Figure 1AA schematic cross-sectional side view of the shadow evaporation mask 100 and substrate 110 along line 1B-1B, and Figure 1C It is along Figure 1A A schematic cross-sectional side view of the shadow evaporation mask 100 and substrate 110 along line 1C-1C.

[0035] like Figure 1A , Figure 1B and Figure 1C As shown, the shadow evaporation mask 100 includes a first resist layer 101 (or support layer) and a second resist layer 102 (or imaging layer), which are etched to form patterned openings 103, thereby exposing the region of the underlying substrate 110 where a superconducting tunnel junction device will be fabricated. Generally, the patterned openings 103 in the second resist layer 102 include quadrilateral openings 103-1 (having at least one non-right angle) defined by a first edge e1, a second edge e2, a third edge e3, and a fourth edge e4. Additionally, the patterned openings 103 in the second resist layer 102 include rectangular extensions 103-2 and 103-3. In an exemplary embodiment, the quadrilateral opening 103-1 includes a parallelogram opening (having a non-right angle). As explained below, the quadrilateral opening 103-1 (having at least one non-right angle) is configured to generate images of a first device electrode and a second device electrode forming a well-defined overlapping region of a given superconducting tunnel junction device, and the rectangular extensions 103-2 and 103-3 are configured to generate images of a first contact pad of the first device electrode and a second contact pad of the second device electrode of the given superconducting tunnel junction device. For the purposes of discussion, exemplary embodiments of this disclosure will be discussed in the context of the quadrilateral opening 103-1 being a parallelogram opening with non-right angles; however, other types of quadrilateral openings with non-right angles may be implemented.

[0036] like Figure 1A and Figure 1B As further schematically shown, the second resist layer 102 of the shadow evaporation mask 100 includes overhangs 102-1 and 102-2 (or suspended portions) disposed above corresponding undercut regions 101-1 and 101-2 of the first resist layer 101. In this respect, the patterned opening 103 is further defined by the undercut regions 101-1 and 101-2 of the first resist layer 101. As explained in further detail below, the undercut regions 101-1 and 101-2 of the first resist layer 101 contribute to forming a shadow image of the patterned opening 103, which will be projected onto the same region of the substrate 110 by performing two evaporation deposition steps at different angles (but with a given lateral offset) to create a capping layer of two metal layers with a defined geometry that defines a superconducting tunnel junction device.

[0037] Reference Figure 1A The parallelogram opening 103-1 in the second resist layer 102 includes a first angled edge and a second angled edge, at least partially defined by a first edge e1 and a second edge e2. The first angled edge and the second angled edge are arranged at an angle θ relative to a first central axis (e.g., the X direction) of the substrate 110. As explained in further detail below, the angle θ is designed to be greater than the maximum evaporation angle of the conical evaporated metal stream generated by the evaporation source during the execution of the first and second evaporation processes. ,in These are exemplary design parameters that enable the uniform fabrication of superconducting tunnel junction devices in different regions of a substrate (e.g., a wafer), regardless of the location of the superconducting tunnel junction devices above the substrate.

[0038] It should be understood that, for ease of explanation and interpretation, Figure 1A , 1B Figure 1C depicts only one patterned opening 103 in a given region of the shadow evaporation mask 100. However, it should be understood that in some embodiments, the shadow evaporation mask 100 will be fabricated as multiple instances of the same patterned opening 103 in different regions of the shadow evaporation mask 100 (e.g., the same size and geometry and orientation) to enable the dual-angle shadow evaporation fabrication of multiple superconducting tunnel junction devices in different regions of the substrate 110, having the same overlap area of ​​the first and second metal electrodes, and using patterned openings 103 of the same size on a large area of ​​the substrate 110.

[0039] The shadow evaporation mask 100 can be fabricated using suitable techniques and materials. For example, in some embodiments, the shadow evaporation mask 100 comprises a double-layer resist stack formed by depositing a first resist material (comprising a first resist layer 101) on a substrate 110 and depositing a second resist material (comprising a second resist layer 102) on the first resist material. In some embodiments, the first resist layer 101 comprises a methyl methacrylate (MMA) layer spin-coated onto the surface of the substrate 110 (e.g., a silicon wafer), and the second resist layer 102 comprises a polymethyl methacrylate (PMMA) layer spin-coated onto the first resist layer 101. In some embodiments, the first resist layer 101 and the second resist layer 102 are then patterned using scanning electron beam lithography and a suitable developing solution to form patterned openings 103 and control the formation of undercut regions 101-1 and 101-2 in the first resist layer 101.

[0040] For example, in some embodiments, different regions of the bilayer resist stack are exposed to different doses of electron beam energy to facilitate the formation of patterned openings 103 through the first and second resist layers 101 and 102, and to control the formation of undercut regions 101-1 and 101-2 in the first resist layer 101. Specifically, in some embodiments, the projected area of ​​the bilayer resist stack corresponding to the patterned openings 103 is exposed to a “full dose” of electron beam energy sufficient to expose portions of the first and second resist layers 101 and 102 so that the exposed portions can be removed using a suitable developer solution. Furthermore, the projected areas corresponding to the overhanging portions 102-1 and 102-2 of the second resist layer 102 and the corresponding undercut regions 101-1 and 101-2 of the first resist layer 101 are exposed to a low dose (e.g., ghosting dose) of electron beam energy sufficient to penetrate the second resist layer 102 without affecting it, while allowing the areas of the first resist layer 101 corresponding to the undercut regions 101-1 and 101-2 to be selectively exposed and removed by a developer solution. After electron beam exposure, the exposed portions of the first and second resist layers 101 and 102 are then removed using a suitable developer solution (or multiple solutions), thereby forming a patterned opening 103 (which extends downward through the first and second resist layers 101 and 102 to the surface of the substrate 110) and forming undercut regions 101-1 and 101-2 in the first resist layer 101, thereby producing Figure 1A , 1B And the exemplary patterned opening 103 shown in 1C. Using this process, the extent of the undercut regions 101-1 and 101-2 in the first resist layer 101 is photolithographically defined and thus precisely controlled.

[0041] While a shadow evaporation mask 1 00 can be fabricated by patterning a double-layer MMA / PMMA resist using electron beam lithography, in other embodiments, optical lithography can be used to fabricate shadow evaporation masks for wafer-level fabrication of tunnel junction devices. In practice, since exemplary masks for shadow evaporation of, for example, Josephson junctions are fabricated with the same size and configuration as patterned openings for bi-angle evaporation of junction electrodes over a large wafer region, it is unnecessary (as with some conventional methods) to calculate and then fabricate patterned openings of different sizes in the shadow evaporation mask to compensate for variations in evaporation angles at different locations on the large wafer region. In electron beam lithography, patterned openings of different sizes can be calculated and then formed individually one at a time using electron beam lithography. However, the combination of computational methods and electron beam-based lithography is not an ideal solution for fabricating shadow evaporation masks, especially for large-scale manufacturing. On the other hand, optical lithography-based fabrication of shadow evaporation masks is more ideal for wafer-level fabrication of, for example, Josephson junctions, where computational solutions are less suitable for optical lithography-based fabrication of shadow evaporation masks.

[0042] An exemplary shadow evaporation mask 100 can be used to perform a dual-angle shadow evaporation process to fabricate first and second metal electrodes of a given superconducting tunnel junction device, the device including a shadow image of a patterned opening 103, wherein the first and second electrodes are geometrically similar but laterally offset from each other to provide an overlapping region defining a region of the given superconducting tunnel junction device. For example... Figure 2A , Figure 2B and Figure 2C A dual-angle shadow evaporation process for wafer-level fabrication of tunnel junction devices according to exemplary embodiments of the present disclosure is schematically illustrated. In particular, Figure 2A and 2B An exemplary dual-angle shadow evaporation process is schematically illustrated, which utilizes a shadow evaporation mask 100 to perform wafer-level fabrication of overlapping metal electrodes for a tunnel junction device, wherein... Figure 2A The configuration of a dual-angle shadow evaporation process 200 for wafer-level fabrication of tunnel junction devices is schematically illustrated. Figure 2B An exemplary tunnel junction device, fabricated using a dual-angle shadow evaporation process, is schematically illustrated according to an exemplary embodiment of the present disclosure. Additionally, Figure 2C It is along Figure 2B Line 2C-2C in the middle Figure 2B A schematic cross-sectional view of an exemplary overlapping region of a tunnel junction device.

[0043] like Figure 2AAs schematically illustrated, an exemplary dual-angle shadow evaporation process 200 is configured for wafer-level fabrication of tunnel junction devices on a given wafer 210 (e.g., a silicon wafer) comprising a plurality of chips 220. In an exemplary embodiment, chip 220 includes a quantum chip comprising qubits and other quantum components constructed using superconducting tunnel junction devices (e.g., Josephson junctions). To explain the exemplary configuration of the dual-angle shadow evaporation process 200, Figure 2A A three-dimensional Cartesian coordinate system is shown, comprising an X-axis (which may be alternatively referred to herein as the parallel axis), a Y-axis (which may be alternatively referred to herein as the perpendicular axis), and a Z-axis, and having an origin corresponding to the center point of wafer 210. In this respect, the surface of wafer 210 defines an XY plane at Z=0. The X-axis (or parallel axis) includes a first central longitudinal axis extending through the center point of wafer 210 (in the XY plane), and the Y-axis (or perpendicular axis) includes a second central longitudinal axis extending through the center point of wafer 210 (in the XY plane), wherein the second central longitudinal axis (e.g., the Y-axis) is perpendicular to the first central longitudinal axis (e.g., the X-axis).

[0044] like Figure 2A Further schematically illustrated, the exemplary dual-angle shadow evaporation process 200 includes: (i) a first evaporation process E1, which is performed by guiding evaporated metal material to wafer 210 through a given shadow evaporation mask, wherein the evaporated metal material is emitted from evaporation (point) source 230-1 at a first deposition angle; and (ii) a second evaporation process E2, which is performed by guiding evaporated metal material to wafer 210 through a given shadow evaporation mask, wherein the evaporated metal material is emitted from evaporation (point) source 230-2 at a second deposition angle. In some embodiments, the exemplary dual-angle shadow evaporation process 200 is configured such that the first evaporation process E1 and the second evaporation process E2 are performed at the same vertical height (e.g., Z coordinate) above a reference plane (e.g., the XY plane of wafer 210 or the surface of the stage on which wafer 210 is mounted).

[0045] Figure 2B The use is illustrated schematically. Figure 2A The dual-angle shadow evaporation process 200 combined Figure 1A-1C An exemplary tunnel junction device fabricated using an exemplary shadow evaporation mask 100, wherein it is assumed that patterned openings 103 are disposed in the central region of wafer 210, near... Figure 2BThe origin of the XYZ coordinate system is shown, and the edges e3 and e4 of the patterned opening 103 are aligned in the Y direction. In the illustrative embodiment, a first evaporation process E1 results in the formation of a first metal electrode 231, which includes a shaded image of the patterned opening 103. After the first evaporation process E1, an oxide layer 232 is formed on the exposed surface of the first metal electrode 231, wherein the oxide layer 232 serves as a tunnel barrier layer for the tunnel junction device. Next, a second evaporation process E2 results in the formation of a second metal electrode 233, which includes a shaded image of the patterned opening 103 but is laterally offset from the first metal electrode 231, thereby forming an overlapping region 234 that defines the region of the tunnel junction device.

[0046] like Figure 2B As schematically shown, the overlapping region 234 includes a parallelogram region (with non-right angles) which is formed by the overlap of the first metal electrode 231 and the second metal electrode 233 in the x-direction by a given amount (denoted as X). O The first metal electrode 231 and the second metal electrode 233 overlap in the y-direction by a given amount (denoted as Y). O ( ) is limited. For example... Figure 2C As shown, the overlapping region 234 of the parallelogram shape of the first metal electrode 231 and the second metal electrode 233, and a portion of the oxide layer 232 disposed therebetween define the region of the tunnel junction device.

[0047] like Figure 2A The diagram schematically illustrates that during electron beam evaporation processes E1 and E2, evaporation (point) sources 230-1 and 230-2 generate corresponding divergent metal flows with conical shapes. In this respect, when the deposition angles of the first and second evaporation processes E1 and E2 are set relative to the central region (e.g., the origin) of wafer 210, the actual deposition angle will vary across the region of wafer 210 from the center point to the edge of wafer 210. For conventional shadow evaporation mask designs, variations in the deposition angle across the region of wafer 210 will result in different shadow sizes of the patterned openings of the shadow evaporation mask, leading to nanoscale misalignments of junction electrode positions and variations in the linear dimensions of the junction electrodes on the wafer. This, in turn, causes variations in the size (area) of tunnel junction devices in different chips 220 disposed in different regions of wafer 210.

[0048] In contrast, the exemplary shadow evaporation mask design disclosed herein is configured to enable dual-angle shadow evaporation fabrication of tunnel junction devices (e.g., Josephson junctions) at the wafer level, wherein the tunnel junction devices are fabricated with a uniform area on the wafer region, although the deposition angle varies depending on the different positions of the tunnel junction devices on the wafer region. The exemplary shadow evaporation mask is configured to provide self-correction of the junction area of ​​the tunnel junction devices over a relatively large wafer region, such that the junction area of ​​the tunnel junction devices remains constant on the wafer region; that is, the junction area of ​​the tunnel junction devices does not change depending on the position of the tunnel junction devices on the wafer.

[0049] An exemplary shadow evaporation mask is configured to compensate for geometric dimensional errors in the x and y directions, such that the overlap of the first and second metal electrodes of each tunnel junction device is the same in both lateral (x and y) directions, i.e., the overlap of the first and second metal electrodes of the tunnel junction device in the x and y directions is the same. O and Y O The overlap is substantially the same and largely constant across different regions / areas (e.g., chips) on the wafer, and is independent of positional variations in the evaporation deposition angle. For example, in Figure 2A In the context of the exemplary configuration of the dual-angle shadow evaporation process 200 shown, the shadow evaporation mask is designed with patterned openings configured to compensate for (i) a first error component caused by the vertical position of a given tunnel junction device in the y direction relative to the central (parallel) x-axis, and (ii) a second error component caused by the parallel position of a given tunnel junction device in the x direction relative to the central (perpendicular) y-axis.

[0050] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G and Figure 3H A dual-angle shadow evaporation process for wafer-level fabrication of a tunnel junction device according to exemplary embodiments of the present disclosure is schematically illustrated. For illustrative purposes, the exemplary dual-angle shadow evaporation process 300 will be discussed in the context of an exemplary configuration / positioning of an exemplary wafer 210 and a shadow evaporation mask 100, and evaporation (point) sources 310-1 and 310-2, the exemplary configuration / positioning of which is similar to that of... Figure 2AThe evaporation (point) sources 230-1 and 230-2 are shown in their configuration / position relative to the first central longitudinal (X) axis (or parallel axis) and the second central longitudinal (Y) axis (or vertical axis). Furthermore, for illustrative purposes, an exemplary dual-angle shadow evaporation process 300 will be discussed in the context of a shadow evaporation mask, which includes an example of at least three patterned openings 103 (such as...). Figure 1A-1C (as shown in 2B), used for evaporation fabrication of three tunnel junction devices 320, 330 and 340.

[0051] For example, Figure 3A A first evaporation process E1 is schematically illustrated, which is performed by guiding evaporating metal material at wafer 210 from evaporation (point) source 310-1 through a given shaded evaporation mask having three patterned openings 103A, 103B, and 103C, each patterned opening having the same geometry and configuration based on patterned opening 103 as described above. For the purposes of discussion, it is assumed that patterned openings 103A, 103B, and 103C are aligned in the Y direction along the vertical axis (second central longitudinal (Y) axis) of wafer 210, and that patterned opening 103B is aligned with the parallel axis (first central longitudinal (X) axis) of wafer 210. Furthermore, it is assumed that patterned opening 103A is located near the edge of wafer 210 at the positive Y position farthest from the center point (e.g., origin) of wafer 210 on the vertical axis, and that patterned opening 103C is located near the edge of wafer 210 at the negative Y position farthest from the center point of wafer 210 on the vertical axis. Additionally, assume that the evaporation (point) source 310-1 is located in the XZ plane at a given height h (positive Z point) above the XY plane, and at a linear distance d from the center point (XYZ origin) of the wafer 210 along the X axis (e.g., negative X point).

[0052] In some embodiments, the first evaporation process E1 is performed by evaporating a superconducting metal (e.g., aluminum) in a vacuum environment and guiding the evaporated superconducting metal from the evaporation (point) source 310-1 through patterned openings 103A, 103B, and 103C onto the wafer 210 to deposit the evaporated metal onto the surface of the wafer 210, wherein the evaporated metal material then condenses to form the respective first metal electrodes 321, 331, and 341 of the respective tunnel junction devices 320, 330, and 340. Figure 3A The diagram schematically illustrates that, assuming the evaporation (point) source 310-1 is essentially a point source, the flow of evaporating metal has a conical shape, represented by dashed vectors V1, V2, and V3, which result in different evaporation angles in the direction along the vertical (Y) axis.

[0053] In particular, such as Figure 3AThe diagram schematically illustrates that the dashed vector V2 represents the flow of evaporated metal guided at the patterned opening 103B, where the evaporated metal flows in a direction along the XZ plane, such that the dashed vector V2 has an angle of 0 degrees relative to the XZ plane. On the other hand, the dashed vector V1 represents the flow of evaporated metal pointing towards the patterned opening 103A, where the evaporated metal forms an angle relative to the XZ plane. The flow proceeds in the direction of the patterned opening 103A, which is located at a positive Y position on the vertical Y-axis near the edge of wafer 210. Similarly, the dashed vector V3 represents the flow of evaporated metal guided at the patterned opening 103C, where the evaporated metal forms relative to the XZ plane. The flow direction of the angle is to reach the patterned opening 103C, which is located at a negative Y position on the vertical Y axis near the opposite edge of the wafer 210.

[0054] Due to the change in angle, Figure 3A The shaded images showing the first metal electrodes 321, 331, and 341 produced by the corresponding patterned openings 103A, 103B, and 103C due to the evaporation process E1 will have similar shapes but different offsets relative to the patterned openings 103A, 103B, and 103C. Specifically, as Figure 3A As schematically shown, the positions of the first metal electrodes 321, 331, and 341 gradually shift in the downward direction (negative y-direction), such that an increasing portion of the first metal electrodes 321, 331, and 341 is formed below the corresponding overhangs 102-2 of the patterned openings 103A, 103B, and 103C. However, at the maximum angle described above... Without exceeding the angle θ between the central X-axis (e.g., parallel axis) of wafer 210 and each of the first and second angled edges e1 and e2 of the overhanging portions 102-1 and 102-2 of patterned openings 103A, 103B and 103C, the variational offset of the first metal electrodes 321, 331 and 341 will not adversely affect the area uniformity of the resulting tunnel junction devices 320, 330 and 340.

[0055] Figure 3A The first evaporation process E1 in the process is composed of Figure 3B and Figure 3C Further shown, in Figure 3B It is along Figure 3A A schematic cross-sectional side view of line 3B-3B in the diagram, and Figure 3C It is along Figure 3A A schematic cross-sectional side view of line 3C-3C in the diagram. Specifically, Figure 3B and 3CThe diagram schematically illustrates an intermediate stage in the fabrication of the tunnel junction device 330, wherein a shadow image of the first metal electrode 331 is formed on the surface of the wafer 210 by a first evaporation process E1 through patterned openings 103B of a shadow evaporation mask 100. Figure 3B and Figure 3C A dashed vector is shown representing the flow of evaporated metal guided to the patterned opening 103B due to evaporation process E1, where evaporation is at an angle α to the Z-axis. In some embodiments, angle α represents the evaporation angle selected by the first evaporation process E1, where angle α represents the angle of the direct path from the evaporation (point) source 310-1 to the center point (origin) of wafer 210, assuming that the patterned opening 103B is located near the center point of wafer 210. Assuming a long distance between the evaporation (point) source 310-1 and the patterned opening 103B relative to the nanometer size of the patterned opening 103B, the dashed vector representing the flow of evaporated metal guided at the patterned opening 103B is substantially parallel.

[0056] Following the first evaporation process E1, an in-situ oxidation process is performed to form an oxide layer on the exposed surfaces of the first metal (aluminum) electrodes 321, 331, and 341. For example, in some embodiments, immediately after the first evaporation process E1, oxygen (O2) is introduced into the evaporation chamber (without breaking the vacuum) to expose the metal electrodes to oxygen at a fixed concentration and pressure for a given time. This oxidation of the exposed surfaces of the first metal electrodes 321, 331, and 341 is achieved via diffusion oxidation, thereby forming a thin oxide layer (e.g., aluminum oxide) on the first metal (aluminum) electrodes 321, 331, and 341. The oxide layer serves as the tunnel barrier layer for the tunnel junction device. The desired thickness of the oxide layer is selected to achieve the desired operating characteristics of the tunnel junction device. For example, for a superconducting Josephson junction, the tunnel barrier thickness is designed to achieve the desired critical current of the Josephson junction.

[0057] exist Figure 3D and 3E The result of the oxidation process is schematically shown in the figure, wherein a thin oxide layer 332 is formed on the exposed surface of the first metal electrode 331. Figure 3D It corresponds to Figure 3B A schematic cross-sectional side view of the diagram illustrates the structure obtained after a thin oxide layer 332 (e.g., an aluminum oxide layer) has been formed on the exposed surface of the first metal electrode 331 (e.g., an aluminum electrode). Similarly, Figure 3E It corresponds to Figure 3C A schematic cross-sectional side view showing the resulting structure after a thin oxide layer 332 (e.g., an aluminum oxide layer) has been formed on the exposed surface of the first metal electrode 331 (e.g., an aluminum electrode).

[0058] Following the oxidation process, a second evaporation process (without disrupting the vacuum in the evaporation chamber) is performed to form the corresponding second electrodes of the tunnel junction devices 320, 330, and 340. For example, Figure 3F The second evaporation process E2 is schematically illustrated, which guides the evaporated metallic material from the evaporation (point) source 310-2 through a process having three patterned openings 103A, 103B, and 103C. Figure 3A The shadow evaporation mask is applied at wafer 210. Similar to... Figure 3A Patterned openings 103A, 103B, and 103C are aligned in the Y direction along the vertical axis (second central longitudinal (Y) axis) of wafer 210, and patterned opening 103B is aligned with the parallel axis (first central longitudinal (X) axis) of wafer 210. Additionally, it is assumed that evaporation (point) source 310-2 is located in the XZ plane at a given height above the XY plane. Furthermore, it is assumed that evaporation (point) source 310-1 is located in the XZ plane at a given height h (positive Z point) above the XY plane, and is linearly distanced d from the center point (XYZ origin) of wafer 210 along the X-axis.

[0059] In some embodiments, Figure 3F The configuration of the second evaporation process E2 is similar to Figure 3A The configuration of the first evaporation process E1, besides Figure 3F The evaporation (point) source 310-2 is located at a position in the XZ plane, which corresponds to Figure 3A The location of the evaporation (point) source 310-1 is such that the XZ plane is rotated 180 degrees about the Z-axis. In this respect, evaporation sources 310-1 and 310-2 can be the same evaporation source, which is rotated only 180 degrees about the Z-axis to provide two separate evaporation angles. In another embodiment, Figure 3A The position of the evaporation (point) source 310-1 can be kept fixed, while the wafer 210 is rotated 180 degrees and the second evaporation process E2 is performed using the fixed evaporation source.

[0060] In some embodiments, the second evaporation process E2 is performed by evaporating a superconducting metal (e.g., aluminum) in a vacuum environment and guiding the evaporated metal from the evaporation (point) source 310-2 through patterned openings 103A, 103B, and 103C onto the wafer 210 to deposit the evaporated metal material onto the surface of the wafer 210, and then condensing the evaporated metal material to form the respective second metal electrodes 323, 333, and 343 of the respective tunnel junction devices 320, 330, and 340. Figure 3F As illustrated in the diagram, assuming that the evaporation (point) source 310-2 is essentially a point source, the flow of the evaporating metal has a conical shape, represented by the dashed vectors V1', V2', and V3', which results in different evaporation angles along the direction perpendicular to the (Y) axis.

[0061] The dashed vectors V1', V2', and V3' correspond to respectively Figure 3A The dashed vectors V1, V2, and V3. For example, as... Figure 3F As schematically shown, the dashed vector V2' represents the flow of evaporated metal pointing towards the patterned opening 103B, wherein the evaporated metal flows along the direction of the XZ plane, such that the dashed vector V2' has an angle of 0 degrees relative to the XZ plane. On the other hand, the dashed vector V1' represents the flow of evaporated metal pointing towards the patterned opening 103A, wherein the evaporated metal flows along a direction relative to the XZ plane. The flow direction of the angle is to reach the patterned opening 103A located at a positive Y position on the vertical Y-axis near the edge of wafer 210. Similarly, the dashed vector V3' represents the flow of evaporated metal pointing towards the patterned opening 103C, where the evaporated metal forms relative to the XZ plane. The angle flows in the direction to reach the patterned opening 103C, which is located at a negative Y position on the vertical Y axis near the opposite edge of the wafer 210.

[0062] Due to the change in angle, Figure 3F The shaded images showing the second metal electrodes 323, 333, and 343 produced by the corresponding patterned openings 103A, 103B, and 103C due to the second evaporation process EE will have similar shapes but different offsets relative to the patterned openings 103A, 103B, and 103C. Specifically, as... Figure 3F As schematically shown, the positions of the second metal electrodes 323, 333 and 343 gradually shift in the downward direction (negative y direction), so that the areas of the second metal electrodes 323, 333 and 343 formed below the corresponding overhang portions 102-1 of the patterned openings 103A, 103B and 103C become smaller and smaller.

[0063] However, at the maximum angle as described above Without exceeding the angle θ between the central X-axis (e.g., a parallel axis) of wafer 210 and each of the first and second angled edges e1 and e2 of the overhanging portions 102-1 and 102-2 of patterned openings 103A, 103B, and 103C, the variational offset of the second metal electrodes 323, 333, and 343 has no adverse effect on the area uniformity of the resulting tunnel junction devices 320, 330, and 340. In fact, as Figure 3F As schematically illustrated, tunnel junction devices 320, 330 and 340 are defined by corresponding overlapping regions 324, 334 and 344 of associated first and second metal electrodes, wherein the overlapping regions 324, 334 and 344 are parallelogram-shaped and have substantially the same size and therefore substantially the same projected area.

[0064] Figure 3G and Figure 3H Further shown Figure 3F The second evaporation process E2 in which Figure 3G It is along Figure 3F A schematic cross-sectional side view of line 3G-3G in the diagram, and Figure 3H It is along Figure 3F A schematic cross-sectional side view of line 3H-3H in the diagram. Specifically, Figure 3G and 3H The final stage of fabrication of the tunnel junction device 330 is schematically shown, wherein the shadow image of the second metal electrode 333 is formed by the second evaporation process E2 through the patterned opening 103B of the shadow evaporation mask 100. Figure 3G and Figure 3H The dashed vector represents the flow of evaporated metal guided to the patterned opening 103B due to the second evaporation process E2, wherein the evaporation is at an angle to the Z-axis. As described above, in some embodiments, the angle The evaporation angle selected for the second first evaporation process E2 is represented by the angle of the direct path from the evaporation (point) source 310-2 to the center point (origin) of the wafer 210, assuming that the patterned opening 103B is located near the center point of the wafer 210. The dashed vector representing the evaporated metal flow guided at the patterned opening 103B is assumed to be substantially parallel over a long distance between the evaporation (point) source 310-2 and the patterned opening 103B, relative to the nanometer size of the patterned opening 103B.

[0065] like Figure 3G and 3H As schematically shown, the second metal electrode 333 overlaps with the first metal electrode 331 by an amount Y0 in the Y direction and by an amount X0 in the X direction, wherein the X0 overlap and the Y0 overlap define... Figure 3F The overlapping region 334 shown. The overlapping region 334 between the first metal electrode 331 and the second metal electrode 333 (with a portion of the thin oxide layer 332 disposed therebetween) defines the region of the tunnel junction device 330. Utilizing Figures 3A to 3F In the exemplary process shown, (i) the corresponding X0 overlap and Y0 overlap between the first metal electrode 321 and the second metal electrode 323 of the tunnel junction device 320, (ii) the first metal electrode 331 and the second metal electrode 333 of the tunnel junction device 330, and (ii) the first metal electrode 341 and the second metal electrode 343 of the tunnel junction device 340 will be the same or substantially the same, thereby causing the corresponding overlap regions 324, 334 and 344 to have the same or substantially the same size and projected area.

[0066] As described above, the exemplary shadow evaporation mask design disclosed herein is configured to enable dual-angle shadow evaporation fabrication of tunnel junction devices (e.g., Josephson junctions) at the wafer level, wherein the tunnel junction devices are fabricated with a uniform area on the wafer region despite variations in the deposition angle based on different locations of the tunnel junction devices on the wafer region. The exemplary shadow evaporation mask is configured to compensate for geometric dimensional errors in the x and y directions such that the overlap amount of the first and second metal electrodes of each tunnel junction device is the same in both lateral (x and y) directions; that is, the X0 and Y0 overlap amounts of the first and second metal electrodes of the tunnel junction device are substantially the same and substantially constant on different regions / areas (e.g., chips) of the wafer, independent of position-related variations in the evaporation deposition angle. Figure 4A , 4B Figures 5 and 6 illustrate exemplary configurations of shadow evaporation mask designs to provide self-correction of tunnel junction device junction area on large-area wafers, thereby providing uniform tunnel junction device junction area for large-scale wafer fabrication.

[0067] For example, Figure 4A and 4B A method for configuring a shadow evaporation mask to compensate for a first error component in the fabrication of the metal electrodes of a tunnel junction device, according to exemplary embodiments of the present disclosure, is illustrated. Specifically, Figure 4A This demonstrates how an exemplary shadow evaporation mask can be configured to provide second-order correction for errors caused by the thickness of the shadow evaporation mask relative to its vertical position along the vertical axis (Y-axis). Figure 4A An exemplary shadow evaporation mask 100 and patterned openings 103 are schematically shown, wherein the shadow evaporation mask 100 is formed on a wafer 210, and the wafer 210 is disposed on a stage 400 within an evaporation chamber. Additionally, Figure 4A A first evaporation process E1 is schematically shown, which is performed to deposit a first metal electrode 410 on the surface of wafer 210, including a shaded image of patterned openings 103.

[0068] Figure 4A This illustrates the effect of variations in the thickness of the shadow evaporation mask (e.g., the thickness of the second reagent layer 102 (e.g., a PMMA layer)). The resulting geometric offset error 410-1 of the first metal electrode 410 in the Y direction will not adversely affect the electrode overlap area of ​​the tunnel junction device, because, for example, the region of the first metal electrode 410 including the geometric offset error 410-1 will be located in the undercut region 101-2 of the first anti-reagent layer 101 below the overhang portion 102-2 of the second anti-reagent layer 102.

[0069] also, Figure 4BThe shadow evaporation fabrication of the second metal electrode 412 is schematically illustrated. Any geometric offset error 412-1 of the second metal electrode 412 in the Y direction due to the thickness variation of the shadow evaporation mask 100 will be located in the undercut region 101-1 of the first reagent layer 101, which is located below the overhang portion 102-1 of the second reagent layer 102. Figure 4B As shown, the regions of potential geometric offset errors 410-1 and 412-1 are outside the overlap region 414 between the first metal electrode 410 and the second metal electrode 412. This indicates that no error is caused in the junction area of ​​the resulting tunnel junction device due to variations in the thickness of the shadow evaporation mask 100, particularly the shadow evaporation mask 100. Therefore, regardless of the error in the desired thickness of the shadow evaporation mask 100, the tunnel junction device fabricated on wafer 210 will have the same Y-axis between the corresponding first and second metal electrodes. O overlapping.

[0070] Next, Figure 5 and Figure 6 An exemplary embodiment of the present disclosure illustrates a method for configuring a shadow evaporation mask in combination with shadow evaporation parameters to compensate for a second error component in the fabrication of the metal electrodes of a tunnel junction device. Specifically, Figure 5 The illustration schematically depicts a method for determining the lateral overlap of metal electrodes in a tunnel junction device manufactured using a dual-angle shadow evaporation process, according to an exemplary embodiment of the present disclosure. Figure 6 An exemplary configuration of a dual-angle shadow evaporation process for wafer-level fabrication of tunnel junction devices according to exemplary embodiments of the present disclosure is illustrated to achieve the same amount of lateral overlap of the metal electrodes of the respective tunnel junction devices formed in different regions of the wafer. Figure 5 and Figure 6 This schematically illustrates how an exemplary shadow evaporation mask and shadow evaporation parameters can be configured to correct the X-ray difference between the respective first and second metal electrodes of a tunnel junction device on a wafer. O Overlap error, to ensure that each tunnel junction device along its respective path Figure 2A Parallel axes (X-axis) in the same or substantially the same X-axis have the same or substantially the same X-axis. O Overlap, regardless of the evaporation angle deviation in different parts of the wafer region.

[0071] Figure 5 An exemplary shadow evaporation mask 100 and patterned openings 103 are schematically shown, wherein the shadow evaporation mask 100 is formed on a wafer 210 and the wafer 210 is disposed on a stage 510 in an evaporation chamber. Figure 5A first evaporation process E1 is schematically illustrated, which is performed to deposit a first metal electrode 511 on the surface of wafer 210, including a shaded image of patterned openings 103, followed by an in-situ oxidation process to form an oxide layer 512 on the exposed surface of the first metal electrode 511. Additionally, Figure 5 The diagram schematically illustrates a second evaporation process E2 performed to deposit a second metal electrode 513, the second metal electrode 513 including a patterned opening 103 in a shaded image.

[0072] Figure 5 It is also shown that the patterned opening 103 in the X direction includes a lateral dimension X, and the resulting tunnel junction device is formed by an overlapping region having an X0 overlap between the first metal electrode 511 and the second metal electrode 513, wherein a portion of the oxide layer 512 is disposed between the overlapping first metal electrode 511 and the second metal electrode 513. The evaporated metal of the first evaporation process E1 is shown having a first incident angle α to the surface of the wafer 210, and the evaporated metal of the second evaporation process E2 is shown having a second incident angle β to the surface of the wafer 210, wherein the first angle α and the second angle β are different angles, and based on the position of the patterned opening 103 on the region of the wafer 210. Figure 5 The exemplary parameters shown herein, wherein the X0 overlap between the first metal electrode 511 and the second metal electrode 513 is determined as follows: .

[0073] Figure 6 Exemplary evaporation parameters according to exemplary embodiments of the present disclosure are schematically illustrated. These evaporation parameters are selected to ensure that wafer-level fabrication of the tunnel junction device results in the tunnel junction device having the same amount of X0 overlap between its respective first and second metal electrodes, regardless of the tunnel junction device's location on the wafer. In particular, Figure 6 An exemplary configuration 600 of a dual-angle shadow evaporation process is shown to enable wafer-level fabrication of tunnel junction devices on a wafer 210 disposed on a wafer stage 610. Figure 6A first crucible 601 (or first evaporation (point) source) for performing a first evaporation process E1 and a second crucible 602 (or second evaporation (point) source) for performing a second evaporation process E2 are schematically shown. As is known in the art, a crucible is a component comprising the material to be evaporated (evaporated material) and the material to be deposited. The evaporated material (e.g., a superconducting metallic material such as aluminum) is heated to evaporate, and the evaporated material is guided at a given angle to the surface of a wafer to form thin film features, such as metal electrodes for tunnel junction devices. Although a separate first crucible 601 and second crucible 602 are shown for illustrative purposes, in some embodiments, the electron beam evaporation system will include a single crucible positioned by moving the crucible or rotating the wafer 210 and used for both evaporation processes E1 and E2. Furthermore, in some embodiments, the wafer stage 610 is configured for rotation and tilting, wherein tilting of the wafer stage 610 allows for changing the evaporation angle, as will be discussed below. Figure 7A and 7B Further detailed discussion is needed.

[0074] Figure 6 A first point P1 on the surface of wafer 210 is schematically shown, where the evaporated metal of the first evaporation process E1 is shown with a first incident angle α to the surface of wafer 210, and the evaporated metal of the second evaporation process E2 is shown with a second incident angle β to the surface of wafer 210, wherein the first angle α and the second angle β are different angles. Additionally, Figure 6 A second point P2 on the surface of wafer 210 is schematically shown, wherein the incident angle of the evaporated metal of the corresponding first evaporation process E1 and the second evaporation process E2 at the second point P2 is shown as different from the incident angles α and β of the evaporated metal of the corresponding first evaporation process E1 and the second evaporation process E2 at the first point P1.

[0075] In some embodiments, to ensure that the X0 overlap between the first and second metal electrodes of the first tunnel junction device formed at a first point P1 on the surface of wafer 210 is the same as or substantially similar to the X0 overlap between the first and second metal electrodes of the second tunnel junction device formed at a second point P2 on the surface of wafer 210, the following evaporation parameters are selected. For example, the height h of the first crucible 601 and the height H of the second crucible 602 are set at the same height above the surface of the wafer stage 610 in the XZ plane, i.e., h=H. Furthermore, the first crucible 601 and the second crucible 602 are disposed in the XZ plane (Y=0) at a lateral distance L (in the X direction), and wherein the first crucible 601 and the second crucible 602 are disposed at a lateral distance L / 2 (in the X direction) from the center point of wafer 210.

[0076] In this exemplary configuration, by setting =A constant is used to apply a constant overlap region, where Based on the relationship between different parameters, the lateral distance L is equal to: It can be restated as: However, when h=H, then Using these exemplary conditions, the X-rays between the first and second metal electrodes of the tunnel junction device across the surface of wafer 210... O The overlap will be a constant: .

[0077] Next, Figure 7A and 7B A dual-angle shadow evaporation process for wafer-level fabrication of tunnel junction devices according to another exemplary embodiment of the present disclosure is schematically illustrated. In particular, Figure 7A and 7B An exemplary electron beam evaporation system 700 is schematically shown, which includes a single evaporation source 702 and a wafer stage 710 configured to rotate and tilt. Figure 7A An exemplary configuration is schematically shown, in which a wafer 210 (with a shadow evaporation mask formed on its surface) is arranged on a wafer stage 710, and the center point (origin) of the wafer 210 is arranged at a lateral distance (in the X direction) of L / 2. Furthermore, Figure 7A The diagram shows (i) the evaporation angle γ, which represents the angle between the evaporation source 702 and the center point of the wafer 210, (ii) the dashed line R, which represents the distance (beam vector) from the evaporation source 702 to the center point of the wafer 210, and (iii) the height h of the evaporation source 702 along the surface normal of the wafer stage 710.

[0078] In the exemplary configuration, the height h is determined as And the parameter L is determined to be To ensure that the X0 overlap between the first and second metal electrodes of the tunnel junction device formed on the surface of wafer 210 is constant, the same evaporation angle γ is used for the first and second evaporation processes E1 and E2, such as... Figure 7A and 7B As shown, the constant X0 overlaps as follows: Where X represents the lateral dimension X of the exemplary patterned opening 103 of the shadow evaporation mask 100. This represents the total thickness of the shadow evaporation mask, for example, combined with the above. Figure 5 and 6 As shown and discussed.

[0079] Figure 7AThe first evaporation process E1 is schematically illustrated, which is performed by tilting the wafer stage 710 such that the XY plane of the wafer stage 710 is set at the height h of the normal to the XY plane of the wafer stage 710 and at the target evaporation angle. Degree. In Figure 7A In the wafer stage 710, the first side 710-1 is tilted upwards, and the second side 710-2 is tilted downwards. On the other hand, Figure 7B The second evaporation process E2 is schematically illustrated, which is performed by rotating the wafer stage 710 by 180 degrees, such that the first side 710-1 of the wafer stage 710 is tilted downward away from the evaporation source 720, and the second side 710-2 of the wafer stage 710 is tilted upward toward the evaporation source 720. In this exemplary system 700, the evaporation source 702 remains fixed, while the desired evaporation angles of the first evaporation process E1 and the second evaporation process E2 are configured by correspondingly rotating and tilting the wafer stage 710. And height h, while the center point of wafer 210 remains aligned with the center point of wafer stage 710.

[0080] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that this disclosure is not limited to those precise embodiments, and various other changes and modifications can be made therein by those skilled in the art without departing from the scope of the appended claims.

Claims

1. A method comprising: A shadow evaporation mask is formed on a substrate, the shadow evaporation mask including a plurality of patterned openings in different regions of the substrate, each of the patterned openings including an opening of the same size and shape; and A dual-angle evaporation process is performed using a shadow evaporation mask to form multiple tunnel junction devices in each different region of a substrate. Each tunnel junction device includes a first metal layer and a second metal layer with overlapping regions, wherein the overlapping regions of the tunnel junction devices remain unchanged in different regions of the substrate.

2. The method according to claim 1, wherein, The patterned openings of the shadow evaporation mask are configured to provide self-correction of geometric errors when forming the first metal layer and the second metal layer of the tunnel junction device in different regions of the substrate, so as to ensure that the amount of overlap between the first metal layer and the second metal layer of each tunnel junction device remains constant in different regions of the substrate.

3. The method according to any one of the preceding claims, wherein, Performing the dual-angle evaporation process includes: A first evaporation process is performed at a first angle to deposit the first metal layer of each tunnel junction device, wherein the first metal layer of each tunnel junction device includes a first shadow image of a corresponding patterned opening in the patterned opening; An insulating layer is formed on the first metal layer of each tunnel junction device; and A second evaporation process is performed at a second angle to deposit the second metal layer of each tunnel junction device, wherein the second metal layer of each tunnel junction device includes a second shadow image of a corresponding patterned opening in the patterned opening.

4. The method according to any one of the preceding claims, wherein, The patterned openings of the shadow evaporation mask each comprise a quadrilateral opening of the same size and having at least one non-right-angled opening.

5. A method comprising: A shadow evaporation mask is formed on a substrate, the shadow evaporation mask including a plurality of patterned openings in different regions of the substrate, wherein each patterned opening includes a quadrilateral opening of the same size and having at least one non-right-angled opening; A first evaporation process is performed at a first angle to deposit a first metal layer, the first metal layer including a first shadow image of the patterned opening; An insulating layer is formed on each of the first metal layers; and A second evaporation process is performed at a second angle to deposit a second metal layer, the second metal layer including a second shadow image of the patterned openings; Wherein, a portion of the second metal layer overlaps with a corresponding portion of the first metal layer to form a corresponding tunnel junction device in different regions of the substrate, the tunnel junction device comprising overlapping metallized regions having the same size and having at least one non-right-angled quadrilateral projection region.

6. The method of claim 5, wherein the first evaporation process and the second evaporation process are each performed at the same height above the substrate along the central axis of the substrate.

7. The method according to any one of claims 5 to 6, wherein: The quadrilateral openings in the patterned openings of the shadow evaporation mask include parallelogram openings with non-right angles. Each parallelogram opening includes a first angled edge and a second angled edge; and The first angled edge and the second angled edge each include an angle relative to the central axis of the substrate, the angle being greater than the maximum evaporation angle of the conical evaporation metal stream generated by the evaporation source during the execution of the first evaporation process and the second evaporation process.

8. The method according to any one of claims 5 to 7, wherein: Performing the first evaporation process includes evaporating and depositing a superconducting metal material to form the first metal layer; Forming an insulating layer on each of the first metal layers includes oxidizing the exposed surfaces of the first metal layers to form a metal oxide layer; and Performing the second evaporation process includes evaporating and depositing the superconducting metal material to form the second metal layer.

9. The method according to any one of claims 5 to 8, wherein: Each of the first metal layers includes an extension portion that provides a first contact pad for a corresponding tunnel junction device; and Each of the second metal layers includes an extension portion that provides a second contact pad for the tunnel junction device.

10. The method according to any one of claims 5 to 9, wherein, The tunnel junction device includes a Josephson junction of superconducting qubits.

11. The method according to any one of claims 5 to 10, wherein, Forming the shadow evaporation mask on the substrate includes: A first resist layer is deposited on the substrate; Deposit a second resist layer on the first resist layer; The first resist layer and the second resist layer are patterned to form patterned openings in the first resist layer and the second resist layer; The patterned openings in the second resist layer each include a first suspension portion and a second suspension portion, wherein the first suspension portion and the second suspension portion include corresponding first and second angled edges of the quadrilateral opening; and The patterned openings of the first resist layer each include a first undercut region below the first suspension portion and a second undercut region below the second suspension portion.

12. The method according to claim 11, wherein: The first resist layer comprises a spin-coated methyl methacrylate layer; and The second resist layer comprises a spin-coated polymethyl methacrylate layer.

13. A device comprising a shadow evaporation mask including a first layer and a second layer disposed above the first layer, and a plurality of uniformly patterned openings configured to fabricate a tunnel junction device of a corresponding uniform shape on a substrate by bi-angle shadow evaporation.

14. The device according to claim 13, wherein, Each patterned opening includes a quadrilateral opening with at least one right angle, the opening being configured to generate a shadow image of the overlapping electrodes of the corresponding tunnel junction device.

15. A device comprising: A first metal layer is disposed on a substrate; An insulating layer disposed on the first metal layer; and A second metal layer is disposed on the insulating layer; Wherein, a portion of the second metal layer overlaps with a portion of the first metal layer to form a stacked structure, the stacked structure including overlapping metallized regions, wherein a portion of the insulating layer is disposed between the overlapping metallized regions, wherein the stacked structure includes a tunnel junction device having at least one non-right-angled quadrilateral projection area.

16. The device according to claim 15, wherein: The first metal layer and the second metal layer each comprise a superconducting metal; and The insulating layer comprises an oxide of a superconducting metal.

17. The device according to any one of claims 15 to 16, wherein: The quadrilateral projection area of ​​the tunnel junction device includes a parallelogram projection area with non-right angles; and The first metal layer and the second metal layer each include a parallelogram region with non-right angles.

18. The device according to claim 17, wherein: The first metal layer includes an extension that provides a first contact pad for the tunnel junction device; and The second metal layer includes an extension that provides a second contact pad for the tunnel junction device.

19. The device according to claim 16, wherein, The tunnel junction device includes a Josephson junction of superconducting qubits.

20. A device comprising: Multiple tunnel junction devices are disposed on a substrate; Each tunnel junction device includes a corresponding stacked structure, the stacked structure including an overlapping portion of a first metal layer and a second metal layer, and an insulating layer disposed between the overlapping portions; and The corresponding stacked structure includes a quadrilateral projection area with at least one non-right angle.

21. The device according to claim 20, wherein, The quadrilateral projection areas of the stacked structure have substantially the same projection area.

22. The device according to any one of claims 20 to 21, wherein: The first metal layer and the second metal layer each comprise a superconducting metal; and The insulating layer comprises an oxide of a superconducting metal.

23. The device according to any one of claims 20 to 22, wherein: The first metal layer and the second metal layer each include a quadrilateral projection area having at least one non-right-angled quadrilateral; and The overlapping portion of the first metal layer and the second metal layer forms a quadrilateral projection area of ​​the stacked structure.

24. The device according to any one of claims 20 to 23, wherein: The first metal layer includes an extension that provides a first contact pad for the tunnel junction device; and The second metal layer includes an extension that provides a second contact pad for the tunnel junction device.

25. The device according to any one of claims 20 to 24, wherein the tunnel junction device comprises a Josephson junction of a superconducting quantum bit.

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