An asynchronous envelope detector based on zero-crossing events of an input signal

Abstract

The present application belongs to the field of digital-analog hybrid integrated circuits, and particularly relates to an asynchronous envelope detector based on zero-crossing events of an input signal. The asynchronous envelope detector based on zero-crossing events of the input signal can flexibly adapt to input signals of different frequencies, and the detection timing thereof is directly driven by zero-crossing events of the input signal, so that real-time envelope detection can be realized without an external clock. The design completely relies on dynamic characteristics of the input signal itself to realize asynchronous adaptive operation, so that the working frequency of the envelope detector can be automatically adjusted according to the change of the input signal frequency, thereby maintaining stable detection precision and rapid response capability under the condition of wide-band signals from low frequency to high frequency. The present application does not require complex clock distribution and control logic, significantly reduces system power consumption and design complexity, can realize high real-time and high energy efficiency envelope extraction in a high-speed signal environment, and is very suitable for integrated implementation and high-speed signal processing applications.

Description

Technical Field

[0001] This invention belongs to the field of digital-analog hybrid integrated circuits, specifically an asynchronous envelope detector based on the zero-crossing event of the input signal. Background Technology

[0002] In modern communication systems, high-speed signals are widely used for information transmission, and their envelope amplitude carries important intensity information. Traditional envelope detection typically employs a sample-and-hold structure, where the detection process relies on an external clock to control the peak capture and reset timing. This type of detection method can function normally under low-speed or fixed-frequency conditions, but it exhibits significant limitations in high-speed, wideband, or dynamically changing frequency signal environments.

[0003] In high-speed signal scenarios, clock-sampling envelope detection circuits require high-precision clock allocation and synchronization control logic. This not only results in complex structures and high power consumption, but also makes it difficult to ensure that the sampling phase remains consistent with the input signal, leading to errors or distortion in envelope detection. Furthermore, to adapt to signals of different frequencies, these envelope detection circuits often require additional clock multiplication, division, or reset control units, further increasing the complexity of the system design.

[0004] In summary, existing technologies for envelope detection of high-speed signals suffer from problems such as complex structure, insufficient real-time performance, and high power consumption. There is an urgent need for a novel detection mechanism that can achieve envelope detection based on the characteristics of the input signal itself, without requiring an external clock drive. Summary of the Invention

[0005] To address the aforementioned problems or shortcomings, this invention provides an asynchronous envelope detector based on zero-crossing events of the input signal. By continuously comparing the input signal with multiple reference levels within each half-cycle and automatically latching the results, real-time extraction of the signal envelope is achieved. Since the zero-crossing event of the input signal drives result storage and circuit reset, the detection timing is entirely driven by the zero-crossing event, requiring no external clock and achieving fully asynchronous timing logic.

[0006] The technical solution of the present invention is as follows:

[0007] An asynchronous envelope detector based on the zero-crossing event of an input signal includes a zero-crossing comparator, a reference level generation module, a continuous-time comparator, and a comparison result self-locking module.

[0008] The zero-crossing comparator compares the input signal VIN with the common-mode level VCM in real time, detects the zero-crossing reversal event of the input signal, divides the signal into half-cycles, and generates a control signal at the half-cycle boundary.

[0009] The reference level generation module, through 2 NA resistor series voltage divider network, consisting of resistors of equal resistance and two reference voltages Vrefp and Vrefn, is used to generate 2... N -1 equally spaced reference level , , …… One of the reference levels Equivalent to the common-mode level VCM; N represents the resolution of envelope detection, corresponding to a quantization level of 2. N .

[0010] The continuous-time comparator is divided into two groups, each with 2... N-1 -1 item, totaling 2 N -2, connected in a one-to-one correspondence except 2 outside N -2 reference levels are used to compare the input signal with the output signal. 2 outside N - Two reference levels are compared in real time to obtain the maximum amplitude of the input signal in the current half-cycle, and the result is output to the comparison result self-locking module; two sets of continuous time comparators compare two different signal half-cycles when VIN is greater than and less than the common-mode level.

[0011] The comparison result self-locking module is divided into two groups, with 2 modules in each group. N-1 -1 item, totaling 2 N -2, connected in a one-to-one correspondence between the two groups, totaling 2 N - After two continuous-time comparators, the result is automatically latched immediately when the two sets of continuous-time comparators compare the results, and remains unchanged for the remaining half-cycle of the signal until the next zero-crossing event of the input signal triggers the reset signal; the output of the comparison result self-locking module represents the envelope size of the input signal in the form of thermometer code.

[0012] Furthermore, the comparison result self-locking module adopts an SR latch architecture, which replaces the traditional synchronous clock trigger with automatic latching logic to achieve asynchronous timing without external clock driving. This module, through its simple combinational logic path, minimizes the propagation delay from comparison completion to data latching, significantly improving system bandwidth. Combined with preset non-overlapping timing constraints, it achieves fast response while mitigating the metastability risk of the SR latch from a mechanism perspective.

[0013] Furthermore, the two groups total 2 N - Two comparison results are each followed by a D flip-flop. The D flip-flops are divided into two groups, each with 2 flip-flops. N-1 -1 item, total 2 N-2, connected in a one-to-one correspondence after the comparison result self-locking module; the D flip-flop uses the pulse signal generated by the zero-crossing event as the trigger source to store the result automatically latched by the comparison result self-locking module of the previous half cycle; the D flip-flop only performs state refresh at the half cycle boundary, filtering out the dynamic fluctuations of the automatically latched result within the half cycle, thereby outputting a stable digital envelope output with no glitches and a step-by-step smooth update.

[0014] Furthermore, the D flip-flop adopts a true single-phase clock architecture, which avoids the stringent requirements of traditional D flip-flops for differential clock complementarity from the source through the single-phase clock driving mechanism; with its simple transistor topology, this module significantly reduces dynamic power consumption while greatly increasing the upper limit of the operating frequency and significantly improving the system bandwidth.

[0015] In this invention, the envelope detector uses zero-crossing events as markers to divide the signal into half-cycles. It compares the input signal with multiple reference levels to obtain the maximum value of the signal within the current half-cycle, i.e., the envelope size. This result is automatically latched and stably stored at the next zero-crossing event, and a new round of envelope detection begins. The detection timing is driven by the zero-crossing events of the input signal, operating completely asynchronously.

[0016] Furthermore, the envelope detector divides the signal into two half-cycles: one when the input signal is greater than the common-mode level and the other when it is less than the common-mode level. Envelope detection is performed within each half-cycle, and the result of the previous half-cycle is stored and the circuit is reset at the next zero-crossing event, preparing for the next round of detection. Since no external clock drive or reset is required, the operating frequency of the envelope detector can follow the change of the input signal frequency. Therefore, this structure can achieve real-time envelope detection under wideband signal conditions from low frequency to high frequency.

[0017] Furthermore, the specific workflow of the asynchronous envelope detector based on the zero-crossing event of the input signal described above is as follows:

[0018] When VIN is maintained at the common-mode level, the output of the zero-crossing comparator does not flip and does not trigger the flag signal. At the same time, the continuous-time comparator does not work, and the outputs remain unchanged. The envelope detector is in the waiting stage.

[0019] When VIN is greater than the common-mode level, one end of the differential output of the zero-crossing comparator flips, triggering flag signal ZC1. Conversely, when VIN is less than the common-mode level, the other end of the differential output of the zero-crossing comparator flips, triggering flag signal ZC2. Based on the flag signals ZC1 and ZC2 triggered by the zero-crossing event, the complete period of the input signal is divided into two half-cycles. Within each half-cycle, there are two sets of 2... N-1 -1 continuous-time comparators operate, comparing the input signal with multiple reference levels.

[0020] Within the half-cycle corresponding to VIN being greater than the common-mode level, one group of 2 N-1 -1 continuous-time comparator compares VIN with... , ... 2 in total N-1 -1 reference level is compared, where the reference level is obtained by voltage division of the reference voltages Vrefp and Vrefn through a resistor series. When VIN is greater than And less than When 1≤i<2 N-1 -1, the outputs of the first i comparators from the least significant bit to the most significant bit are flipped, leaving 2. N-1 -1-i comparator outputs do not flip; while when VIN is greater than... At that time, all 2 in the group N-1 -1. The outputs of all comparators are flipped.

[0021] During the half-cycle corresponding to VIN being less than the common-mode level, another set of 2 N-1 -1 continuous-time comparator compares VIN with... , ... 2 in total N-1 -1 reference level is compared, when VIN is less than And greater than When 1≤j<2 N-1 -1, the first j comparator outputs from the most significant bit to the least significant bit are flipped, leaving 2. N-1 -j-1 comparator outputs do not flip, while when VIN is less than At that time, all 2 in the group N-1 -1. The outputs of all comparators are flipped.

[0022] 2 per group N-1 The toggle result of -1 continuous-time comparator corresponds to 2. N-1 -1 bit numeric codeword VOUT_C<1:2 N-1 -1>, this result is obtained through the corresponding set of 2 N-1 -1 comparison result is automatically latched by the self-locking module, resulting in a signal envelope output in thermometer code form, VOUT_L<1: 2 N-1 -1>, Once the comparison result is automatically latched, even if the input signal changes, the output VOUT_L<1: 2 will remain active until the self-locking module is reset by the next zero-crossing event. N-1 -1> remains unchanged, thus achieving the maximum amplitude reached within half a cycle of the recorded input signal.

[0023] When VIN changes from less than the common-mode level to greater than the common-mode level, one end of the differential output of the zero-crossing comparator flips, triggering the flag signal ZC1; and when VIN changes from greater than the common-mode level to less than the common-mode level, the other end of the differential output of the zero-crossing comparator flips, triggering the flag signal ZC2; the rising edge of the flag signal ZC1 or ZC2 generates a reset pulse signal RESET_L, which resets the comparison result self-locking module to prepare for a new round of detection; at the same time, the continuous time comparator corresponding to the current half-cycle starts working and begins to record the maximum amplitude of the input signal in the current half-cycle.

[0024] As VIN continuously crosses the common-mode level, the envelope detector detects the maximum value reached by the signal in each half-cycle in real time. The output of the self-locking module always represents the latest envelope size of the signal until VIN is maintained at the common-mode level again, at which point the envelope detector stops working.

[0025] In summary, the asynchronous envelope detector based on zero-crossing events of the input signal of this invention can flexibly adapt to input signals of different frequencies. Its detection timing is directly driven by the zero-crossing events of the input signal, achieving real-time envelope detection without the need for an external clock. This design relies entirely on the dynamic characteristics of the input signal itself to achieve asynchronous adaptive operation, enabling the operating frequency of the envelope detector to automatically adjust with changes in the input signal frequency. This maintains stable detection accuracy and fast response capability under wideband signal conditions from low to high frequencies. This invention eliminates the need for complex clock allocation and control logic, significantly reducing system power consumption and design complexity. It can achieve high real-time performance and high energy efficiency envelope extraction in high-speed signal environments, making it highly suitable for integrated implementation and high-speed signal processing applications. Attached Figure Description

[0026] Figure 1 This is a block diagram of the overall structure of the envelope detector of the present invention;

[0027] Figure 2 This is a specific structural block diagram of the present invention;

[0028] Figure 3 This is a detailed structural block diagram of the embodiment;

[0029] Figure 4 for Figure 3 Schematic diagram of the embodiment. Detailed Implementation

[0030] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0031] Figure 1The diagram shows the overall structure of the asynchronous envelope detector based on the zero-crossing event of the input signal according to the present invention. It consists of three parts: a zero-crossing comparator 101, a reference level generation module 102, and an amplitude detection module 103. The input signal VIN is detected by the zero-crossing comparator 101 to generate a half-cycle flag signal ZC to divide the overall working timing. The reference level generation module 102 generates multiple levels of reference levels for comparison by the amplitude detection module. Driven by the flag signal ZC, the amplitude detection module 103 performs amplitude comparison and result latching on the input signal within half a cycle, thereby realizing asynchronous envelope detection.

[0032] Figure 2 This is a block diagram of the specific structure of the N-bit asynchronous envelope detector based on the zero-crossing event of the input signal of the present invention, including a zero-crossing comparator 201, a reference level generation module 202, a continuous-time comparator 203, and a comparison result self-locking module 204; where N represents the resolution of the envelope detection, and the corresponding quantization level is 2. N .

[0033] An example of an asynchronous envelope detector based on zero-crossing events of the input signal with a resolution of 4 bits will be described.

[0034] The specific structural block diagram of this embodiment is as follows: Figure 3 As shown, it includes a zero-crossing comparator 301, a reference level generation module 302, two sets of seven continuous-time comparators 303, a comparison result self-locking module 304, a D flip-flop 305, and a binary encoder 306. The envelope detection resolution is 4, corresponding to a quantization level of 16. ZC1 and ZC2 represent the flag signals triggered by the zero-crossing event, CLK_D1 and CLK_D2 represent the trigger signals generated by the flag signals ZC1 and ZC2, and REST_L1 and REST_L2 represent the reset pulse signals generated by the trigger signals CLK_D1 and CLK_D2. V ref1 V ref2 ... V ref15 This represents the reference levels generated by the reference level generation module, which are equally spaced.

[0035] The zero-crossing comparator 301 compares the input signal VIN with the common-mode level VCM in real time, detects the zero-crossing reversal event of the input signal, divides the signal into half-cycles, and generates a control signal at the half-cycle boundary.

[0036] The reference level generation module 302 uses a resistor series voltage divider network composed of 16 resistors of equal value and two reference voltages Vrefp and Vrefn to generate 15 equally spaced reference levels V. ref1 V ref2 ... V ref15 One of the reference levels V ref7Equivalent to the common-mode level VCM.

[0037] The continuous-time comparators 303 are divided into two groups of seven, totaling 14, and are connected in a one-to-one correspondence except for V. ref7 The 14 reference levels, excluding V, are used to compare the input signal with... ref7 The system compares 14 reference levels in real time to obtain the maximum amplitude of the input signal within the current half-cycle, and outputs the result to the comparison result self-locking module. Two sets of continuous-time comparators compare two different signal half-cycles when VIN is greater than and less than the common-mode level.

[0038] The comparison result self-locking module 304 is divided into two groups of seven, totaling 14 modules, which are connected in a one-to-one correspondence after the two groups of 14 continuous-time comparators. It is used to automatically latch the comparison result immediately after the continuous-time comparator comparison is completed, and keep it unchanged for the remaining half-cycle of the signal until the next zero-crossing event of the input signal triggers the reset signal. The output of the comparison result self-locking module represents the envelope size of the input signal in the form of thermometer code.

[0039] The D flip-flops 305 are divided into two groups of 7, for a total of 14. They are connected in a one-to-one correspondence to the two groups of 14 comparison result self-locking modules. When a zero-crossing event occurs, the result of the automatic latching of the previous half-cycle is stored to obtain a stable digital envelope output.

[0040] There are two binary encoders 306, which are connected after the two sets of D flip-flops respectively, and are used to convert the 7-bit thermometer code output of each of the two sets of D flip-flops into a 3-bit binary code output.

[0041] The principle of this embodiment is as follows: Figure 4 As shown:

[0042] The following example illustrates the process of the input signal VIN starting above the common-mode level, gradually decreasing to below the common-mode level, and then increasing back above the common-mode level.

[0043] During the half-cycle corresponding to VIN being greater than the common-mode level, a group of seven continuous-time comparators compare VIN with V... ref9 V ref10 ... V ref15 A total of 7 reference levels are compared. When VIN is greater than V... ref8+i And less than V ref9+i When (1≤i<7), the outputs of the first i comparators from the least significant bit to the most significant bit are toggled, while the outputs of the remaining 7-i comparators are not toggled; however, when VIN is greater than V... ref15At this time, all seven comparator outputs toggle. The comparison result VOUT_C1<1:7> is automatically latched by a set of seven self-locking modules, resulting in a signal envelope output VOUT_L1<1:7> in the form of thermometer code. Even if the input signal decreases, causing the comparison result to change from high to low, after the comparison result is automatically latched, the signal envelope output VOUT_L1<1:7> remains unchanged until the self-locking module is reset at the next zero-crossing point, thus recording the maximum amplitude reached within the current half-cycle.

[0044] As VIN gradually decreases below the common-mode level, the differential output of the zero-crossing comparator flips, triggering the flag signal ZC2. ZC2 first generates a trigger signal CLK_D1, which triggers a set of seven D flip-flops to store the output VOUT_L1<1:7> of the seven comparison result self-locking modules corresponding to the previous half-cycle, obtaining a stable digital envelope output VOUT_D1<1:7>. Then, the corresponding binary encoder converts the 7-bit thermometer code into a 3-bit binary encoded output VOUT_E1<1:3>. After VOUT_L1<1:7> is stored, the trigger signal CLK_D1 generates a reset pulse signal RESET_L1 to reset the seven comparison result self-locking modules corresponding to the previous half-cycle, preparing for a new round of detection.

[0045] During the half-cycle corresponding to VIN being less than the common-mode level, another set of seven continuous-time comparators compares VIN with V... ref7 V ref6 ... V ref1 A total of 7 reference levels are compared. When VIN is less than V... ref8-j And greater than V ref7-j When VIN is less than V (1≤j<7), the outputs of the first j comparators from the most significant bit to the least significant bit are flipped, while the outputs of the remaining 7-j comparators are not flipped; however, when VIN is less than V ref1 At that time, all 7 comparator outputs are flipped.

[0046] When VIN increases and exceeds the common-mode level, the differential output of the zero-crossing comparator flips, triggering the flag signal ZC1. ZC1 first generates a trigger signal CLK_D2, which triggers a set of seven D flip-flops to store the output VOUT_L2<1:7> of the seven comparison result self-locking modules corresponding to the previous half-cycle, obtaining a stable digital envelope output VOUT_D2<1:7>. Then, the corresponding binary encoder converts the 7-bit thermometer code into a 3-bit binary output signal VOUT_E2<1:3>. After VOUT_L2<1:7> is stored, the trigger signal CLK_D2 generates a reset pulse signal RESET_L2, resetting the seven comparison result self-locking modules corresponding to the previous half-cycle to prepare for a new round of detection.

[0047] When VIN is maintained at the common-mode level, the envelope detector is in the waiting phase, the output of the zero-crossing comparator does not flip, there is no trigger flag signal, and all continuous-time comparators are not working, their outputs remain unchanged.

[0048] As can be seen from the above embodiments, this invention fully utilizes the zero-crossing characteristics of the input signal itself to trigger the detection timing, achieving envelope detection without the need for external clock control. This structure automatically divides the signal period using zero-crossing events detected by a zero-crossing comparator, and uses multiple continuous-time comparators to compare the input signal with a reference level in real time, thereby accurately extracting the maximum amplitude of the signal within each half-cycle. The comparison result is held by a self-locking module and is stored and reset upon the arrival of the next zero-crossing event, forming an asynchronous adaptive detection process. Compared with traditional clock-sampling envelope detection circuits that rely on an external clock, this invention significantly reduces system power consumption and timing complexity, while improving detection real-time performance and frequency adaptability. This technology is particularly suitable for real-time extraction of envelope information in broadband, high-speed, low-power signal processing systems.

Claims

1. An asynchronous envelope detector based on zero-crossing events of the input signal, characterized in that: It includes a zero-crossing comparator, a reference level generation module, a continuous-time comparator, and a comparison result self-locking module; The zero-crossing comparator compares the input signal VIN with the common-mode level VCM in real time, detects the zero-crossing reversal event of the input signal, divides the signal into half-cycles, and generates control signals at the half-cycle boundaries. The reference level generation module, through 2 N A resistor series voltage divider network, consisting of resistors of equal resistance and two reference voltages Vrefp and Vrefn, is used to generate 2... N -1 equally spaced reference level , , …… One of the reference levels Equivalent to the common-mode level VCM; N represents the resolution of envelope detection, corresponding to a quantization level of 2. N ; The continuous-time comparator is divided into two groups, each with 2... N-1 -1 item, totaling 2 N -2, connected in a one-to-one correspondence except 2 outside N -2 reference levels are used to compare the input signal with the output signal. 2 outside N - Two reference levels are compared in real time to obtain the maximum amplitude of the input signal in the current half-cycle, and the result is output to the comparison result self-locking module; two sets of continuous time comparators compare two different signal half-cycles when VIN is greater than and less than the common-mode level; The comparison result self-locking module is divided into two groups, each group has 2 N-1 -1, a total of 2 N -2, connected in a one-to-one corresponding manner in the two groups N -2 continuous time comparators, for automatically latching the comparison result when the two groups of continuous time comparators compare the result, and keeping unchanged for the remaining signal half cycle until the next input signal zero crossing event triggers the reset signal; the output result of the comparison result self-locking module represents the envelope size of the input signal in the form of thermometer code.

2. The asynchronous envelope detector based on zero-crossing events of the input signal as described in claim 1, characterized in that: The comparison result self-locking module adopts an SR latch architecture, which replaces the traditional synchronous clock triggering with automatic latching logic to achieve asynchronous timing without external clock driving.

3. The asynchronous envelope detector based on zero-crossing events of the input signal as described in claim 1, characterized in that: The two groups are 2 N -2 comparison results are connected with D flip-flop after the self-locking module, and the D flip-flop is divided into two groups, 2 N-1 -1, a total of 2 N -2, connected in one-to-one correspondence after the comparison result self-locking module; the D flip-flop takes the pulse signal generated by the zero-crossing event as the trigger source, and stores the result automatically latched by the previous half-cycle comparison result self-locking module; the D flip-flop only performs state refresh at the half-cycle boundary.

4. The asynchronous envelope detector based on zero-crossing events of the input signal as described in claim 3, characterized in that: The D flip-flop adopts a true single-phase clock architecture. Through the single-phase clock driving mechanism, it avoids the stringent requirements of traditional D flip-flops for differential clock complementarity from the source. With its simple transistor topology, this module significantly reduces dynamic power consumption while greatly increasing the upper limit of the operating frequency and significantly improving the system bandwidth.

5. The asynchronous envelope detector based on zero-crossing events of the input signal as described in claim 1, characterized in that, The specific workflow is as follows: When VIN is maintained at the common-mode level, the output of the zero-crossing comparator does not flip and does not trigger the flag signal. At the same time, the continuous-time comparator does not work and the outputs remain unchanged. The envelope detector is in the waiting stage. When VIN is greater than the common-mode level, one end of the differential output of the zero-crossing comparator flips, triggering flag signal ZC1. When VIN is less than the common-mode level, the other end of the differential output of the zero-crossing comparator flips, triggering flag signal ZC2. Based on the flag signals ZC1 and ZC2 triggered by the zero-crossing event, the complete period of the input signal is divided into two half-cycles. Within each half-cycle, there are two groups of 2... N-1 -1 continuous-time comparator operates to compare the input signal with multiple reference levels; Within the half-cycle corresponding to VIN being greater than the common-mode level, one group of 2 N-1 -1 continuous-time comparator compares VIN with... , ... 2 in total N-1 -1 reference level is compared, where the reference level is obtained by voltage division of the reference voltages Vrefp and Vrefn through a resistor series; when VIN is greater than And less than When 1≤i<2 N-1 -1, the outputs of the first i comparators from the least significant bit to the most significant bit are flipped, leaving 2. N-1 -1-i comparator outputs do not flip; while when VIN is greater than... At that time, all 2 in the group N-1 -1. The outputs of the comparators are all flipped; During the half-cycle corresponding to VIN being less than the common-mode level, another set of 2 N-1 -1 continuous-time comparator compares VIN with... , ... 2 in total N-1 -1 reference level is compared, when VIN is less than And greater than When 1≤j<2 N-1 -1, the first j comparator outputs from the most significant bit to the least significant bit are flipped, leaving 2. N-1 -j-1 comparator outputs do not flip, while when VIN is less than At that time, all 2 in the group N-1 -1. The outputs of the comparators are all flipped; 2 per group N-1 The toggle result of -1 continuous-time comparator corresponds to 2. N-1 -1 bit numeric codeword VOUT_C<1: 2 N-1 -1>, this result is obtained through a corresponding set of 2 N-1 -1 comparison result is automatically latched by the self-locking module, resulting in a signal envelope output in thermometer code form, VOUT_L<1: 2 N-1 -1>, Once the comparison result is automatically latched, even if the input signal changes, the output VOUT_L<1: 2 will remain active until the self-locking module is reset by the next zero-crossing event. N-1 -1> remains unchanged, thereby achieving the maximum amplitude reached within half a cycle of the recorded input signal; When VIN changes from less than the common-mode level to greater than the common-mode level, one end of the differential output of the zero-crossing comparator flips, triggering the flag signal ZC1; and when VIN changes from greater than the common-mode level to less than the common-mode level, the other end of the differential output of the zero-crossing comparator flips, triggering the flag signal ZC2; the rising edge of the flag signal ZC1 or ZC2 generates a reset pulse signal RESET_L, resetting the comparison result self-locking module to prepare for a new round of detection; at the same time, the continuous-time comparator corresponding to the current half-cycle starts working, starting to record the maximum amplitude of the input signal in the current half-cycle; As VIN continuously crosses the common-mode level, the envelope detector detects the maximum value reached by the signal in each half-cycle in real time. The output of the self-locking module always represents the latest envelope size of the signal until VIN is maintained at the common-mode level again, at which point the envelope detector stops working.

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