Test machine
By designing a special connection method between the probe unit and the chipset, multiple chips can share a test channel, solving the problem of limited test resources and improving the efficiency and capacity of chip testing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI OPTICAL COMMUNICATIONS CORP
- Filing Date
- 2024-12-19
- Publication Date
- 2026-06-23
AI Technical Summary
In the chip testing process, testing resources are limited, and maximizing testing efficiency and capacity is a challenge.
Design a test bench that uses probe units connected to chipsets. Through a special connection method of the target probe subunit, multiple chips can share a test channel, reducing the number of channels occupied by a single chip. This includes the connection method of the first and third probes in the probe subunit, which ensures that the signals received by the chip select pins of different chips are different, ensuring that only one chip is selected to execute the test command when it receives the chip select instruction.
By sharing test channels, the efficiency and capacity of chip testing have been significantly improved, the number of channels occupied per chip has been reduced, and testing efficiency has been enhanced.
Smart Images
Figure CN122260072A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor equipment, and in particular to a testing machine. Background Technology
[0002] After chip manufacturing is completed, to ensure the chips function properly, they must be rigorously tested using an ATE (Automatic Test Equipment) machine to screen out qualified chips. The chip testing process is as follows: the test machine inputs test signals (excitation) into the chip, the chip processes them, and then the chip sends output feedback to the test machine. The test machine then makes a judgment to determine whether the chip is functioning correctly.
[0003] Therefore, given the limited testing resources (such as the number of test machines and the number of test channels on the test machines), maximizing testing efficiency and testing capacity has always been the focus of chip testing efforts. Summary of the Invention
[0004] This application provides a testing machine.
[0005] The testing equipment provided in this application includes:
[0006] A pattern generator is used to generate test signals, test commands, chip select instructions, and fixed signals.
[0007] The probe unit provides the test signal, the test command, the chip select instruction and the fixed signal to the chipset through the probe unit. The chipset includes at least two chips, and the at least two chips include a target chip. The target chip has a first pin, a second pin and at least two chip select pins.
[0008] The probe unit has at least two probe subunits corresponding to the at least two chips respectively, and is used to provide the test signal, the test command, the chip select instruction and the fixed signal to the at least two chips respectively. The at least two probe subunits include a target probe subunit corresponding to the target chip.
[0009] The target probe subunit includes a first probe, a second probe, and a third probe. The first probe is used to provide the test signal to the chip select pin of the target chip. The second probe is used to provide the test command and the chip select instruction to the first pin of the target chip. The third probe is used to provide a fixed signal to the second pin of the target chip.
[0010] At least one of the first probes in the target probe subunit is connected to the third probe. The at least one first probe connected to the third probe in different target probe subunits is not exactly the same, and the second probes in different target probe subunits are connected accordingly.
[0011] In some embodiments, the fixed signal is a power signal or a ground signal.
[0012] In some embodiments, the third probes of different probe subunits are connected accordingly.
[0013] In some embodiments, the second probes of different probe subunits are connected accordingly. Attached Figure Description
[0014] Those skilled in the art will understand that the accompanying drawings are provided to better understand this application and do not constitute any limitation on the scope of this application.
[0015] Figure 1A A schematic diagram of the pin mapping between a test instrument and a chipset provided in an embodiment of this application;
[0016] Figure 1B A schematic diagram of a portion of the third probe of a probe subunit corresponding to a chip select pin, provided in yet another embodiment of this application;
[0017] Figure 1C A schematic diagram of a portion of the third probe of a probe subunit corresponding to a chip select pin, provided in yet another embodiment of this application;
[0018] Figure 2 A schematic diagram of the timing action of the test vector in the test unit provided in another embodiment of this application;
[0019] Figure 3 This is a schematic diagram showing the arrangement of eight chips in four chipsets provided in another embodiment of this application. Detailed Implementation
[0020] To make the objectives, advantages, and features of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, used only to facilitate and clarify the illustration of the embodiments of this application. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and sometimes use different scales.
[0021] As used herein, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.
[0022] An embodiment of this application provides a testing machine, comprising:
[0023] A pattern generator is used to generate test signals, test commands, chip select instructions, and fixed signals.
[0024] The probe unit provides the test signal, the test command, the chip select instruction and the fixed signal to the chipset through the probe unit. The chipset includes at least two chips, and the at least two chips include a target chip. The target chip has a first pin, a second pin and at least two chip select pins.
[0025] The probe unit has at least two probe subunits corresponding to the at least two chips respectively, and is used to provide the test signal, the test command, the chip select instruction and the fixed signal to the at least two chips respectively. The at least two probe subunits include a target probe subunit corresponding to the target chip.
[0026] The target probe subunit includes a first probe, a second probe, and a third probe. The first probe is used to provide a fixed signal to a first pin of the target chip. The second probe is used to provide the test command and the chip select instruction to the first pin of the target chip. The third probe is used to provide the test signal to the chip select pin of the target chip.
[0027] At least one of the third probes in the target probe subunit is connected to the first probe. The at least one third probe connected to the first probe in different target probe subunits is not exactly the same, and the second probes in different target probe subunits are connected accordingly.
[0028] In some embodiments of this application, Figure 1A This is a schematic diagram showing the pin mapping between a test bench and a chipset provided in an embodiment of this application. Figure 1AAs shown, the mode generator 30 is used to generate test signals, test commands, chip select instructions, and fixed signals. The chipset 10 includes chips 11 and 12. Chips 11 and 12 each include chip select pins CS1 and CS2. Chips 11 and 12 also include a first pin CMD, which is used to receive test commands and chip select instructions. Chips 11 and 12 also include a second pin VDD, which is used to receive fixed signals.
[0029] In some embodiments of this application, the chipset has 2 chips. N If there are 2N chip select pins for each chip, and N probe subunits within a probe unit, then each probe subunit has 2N third probes, where N is a natural number greater than or equal to 1. For example, one third probe can be connected to the first probe, and the third probe connected to the first probe in each probe subunit is different. Alternatively, each probe subunit can have 2N-1 third probes connected to the first probe, and the third probes connected to the first probe in each probe subunit are not identical.
[0030] In some embodiments of this application, such as Figure 1A As shown, taking N=1 as an example, probe unit 20 includes probe subunit 21 and probe subunit 22, and chipset 10 includes chip 11 and chip 12. When chip 11 is the target chip, probe subunit 11 is the target probe subunit; when chip 12 is the target chip, probe subunit 22 is the target probe subunit.
[0031] In some embodiments of this application, such as Figure 1AAs shown, taking N=1 as an example, probe unit 20 includes probe subunit 21 and probe subunit 22. Probe subunit 21 includes a third probe 213 for transmitting a test signal to the chip select pin CS1 of chip 11, a third probe 214 for transmitting a test signal to the chip select pin CS2 of chip 11, a second probe 212 for transmitting test commands and chip select instructions to the command pin CMD of chip 11, and a first probe 211 for transmitting a fixed signal to the first pin Vdd of chip 11. The third probe 213 and the first probe 211 are connected, that is, the test signal transmitted by the third probe 213 to the chip select pin CS1 of chip 11 is the same as the fixed signal transmitted by the first probe 211 to the first pin Vdd of chip 11. The probe subunit also includes a fifth probe 215 for transmitting a clock signal to the clock pin CLK of chip 11. The probe subunit 22 includes a third probe 223 for transmitting a test signal to the chip select pin CS1 of chip 12, a third probe 224 for transmitting a test signal to the chip select pin CS2 of chip 12, a second probe 222 for transmitting a test command and chip select instruction to the command pin CMD of chip 12, and a first probe 221 for transmitting a fixed signal to the first pin Vdd of chip 12. That is, the test signal transmitted by the third probe 223 to the chip select pin CS2 of chip 12 is the same as the fixed signal transmitted by the first probe 221 to the first pin Vdd of chip 12. It also includes a fifth probe 225 for transmitting a clock signal to the clock pin CLK of chip 12. This configuration ensures that the signals received by the chip select pins of chip 11 and chip 12 are different, so that when the chipset receives a chip select instruction and a test command, only one chip can be selected by the chip select instruction and execute the test command during testing.
[0032] In some embodiments of this application, Figure 1B This is a schematic diagram of a portion of the third probe of a probe subunit corresponding to a chip select pin, provided in some embodiments. For example... Figure 1B As shown, taking N=2 as an example, the chipset 100 has 4 chips, each with 4 chip select pins CS1 to CS4. The mode generator 300 is used to generate test signals, test commands, chip select instructions, and fixed signals. The probe unit 200 includes four probe subunits 210, 220, 230, and 240. Each probe subunit includes 4 third probes, with only one third probe in each subunit connected to the first probe. For details, please refer to... Figure 1BThe diagram illustrates how a third probe connected to the first probe in a probe subunit corresponds to a chip select pin of a chip. The third probes in different probe subunits that are connected to the first probe correspond to different chip select pins within the chip group. In probe subunit 210, the third probe 2110 is connected to the first probe 2150, and the third probe 2110 is used to transmit a test signal to the chip select pin CS1 of chip 110. In probe subunit 220, the third probe 2220 is connected to the first probe 2250, and the third probe 2220 is used to transmit a test signal to the chip select pin CS2 of chip 120. In probe subunit 230, the third probe 2330 is connected to the first probe 2350, and the third probe 2330 is used to transmit a test signal to the chip select pin CS2 of chip 130. The chip select pin CS3 of chip 140 transmits the test signal. The third probe 2440 in probe subunit 24 is connected to the first probe 2450. The third probe 2440 is used to transmit the test signal to the chip select pin CS4 of chip 140. The chip select pins CS2-CS4 of chip 110, CS1, CS3 and CS4 of chip 120, CS1, CS2 and CS4 of chip 130, and CS1-CS3 of chip 140 receive the same test signal. At this time, the signals received by the chip select pins of different chips in a chipset are different. Therefore, when the chipset receives a chip select instruction and a test command, only one chip can be selected by the chip select instruction and execute the test command. In this way, the first probe and one of the third probes of each probe subunit share a test channel, which is equivalent to one test channel simultaneously providing power signals to one of the chip select pins and the first pin of the chip under test, thereby reducing the number of channels occupied by a single chip.
[0033] In some embodiments of this application, Figure 1C A schematic diagram of the chip select pin corresponding to a portion of the third probe of the probe subunit provided in some embodiments, such as... Figure 1C As shown, taking N=2 as an example, the chipset contains 4 chips, each with 4 chip select pins CS1 to CS4. The mode generator 130 is used to generate test signals, test commands, chip select instructions, and fixed signals. The probe unit 120 includes four probe subunits 121, 122, 123, and 124. Each probe subunit includes 4 third probes, of which 3 third probes are connected to the first probe. For details, please refer to... Figure 1BThe diagram illustrates how a third probe connected to the first probe in a probe subunit is connected to a chip select pin of the chip. The third probes connected to the first probe in different probe subunits are not entirely the same. In probe subunit 121, third probes 1212, 1213, and 1214 are connected to the first probe 1215, and are used to transmit test signals to the chip select pins CS2, CS3, and CS4 of chip 111, respectively. In probe subunit 122, third probes 1221, 1223, and 1224 are connected to the first probe 1225, and are used to transmit test signals to the chip select pins CS1, CS3, and CS4 of chip 112, respectively. In probe subunit 123, third probes 1231, 1232, and 1234 are connected to the first probe 1235. The third probes 1231, 1232, and 1234 are used to transmit test signals to the chip select pins CS1, CS2, and CS4 of chip 113, respectively. The third probes 1241, 1242, and 1243 in probe subunit 124 are connected to the first probe 1245. The third probes 1241, 1242, and 1243 are used to transmit test signals to the chip select pins CS1, CS2, and CS3 of chip 114, respectively. The chip select pins CS1 in chip 111, CS2 in chip 12, CS3 in chip 113, and CS4 in chip 114 receive the same test signal. At this time, the signals received by the chip select pins of different chips in a chipset are different. Therefore, when the chipset receives a chip select instruction and a test command, only one chip can be selected by the chip select instruction and execute the test command during the test. In this way, the first probe and three of the third probes in each probe subunit share a test channel, which is equivalent to one test channel simultaneously providing a fixed signal to one of the chip select pins and the first pin of the chip, thereby reducing the number of channels occupied by a unit chip.
[0034] In some embodiments of this application, the first pin of the chip is a power supply pin, receiving a power supply signal or a ground signal. For example, when the first pin of the chip receives a power supply signal, the third pin connected to the first probe receives the same power supply signal, while the third pin not connected to the first probe receives a low-level signal; when the first pin of the chip receives a ground signal, the third pin connected to the first probe receives the same ground signal, while the third pin not connected to the first probe receives a high-level signal.
[0035] In some embodiments of this application, the second probes of different probe subunits are connected, that is, the second probes of all probe subunits within a probe unit are connected accordingly. This is equivalent to a test channel simultaneously providing the same test commands and chip select instructions to all (at least two) chips in a chipset, thereby further reducing the number of channels occupied by a single chip.
[0036] In some embodiments of this application, such as Figure 1A As shown, probes of the same type of pins on the chip can be connected to each other in different probe subunits to reduce the number of channels occupied by a single chip. For example, the first probes 211 and 221 corresponding to the power supply pins of the chip can be connected to each other, or the fifth probes 215 and 225 corresponding to the clock pins of the chip can be connected to each other.
[0037] In some embodiments of this application, such as Figure 1A As shown, in probe subunit 21, the first probe 211 and the third probe 213 are connected to the first channel Ch1; in probe subunit 22, the first probe 221 and the third probe 224 are connected to the fifth channel Ch5; in probe subunit 21, the second probe 212 and the second probe 222 are connected to the second channel Ch2; in probe subunit 21, the third probe 214 and the third probe 223 are connected to the fourth channel Ch4; and in probe subunit 21, the fifth probe 215 and the fifth probe 225 are connected to the third channel Ch3. Figure 1A The probe card structure shown can complete the testing of two chips using only 5 channels.
[0038] In some embodiments of this application, the chips in the chipset may be chips of the same model. The chips may be dies on a semiconductor substrate (e.g., a wafer) before the packaging process, or finished chips after the packaging and dicing processes. They may be fixed to a carrier board (load board) using test sockets and arranged in an array.
[0039] In some embodiments of this application, a chipset includes 2 N There are 2 chips, where N is an integer greater than or equal to 1. The pattern generator generates N sets of signals sequentially, including test signals, test commands, chip select instructions, and fixed signals. The chip select instructions in each set of signals are different. N Each chip receives N sets of signals in sequence, and each of the N chips executes the corresponding test command in sequence according to the N sets of signals.
[0040] In some embodiments of this application, Figure 1ATaking the structure shown as an example, the level of chip select pin CS1 on chip 11, which is connected to the third probe 213 of probe subunit 21, is high, the level of chip select pin CS2 on chip 11 is low, the chip select information of chip 11 is 10 (which indicates that the potential of chip select pin CS1 is high and the potential of chip select pin CS2 is low), and the chip select information of chip 12 is 01 (which indicates that the potential of chip select pin CS1 is low and the potential of chip select pin CS2 is high). When the mode generator generates a chip select instruction of 10 for the first time, chip 11 is selected and the test command is executed. Then the mode generator 30 generates a chip select instruction of 01 again, and chip 12 is selected and the test command is executed. Figure 1B In the structure shown, the chip select information of chip 11 is 1000, the chip select information of chip 12 is 0100, the chip select information of chip 13 is 0010, and the chip select information of chip 14 is 0001. The mode generator 30 generates chip select instructions of 1000, 0100, 0010 and 0001 in sequence, and selects chips 11-14 in sequence to execute test commands.
[0041] In some embodiments of this application, Figure 2 This is a timing diagram illustrating the test vector actions within a set of test units. In step ①, the test equipment sends the command "[Prepare to output data] cmd1" to all chips in the chipset; in step ②, the chips in the chipset receive the "Prepare to output data" command and the waiting time for data preparation; in step ③, the test equipment sends the command "[Chip select command] cs1 + [Start output data] cmd2", selecting one chip for data output; in step ④, the selected chip outputs data; in step ⑤, the test equipment sends the command "[Chip select command] cs2 + [Start output data] cmd2", selecting another chip for data output; in step ⑥, the other selected chip outputs data.
[0042] In some embodiments of this application, Figure 3 This is a schematic diagram showing the arrangement of eight chips in four chipsets according to another embodiment of this application. The eight chips are divided into four chipets (group 1 to group 4), and each test unit corresponds to two chips (number 1 and number 2). The configuration within each chipet can be as follows: Figure 1AAs shown, each chip also includes data import. Therefore, using the aforementioned test equipment to simultaneously test eight chips requires only eight power channels (one for each chip, shared with at least one chip select pin) and one clock channel. Due to the actual requirements of DC testing, each chip requires at least one independent power channel. When calculating channel utilization, the number of power channels can be ignored, and the assumption that each chip has one data pin is for illustration only; in reality, it requires a set of data pins (including at least two). Test efficiency (approximate channel utilization) = number of simultaneous tests ÷ number of channels other than power channels ÷ test time. When using the above formula to calculate test efficiency, the comparison between this embodiment and related technologies can be seen in the following table:
[0043]
[0044] In the table above, clk represents the clock channel, cs represents the chip select channel, dq represents the data channel, t1 represents the input stage, t2 represents the wait stage, and t3 represents the output stage. In related technologies, the test efficiency of t1 to t3 is 8 / 24 / x = 0.33 / x. In this embodiment, the test efficiency of t1 and t2 is 8 / 5 / x = 1.6 / x, and the test efficiency of t3 is 8 / 5 / 2x = 0.8x. This embodiment uses the same digital channel to output data to the two chips alternately, and its test time is twice that of a single chip outputting data. It is clear from the above chart that the test method in this embodiment can significantly improve test efficiency in each stage of chip testing (t1 to t3).
[0045] The above description is merely a description of preferred embodiments of this application and is not intended to limit the scope of this application in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A testing machine, characterized in that, include: A pattern generator is used to generate test signals, test commands, chip select instructions, and fixed signals. The probe unit provides the test signal, the test command, the chip select instruction and the fixed signal to the chipset through the probe unit. The chipset includes at least two chips, and the at least two chips include a target chip. The target chip has a first pin, a second pin and at least two chip select pins. The probe unit has at least two probe subunits corresponding to the at least two chips respectively, and is used to provide the test signal, the test command, the chip select instruction and the fixed signal to the at least two chips respectively. The at least two probe subunits include a target probe subunit corresponding to the target chip. The target probe subunit includes a first probe, a second probe, and a third probe. The first probe is used to provide a fixed signal to a first pin of the target chip. The second probe is used to provide the test command and the chip select instruction to a second pin of the target chip. The third probe is used to provide the test signal to the chip select pin of the target chip. At least one of the third probes in the target probe subunit is connected to the first probe. The at least one third probe connected to the first probe in different target probe subunits is not exactly the same, and the second probes in different target probe subunits are connected accordingly.
2. The testing machine according to claim 1, characterized in that, The fixed signal is either a power signal or a ground signal.
3. The testing machine according to claim 1, characterized in that, The first probes of different probe subunits are connected accordingly.
4. The testing machine according to claim 1, characterized in that, The second probes of different probe subunits are connected accordingly.