Wafer map generation method and system
By dividing the wafer diagram into multiple sub-units and managing them using a MySQL database, the problems of large data volume and inaccurate analysis of wafer diagrams are solved, enabling efficient and accurate data retrieval and analysis.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ANSEC SEMICON TECH (YIWU) CO LTD
- Filing Date
- 2026-03-24
- Publication Date
- 2026-06-23
AI Technical Summary
In existing technologies, wafer image data is large in volume, resulting in low efficiency when calling it, and the difference in chip measurement values between the wafer edge and center positions leads to inaccurate analysis.
The wafer image is divided into multiple equal-sized sub-units along the horizontal or vertical direction. The attribute data of each sub-unit is stored independently and managed using a MySQL database. Tags or indexes are created to facilitate searching and remove chips that exceed the wafer outline.
It improves data retrieval efficiency, enhances the accuracy of data analysis, enables targeted retrieval of data from a specific region, reduces data transmission volume, and ensures independent analysis between edge chips and central chips.
Smart Images
Figure CN122260076A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of wafer testing, and more specifically, relates to a wafer map generation method and system. Background Technology
[0002] A wafer map is used to display the test results of individual chips on a wafer, aiding in defect analysis and localization. As a visualization tool in chip testing, the wafer map transforms key data from chip testing and manufacturing processes into intuitive and easy-to-understand graphics, providing decision support for the entire semiconductor manufacturing process. Wafer maps include grading maps, parameter maps, and defect maps. Grading maps are a fundamental tool in the wafer testing phase, visually presenting the distribution of qualified and unqualified chips on the wafer by classifying and labeling the test results of each chip. Parameter maps display continuous test values on the wafer, using color gradients to show the continuous changes in chip electrical parameters and revealing the performance distribution patterns on the wafer surface. Defect maps display physical defects generated during wafer manufacturing (such as particle contamination, scratches, and image distortion). Currently, wafer maps contain large amounts of data, requiring significant data processing when accessing data, resulting in low efficiency. Summary of the Invention
[0003] This application provides a wafer map generation method and apparatus. When calling data in the wafer map, it can selectively call data from a specific area in the wafer map, reducing the amount of data transmitted and improving efficiency.
[0004] In a first aspect, embodiments of this application provide a wafer map generation method, including:
[0005] Acquire test data for the target wafer, the test data including coordinate information of the chips on the target wafer and test result values; A wafer map is generated based on the test data, and the wafer map is divided into multiple sub-units along the horizontal or vertical direction. Obtain the attribute data of each sub-unit, including the coordinate position of the sub-unit, the number of chips, and the test data of the chips; The attribute data of each sub-cell of the wafer diagram is stored independently.
[0006] This also includes: if a chip extends beyond the edge of the wafer outline, removing that chip from the wafer drawing.
[0007] The step of independently storing the attribute data of each sub-unit of the wafer diagram includes: storing each sub-unit as an independent unit in a MySQL database, and storing the attribute data of the sub-unit in the database, the attribute data including failure categories.
[0008] Wherein, the sub-units are of equal size or the sub-units are circles with the same center as the wafer pattern but different radii.
[0009] This also includes: establishing a label or index for each sub-unit, wherein the label is determined according to the failure category.
[0010] The process also includes: acquiring a point cloud image of the target wafer, setting pixels with gray values greater than a first threshold in the point cloud image to 255, and setting pixels with gray values less than the first threshold in the point cloud image to 0, to obtain a binarized image; determining multiple independent regions in the binarized image, deleting independent regions with areas smaller than a second threshold, and the remaining independent regions being the regions corresponding to the chip.
[0011] Secondly, this application provides a wafer mapping generation system, comprising: The first acquisition unit is used to acquire test data of the target wafer, the test data including the coordinate information of the chips on the target wafer and the test result values; A partitioning unit is used to generate a wafer map based on the test data and divide the wafer map into multiple sub-units along the horizontal or vertical direction; The second acquisition unit is used to acquire the attribute data of each sub-unit, the attribute data including the coordinate position of the sub-unit, the number of chips, and the test data of the chips; Storage unit, used to independently store the attribute data of each sub-unit of the wafer diagram.
[0012] The system is also used to remove chips from the wafer drawing if a chip extends beyond the edge of the wafer outline.
[0013] The storage unit is used to store each sub-unit as an independent unit in a MySQL database. The database stores the attribute data of the sub-unit, including the failure category.
[0014] Thirdly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the methods described above.
[0015] Fourthly, embodiments of this application provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of any of the methods described above.
[0016] The wafer map generation method and system of this application have the following beneficial effects: In this application, test data of the target wafer is acquired, a wafer map is generated based on the test data, and the wafer map is then divided into multiple equal-sized sub-units along the horizontal or vertical direction. The attribute data of each sub-unit is acquired and stored independently. This allows for targeted retrieval of data from a specific region (sub-unit) within the wafer map during subsequent data access, reducing data transmission volume and improving the efficiency of data retrieval. Chips at the wafer edges experience less force than those at the wafer center, resulting in measurement discrepancies. In practical applications, analyzing these forces together may fail to identify problems or lead to inaccurate conclusions. Therefore, separate analysis is necessary to uncover the true issues. Analyzing data from a specific region (sub-unit) within the wafer map improves the accuracy of data analysis. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the wafer map generation method according to an embodiment of this application; Figure 2 This is a schematic diagram of the wafer map generation system according to an embodiment of this application. Detailed Implementation
[0018] The present application will be further described below with reference to the accompanying drawings and embodiments.
[0019] In the following description, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The following description provides multiple embodiments of the invention, which can be substituted or combined with each other. Therefore, this application can also be considered to include all possible combinations of the same and / or different embodiments described. Thus, if one embodiment includes features A, B, and C, and another embodiment includes features B and D, then this application should also be considered to include embodiments containing one or more other possible combinations of features A, B, C, and D, even if such embodiments are not explicitly described in the following text.
[0020] like Figure 1 As shown, the wafer map generation method of this application includes: S101, acquiring test data of a target wafer, the test data including coordinate information of chips on the target wafer and test result values; S103, generating a wafer map based on the test data, and dividing the wafer map into multiple sub-units along the horizontal or vertical direction; S105, acquiring attribute data of each sub-unit, the attribute data including the coordinate position of the sub-unit, the number of chips, and the test data of the chips; S107, independently storing the attribute data of each sub-unit of the wafer map. In some embodiments, this application further includes: if a chip exceeds the edge of the wafer outline, removing the chip from the wafer map.
[0021] Wafer Acceptance Test (WAT) is a critical electrical testing step in semiconductor manufacturing. It verifies the completion quality and stability of process parameters for each process step by measuring the electrical performance of micro-devices at specific locations on the wafer. The main purpose of WAT testing is to ensure that the wafer meets the expected electrical standards after each process step, thereby providing quality assurance and performance support for subsequent process steps.
[0022] WAT testing analyzes the quality of semiconductor manufacturing processes by precisely measuring electrical parameters on the wafer, such as threshold voltage, leakage current, and drive current. These measurements help identify manufacturing deviations and defects, such as doping anomalies or linewidth deviations, allowing for timely process adjustments to ensure product quality. This testing is crucial in semiconductor manufacturing because it ensures that wafer products meet predetermined electrical performance requirements before proceeding to the next process.
[0023] Chip testing (CP) is performed after semiconductor manufacturing is completed and before the chips are diced from the wafer and packaged. Probe cards are used to contact the chips on the wafer to perform electrical tests to ensure that they meet specifications. These tests generally include threshold voltage, on-resistance, source-drain breakdown voltage, gate-source leakage current, and drain-source leakage current. The parameters for testing vary depending on the type of product.
[0024] CP testing targets every single chip in the entire wafer. Its purpose is to ensure that each chip in the entire wafer can basically meet the characteristics or design specifications of the device. It usually includes verification of voltage, current, timing and function, and can obtain the wafer yield.
[0025] Each completed wafer test generates a test map, which includes the product's corresponding menu name, size, step size, and the natural attributes (Mark, Skip, Test, etc.) and result attributes (Pass / Fail, Soft Bin, etc.) for each chip. TSKMap has three data structures: a Normal Map Data File, a Map Data File for a maximum of 250,000 chips, and a Map Data File for 256 multi-sites. To reduce testing costs, multi-site parallel testing has become the norm.
[0026] The header information in the wafer diagram stores parameters such as product name, size, flat / notch, and test time. The TSK Map version information can be obtained from the Map Version bytes, and the Option item's enabling / disabling status can be obtained from the Map File Configuration bytes. Whether the Option item is enabled or disabled depends on the wafer's workstation, Soft Bin, and other requirements. Each die's test data block stores the chip's inherent and result attributes.
[0027] A wafer map is generated based on test data. This wafer map is then divided into multiple sub-units horizontally or vertically. The sub-units are either of equal size or are circles with the same center as the wafer map but different radii. In this application, each sub-unit is stored as an independent unit in a MySQL database. The database stores the attribute data of the sub-unit, including the failure category. MySQL is an open-source relational database management system characterized by high performance, ease of use, and cross-platform support. It supports SQL (Structured Query Language) for data management and manipulation and provides multiple storage engines to meet different scenario requirements. This application also includes creating tags or indexes for each sub-unit to facilitate searching and retrieval. Tags can be determined based on the failure category.
[0028] In some embodiments, the wafer map generation method of this application further includes: acquiring a point cloud image of the target wafer; setting pixels with gray values greater than a first threshold in the point cloud image to 255; setting pixels with gray values less than the first threshold in the point cloud image to 0; obtaining a binarized image; determining multiple independent regions in the binarized image, where each independent region is a region different from its surroundings; deleting independent regions with areas smaller than a second threshold; and leaving the remaining independent regions as regions corresponding to the chip. The generated image can be used for subsequent analysis.
[0029] In this application, test data of the target wafer is acquired, a wafer map is generated based on the test data, and the wafer map is then divided into multiple equal-sized sub-units along the horizontal or vertical direction. The attribute data of each sub-unit is acquired and stored independently. This allows for targeted retrieval of data from a specific region (sub-unit) within the wafer map during subsequent data access, reducing data transmission volume and improving the efficiency of data retrieval. Chips at the wafer edges experience less force than those at the wafer center, resulting in measurement discrepancies. In practical applications, analyzing these forces together may fail to identify problems or lead to inaccurate conclusions. Therefore, separate analysis is necessary to uncover the true issues. Analyzing data from a specific region (sub-unit) within the wafer map improves the accuracy of data analysis.
[0030] likeFigure 2 As shown, the wafer map generation system of this application includes: a first acquisition unit 201, used to acquire test data of a target wafer, the test data including coordinate information of chips on the target wafer and test result values; a division unit 202, used to generate a wafer map based on the test data, dividing the wafer map into multiple sub-units along the horizontal or vertical direction; a second acquisition unit 203, used to acquire attribute data of each sub-unit, the attribute data including the coordinate position of the sub-unit, the number of chips, and the test data of the chips; and a storage unit 204, used to independently store the attribute data of each sub-unit of the wafer map.
[0031] In some embodiments, the wafer map generation system of this application is further used to: remove a chip from the wafer map if it exceeds the edge of the wafer outline. The storage unit is used to store each sub-unit as an independent unit in a MySQL database, and the database stores the attribute data of the sub-unit.
[0032] In this application, the wafer map generation system embodiment is basically similar to the wafer map generation method embodiment. For relevant details, please refer to the description of the wafer map generation method embodiment.
[0033] This application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of any of the above-described wafer map generation methods.
[0034] This invention also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the wafer map generation method steps described above. The computer-readable storage medium may include, but is not limited to, any type of disk, including floppy disks, optical disks, DVDs, CD-ROMs, microdrives, as well as magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, DRAMs, VRAMs, flash memory devices, magnetic cards or optical cards, nanosystems (including molecular memory ICs), or any type of medium or device suitable for storing instructions and / or data.
[0035] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed may be through some interfaces, indirect coupling or communication connection of devices or units, and may be electrical, mechanical, or other forms.
[0036] In the various embodiments of the present invention, all functional units can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.
[0037] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for generating wafer maps, characterized in that, include: Acquire test data for the target wafer, the test data including coordinate information of the chips on the target wafer and test result values; A wafer map is generated based on the test data, and the wafer map is divided into multiple sub-units along the horizontal or vertical direction. Obtain the attribute data of each sub-unit, including the coordinate position of the sub-unit, the number of chips, and the test data of the chips; The attribute data of each sub-cell of the wafer diagram is stored independently.
2. The wafer map generation method according to claim 1, characterized in that, Also includes: If a chip extends beyond the edge of the wafer outline, remove that chip from the wafer drawing.
3. The wafer map generation method according to claim 1 or 2, characterized in that, The step of independently storing the attribute data of each sub-unit of the wafer diagram includes: storing each sub-unit as an independent unit in a MySQL database, and storing the attribute data of the sub-unit in the database.
4. The wafer map generation method according to claim 1 or 2, characterized in that, The sub-units are of equal size or are circles with the same center as the wafer pattern but different radii.
5. The wafer map generation method according to claim 1 or 2, characterized in that, Also includes: A label or index is created for each sub-unit, and the label is determined according to the failure category.
6. The wafer map generation method according to claim 1 or 2, characterized in that, Also includes: A point cloud image of the target wafer is acquired. Pixels with gray values greater than a first threshold in the point cloud image are set to 255, and pixels with gray values less than the first threshold in the point cloud image are set to 0, resulting in a binarized image. Multiple independent regions in the binarized image are determined, and independent regions with areas smaller than a second threshold are deleted. The remaining independent regions are the regions corresponding to the chip.
7. A wafer mapping generation system, characterized in that, include: The first acquisition unit is used to acquire test data of the target wafer, the test data including the coordinate information of the chips on the target wafer and the test result values; A partitioning unit is used to generate a wafer map based on the test data and divide the wafer map into multiple sub-units along the horizontal or vertical direction; The second acquisition unit is used to acquire the attribute data of each sub-unit, the attribute data including the coordinate position of the sub-unit, the number of chips, and the test data of the chips; Storage unit, used to independently store the attribute data of each sub-unit of the wafer diagram.
8. The wafer mapping generation system according to claim 7, characterized in that, The storage unit is used to store each sub-unit as an independent unit in a MySQL database. The database stores the attribute data of the sub-unit, including the failure category.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by a processor, it implements the steps of the method described in any one of claims 1-6.
10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method according to any one of claims 1-6.