Waveguide modulator structure and method of fabrication

Abstract

The application relates to the field of silicon-based optoelectronic integrated chips, and provides a waveguide modulator structure and a preparation method.The waveguide modulator structure comprises a lower-layer silicon-based passive optical path and an upper-layer composite active waveguide structure; the upper-layer active structure comprises modulation units corresponding to two arms respectively; each modulation unit comprises, from bottom to top, a first waveguide material layer, a lower-layer graphene, a first high-dielectric-constant dielectric layer, an upper-layer graphene, a second high-dielectric-constant dielectric layer and a second waveguide material layer forming a waveguide ridge; the lower-layer and upper-layer graphenes overlap to form a capacitive modulation area in a region directly below the waveguide ridge; and the center of an optical axis of a vertical coupler is coincident with the center of the waveguide ridge.The application places graphene in the center of a waveguide to maximize the interaction between a mode light field and graphene, thereby realizing larger phase movement under the same gate voltage.Secondly, the vertical coupler is used to realize low-loss coupling of a silicon waveguide and a graphene embedded composite waveguide.

Description

Technical Field

[0001] This invention relates to the field of silicon-based optoelectronic integrated chips, and in particular to a waveguide modulator structure and its fabrication method. Background Technology

[0002] In the classic graphene modulator structure, whether it is a graphene-dielectric-silicon modulator or a graphene-dielectric-graphene modulator, the graphene is placed on top of the waveguide and isolated by the silicon oxide cladding. In this case, the interaction between the graphene and the light in the waveguide comes from evanescent wave coupling.

[0003] Graphene-dielectric-silicon modulators utilize the capacitive structure between graphene and silicon to adjust the carrier density of graphene, thereby altering the effective refractive index of the modes in the waveguide. This enables phase modulation similar to that of a Mach-Zehnder interferometer (MZI) type modulator. The thickness of the waveguide's upper cladding affects both the coupling between the optical field and graphene and the carrier density injected by the applied gate voltage. Graphene-dielectric-graphene modulators utilize the capacitive structure between the upper and lower graphene layers to adjust the carrier density of graphene, with the upper cladding thickness of the waveguide influencing the coupling between the optical field and graphene.

[0004] As the thickness of the upper cladding layer increases, the intensity of the evanescent wave light field decreases exponentially, and the interaction between graphene and the light field weakens. Consequently, the effective refractive index change caused by the change in graphene conductivity decreases, and the modulation efficiency weakens. Summary of the Invention

[0005] This invention provides a waveguide modulator structure and fabrication method to overcome the limitation of the modulation efficiency of graphene modulators in the prior art due to structural constraints.

[0006] This invention provides a waveguide modulator structure, comprising: The lower silicon-based passive optical path includes a first silicon waveguide arm and a second silicon waveguide arm with different optical path lengths, and both the first silicon waveguide arm and the second silicon waveguide arm are provided with vertical couplers. The upper composite active waveguide structure is spaced vertically from the lower silicon-based passive optical path by a spacer dielectric layer; the upper composite active waveguide structure includes a first modulation unit and a second modulation unit corresponding to the first silicon waveguide arm and the second silicon waveguide arm, respectively. Each modulation unit comprises, from bottom to top, the following components arranged sequentially: First waveguide material layer; The lower graphene layer is disposed on the upper surface of the first waveguide material layer; A first high dielectric constant dielectric layer covers the underlying graphene layer; The upper graphene layer is disposed on the upper surface of the first high dielectric constant dielectric layer; A second high dielectric constant dielectric layer covers the upper graphene layer; The second waveguide material layer protrudes from the upper surface of the second high dielectric constant dielectric layer to form a waveguide ridge structure; The lower graphene layer and the upper graphene layer are arranged opposite each other in the region directly below the waveguide ridge, and together with the first high dielectric constant dielectric layer, they form a capacitance modulation region. The lower graphene layer and the upper graphene layer also have contact areas that extend outward from the capacitor modulation region and are spatially separated from each other; and the optical axis center of the vertical coupler in the first silicon waveguide arm coincides with the center of the waveguide ridge of the first modulation unit in the vertical direction; the optical axis center of the vertical coupler in the second silicon waveguide arm coincides with the center of the waveguide ridge of the second modulation unit in the vertical direction.

[0007] According to the waveguide modulator structure provided by the present invention, the ratio of the overlap width of the lower graphene layer and the upper graphene layer directly below the waveguide ridge to the width of the waveguide ridge is 0.7 to 1.2.

[0008] According to the waveguide modulator structure provided by the present invention, both the upper graphene layer and the lower graphene layer are single-layer graphene.

[0009] According to the waveguide modulator structure provided by the present invention, the first high dielectric constant dielectric layer and / or the second high dielectric constant dielectric layer contain hafnium dioxide.

[0010] According to the waveguide modulator structure provided by the present invention, the first waveguide material layer and / or the second waveguide material layer comprises silicon nitride.

[0011] According to the waveguide modulator structure provided by the present invention, the thickness of the first high dielectric constant dielectric layer is 25 nm to 60 nm; the thickness of the second high dielectric constant dielectric layer is less than 15 nm; the thickness of the first waveguide material layer is 70 nm to 110 nm; and the width of the waveguide ridge is 700 nm to 900 nm and the height is 110 nm to 140 nm.

[0012] The waveguide modulator structure provided by the present invention further includes a metal electrode assembly, the metal electrode assembly including a lower electrode electrically connected to the contact area of ​​the lower graphene layer, and an upper electrode electrically connected to the contact area of ​​the upper graphene layer; wherein the lower electrode penetrates the second high dielectric constant dielectric layer and the first high dielectric constant dielectric layer.

[0013] According to the waveguide modulator structure provided by the present invention, the lower electrode is located in the middle region between the two waveguide ridges; the upper electrode includes two upper electrode portions located on the outer layer of the waveguide ridge width direction.

[0014] According to the waveguide modulator structure provided by the present invention, both the lower electrode and / or the upper electrode comprise palladium and gold.

[0015] A method for fabricating a waveguide modulator structure based on the above includes the following steps: Step S10: Obtain an SOI substrate and fabricate a lower passive optical path on the SOI substrate. The passive optical path forms a Mach-Zehnder interferometer structure with unequal arm lengths, and vertical couplers are formed in the two arms of the interferometer respectively. Step S20: On the SOI substrate on which the passive optical path is prepared, a spacer dielectric layer is formed; Step S30: On the spacer dielectric layer, corresponding to the positions of each of the vertical couplers, fabricate a composite active waveguide unit, specifically including: Step S301: A first waveguide material layer is formed using plasma-enhanced chemical vapor deposition (PECVD). Step S302: Transfer and pattern graphene to form the lower layer of graphene; Step S303: Prepare a lower metal electrode that is electrically connected to the lower graphene layer; Step S304: Using atomic layer deposition (ALD) technology, deposit a first high dielectric constant dielectric layer covering the underlying graphene. Step S305: Transfer and pattern the graphene to form the upper graphene layer; Step S306: Prepare an upper metal electrode that is electrically connected to the upper graphene layer; Step S307: Using atomic layer deposition (ALD) technology, deposit a second high dielectric constant dielectric layer covering the upper graphene layer; Step S308: A second waveguide material layer is formed using plasma-enhanced chemical vapor deposition (PECVD). Step S309: Pattern the second waveguide material layer to form a waveguide ridge; and in the same patterning step, remove the second waveguide material layer covering the upper metal electrode and the lower metal electrode to expose the upper metal electrode and the lower metal electrode. In steps S302 and 305, the patterned graphene is made such that the lower graphene layer overlaps with the upper graphene layer in the region directly below the waveguide ridge that is subsequently formed. In step S309, when patterning the second waveguide material layer, the center of the formed waveguide ridge is controlled to be aligned with the center of the corresponding vertical coupler in the vertical direction.

[0016] The waveguide modulator structure and fabrication method provided by this invention maximize the interaction between the mode optical field and graphene by placing graphene in the center of the waveguide, thereby achieving a larger phase shift under the same gate voltage. Secondly, a vertical coupler is used to achieve low-loss coupling between the silicon waveguide and the graphene-embedded composite waveguide. The three-dimensional waveguide structure can separate the active and passive regions, allowing graphene to be transferred on the flat active layer, which is beneficial for the fabrication of arrayed devices. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the layered structure of the waveguide modulator structure provided by the present invention.

[0019] Figure 2 This is an overall structural diagram of the waveguide modulator structure provided by the present invention.

[0020] Figure 3 This is a schematic diagram of the actual product of the waveguide modulator structure provided by the present invention.

[0021] Figure 4 This is the output spectrum of the waveguide modulator provided by the present invention.

[0022] Figure 5 It is the output spectrum of an evanescent wave coupled modulator under different applied voltages in the existing technology.

[0023] Figure 6 The output spectrum of the waveguide modulator provided by this invention under different applied voltages is shown.

[0024] Figure 7 It is a curve showing the change in wavelength shift as applied voltage varies, corresponding to the minimum value of the output spectral trough.

[0025] Figure 8 This is one of the flowcharts of the preparation method provided by the present invention.

[0026] Figure 9 This is the second flowchart of the preparation method provided by the present invention.

[0027] Figure label: 1. First silicon waveguide arm; 2. Second silicon waveguide arm; 3. First waveguide material layer; 4. First high dielectric constant dielectric layer; 5. Second high dielectric constant dielectric layer; 6. Lower graphene layer; 7. Upper graphene layer; 8. Lower electrode; 9. Upper electrode. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0029] In the description of the embodiments of the present invention, it should be noted that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the purpose of clarifying the embodiments of the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of the present invention. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0030] In the description of the embodiments of the present invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of the present invention according to the specific circumstances.

[0031] In embodiments of the present invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0032] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0033] In related technologies, whether it's a graphene-dielectric-silicon modulator or a graphene-dielectric-graphene modulator, graphene is placed on top of the waveguide and isolated by a silicon oxide cladding. As the thickness of the cladding increases, the evanescent wave light field intensity decreases exponentially, and the interaction between graphene and the light field weakens. Consequently, the effective refractive index change resulting from the change in graphene conductivity decreases, leading to reduced modulation efficiency. This makes it difficult to improve the modulation efficiency of the modulator.

[0034] Regarding the problems in related technologies, such as Figure 1 , Figure 2 As shown. Among them, Figure 1 The device structure consists of two parts: a passive optical path composed of a lower silicon waveguide and an active optical path composed of a composite waveguide ridge made of silicon nitride and graphene-dielectric-graphene. Figure 2The diagram illustrates a graphene-embedded waveguide in one arm of a modulator. Light is coupled from the lower silicon waveguide to the upper composite waveguide, where the two graphene layers are located at the position of strongest electric field in the mode (i.e., the central position). This invention provides a waveguide modulator structure comprising a lower silicon-based passive optical path and an upper composite active waveguide structure, the two layers being spaced apart by a dielectric layer. The lower silicon-based passive optical path includes a first silicon waveguide arm 1 and a second silicon waveguide arm 2 with different optical path lengths, and both the first silicon waveguide arm 1 and the second silicon waveguide arm 2 contain vertical couplers. The upper composite active waveguide structure includes a first modulation unit and a second modulation unit corresponding to the first silicon waveguide arm 1 and the second silicon waveguide arm 2, respectively. Each modulation unit (i.e., the first modulation unit and the second modulation unit) includes, from bottom to top, the following layers arranged sequentially: a first waveguide material layer 3, a lower graphene layer 6, a first high dielectric constant dielectric layer 4, an upper graphene layer 7, a second high dielectric constant dielectric layer 5, and a second waveguide material layer; the lower graphene layer 6 is disposed on the upper surface of the first waveguide material layer 3; the first high dielectric constant dielectric layer 4 covers the lower graphene layer 6; the upper graphene layer 7 is disposed on the upper surface of the first high dielectric constant dielectric layer 4; the second high dielectric constant dielectric layer 5... A first high-dielectric-constant dielectric layer 4 is formed by covering an upper graphene layer 7 and a second waveguide material layer protruding from the upper surface of the second high-dielectric-constant dielectric layer 5 to form a waveguide ridge structure. A lower graphene layer 6 and an upper graphene layer 7 are positioned vertically opposite each other in the region directly below the waveguide ridge, and together with the first high-dielectric-constant dielectric layer 4, they constitute a capacitance modulation region. The lower graphene layer 6 and the upper graphene layer 7 also have contact areas extending outward from the capacitance modulation region and spatially separated from each other. Furthermore, the optical axis center of the vertical coupler in the first silicon waveguide arm 1 coincides with the center of the waveguide ridge of the first modulation unit in the vertical direction; the optical axis center of the vertical coupler in the second silicon waveguide arm 2 coincides with the center of the waveguide ridge of the second modulation unit in the vertical direction. In related technologies, graphene is typically placed at the top of the waveguide, resulting in weak coupling with the optical field via evanescent waves, thus limiting modulation efficiency. This example constructs a three-dimensional heterogeneous structure to separate the active modulation region (containing graphene) from the passive optical path, enabling it to shift the spectral wavelength more at the same voltage difference compared to traditional devices, thereby improving modulation efficiency.

[0035] In other words, this embodiment precisely embeds a capacitor structure composed of two layers of graphene directly beneath the ridge of the upper composite waveguide, placing it in the region of strongest waveguide mode electric field, thus achieving strong interaction between the optical field and graphene. Simultaneously, through a vertical coupler and rigorous alignment design, low-loss coupling and return of the optical field from the lower silicon waveguide to the upper composite waveguide are achieved. This structure fundamentally changes the way light interacts with graphene, thereby significantly improving modulation efficiency. Furthermore, the layered design allows graphene to be transferred onto a flat surface, reducing fabrication complexity, improving device uniformity and yield, and laying the foundation for large-scale array integration.

[0036] Specifically, in this embodiment, the lower silicon-based passive optical path is fabricated on a standard 220nm thick silicon-on-insulator (SOI) wafer. Using electron beam lithography (EBL) and inductively coupled plasma (ICP) etching processes, a complete Mach-Zehnder interferometer (MZI) optical path is defined, including input / output grating couplers, a 1×2 multimode interference (MMI) beam splitter, unequal-length strip waveguide arms, and the key structure—an inverted conical vertical coupler.

[0037] The optical path difference between the two arms of the MZI is achieved by designing different waveguide path lengths; for example, one arm is a straight waveguide, while the other arm incorporates one or more curved waveguides to increase its length. The inverted conical vertical coupler is designed at the modulation points in both arms. Its shape transitions from a 500nm width at the connection point of the straight waveguide to a 200nm width at the end along the optical transmission direction, with a total length of 45μm and a thickness consistent with the silicon waveguide layer (220nm). The upper composite active waveguide structure is isolated from the lower optical path by a 100nm thick silicon dioxide (SiO2) spacer layer. This SiO2 layer, grown by plasma-enhanced chemical vapor deposition (PECVD), serves both as an electrical insulating layer and an optical spacer layer to optimize the coupling efficiency of the vertical coupler.

[0038] In each modulation unit of the upper layer, the first waveguide material layer 3 is a 100nm thick silicon nitride (Si3N4) planar layer, grown at a low temperature (approximately 300°C) using PECVD to ensure compatibility with subsequent graphene processes. The lower graphene layer 6 is a monolayer graphene grown by chemical vapor deposition (CVD), patterned using PMMA-assisted wet transfer technology and electron beam lithography and oxygen reactive ion etching (O2RIE) ​​to ensure continuity within the region directly below the subsequent waveguide ridge (approximately 500nm wide) and to extend to both sides as "wings" for electrode contacts. The first high-dielectric-constant dielectric layer 4 is a 50nm thick hafnium dioxide (HfO2) layer, conformally covered on the lower graphene layer 6 and the exposed Si3N4 surface using atomic layer deposition (ALD). The upper graphene layer 7 is also a patterned monolayer CVD graphene, transferred and coated on the first HfO2 layer. It precisely overlaps with the lower graphene layer 6 in the corresponding region (below the waveguide ridge) to form a parallel plate capacitor structure, with an overlap width of 500 nm. The second high-dielectric-constant dielectric layer 5 is an HfO2 isolation layer about 7 nm thick, also deposited by ALD process, completely covering the upper graphene layer 7, and playing a role in electrical isolation and protection. The second waveguide material layer is a PECVD-grown Si3N4 thin film with a thickness of about 130 nm. It is patterned into a strip ridge with a width of 700 nm by electron beam lithography and reactive ion etching (RIE) processes. This ridge is precisely aligned with the center of the lower inverted conical vertical coupler in the vertical direction, and has an overlap area of ​​about 10 μm with the coupler in the optical transmission direction to ensure efficient and stable optical coupling.

[0039] Understandably, by constructing a vertically stacked embedded capacitive waveguide structure consisting of a "Si3N4 ridge / HfO2 isolation layer / upper graphene 7 / HfO2 dielectric layer / lower graphene 6 / Si3N4 flat plate," the modulated active region was successfully positioned at the center of the mode field of the Si3N4 waveguide ridge. When a voltage is applied, the vertical electric field formed between the two graphene layers can efficiently modulate the Fermi level of the graphene, thereby changing its dielectric constant. Since the graphene is located at the point of maximum light intensity, a small change in its refractive index can be perceived by the light field to the greatest extent, which is converted into a significant change in the effective refractive index of the waveguide, ultimately manifesting as strong light intensity modulation at the MZI output. At the same time, the three-dimensional heterogeneous architecture of "lower passive silicon waveguide + upper active composite waveguide" achieves functional partitioning and process decoupling.

[0040] Furthermore, in this invention, the term "high dielectric constant dielectric" or "high dielectric constant dielectric layer" refers to an insulating material with a relative permittivity significantly higher than that of silicon dioxide (SiO2). Silicon dioxide typically has a relative permittivity of approximately 3.9 in the optical communication band and is a commonly used low-refractive-index cladding material in integrated photonics.

[0041] In a preferred embodiment of the present invention, the first and / or second high dielectric constant dielectric layer 5 is hafnium dioxide (HfO2), with a relative dielectric constant εr of approximately 10-16 (greater than 3.9), and can be formed into a high-quality, low-loss thin film using advanced processes such as atomic layer deposition (ALD), perfectly meeting the above requirements. However, the present invention is not limited to HfO2. Other dielectric materials that meet the above definition of "high dielectric constant," such as, but not limited to, zirconium dioxide (ZrO2), alumina (Al2O3), titanium dioxide (TiO2) or their composites, stacks, etc., as long as they can meet the electrical (high capacitance) and optical (low loss) performance requirements and are compatible with other layers (such as graphene, waveguide materials) in terms of process, may be considered for realizing the concept of the present invention.

[0042] In some embodiments, such as Figure 1 As shown, the overlap width between the lower graphene layer 6 and the upper graphene layer 7 directly below the waveguide ridge is 0.7 to 1.2 in ratio to the waveguide ridge width. In this example, by controlling the ratio (Wd / Wr) of the graphene overlap width (Wd) to the waveguide ridge width (Wr) within the range of 0.7 to 1.2, a balance in modulation efficiency can be achieved, resulting in superior tuning efficiency.

[0043] In this embodiment, limiting the proportion of the overlapping region serves two purposes: first, it maximizes the spatial overlap integral between the modulation region (graphene overlapping region) and the optical mode field (mainly concentrated within and near the ridge), thereby maximizing the modulation efficiency per unit length; second, it avoids unnecessary insertion loss (graphene absorbs light to some extent) due to excessive graphene broadening (too large a proportion), or insufficient graphene width (too small a proportion) resulting in some optical field not being modulated, thus reducing efficiency. Through optical simulation optimization, this proportion range was determined to be the preferred window for achieving high modulation efficiency while maintaining low optical loss.

[0044] Specifically, the pattern of the two graphene layers is precisely controlled using electron beam lithography. For a Si3N4 ridge with a width Wr of 700 nm, the overlap region Wd of the lower and upper graphene layers 7 directly below the ridge is designed to be 500 nm to 840 nm (i.e., Wd / Wr ≈ 0.71 to 1.2). In a preferred example, approximately 700 nm (Wd / Wr = 1) is used, such as... Figure 3 As shown in the figure, the scale bar is 50 μm, and the length of the active graphene region is marked as L. During fabrication, the lower graphene layer 6 is patterned first, followed by the deposition of an HfO2 dielectric layer. Then, with the assistance of a photolithography alignment system, the upper graphene layer 7 is patterned, ensuring precise alignment with the lower graphene layer 6 in the ridge region and achieving the designed overlap width. This overlap method ensures that the graphene capacitor effectively covers most of the high-intensity optical field in the waveguide ridge.

[0045] In the above embodiments, both the upper graphene 7 and the lower graphene 6 are single-layer graphene. This example uses single-layer graphene, which is beneficial for improving modulation efficiency.

[0046] The main reason is that monolayer graphene possesses a unique linear dispersion relation and extremely high carrier mobility. Its Fermi level can shift over a wide range near the Dirac point with relatively low voltage, resulting in a significant change in its optical conductivity (and corresponding dielectric constant). This change is crucial for electro-optic modulation. In contrast, multilayer graphene or graphene films behave more like traditional semiconductors or half-metals, and their electro-optic response characteristics (such as modulation depth and speed) may be inferior to those of monolayer graphene.

[0047] Furthermore, the ultrathin thickness of monolayer graphene results in minimal absorption and scattering of light waves, which helps reduce the inherent insertion loss of the device. Therefore, this embodiment improves modulation efficiency by employing monolayer graphene.

[0048] In some embodiments, the first high dielectric constant dielectric layer 4 and / or the second high dielectric constant dielectric layer 5 comprise hafnium dioxide (HfO2). In this example, hafnium dioxide (HfO2) is preferred as a high dielectric constant (high K) dielectric material, resulting in more stable device performance.

[0049] Understandably, HfO2 has a higher relative permittivity (k ~ 10⁻¹⁶), far exceeding that of SiO2 (k ~ 3.9). According to the parallel-plate capacitor formula, the capacitance C is directly proportional to the dielectric constant ε of the dielectric layer and inversely proportional to the thickness d. Using high-k HfO2 can achieve a larger capacitance per unit area with the same physical thickness. A larger capacitance means that under the same applied voltage, more charge can be induced on the graphene, resulting in a stronger electro-optic modulation effect (a larger refractive index change Δn), directly improving modulation efficiency.

[0050] In addition, the HfO2 thin film grown by the ALD process has excellent density, uniformity and low leakage current characteristics, and can withstand high electric field strength, ensuring the reliability and stability of the device operation.

[0051] In conjunction with the above embodiments, the first waveguide material layer 3 and / or the second waveguide material layer comprise silicon nitride (Si3N4). In related technologies, silicon optical waveguides are the mainstream, but they exhibit absorption in the visible light and some near-infrared bands. In this example, the upper waveguide uses silicon nitride (Si3N4) material, which facilitates subsequent expansion and integration.

[0052] Understandably, Si3N4 has a wide transparency window (from visible light to mid-infrared), and when integrated with graphene at communication wavelengths (such as 1550 nm), its refractive index interacts with graphene to produce a suitable mode distribution, which is beneficial for concentrating optical energy at the center of the waveguide. Simultaneously, the large refractive index difference between Si3N4 and SiO2 (the spacer layer) helps confine the optical field within the Si3N4 ridges, reducing mode field expansion and thus enhancing the interaction strength with the embedded graphene.

[0053] In addition, the Si3N4 thin film grown by PECVD is a mature process with controllable stress, good compatibility with CMOS back-end processes, and is easy to integrate on a large scale.

[0054] In conjunction with the above embodiments, the thickness of the first high-dielectric-constant dielectric layer 4 is 25 nm to 60 nm; the thickness of the second high-dielectric-constant dielectric layer 5 is less than 15 nm; the thickness of the first waveguide material layer 3 is 70 nm to 110 nm; the waveguide ridge width is 700 nm to 900 nm, and the height is 110 nm to 140 nm. This example, through systematic optical and electrical simulations, determines the preferred range of the above-mentioned key dimensions, and these dimensional constraints enable comprehensive optimization of electro-optic modulation performance (efficiency, loss, and speed).

[0055] The specific explanation is as follows: First HfO2 layer thickness (25-60nm): This thickness range represents a balance between capacitance (modulation strength) and breakdown voltage / operating voltage. Thinner dielectric layers (e.g., <25nm) offer greater capacitance and modulation efficiency, but may face reliability challenges (such as increased gate leakage and breakdown risk) and limit the maximum operating voltage. Thicker dielectric layers (e.g., >60nm) will decrease capacitance and efficiency. 50nm is the preferred value in this embodiment.

[0056] The second HfO2 insulating layer thickness (<15nm): This ultrathin layer is used to prevent damage to the graphene layer during the etching of the silicon nitride layer to form waveguide ridges, and it can isolate the graphene from the air, preventing graphene from becoming doped due to the adsorption of water and oxygen molecules from the air, thus avoiding instability. Its thickness needs to be sufficiently thin to minimize its impact on the light field distribution and prevent the light field from being pushed away from the graphene region, while ensuring sufficient insulation. Approximately 7nm is a preferred value in this embodiment.

[0057] First Si3N4 layer (planar) thickness (70-110 nm): This layer thickness affects the bottom layer confinement and mode field distribution of the waveguide. An optimal thickness of 100 nm helps to achieve a balance between confining the optical field and maintaining appropriate mode size.

[0058] Waveguide ridge dimensions (700-900 nm wide, 110-140 nm high): These dimensions collectively determine the single-mode transmission conditions, mode field size, and overlap factor with graphene. An optimal design with a width of 700 nm and a height of 130 nm ensures single-mode operation while stably positioning the maximum electric field of the TE fundamental mode at the center vertically of the ridge, precisely aligned with the embedded graphene layer, thus achieving maximum photo-graphene interaction intensity.

[0059] Specifically, in this embodiment, the waveguide mode is simulated using finite element electromagnetic simulation software. The above parameters are adjusted to maximize the integral of light intensity in the graphene region as the optimization objective, while ensuring low transmission loss and single-mode characteristics. Finally, the above-mentioned preferred size range and its specific values ​​are determined.

[0060] In some embodiments, a metal electrode assembly is also included, comprising a lower electrode 8 electrically connected to the contact area of ​​the lower graphene 6 and an upper electrode 9 electrically connected to the contact area of ​​the upper graphene 7; wherein the lower electrode 8 penetrates the second high-dielectric-constant dielectric layer 5 and the first high-dielectric-constant dielectric layer 4. This example employs a through-type electrode structure to achieve electrical connection with the lower graphene 6, which enables more stable device performance.

[0061] Depend on Figure 1 As shown, the fabrication of the lower electrode 8 is completed before the deposition of the first high-dielectric-constant dielectric layer 4. Specifically, after the patterning of the lower graphene 6, the lower metal electrode 8 is directly formed on the contact "wings" of the lower graphene 6 through photolithography, metal deposition, and lift-off processes. Subsequently, the first high-dielectric-constant dielectric layer 9, deposited using atomic layer deposition, conformally covers the lower graphene 6 and the lower metal electrode 8. This "electrode first, dielectric cover later" process sequence ensures a direct, robust, and low-resistance ohmic contact between the electrode metal and the lower graphene 6, eliminating the need for subsequent via etching, simplifying the process steps, and guaranteeing the quality and stability of the contact interface. Finally, in the waveguide ridge patterning step, the silicon nitride layer covering the electrode area is etched away, exposing the lower metal electrode 8 for subsequent electrical testing and packaging.

[0062] First, the electrode contact window pattern is defined using electron beam lithography. Then, a 5 nm thick layer of palladium (Pd) and a 90 nm thick layer of gold (Au) are sequentially deposited using electron beam evaporation. The palladium layer serves as an adhesion layer and promotes ohmic contact with the graphene. Finally, the photoresist and excess metal are removed using a lift-off process to form the patterned electrode. The fabrication of the upper electrode 9 is the same as that of the lower metal electrode 8, employing similar photolithography, evaporation, and lift-off processes.

[0063] In conjunction with the above embodiments, the lower electrode 8 is located in the central region between the two waveguide ridges; the upper electrode 9 includes two upper electrode portions 9 located on the outer layer in the width direction of the waveguide ridges. This example provides an optimized electrode planar layout scheme, which can further enhance the reliability of the device and is suitable for high-frequency dynamic performance measurement.

[0064] like Figure 1 As shown, the lower electrode 8 is positioned in the middle region between the two waveguide ridges (corresponding to the two modulation arms of the MZI) as a ground terminal. This compact layout facilitates symmetrical wiring and reduces interference from electrode leads to the optical path and the introduction of parasitic capacitance. The upper electrode 9 is designed as two electrode portions located on the outer side of each waveguide ridge in the width direction (e.g., one upper electrode 9 contact point on each side of each ridge). This "two-sided contact" design ensures that the two electrodes independently control the voltage applied to the graphene in the two arms. This electrode design is compatible with GSGSG RF probes that may be used in future dynamic performance measurements.

[0065] Meanwhile, placing the upper electrode 9 on the outside of the ridge and spatially separating it from the lower electrode 8 located in the middle between the ridges minimizes the risk of short circuits or large parasitic capacitances between the upper and lower electrodes 8 due to their close proximity, thereby improving the reliability and electrical performance of the device.

[0066] Specifically, in the MZI modulator of this embodiment, each modulation arm corresponds to an upper composite waveguide unit and its ridge. The lower electrode 8 is a suitably shaped metal pad located between the two ridges, connected to the extension regions of the lower graphene 6 below the two ridges. For each ridge, the two contact "wings" of the corresponding upper graphene 7 are located on both sides of the ridge (along the width direction), and a metal contact point (i.e., the upper electrode 9) is formed on each "wing" through the above-described electrode process. These two electrode parts are circuitically independent, and the voltage applied to the graphene on the two arms can be independently controlled, so that the refractive index change on the two arms can be changed independently.

[0067] In conjunction with the foregoing embodiments, both the lower electrode 8 and / or the upper electrode 9 comprise palladium (Pd) and gold (Au). This example preferably uses a combination of palladium (Pd) and gold (Au) as the contact metal, as the low contact resistance of Pd / Au and graphene is beneficial for improving response speed.

[0068] Gold (Au) possesses excellent electrical conductivity and corrosion resistance, making it an ideal electrode substrate material. The key lies in selecting palladium (Pd) as the adhesion layer and interface metal for direct contact with graphene. Studies have shown that palladium (Pd) can form a good ohmic contact with graphene, and its work function matches graphene well, which helps to reduce the Schottky barrier.

[0069] Meanwhile, the palladium layer adheres well to the surfaces of graphene and dielectric layers during electron beam evaporation, improving the adhesion and stability of the electrode. The use of a Pd / Au bilayer metal structure, combined with a through-hole design, enables stable, low-resistance ohmic contacts, which is crucial for reducing modulator drive voltage and improving response speed.

[0070] like Figure 8 , Figure 9 As shown, a method for fabricating a waveguide modulator structure based on the above embodiments includes the following steps: Step S10: Obtain the SOI substrate and fabricate the lower passive optical path on the SOI substrate. The passive optical path forms a Mach-Zehnder interferometer structure with unequal arm lengths, and vertical couplers are formed in the two arms of the interferometer. This step uses mature silicon photonics standard processes to fabricate the passive substrate of the device. Its typical structure is: a 220 nm thick single-crystal silicon layer (device layer) on the surface, a 3 μm thick silicon dioxide buried oxide layer (BOX) below, and a silicon substrate below that.

[0071] Step S20: On the SOI substrate with a passive optical path, a spacer dielectric layer is formed. Specifically, after the lower silicon waveguide structure is fabricated, a silicon dioxide (SiO2) layer is globally deposited on top of it as a spacer dielectric layer. This layer is grown using plasma-enhanced chemical vapor deposition (PECVD).

[0072] Step S30: On the spacer dielectric layer, corresponding to the positions of each vertical coupler, fabricate composite active waveguide units, specifically including: Step S301: The first waveguide material layer 3 is formed using plasma-enhanced chemical vapor deposition (PECVD) process; Step S302: Transfer and pattern the graphene to form the lower layer of graphene 6; Step S303: Prepare a lower metal electrode that is electrically connected to the lower graphene 6; Step S304: Using atomic layer deposition (ALD) process, deposit the first high dielectric constant dielectric layer 4 covering the underlying graphene 6; Step S305: Transfer and pattern the graphene to form the upper graphene layer 7; Step S306: Prepare an upper metal electrode that is electrically connected to the upper graphene 7; Step S307: Using atomic layer deposition (ALD) technology, deposit a second high dielectric constant dielectric layer 5 covering the upper graphene 7; Step S308: A second waveguide material layer is formed using plasma-enhanced chemical vapor deposition (PECVD). Step S309: Pattern the second waveguide material layer to form a waveguide ridge, and remove the second waveguide material layer covering the upper metal electrode and the lower metal electrode in the same patterning step to expose the upper electrode 9 and the lower electrode 8. In steps S302 and S305, the graphene is patterned so that the lower graphene 6 and the upper graphene 7 overlap in the region directly below the waveguide ridge that is subsequently formed; in step S309, when the second waveguide material layer is patterned, the center of the formed waveguide ridge is controlled to be aligned with the center of the corresponding vertical coupler in the vertical direction.

[0073] In this example, the fabrication method first prepares a complete passive optical path at the bottom layer, and then constructs an active modulation region layer by layer on a flat surface, forming a "three-dimensional heterogeneous, sequential integration" strategy. This method first utilizes mature silicon photonics processes to fabricate a high-precision, high-performance passive optical path; then, on the surface of a flat dielectric layer, through a strict process sequence (PECVD growth of Si3N4, graphene transfer and patterning, ALD growth of HfO2, etc.) and key alignment steps, a composite waveguide active region with embedded graphene capacitors is constructed. This method not only reduces the difficulty of graphene transfer and patterning, improving the consistency and yield of device performance, but also allows the active region's fabrication (especially ALD and graphene processing) to be performed under relatively independent and optimized conditions.

[0074] In steps S302 and S304, high-precision electron beam lithography and etching techniques are used to pattern the two layers of graphene, and a lithography alignment system is used to ensure that the two layers of graphene are precisely overlapped at the designed ridge positions, which is the basis for forming a high-efficiency capacitance modulation region.

[0075] In steps S303 and S305, HfO2 is deposited using the ALD process. This process provides atomic-level thickness control and perfect step coverage, ensuring that the dielectric layer is uniform, dense, and free of pinholes, which ensures the performance and reliability of the capacitor.

[0076] In step S307, during the patterning of the Si3N4 ridges, an overlay alignment technique is used to ensure that the longitudinal centerline of the final waveguide ridge coincides with the centerline of the pre-fabricated inverted conical silicon vertical coupler in the lower layer on the vertical projection. Precise alignment in three-dimensional space is crucial for achieving low-loss coupling and return of light between the upper and lower waveguide layers, directly determining the device's insertion loss and performance stability. The entire process flow design embodies the principles of functional layer separation and process optimization, providing a practical fabrication path for realizing high-performance, integrable graphene electro-optic modulators.

[0077] Of course, in actual implementation, due to limitations in the precision of the actual fabrication process and the performance errors allowed by the application, a process tolerance range is usually set. Through optical simulation and experimental verification, the deviation between the longitudinal centerline of the final waveguide ridge and the centerline of the pre-fabricated inverted conical silicon vertical coupler is allowed to be less than 100nm ± 50nm. Because the loss is less than 0.5dB within 100nm ± 50nm, the impact on the overall device performance is within an acceptable range. Therefore, in the actual process, a deviation of less than 100nm between the longitudinal centerline of the final waveguide ridge and the centerline of the pre-fabricated inverted conical silicon vertical coupler is considered as coincidence.

[0078] Understandably, the modulators fabricated using the above methods exhibit a high degree of synergy between their structure and fabrication process. The flat surface of the active layer ensures the quality of the graphene and ALD dielectric layers; the three-dimensional heterogeneous design achieves seamless optical path connection through vertical couplers and precise alignment.

[0079] Furthermore, the final tests show that the "graphene-embedded" modulator prepared by this method, under the same structural parameters (such as the difference in MZI arm length, graphene length, and HfO2 thickness), has a half-wave voltage-length product (VπL) that is about 36% lower than that of the traditional "evanescent wave coupled" modulator (e.g., from 1.1 V·cm to 0.7 V·cm). For details, please refer to the following description. This significantly improves the modulation efficiency and verifies the significant effect of the structure and method of this invention.

[0080] To quantitatively verify the significant advantages of the proposed three-dimensional heterogeneous graphene-embedded waveguide modulator in improving modulation efficiency, we designed and implemented a set of comparative experiments. The details are as follows: Experimental Group (Example of the Invention): A graphene-embedded modulator was fabricated using the aforementioned preparation method. Its core feature lies in the precise embedding of a graphene-dielectric-graphene capacitor structure in the central region directly below a waveguide ridge composed of Si3N4.

[0081] Control group (comparative example): As a comparison, a traditional evanescent wave coupled graphene modulator was fabricated. Its structure consists of a graphene-dielectric-graphene structure placed on top of a Si3N4 waveguide ridge and isolated by a 20nm thick silicon dioxide cladding, so that the light wave is weakly coupled to the graphene only through the evanescent field.

[0082] Experimental control variables: To ensure fairness and validity of the comparison, the experimental and control groups maintained consistency in key comparable parameters: Identical capacitor structure: The dielectric layer between the two graphene layers was 50 nm thick hafnium dioxide (HfO2). Identical active region size: The effective modulation length (L) of the graphene was designed to be 150 μm. Identical optical architecture: Except for the active region structure, the passive parts of the Mach-Zehnder interferometer (MZI), including the grating coupler, multimode interference beam splitter, and the unequal-arm waveguide structure that introduces a fixed phase difference, were completely identical. This means that the two devices have the same free spectral range.

[0083] Performance testing and characterization methods: The testing system mainly includes a tunable laser source, an optical detector, a voltage source, and a spectral analysis unit. The testing method strictly follows the half-wave voltage-length product (V_πL) measurement procedure: Measure the output transmission spectrum of the MZI modulator at different gate voltages (e.g. Figure 5 , Figure 6 (As shown). Figure 5 The illustration in the lower left corner is a schematic diagram of an evanescent wave coupled modulator, where a graphene-dielectric-graphene structure is located above the waveguide and separated by an upper cladding. A voltage change from 0 to 12V causes a wavelength change of 0.2nm corresponding to the minimum wave trough. Figure 6 The illustration in the lower left corner is a schematic diagram of a graphene-embedded modulator (the structure of this invention), where a graphene-dielectric-graphene structure is located in the middle of the waveguide. A voltage change from 0 to 12V causes a wavelength change of 0.46nm corresponding to the minimum wave trough.

[0084] Record the wavelength position corresponding to the spectral interference valley at each voltage, and calculate its wavelength offset (Δλ) relative to zero bias voltage.

[0085] Plot the response curve of wavelength offset (Δλ) as a function of applied voltage (V) (e.g.) Figure 7 (As shown).

[0086] Select a voltage change ΔV and its resulting wavelength shift Δλ from the linear interval of the response curve (usually the point of maximum slope).

[0087] From the spectrum at zero bias (e.g.) Figure 4 (As shown) Directly read the free spectral range d.

[0088] Substituting ΔV, Δλ, d, and the known active region length L into the formula: The core indicator characterizing modulation efficiency—the half-wave voltage-length product—was calculated. The smaller the value, the smaller the product of the driving voltage and the device length required to achieve the same amount of phase modulation (π radians), which means the higher the modulation efficiency.

[0089] Experimental Results and Data Analysis: Key Comparison Results: Under stringent comparison conditions, the traditional evanescent wave coupled modulator was measured... The value is 1.1 V·cm, while the embedded modulator of this invention... The value is 0.7 V·cm.

[0090] To further verify the reliability and process robustness of the results, we tested multiple devices with different active region lengths in the same fabrication batch. For the evanescent wave coupled structure, the measured... The values ​​are distributed around 1.4 V·cm and 2.1 V·cm; while for the embedded structure of the present invention, the measured values ​​are... The values ​​are concentrated at excellent levels of 0.8 V·cm and 0.9 V·cm.

[0091] Experimental conclusions and beneficial effects: The comparative experimental data clearly and consistently demonstrate that the graphene-embedded modulator provided by this invention has a half-wave voltage-length product (…). The modulation efficiency is significantly lower than that of traditional evanescent wave coupled structures. Specifically, in this embodiment, the modulation efficiency is improved by approximately 36% (from 1.1 V·cm to 0.7 V·cm). This directly verifies the correctness and superiority of the design concept of moving the graphene capacitor structure from the top of the waveguide to the center of the waveguide where the electric field is strongest.

[0092] like Figure 7 As shown, the electro-optic response of the experimental and control groups was systematically tested. During the test, the wavelength shift of the output spectral interference valley was recorded as the applied voltage was increased stepwise from 0V to 12V. The specific data are recorded in the table below: Voltage (V) Embedded wavelength shift (nm) Evanescent wavelength shift (nm) 0 0.00 0.00 2 0.04 0.00 4 0.08 0.02 6 0.18 0.10 8 0.30 0.14 10 0.38 018 12 0.42 0.2 Based on this data, a response curve of wavelength shift as a function of voltage was plotted, such as... Figure 7 As shown, it is evident that the response amplitude of the embedded modulator (red curve) provided by this invention is significantly superior to that of the conventional evanescent modulator (blue curve) across the entire voltage range. To quantitatively characterize the modulation efficiency, we performed calculations based on this response curve. Selecting a range with good response linearity (e.g., embedded type 6V to 8V), the wavelength shift Δλ caused by a voltage difference ΔV = 2V in this range is approximately 0.12nm for the embedded type and approximately 0.08nm for the evanescent modulator (e.g., evanescent modulator 4V to 6V). Combined with... Figure 4 Substituting the free spectral range d (e.g., approximately 5.6 nm) measured from the spectrum shown, and the active region length L = 150 μm, into the formula: For the embedded modulator (this invention): VπL = (2V / (2×0.12nm))×5.6nm×150μm≈0.7V·cm; For an evanescent waveform modulator (reference example): VπL = (2V / (2×0.08nm))×5.6nm×150μm≈1.1V·cm.

[0093] The modulator of the present invention reduces the VπL value from 1.1V·cm to 0.7V·cm, which means that to achieve the same π phase modulation, the product of the driving voltage and the device length required by the present invention is reduced by about 36%. This intuitively and quantitatively demonstrates the significant technical effect of the present invention in improving modulation efficiency. Figure 7 The stark contrast between the two response curves (red and blue) directly reflects the efficiency improvement in the experimental data.

[0094] In the comparative example, the graphene is located outside the waveguide and couples with the optical field only through an exponentially decaying evanescent wave, resulting in a weak interaction. In this example, through a three-dimensional heterogeneous design of a "lower passive silicon waveguide / upper embedded active waveguide" and precise process alignment, the graphene is directly placed at the center of the mode field of the Si3N4 waveguide ridge. When a modulation voltage is applied, the change in refractive index caused by the change in the Fermi level of the graphene can be perceived to the maximum extent by the most intense optical field, thus efficiently converting it into a larger change in the effective refractive index of the waveguide.

[0095] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A waveguide modulator structure, characterized in that, include: The lower silicon-based passive optical path includes a first silicon waveguide arm and a second silicon waveguide arm with different optical path lengths, and both the first silicon waveguide arm and the second silicon waveguide arm are provided with vertical couplers. The upper composite active waveguide structure is spaced vertically from the lower silicon-based passive optical path by a spacer dielectric layer; the upper composite active waveguide structure includes a first modulation unit and a second modulation unit corresponding to the first silicon waveguide arm and the second silicon waveguide arm, respectively; Each modulation unit comprises, from bottom to top, the following components arranged sequentially: First waveguide material layer; The lower graphene layer is disposed on the upper surface of the first waveguide material layer; A first high dielectric constant dielectric layer covers the underlying graphene layer; The upper graphene layer is disposed on the upper surface of the first high dielectric constant dielectric layer; A second high dielectric constant dielectric layer covers the upper graphene layer; The second waveguide material layer protrudes from the upper surface of the second high dielectric constant dielectric layer to form a waveguide ridge structure; The lower graphene layer and the upper graphene layer are arranged opposite each other in the region directly below the waveguide ridge, and together with the first high dielectric constant dielectric layer, they form a capacitance modulation region. The lower graphene layer and the upper graphene layer also have contact areas that extend outward from the capacitor modulation region and are spatially separated from each other; and the optical axis center of the vertical coupler in the first silicon waveguide arm coincides with the center of the waveguide ridge of the first modulation unit in the vertical direction; the optical axis center of the vertical coupler in the second silicon waveguide arm coincides with the center of the waveguide ridge of the second modulation unit in the vertical direction.

2. The waveguide modulator structure according to claim 1, characterized in that, The ratio of the overlap width between the lower graphene layer and the upper graphene layer directly below the waveguide ridge to the width of the waveguide ridge is 0.7 to 1.

2.

3. The waveguide modulator structure according to claim 1, characterized in that, Both the upper graphene layer and the lower graphene layer are single-layer graphene.

4. The waveguide modulator structure according to claim 1, characterized in that, The first high dielectric constant dielectric layer and / or the second high dielectric constant dielectric layer contain hafnium dioxide.

5. The waveguide modulator structure according to claim 1 or 4, characterized in that, The first waveguide material layer and / or the second waveguide material layer contain silicon nitride.

6. The waveguide modulator structure according to claim 5, characterized in that, The thickness of the first high dielectric constant dielectric layer is 25 nanometers to 60 nanometers; the thickness of the second high dielectric constant dielectric layer is less than 15 nanometers. The thickness of the first waveguide material layer is 70 nanometers to 110 nanometers; the width of the waveguide ridge is 700 nanometers to 900 nanometers, and the height is 110 nanometers to 140 nanometers.

7. The waveguide modulator structure according to claim 1, characterized in that, It also includes a metal electrode assembly, which includes a lower electrode electrically connected to the contact area of ​​the lower graphene layer and an upper electrode electrically connected to the contact area of ​​the upper graphene layer; wherein the lower electrode penetrates the second high dielectric constant dielectric layer and the first high dielectric constant dielectric layer.

8. The waveguide modulator structure according to claim 7, characterized in that, The lower electrode is located in the middle region between the two waveguide ridges; the upper electrode includes two upper electrode portions located on the outer layer of the waveguide ridge in the width direction.

9. The waveguide modulator structure according to claim 7, characterized in that, Both the lower electrode and / or the upper electrode contain palladium and gold.

10. A method for fabricating a waveguide modulator structure based on any one of claims 1-9, characterized in that, Includes the following steps: Step S10: Obtain an SOI substrate and fabricate a lower passive optical path on the SOI substrate. The passive optical path forms a Mach-Zehnder interferometer structure with unequal arm lengths, and vertical couplers are formed in the two arms of the interferometer respectively. Step S20: On the SOI substrate on which the passive optical path is prepared, a spacer dielectric layer is formed; Step S30: On the spacer dielectric layer, corresponding to the positions of each of the vertical couplers, fabricate a composite active waveguide unit, specifically including: Step S301: A first waveguide material layer is formed using plasma-enhanced chemical vapor deposition (PECVD). Step S302: Transfer and pattern graphene to form the lower layer of graphene; Step S303: Prepare a lower metal electrode that is electrically connected to the lower graphene layer; Step S304: Using atomic layer deposition (ALD) technology, deposit a first high dielectric constant dielectric layer covering the underlying graphene. Step S305: Transfer and pattern the graphene to form the upper graphene layer; Step S306: Prepare an upper metal electrode that is electrically connected to the upper graphene layer; Step S307: Using atomic layer deposition (ALD) technology, deposit a second high dielectric constant dielectric layer covering the upper graphene layer; Step S308: A second waveguide material layer is formed using plasma-enhanced chemical vapor deposition (PECVD). Step S309: Pattern the second waveguide material layer to form a waveguide ridge, and remove the second waveguide material layer covering the upper metal electrode and the lower metal electrode in the same patterning step to expose the upper metal electrode and the lower metal electrode; In steps S302 and 305, the patterned graphene is such that the lower graphene layer overlaps with the upper graphene layer in the region directly below the waveguide ridge that is subsequently formed. In step S309, when patterning the second waveguide material layer, the center of the formed waveguide ridge is controlled to be aligned with the center of the corresponding vertical coupler in the vertical direction.

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