Method, device, equipment, storage medium and product for checking connection relationship of components
By using methods and apparatus for checking device connectivity, and employing standard format netlist files and node level matching checks, erroneous level connections in chip design can be identified and resolved, thereby improving chip performance and yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ACTIONS ZHUHAI TECH CO
- Filing Date
- 2024-12-23
- Publication Date
- 2026-06-23
AI Technical Summary
In chip design, driving low-voltage devices with high-voltage signals or vice versa can lead to signal transmission failure or device voltage withstand issues, resulting in chip malfunction, performance failure, or reduced yield.
By acquiring standard format netlist files and node level matching check procedures, we use automated verification and repair circuit design tools to check device connections, identify nodes and connections with incorrect level matching, and resolve incorrect level drive issues by adding level conversion circuits or modifying the design.
The design addressed the issues of substandard chip performance and reduced yield, ensuring the chip's normal function and reliability.
Smart Images
Figure CN122263802A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of chip design technology, and more specifically, to a method, apparatus, device, storage medium, and product for checking device interconnections. Background Technology
[0002] In chip design, different devices operate in different voltage power domains; that is, high-voltage devices generate signals that drive high-voltage devices, and low-voltage devices generate signals that drive low-voltage devices. If a high-voltage signal drives a low-voltage device, or vice versa, signal transmission failure or device voltage withstand issues may occur. A low-voltage signal driving a high-voltage device may cause chip malfunction or performance failure, while a high-voltage signal driving a low-voltage device may reduce chip yield or lead to prolonged chip failure. Summary of the Invention
[0003] To address the aforementioned issues, this disclosure provides a method, apparatus, device, storage medium, and product for inspecting device connectivity.
[0004] According to a first aspect of the present disclosure, a method for checking device connectivity is provided, the method comprising:
[0005] Obtain a standard format netlist file;
[0006] Obtain the node level matching check program;
[0007] The program is used to perform node level matching checks on the standard format netlist file to identify nodes with incorrect level matching and devices with incorrect level connections.
[0008] Optionally, obtaining the standard format netlist file includes:
[0009] Obtain the original non-standard netlist file;
[0010] The original non-standard netlist file is converted to a standard format netlist file.
[0011] Optionally, the node level matching check procedure includes:
[0012] Based on automated verification and repair circuit design tools, obtain node level matching check procedures.
[0013] Optionally, the node level matching check procedure includes:
[0014] Define the name, path, and format of the netlist file to be checked;
[0015] Set basic environment variables;
[0016] Define a node level matching check subroutine, which is used to check the connection status of low-voltage and high-voltage devices.
[0017] Optionally, the defined node level matching check subroutine includes:
[0018] Define the names of the low-voltage device and the high-voltage device to be inspected, and specify the name of the specific port to be inspected;
[0019] All non-power or non-ground nodes in the standard format netlist are used for the subroutine's check;
[0020] Obtain the name of the currently inspected node and perform a connection relationship check on the currently inspected node;
[0021] If the current inspection node is connected to a specific port of the low-voltage device, then the first information of the low-voltage device is obtained, the first information including the number of the low-voltage devices connected to the current inspection node;
[0022] If the current inspection node is connected to a specific port of the high-voltage device, then the second information of the high-voltage device is obtained, the second information including the number of the high-voltage devices connected to the current inspection node;
[0023] Based on the number of low-voltage devices and the number of high-voltage devices, determine whether there are any incorrect connection relationships at the current inspection node.
[0024] Optionally, determining whether there is an erroneous connection relationship at the current inspection node based on the number of low-voltage devices and the number of high-voltage devices includes:
[0025] If the number of both the low-voltage devices and the high-voltage devices is not zero, it is determined that the current inspection node has an incorrect connection relationship. The incorrect connection relationship includes: the current inspection node is connected to both low-voltage devices and high-voltage devices at the same time.
[0026] If only one of the quantities of the low-voltage devices and the high-voltage devices is zero, the connection relationship of the current inspection node is determined to be correct, and there is no incorrect connection.
[0027] Optionally, the method further includes:
[0028] The locations of devices with incorrect voltage level connections are marked using a back-annotation tool to identify the high and low voltage level connection interfaces with connection errors.
[0029] At the high and low voltage level connection interfaces where there are connection errors, add corresponding level conversion circuits or modify the circuit design to avoid incorrect level driving.
[0030] According to a second aspect of the present disclosure, an apparatus for checking device connectivity is provided, the apparatus comprising:
[0031] The first acquisition module is used to acquire standard format netlist files;
[0032] The second acquisition module is used to acquire the node level matching check program;
[0033] The inspection module is used to perform node level matching checks on the standard format netlist file using the program, in order to identify nodes with incorrect level matching and devices with incorrect level connections.
[0034] According to a third aspect of the present disclosure, an electronic device is provided, comprising:
[0035] A memory on which computer programs are stored;
[0036] A processor for executing the computer program in the memory to implement the steps of the method of any one of the first aspects.
[0037] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the method described in any of the first aspects.
[0038] According to a fifth aspect of the present disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the method described in any one of the first aspects.
[0039] In summary, this disclosure provides a method for checking device connectivity. The method includes: acquiring a standard format netlist file; acquiring a node level matching check program; and using the program to perform a node level matching check on the standard format netlist file to identify nodes with incorrect level matching and devices with incorrect level connections. This disclosure can detect nodes and devices with incorrect level connections in a chip design. By modifying the design or adding level conversion circuits, the erroneous level drive problem can be solved, thereby addressing issues such as unsatisfactory chip performance, reduced chip yield, or prolonged chip failure at the design source.
[0040] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description
[0041] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:
[0042] Figure 1 This is a flowchart illustrating a method for checking device connectivity according to an exemplary embodiment.
[0043] Figure 2 This is a flowchart illustrating a method for checking device connectivity according to an exemplary embodiment.
[0044] Figure 3 This is a flowchart illustrating a method for checking device connectivity according to an exemplary embodiment.
[0045] Figure 4 This is a flowchart illustrating a method for checking device connectivity according to an exemplary embodiment.
[0046] Figure 5 This is a flowchart illustrating a method for checking device connectivity according to an exemplary embodiment.
[0047] Figure 6 This is a flowchart illustrating a method for checking device connectivity according to an exemplary embodiment.
[0048] Figure 7 This is a flowchart illustrating a method for checking device connectivity according to an exemplary embodiment.
[0049] Figure 8 This is a block diagram illustrating an apparatus for checking device connection relationships according to an exemplary embodiment.
[0050] Figure 9 This is a block diagram illustrating an electronic device according to an exemplary embodiment. Detailed Implementation
[0051] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.
[0052] It should be understood that the term "comprising" and its variations as used herein are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the following description.
[0053] It should be noted that the concepts of "first," "second," etc., mentioned in this disclosure are used only to distinguish different devices, modules, or units, and are not used to limit the order of functions performed by these devices, modules, or units or their interdependencies. The modifiers "a" and "a plurality of" mentioned in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless explicitly stated in the context, they should be understood as "one or more." In the description of this disclosure, unless otherwise stated, "a plurality of" means two or more, and other quantifiers are similar; "at least one," "one or more," or similar expressions refer to any combination of these items, including any combination of single or multiple items.
[0054] Although operations or steps are described in a specific order in the accompanying drawings in the embodiments of this disclosure, it should not be construed as requiring these operations or steps to be performed in the specific order or serial order shown, or requiring all of the shown operations or steps to be performed to obtain the desired result. In the embodiments of this disclosure, these operations or steps may be performed serially; they may be performed in parallel; or a portion of these operations or steps may be performed.
[0055] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of these messages or information. It is understood that before using the technical solutions disclosed in the embodiments of this disclosure, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in this disclosure in an appropriate manner in accordance with relevant laws and regulations, and user authorization should be obtained.
[0056] First, let's explain the application scenario of this disclosure. In actual chip design, circuits within the same module are generally designed by the same designer, making high and low voltage checks relatively simple and intuitive. However, in mixed-signal design flows, the signal attributes of each module or IP are defined by the module / IP circuit designer through lib files, and then passed to upstream or downstream circuit designers. When upstream or downstream modules call module / IP circuits, they often see a black box; the internal circuitry is implemented by the circuit designer, while upstream or downstream modules can only see its behavioral or gate-level Verilog code or layout data (e.g., GDS files). Therefore, at these analog-digital interfaces, if there is a human error in defining signal attributes, high and low level mismatch will occur, leading to chip performance not meeting expectations, reduced chip yield, or even prolonged chip failure.
[0057] In view of this, there is an urgent need to provide a method, apparatus, device, storage medium, and product for checking device interconnections to solve the above problems. The present disclosure will now be described with reference to specific embodiments.
[0058] Figure 1 This is a flowchart illustrating a method for checking device connectivity according to an exemplary embodiment. Figure 1 As shown in the embodiments of this disclosure, a method for checking device connection relationships is provided, the method including the following steps:
[0059] In step S10, a standard format netlist file is obtained.
[0060] In this step, a standard format netlist file is obtained. For example, the original non-standard netlist file can be obtained first, and then its format can be converted to obtain a standard format netlist file. This standard format netlist file is a SPICE file format netlist file. This standard format netlist file can be a standard format netlist file for the entire chip, or it can be a standard format netlist file for a portion of the chip's functional modules.
[0061] In step S20, the node level matching check procedure is obtained.
[0062] In this step, a node level matching checker is obtained. For example, this checker can be obtained using an automated verification and repair circuit design tool, such as CalibrePerc. This checker can be used to perform node level matching checks on a standard format netlist file to identify nodes with incorrect level matches and devices with incorrect level connections.
[0063] In step S30, the program is used to perform node level matching checks on the standard format netlist file to identify nodes with incorrect level matching and devices with incorrect level connections.
[0064] In this step, automated verification and repair circuit design tools, such as CalibrePerc, are used to perform node level matching checks on standard format netlist files to identify nodes with incorrect level matching and devices with incorrect level connections.
[0065] In summary, this disclosure provides a method for checking device connectivity. The method includes: acquiring a standard format netlist file; acquiring a node level matching check program; and using the program to perform a node level matching check on the standard format netlist file to identify nodes with incorrect level matching and devices with incorrect level connections. This disclosure can detect nodes and devices with incorrect level connections in a chip design. By modifying the design or adding level conversion circuits, the erroneous level drive problem can be solved, thereby addressing issues such as unsatisfactory chip performance, reduced chip yield, or prolonged chip failure at the design source.
[0066] Figure 2 This is a flowchart illustrating a method for checking device connectivity according to an exemplary embodiment. Figure 2 As shown, obtaining the standard format netlist file may include the following steps:
[0067] In step S101, the original non-standard netlist file is obtained.
[0068] In this step, the original non-standard netlist file is obtained. For example, the original non-standard netlist file can be a netlist in Verilog format or a GDS file of the layout. Of course, it can also include non-standard netlist files in other formats, and this disclosure does not impose any limitations.
[0069] In step S102, the original non-standard netlist file is converted to a standard format netlist file.
[0070] In this step, the original non-standard netlist file is converted to a standard format netlist file. For example, if the original non-standard netlist file contains Verilog format, it can be converted to a standard SPICE format netlist file using the calibre v2lvs program; if the original non-standard netlist file is a layout GDS file, it can be extracted into a standard SPICE format netlist file using the calibrelvs program. Generally, since a complete layout file is required for chip design and manufacturing, this method allows for the inspection of the entire chip's layout file, thus avoiding errors or omissions caused by incomplete or incorrect library definitions in the early stages, thereby protecting the correctness of the voltage signal connections throughout the chip. This is the most reliable and foolproof method.
[0071] Figure 3 This is a flowchart illustrating a method for checking device connectivity according to an exemplary embodiment. Figure 3 As shown, the node level matching check procedure may include the following steps:
[0072] In step S201, a node level matching check procedure is obtained based on an automated verification and repair circuit design tool.
[0073] In this step, a node level matching check procedure is obtained based on an automated verification and repair circuit design tool. For example, a program can be written first using an automated verification and repair circuit design tool (such as CalibrePerc): defining the name of the netlist file to be checked, the netlist file path, and the netlist file format; then setting basic environment variables; and finally defining a node level matching check subroutine, which is used to check the electrical connections of low-voltage and high-voltage devices.
[0074] Figure 4 This is a flowchart illustrating a method for checking device connectivity according to an exemplary embodiment. Figure 4 As shown, the node level matching check procedure may include the following steps:
[0075] In step S2011, the name of the netlist file to be checked, the path of the netlist file, and the format of the netlist file are defined.
[0076] In this step, the name, path, and format of the netlist file to be checked are defined in the node level matching check procedure. For example, the netlist file name could be perc_hv2lv_netlist, the path could be svdb, and the format could be spice.
[0077] In step S2012, basic environment variables are set.
[0078] In this step, basic environment variables are set in the node level matching check procedure. For example, the basic environment variables set may include: PERC REPORT MAXIMUM ALL, LVS REPORT MAXIMUM ALL, etc.
[0079] In step S2013, a node level matching check subroutine is defined, which is used to check the connection status of low-voltage devices and high-voltage devices.
[0080] In this step, a node level matching check subroutine is defined to check the connection status of low-voltage and high-voltage devices. For example, defining the node level matching check subroutine can first define the names of the low-voltage and high-voltage devices to be checked, then use all non-power or non-ground nodes in the standard format netlist for the subroutine check, then obtain the name of the currently checked node, and perform a connection relationship check on the currently checked node. If the currently checked node is connected to a low-voltage device, then obtain the first information of the low-voltage device, which includes the number of low-voltage devices connected to the currently checked node; if the currently checked node is connected to a high-voltage device, then obtain the second information of the high-voltage device, which includes the number of high-voltage devices connected to the currently checked node. Then, based on the number of low-voltage devices and the number of high-voltage devices, it is determined whether there are any incorrect connections in the currently checked node.
[0081] Figure 5 This is a flowchart illustrating a method for checking device connectivity according to an exemplary embodiment. Figure 5 As shown, the defined node level matching check subroutine may include the following steps:
[0082] In step S20131, the names of the low-voltage device and the high-voltage device to be inspected are defined, and the specific port name to be inspected is specified.
[0083] In this step, the names of the low-voltage and high-voltage devices to be checked are defined in the node level matching check procedure, and the specific port name to be checked is specified. For example, a device named "n12ll p12ll nt12ll_mis_ckt p12ll_mis_ckt n12ll_mis_ckt" can be defined as a low-voltage device;
[0084] The device with the name "pod33ll nod33ll nod33ll_mis_ckt pod33ll_mis_ckt N_BPW_50_MM RNPPO_MM RSPPO_MM" is defined as a high-voltage device.
[0085] Determine the specific port name to be checked in this inspection, such as checking the Gate port of all devices, or checking the Source port of all devices.
[0086] In step S20132, all non-power or non-ground nodes in the standard format netlist are used for the subroutine check.
[0087] In this step, the node level matching check procedure defines that all non-power or non-ground nodes in the standard format netlist will be used for the subroutine check.
[0088] In step S20133, the name of the current inspection node is obtained, and the connection relationship of the current inspection node is checked.
[0089] In this step, the name of the currently inspected node is obtained, and the connection relationship of the currently inspected node is checked.
[0090] In step S20134, if the current inspection node is connected to the low-voltage device, then the first information of the low-voltage device is obtained, the first information including the number of the low-voltage devices connected to the current inspection node.
[0091] In this step, if the current inspection node is connected to a low-voltage device, then the first information about the low-voltage device is obtained. This first information includes the number of low-voltage devices connected to the current inspection node. For example, if the current inspection node is connected to the Gate terminal of a low-voltage device, then the first information about the low-voltage device is obtained.
[0092] In step S20135, if the current inspection node is connected to the high-voltage device, then the second information of the high-voltage device is obtained, the second information including the number of the high-voltage devices connected to the current inspection node.
[0093] In this step, if the current inspection node is connected to a high-voltage device, then the second information of the high-voltage device is obtained. This second information includes the number of high-voltage devices connected to the current inspection node. For example, if the current inspection node is connected to the gate terminal of a high-voltage device, then the second information of the high-voltage device is obtained.
[0094] In step S20136, based on the number of low-voltage devices and the number of high-voltage devices, it is determined whether there is an incorrect connection relationship in the current inspection node.
[0095] In this step, based on the number of low-voltage devices and the number of high-voltage devices, it is determined whether there are any incorrect connections at the current inspection node. For example, if both the number of low-voltage devices and the number of high-voltage devices are not zero, it can be determined that there are incorrect connections at the current inspection node. Incorrect connections include: the current inspection node is connected to both low-voltage devices and high-voltage devices simultaneously; if only one of the numbers of low-voltage devices and high-voltage devices is zero, the connection of the current inspection node is determined to be correct, and there are no incorrect connections.
[0096] Figure 6 This is a flowchart illustrating a method for checking device connectivity according to an exemplary embodiment. Figure 6 As shown, determining whether there is an erroneous connection relationship at the current inspection node based on the number of low-voltage devices and the number of high-voltage devices may include the following steps:
[0097] In step S201361, if the number of low-voltage devices and the number of high-voltage devices are both not zero, it is determined that the current inspection node has an incorrect connection relationship. The incorrect connection relationship includes: the current inspection node is connected to both low-voltage devices and high-voltage devices at the same time.
[0098] In this step, if both the number of low-voltage devices and the number of high-voltage devices are not zero, it is determined that the current inspection node has an incorrect connection. An incorrect connection includes the current inspection node being connected to both low-voltage and high-voltage devices simultaneously. For example, if both the number of low-voltage devices and the number of high-voltage devices are not zero, it is determined that the current inspection node has an incorrect connection, meaning that the gate terminals of the low-voltage and high-voltage devices are directly connected.
[0099] Returns information on all high-voltage and low-voltage devices connected to the currently inspected node, including device coordinates and / or device names, for use in back-annotation procedures (such as the Calibre RVE procedure) for back-annotation.
[0100] In step S201362, if only one of the quantities of the low-voltage devices and the high-voltage devices is zero, it is determined that the connection relationship of the current inspection node is correct and there is no erroneous connection.
[0101] In this step, if only one of the quantities of low-voltage devices and high-voltage devices is zero, it is determined that the connection relationship of the current inspection node is correct and there is no incorrect connection.
[0102] Figure 7 This is a flowchart illustrating a method for checking device connectivity according to an exemplary embodiment. Figure 7 As shown, the method may further include the following steps:
[0103] In step S40, the location of the device with the incorrect level connection is marked using a back-annotation tool to obtain the high and low voltage level connection interfaces with connection errors.
[0104] In this step, a back-annotation tool (such as the Calibre RVE program tool) is used to mark the locations of devices with incorrect voltage level connections, thereby obtaining the high and low voltage level connection interfaces with connection errors.
[0105] In step S50, at the high and low voltage level connection interface where the connection error exists, a corresponding level conversion circuit is added, or the circuit design is modified, in order to avoid erroneous level driving.
[0106] In this step, at the high and low voltage level connection interfaces where there are connection errors, add the corresponding level conversion circuit or modify the circuit design to avoid incorrect level driving.
[0107] In summary, this disclosure provides a method for checking device connectivity. The method includes: acquiring a standard format netlist file; acquiring a node level matching check program; and using the program to perform a node level matching check on the standard format netlist file to identify nodes with incorrect level matching and devices with incorrect level connections. This disclosure can detect nodes and devices with incorrect level connections in a chip design. By modifying the design or adding level conversion circuits, the erroneous level drive problem can be solved, thereby addressing issues such as unsatisfactory chip performance, reduced chip yield, or prolonged chip failure at the design source.
[0108] Figure 8 This is a block diagram illustrating an apparatus for checking device connectivity according to an exemplary embodiment. Figure 8 As shown, this disclosure provides an apparatus 800 for checking the connection relationship of devices. The apparatus 800 may include the following modules:
[0109] The first acquisition module 810 is used to acquire standard format netlist files.
[0110] The second acquisition module 820 is used to acquire the node level matching check program.
[0111] The inspection module 830 is used to perform node level matching checks on the standard format netlist file using the program, in order to identify nodes with incorrect level matching and devices with incorrect level connections.
[0112] Optionally, the first acquisition module 810 is further configured to:
[0113] Obtain the original non-standard netlist file;
[0114] The original non-standard netlist file is converted to a standard format netlist file.
[0115] Optionally, the second acquisition module 820 is further configured to:
[0116] Based on automated verification and repair circuit design tools, obtain node level matching check procedures.
[0117] Optionally, the second acquisition module 820 is further configured to:
[0118] Define the name, path, and format of the netlist file to be checked;
[0119] Set basic environment variables;
[0120] Define a node level matching check subroutine, which is used to check the connection status of low-voltage and high-voltage devices.
[0121] Optionally, the second acquisition module 820 is further configured to:
[0122] Define the names of the low-voltage device and the high-voltage device to be inspected, and specify the name of the specific port to be inspected;
[0123] All non-power or non-ground nodes in the standard format netlist are used for the subroutine's check;
[0124] Obtain the name of the currently inspected node and perform a connection relationship check on the currently inspected node;
[0125] If the current inspection node is connected to a specific port of the low-voltage device, then the first information of the low-voltage device is obtained, the first information including the number of the low-voltage devices connected to the current inspection node;
[0126] If the current inspection node is connected to a specific port of the high-voltage device, then the second information of the high-voltage device is obtained, the second information including the number of the high-voltage devices connected to the current inspection node;
[0127] Based on the number of low-voltage devices and the number of high-voltage devices, determine whether there are any incorrect connection relationships at the current inspection node.
[0128] Optionally, the second acquisition module 820 is further configured to:
[0129] If the number of both the low-voltage devices and the high-voltage devices is not zero, it is determined that the current inspection node has an incorrect connection relationship. The incorrect connection relationship includes: the current inspection node is connected to both low-voltage devices and high-voltage devices at the same time.
[0130] If only one of the quantities of the low-voltage devices and the high-voltage devices is zero, the connection relationship of the current inspection node is determined to be correct, and there is no incorrect connection.
[0131] Optionally, the device 800 further includes a back-mark modification module, used for:
[0132] The locations of devices with incorrect voltage level connections are marked using a back-annotation tool to identify the high and low voltage level connection interfaces with connection errors.
[0133] At the high and low voltage level connection interfaces where there are connection errors, add corresponding level conversion circuits or modify the circuit design to avoid incorrect level driving.
[0134] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated upon here.
[0135] In summary, this disclosure provides an apparatus for checking device connectivity. The apparatus includes: a first acquisition module for acquiring a standard format netlist file; a second acquisition module for acquiring a node level matching check program; and an inspection module for using the program to perform node level matching checks on the standard format netlist file to identify nodes with incorrect level matching and devices with incorrect level connections. This disclosure can detect nodes and devices with incorrect level connections in a chip design. By modifying the design or adding level conversion circuits, it can resolve erroneous level drive problems, thereby addressing issues such as unsatisfactory chip performance, reduced chip yield, or prolonged chip failure from the design source.
[0136] Figure 9 This is a block diagram illustrating an electronic device according to an exemplary embodiment. Figure 9 As shown, the electronic device 900 may include a processor 901 and a memory 902. The electronic device 900 may also include one or more of a multimedia component 903, an input / output (I / O) interface 904, and a communication component 905.
[0137] The processor 901 controls the overall operation of the electronic device 900 to complete all or part of the steps in the method for checking device connectivity described above. The memory 902 stores various types of data to support the operation of the electronic device 900. This data may include, for example, instructions for any application or method operating on the electronic device 900, and application-related data such as contact data, sent and received messages, pictures, audio, video, etc. The memory 902 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. Multimedia component 903 may include a screen and an audio component. The screen may be, for example, a touchscreen, and the audio component is used to output and / or input audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signals may be further stored in memory 902 or transmitted via communication component 905. The audio component also includes at least one speaker for outputting audio signals. I / O interface 904 provides an interface between processor 901 and other interface modules, such as a keyboard, mouse, buttons, etc. These buttons may be virtual or physical buttons. Communication component 905 is used for wired or wireless communication between the electronic device 900 and other devices. Wireless communication, such as Wi-Fi, Bluetooth, Near Field Communication (NFC), 2G, 3G, 4G, NB-IoT, eMTC, or other 5G technologies, or combinations thereof, is not limited here. Therefore, the corresponding communication component 905 may include: a Wi-Fi module, a Bluetooth module, an NFC module, etc.
[0138] In an exemplary embodiment, the electronic device 900 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the method for checking device connectivity described above.
[0139] In another exemplary embodiment, a computer-readable storage medium including program instructions is also provided, which, when executed by a processor, implement the steps of the method for checking device connectivity described above. For example, the computer-readable storage medium may be the memory 902 including program instructions described above, which may be executed by the processor 901 of the electronic device 900 to complete the method for checking device connectivity described above.
[0140] In another exemplary embodiment, a computer program product is also provided, the computer program product comprising a computer program executable by a programmable device, the computer program having a code portion for performing the above-described method for checking device connection relationships when executed by the programmable device.
[0141] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.
[0142] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.
[0143] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.
Claims
1. A method of checking device connection relationships, characterized by, The method includes: Obtain a standard format netlist file; Obtain the node level matching check program; The program is used to perform node level matching checks on the standard format netlist file to identify nodes with incorrect level matching and devices with incorrect level connections.
2. The method of claim 1, wherein, The process of obtaining the standard format netlist file includes: Obtain the original non-standard netlist file; The original non-standard netlist file is converted to a standard format netlist file.
3. The method according to claim 1, characterized in that, The node level matching check procedure includes: Based on automated verification and repair circuit design tools, obtain node level matching check procedures.
4. The method according to claim 3, characterized in that, The node level matching check procedure includes: Define the name, path, and format of the netlist file to be checked; Set basic environment variables; Define a node level matching check subroutine, which is used to check the connection status of low-voltage and high-voltage devices.
5. The method according to claim 4, characterized in that, The defined node level matching check subroutine includes: Define the names of the low-voltage device and the high-voltage device to be inspected, and specify the name of the specific port to be inspected; All non-power or non-ground nodes in the standard format netlist are used for the subroutine's check; Obtain the name of the currently inspected node and perform a connection relationship check on the currently inspected node; If the current inspection node is connected to a specific port of the low-voltage device, then the first information of the low-voltage device is obtained, the first information including the number of the low-voltage devices connected to the current inspection node; If the current inspection node is connected to a specific port of the high-voltage device, then the second information of the high-voltage device is obtained, the second information including the number of the high-voltage devices connected to the current inspection node; Based on the number of low-voltage devices and the number of high-voltage devices, determine whether there are any incorrect connection relationships at the current inspection node.
6. The method according to claim 5, characterized in that, The step of determining whether there is an incorrect connection relationship at the current inspection node based on the number of low-voltage devices and the number of high-voltage devices includes: If the number of both the low-voltage devices and the high-voltage devices is not zero, it is determined that the current inspection node has an incorrect connection relationship. The incorrect connection relationship includes: the current inspection node is connected to both low-voltage devices and high-voltage devices at the same time. If only one of the quantities of the low-voltage devices and the high-voltage devices is zero, the connection relationship of the current inspection node is determined to be correct, and there is no incorrect connection.
7. The method according to claim 1, characterized in that, The method further includes: The locations of devices with incorrect voltage level connections are marked using a back-annotation tool to identify the high and low voltage level connection interfaces with connection errors. At the high and low voltage level connection interfaces where there are connection errors, add corresponding level conversion circuits or modify the circuit design to avoid incorrect level driving.
8. A device for checking the connection relationship of devices, characterized in that, The device includes: The first acquisition module is used to acquire standard format netlist files; The second acquisition module is used to acquire the node level matching check program; The inspection module is used to perform node level matching checks on the standard format netlist file using the program, in order to identify nodes with incorrect level matching and devices with incorrect level connections.
9. An electronic device, characterized in that, include: A memory on which computer programs are stored; A processor for executing the computer program in the memory to implement the steps of the method according to any one of claims 1-7.
10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the program implements the steps of the method described in any one of claims 1-7.
11. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-7.