A neural computing integration method and system based on a brain-like architecture

Abstract

This invention relates to the field of neural computing technology and discloses a neural computing integration method and system based on a brain-like architecture. The method includes: establishing a state monitoring map and counting the number of impulse events within the glial control domain to generate a congestion index; executing phase transition decision logic to determine a hyperactive state based on the bit-level characteristics of the congestion index; in response to the hyperactive state, triggering source-end modulation, generating a refractory period bias parameter and superimposing it onto the basic refractory period parameter, and correcting the state update equation to extend the physical quiescent duration of neurons; and in response to the background maintenance state, triggering folding scheduling logic. This invention directly intervenes in the neuronal differential equation parameters during congestion, suppressing the generation of invalid impulses, constructing an intrinsic negative feedback loop, and avoiding the backflow of invalid power consumption during congestion.

Description

Technical Field

[0001] This invention relates to a neural computing integration method and system based on a brain-like architecture, belonging to the field of neural computing technology. Background Technology

[0002] In current neural computing hardware systems, spiking neural networks are generally deployed using a static pre-compilation mapping strategy. This strategy parses the pre-trained network connection topology during the compilation phase, solidifies the synaptic weight matrix into the underlying chip physical routing table or memory address pointers, and reserves a fixed computation time slice and communication bandwidth for each neuron node. The static mapping paradigm is based on implicit assumptions that the excitation density of neurons on the time axis is relatively uniform or statistically predictable, ensuring that hardware resource allocation and computational load are statically matched. When processing highly dynamic real-world signals such as dynamic visual sensor data or multimodal sensor fusion, spiking neural networks exhibit extreme spatiotemporal burst characteristics. Unlike the hierarchical synchronous activation of traditional artificial neural networks, neurons in bio-inspired networks are mostly in a silent state. Under the induction of specific external stimuli, they instantly generate a dense burst of pulses with an avalanche-like effect. There is an essential impedance mismatch between the information density of the flowing pulses and the rigid underlying computational and communication topology.

[0003] To alleviate the aforementioned contradictions, the industry has attempted to improve chip architecture to enhance network adaptability. For example, Chinese invention patent CN117273100A discloses a neuromorphic chip architecture with configurable network structure, which adopts a hierarchical multi-core structure and a meta-cross-switch array routing mechanism to reduce pulse routing overhead and improve the scalability and static mapping flexibility of on-chip network. However, the optimization logic of this type of technical solution mainly focuses on solving the problem of physical connection and routing path configuration between computing units. In essence, it is still a static or quasi-static management of network topology. Faced with instantaneous pulse avalanche caused by high dynamic signals, this type of architecture lacks the mechanism to perceive the degree of local congestion in real time and intervene in the internal physical state of neurons. Existing flow control methods mostly passively cache or discard overflow data packets at the data link level, without utilizing biological parameters such as refractory period or membrane potential threshold to achieve adaptive adjustment of excitability. This means that a large number of invalid synapse lookup and state update operations still need to be performed during the congestion of the computing core, which exacerbates the competition for system resources and the deterioration of energy efficiency.

[0004] Therefore, establishing a mechanism for real-time perception of local pulse density changes and dynamic reconstruction of computational resource allocation and neuronal excitability state integration without relying on complex floating-point operations to solve the spatiotemporal mismatch between rigid hardware topology and elastic pulse load becomes the technical problem to be solved by this invention. Summary of the Invention

[0005] To address the problems mentioned in the background art, the technical solution of the present invention is as follows: A neural computing integration method based on a brain-like architecture, used to adjust the allocation of computing resources in a spiking neural network through a virtual glial layer, the method comprising the following steps:

[0006] The state monitoring step divides multiple logical neuron nodes into colloidal control domains at the logical level, and uses a pulse density counter configured in the colloidal control domain to count the number of pulse events within a unit time window to generate a congestion index.

[0007] The phase transition decision step extracts the binary bit-level features of the congestion index. When there is a non-zero value in the high bit range of the congestion index, the colloidal control domain is determined to be in a hyperfunctional state. When the congestion index only flips at the low bit level for a continuous preset period, the colloidal control domain is determined to be in a background maintenance state.

[0008] In the source modulation step, in response to the hyperactive state, the virtual glial layer generates a positive refractory period bias parameter based on the congestion index. When the logical neuron node performs the state reset operation after pulse firing, it superimposes the refractory period bias parameter onto the basic refractory period parameter to correct the state update equation and prolong the physical silence duration of the logical neuron node in the reset phase.

[0009] The folding scheduling step, in response to the background maintenance state, triggers the time-division multiplexing folding logic, reduces the clock gating frequency of the logical neuron nodes, and maps the state update tasks of multiple logical neuron nodes to a single physical computation time slice.

[0010] Preferably, the source-end modulation step is executed before the lateral shielding logic. The lateral shielding logic is used to discard pulse events with synaptic weight values ​​lower than a preset effective bit mask on the signal transmission path. The source-end modulation step suppresses the excitability of logical neuron nodes at the physical source of pulse generation, preventing invalid membrane potential integration and synaptic lookup calculation events from entering the subsequent routing network. This reduces the communication bus load while eliminating dynamic power consumption backflow of logical neuron nodes during congestion.

[0011] Preferably, the method further includes performing a threshold adaptation step based on residual utilization, counting the number of impulse events discarded by the lateral masking logic during the hyperactive state to generate a masking residual value; in response to the masking residual value exceeding a noise tolerance threshold within a preset statistical period, generating a threshold floating instruction; and in response to the threshold floating instruction, the logic neuron node performs incremental adjustment of its threshold parameters according to the following linear drift rule: , where V th_new V is the adjusted issuance threshold. th_base The base threshold is given, μ is a preset sensitivity coefficient, and N is the base threshold. res To mask the residual values, a global sensitivity negative feedback loop is established based on the input signal strength using the discarded pulse events.

[0012] Preferably, the phase transition decision step includes: directly reading the preset high-order bit of the pulse density counter register; when the logic value of the preset high-order bit is not all zero, establishing the criterion that the congestion index meets the functional hyperactivity state; the pulse density counter only performs integer accumulation operation, and the phase transition decision step only involves bit logic operations based on the register state.

[0013] Preferably, in the source-end modulation step, the generation logic of the refractory period bias parameter follows a bit-level mapping rule: the congestion level is determined according to the bit level of the most significant bit in the congestion index, and the congestion level is mapped to the corresponding number of clock cycles as the refractory period bias parameter; the logical neuron node suspends response to any external synaptic input signal during the physical silence duration.

[0014] Preferably, the folding scheduling step includes: detecting the magnitude of the change in the pulse density counter value over M consecutive clock cycles; activating the time-division multiplexing controller when the magnitude of the change in value remains within the preset low-bit flip mask range; the time-division multiplexing controller serializes the membrane potential update calculation tasks of N logical neuron nodes in the same colloidal control domain and reuses the same physical computing core to complete the state update of N logical neuron nodes.

[0015] Preferably, the method is applied to processing highly dynamic spatiotemporal data streams generated by dynamic visual sensors; when the virtual gel layer detects an avalanche-like burst of pulses from the highly dynamic spatiotemporal data stream, it introduces an additional physical silence duration through a source-end modulation step, and uses the self-limiting mechanism of logical neuron nodes to smooth out the synchronous burst intensity of the local network, thereby preventing the computing system from deadlocking.

[0016] Preferably, the lateral shielding logic includes: parsing the header information of the pulse event to be transmitted to obtain its synaptic weight value; performing a bitwise AND operation between the synaptic weight value and the effective bitmask dynamically determined by the congestion index; when the operation result is zero, blocking the injection of the pulse event into the on-chip network and not generating a routing request for the pulse event.

[0017] Preferably, the state update equation is a discretized difference equation based on the leakage integral distribution model. The operation of modifying the state update equation specifically involves modifying the reset constant term used to reset the refractory period counter in the discretized difference equation, thereby increasing the countdown value of the refractory period counter and extending the time window for the logical neuron node to be in the polarized state. This is achieved by configuring a virtual glial layer in the edge logic region of the existing neuromorphic chip. The virtual glial layer operates independently of the membrane potential integration circuit of the logical neuron node and performs real-time read and write control of the basic parameters of the logical neuron node through the state register interface to achieve dynamic reconstruction of computing and communication resources.

[0018] A neuromorphic computing integration system based on a brain-like architecture, the system comprising:

[0019] The state monitoring module is used to divide multiple logical neuron nodes into colloidal control domains at the logical level, and use the pulse density counter configured in the colloidal control domain to count the number of pulse events within a unit time window to generate a congestion index.

[0020] The phase transition decision module is used to extract the binary bit-level features of the congestion index. When there is a non-zero value in the high bit range of the congestion index, it is determined that the colloidal control domain is in a hyperfunctional state. When the congestion index only flips at the low bit level for a continuous preset period, it is determined that the colloidal control domain is in a background maintenance state.

[0021] The source-end modulation module is used to respond to the hyperactive state by generating a positive refractory period bias parameter by the virtual glial layer based on the congestion index, and controlling the logical neuron node to add the refractory period bias parameter to the basic refractory period parameter to correct the state update equation when performing the state reset operation after pulse firing, thereby extending the physical silence duration of the logical neuron node during the reset phase.

[0022] The folding scheduling module is used to trigger time-division multiplexing folding logic in response to the background maintenance state, reduce the clock gating frequency of the logical neuron nodes, and map the state update tasks of multiple logical neuron nodes to a single physical computation time slice.

[0023] Compared with the prior art, the beneficial effects of the present invention are:

[0024] 1. In neuromorphic architecture-based neural computing, this invention configures virtual glial control logic in a group of neuronal computing nodes. It uses bit-level statistical features to monitor the pulse congestion in local areas in real time, driving the system to perform logic phase transitions between lateral shielding and time-division multiplexing states. This mechanism solves the problem that traditional static mapping architectures cannot adapt to the extreme non-uniformity of neuromorphic data on the time axis. During signal burst periods, the system actively removes weak connection information interference using lateral shielding logic to ensure that strongly correlated signals occupy the absolute communication bandwidth. During signal sparse periods, time-division multiplexing logic is used to fold scattered computing tasks into a single physical time slice. Based on the local density dynamic reconstruction mechanism, the latency of the system's response to key synaptic events is no longer constrained by the bus queue length. Under the condition of limited physical computing resources, the temporal determinism of the neuromorphic system in processing highly dynamic unstructured data is established.

[0025] 2. When the glial control domain is in a hyperactive state, the generated refractory period bias parameter directly intervenes in the state reset process of the logical neurons. Unlike the passive flow control method of simply discarding overflow data packets at the routing level in conventional data processing systems, this method utilizes the inherent refractory period parameter of the neuron model to implement negative feedback inhibition at the physical source of pulse generation. When the local excitability of the network is too high, the refractory period lock-in time of the relevant neurons is extended, and the excitation frequency at subsequent moments is physically reduced. This process directly blocks the generation of invalid pulses, avoiding the need for the computing core to perform membrane potential integration, threshold comparison, and synaptic table lookup operations under congestion conditions. This fundamentally eliminates the dynamic power consumption backflow caused by invalid computation and improves the self-limiting protection capability of the system when facing synchronous burst stimulation.

[0026] 3. This invention utilizes discarded pulse events during the execution of lateral shielding logic as a signal characterizing the environmental noise level, establishes an adaptive drift loop for the firing threshold parameter, and statistically analyzes the cumulative residual value of shielded events to dynamically adjust the firing threshold level of logic neurons. This mechanism transforms the traditionally regarded system loss and packet loss data into a feedback source for calibrating the system's signal-to-noise ratio, without the need to introduce complex floating-point learning rules or additional environmental sensors. It enables computing nodes to automatically find the optimal excitability balance point based on the current congestion level. The information reuse logic enables the neural computing network to autonomously adapt to drastic fluctuations in input signal strength and maintain steady-state response capability in an open environment. Attached Figure Description

[0027] Fig. 1 This is a schematic diagram of the neural computation integration method based on congestion monitoring and phase transition decision of the present invention;

[0028] Fig. 2 This is a parameter calibration trend graph showing the change of the sensitivity coefficient in the key performance indicators of the system of the present invention.

[0029] Fig. 3 This is a system architecture block diagram of the present invention that integrates a virtual glial control plane and a neuromorphic hardware base. Detailed Implementation

[0030] The following detailed description is intended to explain the claims of the present invention, and is not intended to limit the scope of protection of the present invention.

[0031] This invention discloses a neural computing integration method and system based on a brain-like architecture, comprising a logical neuron node array, a virtual glial control layer, and a physical computing core array. The logical neuron nodes are responsible for performing membrane potential integration and pulse firing tasks. The virtual glial control layer monitors local pulse density and generates control signals. The physical computing core array provides the computing resources required to execute the above logic. The data flow follows a closed-loop path: synaptic input triggers logical neuron state updates, the virtual glial layer performs real-time congestion determination and parameter modulation, and finally, the physical core executes computation and outputs pulse events to the on-chip routing network. Addressing the engineering challenges of local avalanche-like bursts and background sparsity in spiking neural networks caused by highly dynamic spatiotemporal data flows, this invention logically divides multiple logical neuron nodes into several independent glial control domains. This division does not change the physical connection topology between neuron nodes but serves as a logical granularity for resource scheduling. Within each glial control domain, the system is configured with a dedicated pulse density counter, which is a register with a bit width of W, used to count the pulse density of all neurons within that domain within a unit time window T. win The system calculates the total number of pulse events generated within the system. This statistical process does not involve floating-point operations; it only performs integer accumulation. For example, for a glial control domain containing 16×16 neurons, when any neuron generates a pulse firing event, the pulse density counter corresponding to that domain is incremented by one. Given the instantaneous fluctuation characteristics of pulse density, the system executes phase transition decision logic to determine the current control strategy. This logic is not based on complex statistical entropy calculations but directly extracts the binary bit-level features of the pulse density counter values. The system presets a high-order interval mask M. high and low-bit flip mask M low At the end of each decision cycle, the virtual gel layer reads the value of the pulse density counter. When this value matches the high-order interval mask M... high When the result of a bitwise AND operation is not zero, it indicates that the pulse density has exceeded the threshold of linear processing capability, and the system determines that the colloidal control domain has entered a hyperactive state. Conversely, if the value change of the counter only falls within the low-bit flip mask M within M consecutive decision cycles... low Within the defined range, the system determines that the gelatinous control domain is in the background maintenance state.

[0032] To address the dynamic power consumption backflow problem caused by invalid computation in the neuronal core during hyperfunction, the system immediately triggers a source-end modulation step upon determining that this state has been entered. The core of this step lies in directly intervening in the discretized state update equation of the logical neuron node, particularly its refractory period reset logic. In the standard Leakage Integral Fire (LIF) model, a neuron enters a fixed absolute refractory period after firing a pulse. This invention introduces a dynamic refractory period bias mechanism, whereby the virtual glial layer generates a positive integer refractory period bias parameter ΔR based on the congestion index.inhib The generation of this parameter follows a bit-level mapping rule, that is, the congestion level is determined according to the bit level of the most significant bit in the pulse density counter, and this level is linearly mapped to the corresponding number of clock cycles. When the logical neuron node performs the state reset operation after pulse firing, it no longer resets the refractory period counter to a fixed base value, but instead loads the corrected total refractory period value, which is determined by the base refractory period parameter R. base With refractory period bias parameter ΔR inhib The state update equation is modified by superposition to form a superposition of states. , where R total This represents the total number of physical clock cycles a logical neuron node must wait before it can respond to synaptic input again. Through this source-end modulation, logical neurons are locked in a polarization quiescent state during congestion, physically ceasing the integral response and threshold comparison operations to external synaptic input signals, thereby eliminating the generation of invalid pulses and routing requests at the source. To address the issue of hardware resource idleness in the background maintenance state, the system triggers a folding scheduling step. This step utilizes a time-division multiplexing controller to dynamically adjust the mapping relationship of the computation graph. When the system determines that it has entered the background maintenance state, it activates clock gating logic to reduce the operating frequency of the physical computing core in the corresponding region. At the same time, the time-division multiplexing controller serializes the membrane potential update tasks of N logical neuron nodes in the same colloidal control domain and maps them to the time slice of a single physical computing core for execution. For example, four low-activity neurons that were originally processed by four physical cores are now processed by one physical core in a polling manner, while the other three cores enter a deep sleep state.

[0033] In hyperactive state, in addition to the aforementioned source-end modulation, the system executes lateral shielding logic in parallel to protect the communication bus. This logic parses the header information of the pulse event to be transmitted to obtain its synaptic weight value. The virtual gel layer dynamically generates an effective bitmask based on the current congestion index. The system performs a bitwise AND operation between the synaptic weight value and the effective bitmask. When the operation result is zero, it indicates that the amount of information carried by the pulse is lower than the current transmission priority threshold. The system directly blocks the injection of the pulse event into the on-chip network at the routing entry point and does not generate a routing request for the pulse event. To improve the system's adaptability to the environmental noise baseline, this invention also performs a threshold adaptation step based on residual utilization. A shielding residual counter is added inside the virtual gel layer to count the number of pulse events discarded by the lateral shielding logic during hyperactive state, generating a shielding residual value N. res The system sets a noise tolerance threshold Th noise When N res Exceeding Th within the preset statistical period noiseWhen this occurs, it indicates that the current global issuance threshold is too low, causing the system to be overly sensitive to background noise. At this point, the system generates a threshold increase instruction, and the logical neuron nodes respond to this instruction by adjusting the issuance threshold parameter V. th Incremental adjustment is performed, and the adjustment rule follows a linear drift pattern. , where V th_new V is the adjusted issuance threshold. th_base The base threshold is μ, which is a preset sensitivity coefficient. The value of μ is determined through offline calibration experiments. It is the smallest integer coefficient value that keeps the system packet loss rate below 1% under standard white noise input. Through this negative feedback loop, the system uses discarded pulse data to achieve automatic gain control of the input signal strength. For the physical carrier of the above logic steps, the virtual glial layer is configured as an edge logic module independent of the membrane potential integration circuit of the logic neuron node. The basic parameters of the logic neuron node, including the refractory period reset value, firing threshold, and clock gating signal, are read and written in real time through the state register interface. This design ensures that the execution of the resource scheduling strategy does not occupy the computing power resources of the neuron itself used for neuromorphic computing. In the specific engineering configuration of this embodiment, the system uses a field-programmable gate array (FPGA) to implement the above logic. The pulse density counter and the shielding logic are mapped to combinational logic resources (LUTs) next to the block memory (BRAM) on the chip to ensure the response speed of a single clock cycle.

[0034] For the comprehensive implementation of the underlying circuitry of the virtual glial control layer, this module does not run on a microprocessor instruction sequence. Instead, it constructs a dedicated combinational logic circuit using field-programmable gate array lookup table resources and register arrays. The pulse density counter uses a master clock-driven synchronous binary adder circuit. The input is directly coupled to the read / write port of the neuron state memory within the glial control domain, and the output is hardwired to the phase-change decision logic comparator array. This hardware-level coupling ensures that the congestion index update is strictly synchronized with the neuron state machine master clock signal, guaranteeing that the delay of the phase-change decision logic generation control signal is physically locked within two clock cycles, avoiding the uncertainty and software delay introduced by conventional interrupt handling mechanisms. The high-order interval mask and low-order flip mask in the phase-change decision logic are engineered and configured. During system deployment, a test procedure based on link bandwidth pressure boundary is executed, and the test signal is generated... The generator injects a stepped, increasing Poisson distribution pulse stream into the on-chip routing network. Hardware probes monitor the router's FIFO queue duty cycle. When the average FIFO queue duty cycle reaches 85% of the link's physical bandwidth, the system records the pulse count within a unit time window. The highest effective bit corresponding to this count is established as the high-order effective threshold, generating a high-order interval mask. The low-order flip mask is set based on a value between 5% and 10% of the high-order effective threshold. This constructs a state switching boundary with hysteresis characteristics between the hyperactive state and the background maintenance state, preventing system state oscillations caused by minor signal fluctuations near the threshold. In the specific calculation logic of the source-side modulation module generating the refractory period bias parameter, the system uses a bit-priority encoded barrel shift logic to replace complex arithmetic operations. The system identifies the position k of the highest bit with a value of 1 in the congestion index, based on a hardware-fixed mapping relationship. The bias value is calculated, where B is the preset basic step size coefficient that defines the minimum adjustment granularity, and T is the effective level threshold that shields low-intensity background noise interference. The calculation process is completed entirely through a hardware shifter. The shift logic directly outputs the corresponding integer clock cycle number and writes it to the neuron state update register in real time, overwriting the original reset constant.

[0035] Example 1: This example validates the constructed neural computing integrated system by placing it under the typical operating condition of processing unstructured spatiotemporal data streams generated by high-speed dynamic vision sensors. Under this condition, the input signal exhibits extreme bimodal characteristics, namely, microsecond-level avalanche-like pulse bursts interspersed during millisecond-level background noise. This poses a severe challenge to the real-time throughput and energy efficiency of traditional static mapping architectures. When the system is in the burst period of high-frequency flicker or objects rapidly passing through the field of view, the pulse density counter in the colloidal control domain reaches a certain value within a unit time window T. win The accumulated value within the range rapidly increases, causing the value to deviate from the preset high-bit range mask M. highWhen the result of the bitwise AND operation is non-zero, the virtual gel control layer determines that the current region has entered a hyperactive state based on this bit-level characteristic, and triggers a coordinated response from the source-side modulation logic and the side-shielding logic. The virtual gel layer generates the corresponding number of clock cycles as the refractory period bias parameter ΔR based on the bit level of the most significant bit of the pulse density counter through bit-level mapping rules. inhib When a logical neuron performs a state reset operation after firing a pulse, it directly reads this parameter and adds it to the basic refractory period parameter R. base Above, so that the corrected total refractory period R total This operation extends the physical source of the logical neuron into deep silence, pausing the comparison of the membrane potential integral with the threshold for subsequent high-frequency synaptic inputs, thereby establishing an intrinsic negative feedback inhibition loop.

[0036] At the same time, this source-end suppression mechanism creates the necessary computational margin for the effective execution of the lateral shielding logic, since the physical firing frequency of the logic neurons has been reduced by R. total Constrained within the processing boundaries of the physical computing core, the lateral shielding logic can smoothly parse the header information of the remaining pulse events without congestion or packet loss. It then performs a bitwise AND operation between the synaptic weight value and the effective bitmask dynamically determined by the congestion index, precisely filtering out low-weight noise signals. This synergistic effect of source-end frequency clamping and link weight filtering ensures that even when the input data volume exceeds the bus bandwidth by orders of magnitude, the system can still maintain lossless transmission and processing of high-weight feature information, resolving the throughput contradiction between rigid hardware resources and elastic pulse loads. As the intensity of external excitation decreases or the refractory period suppression effect becomes apparent, the amplitude of the pulse density counter's numerical change converges to the low-bit flip mask M. low Within the defined scope, the system determines that the colloidal control domain has entered the background maintenance state and activates the folding scheduling step. The time-division multiplexing controller dynamically maps the state update tasks of N logical neuron nodes in the sparsely activated state in this domain to be executed serially in the continuous time slice of a single physical computing core. At the same time, the clock gating frequency of this core is reduced. This move folds and compresses the scattered computing load that was originally distributed across multiple cores in the time dimension, eliminating the dark silicon power consumption caused by invalid polling and waiting. The entire process does not require manual intervention or pre-compiled instruction scheduling. The system achieves adaptive reconstruction of computing resources in the spatiotemporal dimension solely by bit-level monitoring of the physical quantity of pulse density, establishing the intrinsic steady-state mechanism of the brain-like architecture when processing highly dynamic real-world signals.

[0037] Example 2: This example aims to verify the actual effectiveness of the aforementioned technical solution in dealing with highly dynamic unstructured data streams by constructing a reproducible control test system, and to quantitatively evaluate its engineering value in congestion control and resource scheduling. The experimental design closely addresses the core technical problem to be solved by this invention, namely, how to balance real-time response to avalanche-like pulse bursts and high-efficiency processing of sparse background signals under limited hardware resource boundaries. The experimental platform is built on a neuromorphic computing array containing 4096 physical computing cores. This array adopts an asynchronous circuit design, with each core having an independent clock gating unit and a state register interface. The input signal source is a standardized Dynamic Vision Sensor (DVS) dataset (N-MNIST), which records the pulse event stream generated when digits move rapidly in the field of view. It has typical temporal sparsity and spatial burst characteristics. To simulate the extreme electromagnetic interference and signal jitter that may be encountered in real industrial settings, a Poisson distribution noise pulse with a signal-to-noise ratio of 10dB is superimposed on the original data stream as a stress test to test the system stability.

[0038] The core of the experiment lies in verifying the synergistic effect of source-end modulation and folding scheduling mechanisms. To this end, three sets of comparative experiments were constructed: Control Group A (Benchmark Group): A traditional static mapping strategy was used, with neurons and physical cores in a one-to-one correspondence, but without dynamic refractory period regulation; Control Group B (Partially Missing Group): Only lateral shielding logic was enabled, lacking the source-end refractory period modulation mechanism; The present invention's prototype group: The entire logic, including state monitoring, phase transition decision, source-end modulation, and folding scheduling, was fully enabled. During the experiment, a high-precision logic analyzer was used to monitor and record the key performance indicators of the three systems in real time when processing the same 100ms high-dynamic pulse stream, especially... The study focused on system behavior during the pulse burst period (between 20ms and 40ms). Data recording and analysis showed that in the early stage of the pulse burst, the communication bus of control group A quickly reached saturation, causing approximately 35% of the subsequent key feature pulses to be lost due to queuing overflow. The system response delay showed an exponential upward trend. Although control group B filtered out some low-weight noise through lateral shielding, due to the lack of source-end inhibition, the neuronal core remained in a high-frequency overload state, with persistently high dynamic power consumption peaks. Furthermore, the effective information throughput was limited by the ineffective flipping of the kernel. In contrast, the sample of this invention rapidly triggered source-end modulation within the microsecond time of detecting the high-level flipping of the pulse density counter, thus adjusting the refractory period parameter R. total The dynamic extension to four times the base value instantly smooths out the excessive excitement of the local network, keeping the pulse flux entering the routing network within the linear response range of the bus bandwidth. Table 1 visually shows a comparison of the key performance data of the three systems during the pulse burst period.

[0039] Table 1: Comparison of Key Performance Indicators During Pulse Burst Phase

[0040]

[0041] Data shows that the prototype of this invention achieves a peak throughput improvement of approximately 98% compared to control group A, while reducing the average response latency by orders of magnitude. More importantly, thanks to the physical suppression of invalid flips by source-end modulation, the peak dynamic power consumption decreases by approximately 62%, achieving a qualitative leap in energy efficiency and improving the effective information retention rate. This confirms that the lateral shielding logic, combined with source-end suppression, can more accurately remove noise, rather than blindly dropping packets. Furthermore, during the 60ms to 100ms background maintenance period, the prototype of this invention automatically switches to the folding scheduling mode. Monitoring data shows that approximately 75% of the physical computing cores enter a deep sleep state at this time, with only a small number of cores maintaining the background activity of logical neurons through time-division multiplexing. The overall static power consumption of the system is reduced by approximately 70% compared to control group A. In summary, this experiment strongly demonstrates that this invention, through a dynamic phase transition mechanism based on pulse density, successfully overcomes the impedance mismatch between static hardware topology and dynamic data flow. Whether in extreme burst states or silent maintenance states, the system can adaptively reconfigure computing and communication resources, minimizing system-level power consumption while ensuring the timing integrity of critical information.

[0042] Example 3: This example combines Figs. 1 to 3 This describes a neural computing integration method and system based on a brain-like architecture, such as... Fig. 1 As shown, the process begins by processing the high-dynamic spatiotemporal data stream from the dynamic vision sensor DVS. While transmitting along the original path, the data is sampled in real-time by the state monitoring module. This module counts the number of impulse events within the colloidal control domain at the logic level to generate a congestion index. The phase transition decision module then extracts the bit-level features of the congestion index to determine whether the system is in a hyperactive state or a background-maintained state. When determined to be in a hyperactive state, the process activates the source-end modulation module, which generates a positive refractory period bias parameter from the virtual colloidal layer and writes it to the logic neuron node. The logic neuron node superimposes this parameter onto the base parameters to correct the state update equation. Simultaneously, it uses lateral shielding logic to parse the packet header weight value and discards low-mask impulse events through mask verification, allowing only valid impulse events to be injected into the on-chip routing network. Furthermore, in this state, a threshold adaptation step can be optionally executed, generating a threshold upward command by statistically analyzing the shielding residual value to adjust the issuance threshold V. th When the background is determined to be in a sustained state, the process activates the folding scheduling module, triggers time-division multiplexing and clock gating logic, and maps the task to a single physical computing time slice to complete the state update of the logical neuron node.

[0043] like Fig. 2As shown, the parameter calibration curves represent the changes in parameters. The horizontal axis represents the sensitivity coefficient μ, which ranges from 1 to 8 (critical integers). The left vertical axis represents the percentage of packet loss rate and false alarm rate (%), and the right vertical axis represents the convergence time (ms). Solid circles indicate the system packet loss rate, dashed squares indicate the noise false alarm rate, and long dashed triangles indicate the convergence time. The data shows that as μ increases from 1 to 4, both the system packet loss rate and the noise false alarm rate decrease, and the convergence time shortens. Within the μ=3 and μ=4 range, each indicator reaches its lowest extreme value. However, when μ further increases to 8, the system packet loss rate rebounds. Fig. 3 As shown, the system architecture comprises three layers: external environment perception, virtual colloid control plane, and neuromorphic hardware base. The external environment perception part outputs a high-dynamic spatiotemporal data stream from a dynamic vision sensor. The virtual colloid control plane, as a logic residency layer, is deployed in the edge logic control area or embedded firmware. Internally, it includes a global density monitoring agent to perceive congestion indicators in real time, and a phase transition decision engine responsible for state feature extraction and adjudication, thereby driving the source-end modulation operator to perform refractory period intervention and the resource folding operator to perform time-division multiplexing scheduling. The neuromorphic hardware base, as the physical execution layer, is deployed in a neuromorphic chip array or many-core computing architecture. It includes an integrated membrane potential integration circuit and a physical computing core cluster that supports clock-gated deep sleep, a parameter storage array that stores synaptic weight tables and state registers, and an on-chip routing network that supports lateral shielding of packet loss. The virtual colloid plane sends the hyperactive state mapping strategy silencing and lateral shielding and background maintenance state mapping strategy calculation tasks serialization and folding to the hardware base through a real-time feedback loop of the state register.

[0044] Example 4: This example aims to address the issues concerning the sensitivity coefficient μ and noise tolerance threshold Th in this invention by describing an offline calibration procedure for key system parameters. noise To address the technical black box issue in the calibration process and ensure the reproducibility of the technical solution in engineering implementation, this procedure utilizes a controllable simulation environment. The input signal source is set to a standard Poisson distribution pulse sequence superimposed with Gaussian white noise. The signal-to-noise ratio (SNR) parameter can be quantized and adjusted to simulate different levels of electromagnetic interference environments in industrial settings. The first stage of the calibration process aims to determine the basic threshold V. th_base At the static operating point in an ideal noise-free environment, with the signal-to-noise ratio of the input signal set to infinity, benchmark tests are performed, and the results are recorded at different V... th_base The effective pulse detection rate and false alarm rate data at the voltage value were analyzed using the receiver operating characteristic (ROC) curve method. The voltage value corresponding to the point closest to the upper left corner of the curve was selected as the system's basic threshold V. th_base The initial calibration values ​​are determined, establishing the system's baseline response characteristics under interference-free conditions; the second stage focuses on the sensitivity coefficient. The optimization calibration maintains the already determined V. th_base Without changing the input signal-to-noise ratio, the signal-to-noise ratio of the input signal is reduced to 10dB to create a strong noise interference condition. Under this condition, the lateral shielding logic is triggered at high frequency, resulting in a shielding residual value N. res As the value of μ increases, a gradient scan experiment with μ as the independent variable is initiated. The range of μ is set to the integer interval [1, 10]. For each μ value, the system runs for 1000 time steps and records the corresponding system packet loss rate and noise false alarm rate.

[0045] Table 2: Sensitivity Coefficients Calibration Experiment Data Table

[0046]

[0047] Table 2 shows the experimental results for different μ values. The data shows that when μ is 1 or 2, the threshold increase is insufficient to effectively suppress strong noise, leading to a high false alarm rate and a high packet loss rate caused by congestion. When μ increases to 3 and 4, both the system packet loss rate and false alarm rate drop below 1%, and the convergence time shortens, indicating that the system can quickly adapt to the current noise level and establish a new threshold balance. However, when μ further increases to 5 or higher, although the false alarm rate remains extremely low, the packet loss rate rebounds. This nonlinear inflection point indicates that an excessively large threshold increment leads to oversuppression, incorrectly blocking some weak signal pulses. Based on the nonlinear characteristics presented by this experimental data, this embodiment determines μ=4 as the optimal sensitivity coefficient for this system configuration; the third stage is used to determine the noise tolerance threshold Th. noise After locking in the optimal μ value, the signal-to-noise ratio is restored to the minimum normal operating level required by the system design specifications, such as 20dB. Under this condition, the system is run, and the average residual value N of the lateral shielding logic is statistically analyzed within a unit statistical period. avg And the standard deviation σ of the residuals, according to the statistical 3σ principle, Th noise Set to N avg +3σ, this setting ensures that the system maintains threshold stability within the normal background noise fluctuation range, and only triggers adaptive drift logic when encountering external interference enhancements that exceed the normal range.

[0048] Example 5: During the initialization and configuration phase before the system formally connects to the high-dynamic visual sensor data stream, the virtual glial control layer executes a set of static mapping and parameter loading procedures based on underlying physical constraints to establish the basic topology of the logic control plane and calibrate the initial sensitivity of the phase transition decision logic. This procedure obtains the instruction storage depth of each physical computing core, the fan-in upper limit of the synaptic routing table, and the maximum time slot bandwidth of the on-chip bus by scanning the physical descriptor file of the underlying neuromorphic chip. Based on these hardware physical boundary conditions, the logical neuron array is divided into several non-overlapping glial control domains, ensuring that the number of logical neuron nodes N×N in each domain satisfies the requirement that the total throughput at the theoretical maximum firing frequency does not exceed the physical bandwidth threshold of the local routing segment. On this basis, the system calculates the high-order interval mask M for determining the hyperactive state based on the physical bandwidth margin of each glial control domain. high And the low-bit flip mask M used for background maintenance state determination low These mask values, which have been physically calibrated, are then fixed into the status registers corresponding to each gel control domain via the sideband configuration bus, thereby completing the parameter adaptation from the general logic architecture to the specific physical hardware platform.

[0049] After completing static resource mapping, the system performs a power-on self-test and functional verification process for the congestion control mechanism before activating the closed-loop control loop. This process aims to ensure the deterministic response of the source-side modulation logic and the side-shielding logic under extreme conditions. The process involves a built-in test pattern generator injecting a deterministic pseudo-random pulse sequence with a preset density gradient into the neuron array. The density envelope covers the full dynamic range from background noise levels to saturation burst levels. During the test, the virtual colloid layer samples the output value of the pulse density counter in real time to verify whether its linearity with input density changes meets design expectations. Particular attention is paid to whether the system can generate the correct positive refractory period bias parameter ΔR within a single clock cycle when the input density reaches a preset congestion threshold. inhib And the corresponding valid bit mask. The global enable signal will only be set when the monitored feedback adjustment parameters are completely consistent with the preset lookup table values ​​and the system does not experience deadlock or illegal address access anomalies. This ensures that the system can stably perform dynamic resource reconstruction based on pulse density when processing real and unpredictable environmental signals.

[0050] Example 6: This example provides a standardized engineering optimization procedure for the key parameter N of the event potential energy monitoring network in the virtual gonioid layer, to solve the engineering black box problem of the lack of basis for setting this geometric parameter under different physical hardware platforms or application scenarios. The procedure is executed in a system-level simulation environment that simulates real hardware constraints. The local SRAM capacity of the physical computing core, the single-hop delay of the on-chip bus, and the average number of synaptic connections per neuron are all parameterized as configurable items. The first step of the optimization procedure is to construct a resource-performance two-dimensional evaluation matrix, and set the N value as an exponential sequence with base 2. For each N value configuration, a test data stream containing Poisson background noise and periodic high-frequency burst signals is injected into the system. During the simulation, two core indicators are collected in real time: one is the congestion response delay, that is, the time difference from the input pulse density exceeding the threshold to the system generating an effective suppression parameter; the other is the control overhead ratio, that is, the percentage of logic gate resources and storage resources occupied by the virtual gonioid layer and its associated counters and status registers in the total system resources.

[0051] The parameter decision logic is executed based on the principle of diminishing marginal utility. Data analysis shows that as the value of N decreases, the congestion response delay exhibits a non-linear decreasing trend, but the proportion of control overhead increases exponentially. The procedure defines a dimensionless comprehensive performance function. , among which, T delay For the normalized response delay, C overhead For the normalized overhead ratio, α and β are preset weighting coefficients based on the sensitivity of real-time performance and cost to specific applications. Finally, the value of N that maximizes the comprehensive performance function E(N) is selected as the optimal granularity of the glue domain for this specific hardware configuration and application scenario. For example, in this calibration experiment for a certain edge FPGA chip, it was calculated that when N=16, the system can achieve microsecond-level congestion response speed while keeping the additional logic resource consumption within 5%.

[0052] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A neural computation ensemble method based on a brain-like architecture, used to regulate the allocation of computational resources in a spiking neural network through a virtual glial layer, characterized in that, The method includes the following steps: The state monitoring step divides multiple logical neuron nodes into colloidal control domains at the logical level, and uses a pulse density counter configured in the colloidal control domain to count the number of pulse events within a unit time window to generate a congestion index. The phase transition decision step extracts the binary bit-level features of the congestion index. When there is a non-zero value in the high bit range of the congestion index, the colloidal control domain is determined to be in a hyperfunctional state. When the congestion index only flips at the low bit level for a continuous preset period, the colloidal control domain is determined to be in a background maintenance state. In the source-end modulation step, in response to the hyperfunctional state, a positive refractory period bias parameter is generated by the virtual colloidal layer based on the congestion index; When a logical neuron node performs a state reset operation after pulse firing, it adds the refractory period bias parameter to the basic refractory period parameter to correct the state update equation and prolong the physical silence duration of the logical neuron node during the reset phase. The folding scheduling step, in response to the background maintenance state, triggers the time-division multiplexing folding logic, reduces the clock gating frequency of the logical neuron nodes, and maps the state update tasks of multiple logical neuron nodes to a single physical computation time slice.

2. The neural computing integration method based on a brain-like architecture according to claim 1, characterized in that, The source-side modulation step is executed before the lateral shielding logic, which is used to discard pulse events with synaptic weight values ​​lower than the preset effective bit mask on the signal transmission path. The source-end modulation step suppresses the excitability of logical neuron nodes at the physical source of pulse generation, preventing invalid membrane potential integration and synapse lookup calculation events from entering the subsequent routing network. This reduces the load on the communication bus while eliminating dynamic power backflow of logical neuron nodes during congestion.

3. The neural computing integration method based on a brain-like architecture according to claim 2, characterized in that, The method also includes performing a threshold adaptation step based on residual utilization to count the number of pulse events discarded by the lateral shielding logic during hyperfunction to generate shielding residual values; In response to the masking residual value exceeding the noise tolerance threshold within a preset statistical period, a threshold upward floating instruction is generated; In response to a threshold float instruction, the logical neuron node performs incremental adjustment of its threshold parameter according to the following linear drift rule: , where V th_new V is the adjusted issuance threshold. th_base The base threshold is given, μ is a preset sensitivity coefficient, and N is the base threshold. res To mask the residual values, a global sensitivity negative feedback loop is established based on the input signal strength using the discarded pulse events.

4. The neural computing integration method based on a brain-like architecture according to claim 1, characterized in that, The phase transition decision steps include: directly reading the preset high-order bit of the pulse density counter register; when the logic value of the preset high-order bit is not all zero, establishing the criterion that the congestion index meets the functional hyperactivity state; the pulse density counter only performs integer accumulation operations, and the phase transition decision steps only involve bit logic operations based on the register state.

5. The neural computing integration method based on a brain-like architecture according to claim 1, characterized in that, In the source-side modulation step, the generation logic of the refractory period bias parameter follows the bit-level mapping rule: the congestion level is determined according to the bit level of the most significant bit in the congestion index, and the congestion level is mapped to the corresponding number of clock cycles as the refractory period bias parameter; the logical neuron node suspends response to any external synaptic input signal during the physical silence period.

6. The neural computing integration method based on a brain-like architecture according to claim 1, characterized in that, The folding scheduling steps include: detecting the magnitude of the pulse density counter's value change over M consecutive clock cycles; activating the time-division multiplexing controller when the magnitude of the value change remains within the preset low-bit flip mask range; serializing the membrane potential update calculation tasks of N logical neuron nodes within the same colloidal control domain using the time-division multiplexing controller, and reusing the same physical computing core to complete the state update of the N logical neuron nodes.

7. The neural computing integration method based on a brain-like architecture according to claim 1, characterized in that, The method is applied to process highly dynamic spatiotemporal data streams generated by dynamic visual sensors. When the virtual colloid layer detects an avalanche-like burst of pulses from the highly dynamic spatiotemporal data stream, it introduces an additional physical silence duration through a source-end modulation step, and uses the self-limiting mechanism of logical neuron nodes to smooth out the synchronous burst intensity of the local network.

8. The neural computing integration method based on a brain-like architecture according to claim 2, characterized in that, The lateral shielding logic includes: parsing the header information of the pulse event to be transmitted to obtain its synaptic weight value; performing a bitwise AND operation between the synaptic weight value and the effective bitmask dynamically determined by the congestion index; and blocking the injection of the pulse event into the on-chip network when the operation result is zero, without generating a routing request for the pulse event.

9. The neural computing integration method based on a brain-like architecture according to claim 1, characterized in that, The state update equation is a discretized difference equation based on the leakage integral distribution model. The specific operation of modifying the state update equation is to modify the reset constant term used to reset the refractory period counter in the discretized difference equation, so as to increase the countdown value of the refractory period counter, thereby extending the time window for the logical neuron node to be in the polarized state. This is achieved by configuring a virtual glial layer in the edge logic region of the existing neuromorphic chip. The virtual glial layer operates independently of the membrane potential integration circuit of the logical neuron node and performs real-time read and write control of the basic parameters of the logical neuron node through the state register interface.

10. A neuromorphic architecture-based neural computing integrated system for performing the method of claim 1, characterized in that the system... include: The state monitoring module is used to divide multiple logical neuron nodes into colloidal control domains at the logical level, and use the pulse density counter configured in the colloidal control domain to count the number of pulse events within a unit time window to generate a congestion index. The phase transition decision module is used to extract the binary bit-level features of the congestion index. When there is a non-zero value in the high bit range of the congestion index, it is determined that the colloidal control domain is in a hyperfunctional state. When the congestion index only flips at the low bit level for a continuous preset period, it is determined that the colloidal control domain is in a background maintenance state. The source-end modulation module is used to respond to the hyperactive state by generating a positive refractory period bias parameter by the virtual glial layer based on the congestion index, and controlling the logical neuron node to add the refractory period bias parameter to the basic refractory period parameter to correct the state update equation when performing the state reset operation after pulse firing, thereby extending the physical silence duration of the logical neuron node during the reset phase. The folding scheduling module is used to trigger time-division multiplexing folding logic in response to the background maintenance state, reduce the clock gating frequency of the logical neuron nodes, and map the state update tasks of multiple logical neuron nodes to a single physical computation time slice.

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