An ozone generator power supply

Abstract

This invention relates to the field of power distribution technology, and provides a power supply for an ozone generator, including a high-voltage power generation device and a control device. The high-voltage power generation device converts the three-phase AC power supplied by the power grid into double-peak high-voltage electricity, and transmits the generated double-peak high-voltage electricity to the discharge unit of the ozone generator. The control device is connected to the high-voltage power generation device and is used to detect and control the operation of the high-voltage power generation device, thereby realizing flexible adjustment of the power output and achieving the purpose of saving energy. At the same time, it adopts diode uncontrolled rectification technology, which has a high power factor of over 92%, effectively suppressing high-order harmonics generated by the power supply and preventing pollution to the power grid.

Description

Technical Field

[0001] This invention belongs to the field of power distribution technology, and particularly relates to a power supply for an ozone generator. Background Technology

[0002] The power supply for an ozone generator is a crucial component of an ozone system. The quality of the power supply directly affects ozone production and power consumption; it is commonly referred to as the heart of the ozone system.

[0003] Currently, ozone generator power supplies in the industry are mainly purchased from frequency converter manufacturers because they are modified from general frequency converters. However, ozone generator power supplies modified from general frequency converters cannot be 100% adapted to the operating environment of ozone generators, resulting in high energy consumption and low efficiency. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides an ozone generator power supply, aiming to solve the problem that ozone generator power supplies modified from general-purpose frequency converters cannot be 100% adapted to the operating environment of ozone generators, resulting in high energy consumption and low efficiency.

[0005] The technical solution provided by this invention is: an ozone generator power supply, the ozone generator power supply including a high-voltage power generation device and a control device; The high-voltage power generating device is used to convert the three-phase AC power provided by the power grid into double-peak high-voltage power, and to transmit the generated double-peak high-voltage power to the discharge unit of the ozone generator. The control device is connected to the high-voltage electric generator and is used to detect and control the operation of the high-voltage electric generator.

[0006] As an improved solution, the high-voltage power generation device includes a rectifier circuit, an inverter circuit, a step-up transformer, and an ozone generator load; The rectifier circuit is used to convert the three-phase alternating current supplied by the power grid into direct current. The inverter circuit is connected to the rectifier circuit and is used to perform single-phase full-bridge inversion on the DC power output by the rectifier circuit, converting it into single-phase AC power with adjustable duty cycle and frequency that matches the load electrical parameters of the ozone generator. The step-up transformer is connected to the inverter circuit and is used to step up the single-phase AC power output by the inverter circuit. The ozone generator load is connected to the step-up transformer and is used to resonate with the high voltage generated by the step-up transformer to generate the double-peak high voltage required for air to discharge and ionize ozone through the dielectric barrier, and to deliver the generated double-peak high voltage to the discharge unit.

[0007] As an improved solution, the control device includes a control board and a drive board; The control board is connected to the rectifier circuit, and the drive board is connected to the control board and the inverter circuit.

[0008] As an improved solution, the control board is equipped with a main control circuit, a DC voltage sampling circuit, an analog quantity sampling circuit, a relay output circuit, a PWM pulse circuit, a 485 communication circuit, and a digital quantity input circuit. The DC voltage sampling circuit, analog sampling circuit, relay output circuit, PWM pulse circuit, 485 communication circuit, and digital input circuit are respectively connected to the main control circuit.

[0009] As an improved solution, the main control circuit includes a main control chip U1; The DC voltage sampling circuit includes a first DC voltage sampling circuit, a second DC voltage sampling circuit, and a third DC voltage sampling circuit. The first DC voltage sampling circuit includes an operational amplifier U4B. The non-inverting input terminal of the operational amplifier U4B is connected to pin 1 of connector P7 after being connected in series with resistors R47, R46, R104 and R103. The inverting input terminal is connected to pin 2 of connector P7 after being connected in series with resistors R69, R68, R108 and R107. The output terminal is connected to pin 15 of the main control chip U1 after being connected in series with resistor R58. The second DC voltage sampling circuit includes an operational amplifier U3A. The non-inverting input terminal of the operational amplifier U3A is connected to pin 1 of connector P8 after being connected in series with resistors R12, R20, R98 and R97. The inverting input terminal is connected to pin 2 of connector P8 after being connected in series with resistors R19, R18, R102 and R101. The output terminal is connected to pin 20 of the main control chip U1 after being connected in series with resistor R14. The third DC voltage sampling circuit includes an operational amplifier U3B. The non-inverting input terminal of the operational amplifier U3B is connected to pin 1 of connector P9 after being connected in series with resistors R44, R42, R106, and R105. The inverting input terminal is connected to pin 2 of connector P9 after being connected in series with resistors R67, R66, R110, and R109. The output terminal is connected to pin 22 of the main control chip U1 after being connected in series with resistor R57.

[0010] As an improved solution, the analog sampling circuit includes a first analog sampling circuit, a second analog sampling circuit, and a third analog sampling circuit, wherein: The first analog sampling circuit includes an operational amplifier U5A. The non-inverting input terminal of the operational amplifier U5A is connected to pin 5 of connector CN2 via a series resistor R51, the inverting input terminal is connected to pin 6 of connector CN2 via a series resistor R71, and the output terminal is connected to pin 14 of the main control chip U1 via a series resistor R62. The second analog sampling circuit includes an operational amplifier U6A. The non-inverting input terminal of the operational amplifier U6A is connected to pin 3 of connector CN2 via a series resistor R13, the inverting input terminal is connected to pin 4 of connector CN2 via a series resistor R26, and the output terminal is connected to pin 11 of the main control chip U1 via a series resistor R17. The third analog sampling circuit includes an operational amplifier U6B. The non-inverting input terminal of the operational amplifier U6B is connected to pin 1 of connector CN2 via a series resistor R54, the inverting input terminal is connected to pin 2 of connector CN2 via a series resistor R73, and the output terminal is connected to pin 10 of the main control chip U1 via a series resistor R64.

[0011] As an improved solution, the digital input circuit includes a first digital input circuit, a second digital input circuit, a third digital input circuit, a fourth digital input circuit, and a fifth digital input circuit, wherein: The first digital input circuit includes an optocoupler OP6. The line from pin 4 of the optocoupler OP6 is connected to pin 56 of the main control chip U1 after being connected in series with resistor R53. The line from pin 3 is grounded. The line from pin 1 is connected to pin 1 of connector P10 after being connected in series with resistor R5 and resistor R3. The line from pin 2 is connected to the drain of field-effect transistor Q4. The source of field-effect transistor Q4 is grounded. The gate of field-effect transistor Q4 is connected to pin 1 of connector P10. The second digital input circuit includes an optocoupler OP3. The line from pin 4 of the optocoupler OP3 is connected to pin 55 of the main control chip U1 after being connected in series with resistor R50. The line from pin 3 is grounded. The line from pin 1 is connected to pin 2 of connector P10 after being connected in series with resistors R9 and R6. The line from pin 2 is connected to the drain of field-effect transistor Q5. The source of field-effect transistor Q5 is grounded. The gate of field-effect transistor Q5 is connected to pin 2 of connector P10. The third digital input circuit includes an optocoupler OP5. The line from pin 4 of the optocoupler OP5 is connected to pin 54 of the main control chip U1 after being connected in series with resistor R52. The line from pin 3 is grounded. The line from pin 1 is connected to pin 3 of connector P10 after being connected in series with resistors R11 and R10. The line from pin 2 is connected to the drain of field-effect transistor Q6. The source of field-effect transistor Q6 is grounded. The gate of field-effect transistor Q6 is connected to pin 3 of connector P10. The fourth digital input circuit includes an optocoupler OP8. The line from pin 4 of the optocoupler OP8 is connected to pin 53 of the main control chip U1 after being connected in series with resistor R70. The line from pin 3 is grounded. The line from pin 1 is connected to pin 1 of connector P11 after being connected in series with resistor R21 and resistor R15. The line from pin 2 is connected to the drain of field-effect transistor Q7. The source of field-effect transistor Q7 is grounded. The gate of field-effect transistor Q7 is connected to pin 1 of connector P11. The fifth digital input circuit includes an optocoupler OP7. The line from pin 4 of the optocoupler OP7 is connected to pin 50 of the main control chip U1 after being connected in series with resistor R61. The line from pin 3 is grounded. The line from pin 1 is connected to pin 2 of connector P11 after being connected in series with resistors R23 and R16. The line from pin 2 is connected to the drain of field-effect transistor Q8. The source of field-effect transistor Q8 is grounded. The gate of field-effect transistor Q8 is connected to pin 2 of connector P11.

[0012] As an improved solution, the relay output circuit includes a first relay output circuit, a second relay output circuit, and a third relay output circuit, wherein: The first relay output circuit includes a packaged chip Q1. The line leading out of the drain D of the packaged chip Q1 is connected to the anode of the diode D5. The line leading out of the cathode of the diode D5 is connected to pin 4 of the relay K1. The line leading out of pin 1 of the relay K1 is connected to the drain D of the packaged chip Q1. The line leading out of pin 2 of the relay K1 is connected to pin 2 of the connector P2. The line leading out of the gate of the packaged chip Q1 is connected to pin 38 of the main control chip U1 after being connected in series with resistor R43. The drain of the packaged chip Q1 is grounded. The second relay output circuit includes a packaged chip Q2. The line leading out from the drain D of the packaged chip Q2 is connected to the anode of the diode D6. The line leading out from the cathode of the diode D6 is connected to pin 4 of the relay K2. The line leading out from pin 1 of the relay K2 is connected to the drain D of the packaged chip Q2. The line leading out from pin 2 of the relay K2 is connected to pin 2 of the connector P3. The line leading out from the gate of the packaged chip Q2 is connected to pin 37 of the main control chip U1 after being connected in series with resistor R37. The drain of the packaged chip Q2 is grounded. The third relay output circuit includes a packaged chip Q3. The line leading out of the drain D of the packaged chip Q3 is connected to the anode of the diode D7. The line leading out of the cathode of the diode D7 is connected to pin 4 of the relay K3. The line leading out of pin 1 of the relay K3 is connected to the drain D of the packaged chip Q3. The line leading out of pin 2 of the relay K3 is connected to pin 2 of the connector P4. The line leading out of the gate of the packaged chip Q3 is connected to pin 33 of the main control chip U1 after being connected in series with a resistor R38. The drain of the packaged chip Q3 is grounded.

[0013] As an improved solution, the driver board is provided with a first driving circuit and a second driving circuit, wherein: The first driving circuit includes a first optocoupler chip U1. A line from pin 3 of the optocoupler chip U1 is connected to pin 1 of connector CN1. A line from pin 7, connected in series with resistor R6, is connected to pin 2 of connector CN1. A resistor R1 is provided on a line from pin 16. The other end of resistor R1 is connected to the cathode of diode D1. The anode of diode D1 is connected to the anode of diode D2. The cathode of diode D2 is connected to pin 1 of connector P3. A first circuit node is provided on the line between pin 16 and resistor R1. A line from the first circuit node is connected to pin 4 of connector P3. A second circuit node is provided on the line between the first circuit node and pin 4 of connector P3. A line from pin 11 of the optocoupler chip U1, connected in series with resistor R3, is connected to a transistor... The base of transistor Q1 is connected, and the line from the collector of transistor Q1 is connected to pin 13 of optocoupler chip U1. The line from the emitter of transistor Q1 is connected in series with resistor R4 and then connected to pin 3 of connector P3. A third circuit node is provided on the line between resistor R3 and the base of transistor Q1. A fourth circuit node is provided on the line between the emitter of transistor Q1 and resistor R4. The line from the third circuit node is connected to the base of transistor Q2. The line from the collector of transistor Q2 is connected to the fourth circuit node. The emitter of transistor Q2 is grounded. A fifth circuit node is provided on the line between resistor R4 and pin 3 of connector P3. The line from the fifth circuit node is connected in series with resistor R15 and diode D10 and then connected to the second circuit node. The second driving circuit includes a second optocoupler chip U5. A line from pin 3 of the optocoupler chip U5 is connected to pin 1 of connector CN1. A line from pin 7 is connected to pin 3 of connector CN1 after being connected in series with resistor R7. A resistor R16 is provided on a line from pin 16, and the other end of resistor R16 is connected to the cathode of diode D7. The anode of diode D7 is connected to the anode of diode D8. The cathode of diode D8 is connected to pin 1 of connector P4. A sixth circuit node is provided on the line between pin 16 and resistor R16. A line from the sixth circuit node is connected to pin 4 of connector P4. A seventh circuit node is provided on the line between the sixth circuit node and pin 4 of connector P4. A line from pin 11 of the optocoupler chip U5 is connected to a transistor after being connected in series with resistor R18. The base of transistor Q5 is connected, and the line from the collector of transistor Q5 is connected to pin 13 of optocoupler chip U5. The line from the emitter of transistor Q5 is connected in series with resistor R19 and then connected to pin 3 of connector P4. An eighth circuit node is provided on the line between resistor R18 and the base of transistor Q5. A ninth circuit node is provided on the line between the emitter of transistor Q5 and resistor R19. The line from the eighth circuit node is connected to the base of transistor Q5. The line from the collector of transistor Q5 is connected to the ninth circuit node. The emitter of transistor Q5 is grounded. A tenth circuit node is provided on the line between resistor R19 and pin 3 of connector P4. The line from the tenth circuit node is connected in series with resistor R21 and diode D11 and then connected to the seventh circuit node.

[0014] In this embodiment of the invention, the ozone generator power supply includes a high-voltage power generation device and a control device. The high-voltage power generation device converts the three-phase AC power supplied by the power grid into double-peak high-voltage power and transmits the generated double-peak high-voltage power to the discharge unit of the ozone generator. The control device is connected to the high-voltage power generation device and is used to detect and control the operation of the high-voltage power generation device, thereby realizing flexible adjustment of the power output and achieving the purpose of saving energy. At the same time, the use of diode uncontrolled rectification technology results in a high power factor, which can reach more than 92%, effectively suppressing high-order harmonics generated by the power supply and preventing pollution to the power grid. Attached Figure Description

[0015] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0016] Figure 1This is a structural block diagram of the ozone generator power supply provided by the present invention; Figure 2 This is a circuit diagram of the main control circuit provided by the present invention; Figure 3 This is a circuit diagram of the DC voltage sampling circuit provided by the present invention; Figure 4 This is a circuit diagram of the analog quantity sampling circuit provided by the present invention; Figure 5 This is a circuit diagram of the digital input circuit provided by the present invention; Figure 6 This is a circuit diagram of the relay output circuit provided by the present invention; Figure 7 This is a circuit diagram of the PWM pulse circuit provided by the present invention; Figure 8 This is a circuit diagram of the power supply voltage circuit provided by the present invention; Figure 9 This is a circuit diagram of the driver board provided by the present invention. Detailed Implementation

[0017] The embodiments of the technical solution of the present invention will now be described in detail with reference to the accompanying drawings. These embodiments are merely illustrative of the present invention and are therefore intended to limit the scope of protection of the present invention.

[0018] Figure 1 This is a structural block diagram of the ozone generator power supply provided by the present invention. For ease of explanation, only the parts related to the embodiments of the present invention are shown in the figure.

[0019] The power supply for an ozone generator includes a high-voltage power generation device and a control device; The high-voltage power generating device is used to convert the three-phase AC power provided by the power grid into double-peak high-voltage power, and to transmit the generated double-peak high-voltage power to the discharge unit of the ozone generator. The control device is connected to the high-voltage electric generator and is used to detect and control the operation of the high-voltage electric generator.

[0020] Combination Figure 1 As shown, the high-voltage power generation device includes a rectifier circuit, an inverter circuit, a step-up transformer, and an ozone generator load; The rectifier circuit is used to convert the three-phase alternating current supplied by the power grid into direct current. The inverter circuit, connected to the rectifier circuit, is used to perform single-phase full-bridge inversion of the DC output from the rectifier circuit, converting it into single-phase AC with adjustable duty cycle and frequency that matches the load electrical parameters of the ozone generator. A step-up transformer is connected to an inverter circuit and is used to step up the voltage of the single-phase AC power output from the inverter circuit. The ozone generator load is connected to the step-up transformer and is used to resonate with the high voltage generated by the step-up transformer to generate the double-peak high voltage required for air to discharge and ionize ozone through the dielectric barrier, and then delivers the generated double-peak high voltage to the discharge unit. The control device includes a control board and a drive board; The control board is connected to the rectifier circuit, and the driver board is connected to the control board and the inverter circuit.

[0021] The control board includes a main control circuit, a DC voltage sampling circuit, an analog sampling circuit, a relay output circuit, a PWM pulse circuit, a 485 communication circuit, and a digital input circuit. Among them, the DC voltage sampling circuit, analog quantity sampling circuit, relay output circuit, PWM pulse circuit, 485 communication circuit and digital quantity input circuit are respectively connected to the main control circuit. The aforementioned driver board is equipped with a first driver circuit and a second driver circuit.

[0022] The embodiments of the present invention employ the above-described technical solution, which has the following technical effects: (1) The ozone generator power supply adopts pulse density modulation and constant voltage, so that the ozone generator power supply is in a high-efficiency working mode and generates double peak discharge, thereby easily achieving output adjustment of 10%-100%, which makes it convenient for users to adjust ozone output in a simple and flexible way, and achieves the purpose of saving energy. (2) The ozone generator power supply is customizable and can provide constant high voltage pulses. The high voltage discharge is a sharp pulse, the ozone ionization energy is highly concentrated, and the power consumption is excellent. It can consume 6~7 kilowatts of electricity per kilogram of ozone, which is better than the national standard requirements. (3) It can detect faults in the power generation chamber and quickly shut off the power supply within a few microseconds when a problem occurs in the power generation chamber, cut off the main power supply, ensure that the equipment is not damaged and the fault range does not spread. At the same time, it has clear fault indications, which facilitates maintenance and troubleshooting. (4) Because it uses diode uncontrolled rectification technology, the power factor is high, reaching more than 92%. The professionally designed circuit can effectively suppress the high-order harmonics generated by the power supply, prevent pollution to the power grid, and meet national standards.

[0023] For ease of explanation, the specific circuit principles of each of the above circuits are given below: like Figure 2As shown, the main control circuit includes a main control chip U1, which is an STM32F1 series chip manufactured by STMicroelectronics. The STM32F1 series is based on the ARM Cortex-M3 core, with a maximum system clock frequency of 72MHz and a single-cycle instruction execution speed of 12MIPS. It can dynamically monitor the operating status of each component of the ozone generator power supply in real time and promptly address any problems that arise during operation. exist Figure 2 Based on, combined Figure 3 As shown, the DC voltage sampling circuit includes a first DC voltage sampling circuit, a second DC voltage sampling circuit, and a third DC voltage sampling circuit. The first DC voltage sampling circuit includes an operational amplifier U4B. The non-inverting input terminal of the operational amplifier U4B is connected to pin 1 of connector P7 after being connected in series with resistors R47, R46, R104 and R103. The inverting input terminal is connected to pin 2 of connector P7 after being connected in series with resistors R69, R68, R108 and R107. The output terminal is connected to pin 15 of the main control chip U1 after being connected in series with resistor R58. The second DC voltage sampling circuit includes an operational amplifier U3A. The non-inverting input terminal of the operational amplifier U3A is connected to pin 1 of connector P8 after being connected in series with resistors R12, R20, R98 and R97. The inverting input terminal is connected to pin 2 of connector P8 after being connected in series with resistors R19, R18, R102 and R101. The output terminal is connected to pin 20 of the main control chip U1 after being connected in series with resistor R14. The third DC voltage sampling circuit includes an operational amplifier U3B. The non-inverting input terminal of the operational amplifier U3B is connected to pin 1 of connector P9 after being connected in series with resistors R44, R42, R106 and R105. The inverting input terminal is connected to pin 2 of connector P9 after being connected in series with resistors R67, R66, R110 and R109. The output terminal is connected to pin 22 of the main control chip U1 after being connected in series with resistor R57. In this embodiment, operational amplifiers U3A, U3B, and U4B are commercially available amplifiers, such as the LM358DR2G model. The models of other components are referenced from [reference needed]. Figure 3 This will not be elaborated upon here.

[0024] exist Figure 2 Based on, combined Figure 4 As shown, the analog sampling circuit includes a first analog sampling circuit, a second analog sampling circuit, and a third analog sampling circuit, wherein: The first analog sampling circuit includes an operational amplifier U5A. The non-inverting input terminal of the operational amplifier U5A is connected to pin 5 of connector CN2 after being connected in series with resistor R51. The inverting input terminal is connected to pin 6 of connector CN2 after being connected in series with resistor R71. The output terminal is connected to pin 14 of the main control chip U1 after being connected in series with resistor R62. The second analog sampling circuit includes an operational amplifier U6A. The non-inverting input terminal of the operational amplifier U6A is connected to pin 3 of connector CN2 after being connected in series with resistor R13. The inverting input terminal is connected to pin 4 of connector CN2 after being connected in series with resistor R26. The output terminal is connected to pin 11 of the main control chip U1 after being connected in series with resistor R17. The third analog sampling circuit includes an operational amplifier U6B. The non-inverting input of the operational amplifier U6B is connected to pin 1 of connector CN2 via a series resistor R54. The inverting input is connected to pin 2 of connector CN2 via a series resistor R73. The output is connected to pin 10 of the main control chip U1 via a series resistor R64.

[0025] In this embodiment, operational amplifiers U5A, U6A, and U6B are commercially available amplifiers, such as the LM358DR2G model. The models of other components are referenced from [reference needed]. Figure 4 This will not be elaborated upon here.

[0026] exist Figure 2 Based on, combined Figure 5 As shown, the digital input circuit includes a first digital input circuit, a second digital input circuit, a third digital input circuit, a fourth digital input circuit, and a fifth digital input circuit, wherein: The first digital input circuit includes an optocoupler OP6. The line from pin 4 of the optocoupler OP6 is connected to pin 56 of the main control chip U1 after being connected in series with resistor R53. The line from pin 3 is grounded. The line from pin 1 is connected to pin 1 of connector P10 after being connected in series with resistor R5 and resistor R3. The line from pin 2 is connected to the drain of field-effect transistor Q4. The source of field-effect transistor Q4 is grounded. The gate of field-effect transistor Q4 is connected to pin 1 of connector P10. The second digital input circuit includes an optocoupler OP3. The line from pin 4 of the optocoupler OP3 is connected to pin 55 of the main control chip U1 after being connected in series with resistor R50. The line from pin 3 is grounded. The line from pin 1 is connected to pin 2 of connector P10 after being connected in series with resistors R9 and R6. The line from pin 2 is connected to the drain of field-effect transistor Q5. The source of field-effect transistor Q5 is grounded. The gate of field-effect transistor Q5 is connected to pin 2 of connector P10. The third digital input circuit includes an optocoupler OP5. The line from pin 4 of the optocoupler OP5 is connected to pin 54 of the main control chip U1 after being connected in series with resistor R52. The line from pin 3 is grounded. The line from pin 1 is connected to pin 3 of connector P10 after being connected in series with resistors R11 and R10. The line from pin 2 is connected to the drain of field-effect transistor Q6. The source of field-effect transistor Q6 is grounded. The gate of field-effect transistor Q6 is connected to pin 3 of connector P10. The fourth digital input circuit includes an optocoupler OP8. The line from pin 4 of the optocoupler OP8 is connected to pin 53 of the main control chip U1 after being connected in series with resistor R70. The line from pin 3 is grounded. The line from pin 1 is connected to pin 1 of connector P11 after being connected in series with resistors R21 and R15. The line from pin 2 is connected to the drain of field-effect transistor Q7. The source of field-effect transistor Q7 is grounded. The gate of field-effect transistor Q7 is connected to pin 1 of connector P11. The fifth digital input circuit includes an optocoupler OP7. The line from pin 4 of the optocoupler OP7 is connected to pin 50 of the main control chip U1 after being connected in series with resistor R61. The line from pin 3 is grounded. The line from pin 1 is connected to pin 2 of connector P11 after being connected in series with resistors R23 and R16. The line from pin 2 is connected to the drain of MOSFET Q8. The source of MOSFET Q8 is grounded. The gate of MOSFET Q8 is connected to pin 2 of connector P11.

[0027] In this embodiment, the aforementioned optical couplers OP6, OP7, OP8, OP5, and OP3 can be EL357N(B)(TA)-G couplers, or other models can be used. The models of other components are as follows: Figure 5 As shown, it will not be elaborated further here.

[0028] exist Figure 2 Based on, combined Figure 6 As shown, the relay output circuit includes a first relay output circuit, a second relay output circuit, and a third relay output circuit, wherein: The first relay output circuit includes a packaged chip Q1. The line from the drain D of the packaged chip Q1 is connected to the anode of diode D5. The line from the cathode of diode D5 is connected to pin 4 of relay K1. The line from pin 1 of relay K1 is connected to the drain D of packaged chip Q1. The line from pin 2 of relay K1 is connected to pin 2 of connector P2. The line from the gate of packaged chip Q1 is connected to pin 38 of main control chip U1 after being connected in series with resistor R43. The drain of packaged chip Q1 is grounded. The second relay output circuit includes packaged chip Q2. The line from the drain D of packaged chip Q2 is connected to the anode of diode D6. The line from the cathode of diode D6 is connected to pin 4 of relay K2. The line from pin 1 of relay K2 is connected to the drain D of packaged chip Q2. The line from pin 2 of relay K2 is connected to pin 2 of connector P3. The line from the gate of packaged chip Q2 is connected to pin 37 of main control chip U1 after being connected in series with resistor R37. The drain of packaged chip Q2 is grounded. The third relay output circuit includes packaged chip Q3. The line from the drain D of packaged chip Q3 is connected to the anode of diode D7. The line from the cathode of diode D7 is connected to pin 4 of relay K3. The line from pin 1 of relay K3 is connected to the drain D of packaged chip Q3. The line from pin 2 of relay K3 is connected to pin 2 of connector P4. The line from the gate of packaged chip Q3 is connected to pin 33 of main control chip U1 after being connected in series with resistor R38. The drain of packaged chip Q3 is grounded.

[0029] In this embodiment, the packaged chips Q1, Q2, and Q3 can be Microchip WSP10N10 packaged chips, and the models of other components are as follows: Figure 6 As shown, I will not repeat myself here.

[0030] In this embodiment of the invention, the main control circuit also includes a buzzer circuit, a PWM pulse circuit, and a power supply voltage circuit, for example... Figure 7 The PWM pulse circuit described Figure 8 The power supply voltage circuit described herein will not be repeated here, but it is not intended to limit the present invention.

[0031] In embodiments of the present invention, such as Figure 9 As shown, the driver board is equipped with a first driving circuit and a second driving circuit, wherein: The first driving circuit includes a first optocoupler chip U1. A line from pin 3 of optocoupler chip U1 is connected to pin 1 of connector CN1. A line from pin 7, connected in series with resistor R6, is connected to pin 2 of connector CN1. A resistor R1 is provided on a line from pin 16. The other end of resistor R1 is connected to the cathode of diode D1. The anode of diode D1 is connected to the anode of diode D2. The cathode of diode D2 is connected to pin 1 of connector P3. A first circuit node is provided on the line between pin 16 and resistor R1. A line from the first circuit node is connected to pin 4 of connector P3. A second circuit node is provided on the line between the first circuit node and pin 4 of connector P3. A line from pin 11 of optocoupler chip U1, connected in series with resistor R3, is connected to... The base of transistor Q1 is connected, and the line from the collector of transistor Q1 is connected to pin 13 of optocoupler chip U1. The line from the emitter of transistor Q1 is connected in series with resistor R4 and then connected to pin 3 of connector P3. A third circuit node is provided on the line between resistor R3 and the base of transistor Q1. A fourth circuit node is provided on the line between the emitter of transistor Q1 and resistor R4. The line from the third circuit node is connected to the base of transistor Q2. The line from the collector of transistor Q2 is connected to the fourth circuit node. The emitter of transistor Q2 is grounded. A fifth circuit node is provided on the line between resistor R4 and pin 3 of connector P3. The line from the fifth circuit node is connected in series with resistor R15 and diode D10 and then connected to the second circuit node. The second driving circuit includes a second optocoupler chip U5. A line from pin 3 of optocoupler chip U5 is connected to pin 1 of connector CN1. A line from pin 7 is connected to pin 3 of connector CN1 after being connected in series with resistor R7. A resistor R16 is provided on a line from pin 16, and the other end of resistor R16 is connected to the cathode of diode D7. The anode of diode D7 is connected to the anode of diode D8. The cathode of diode D8 is connected to pin 1 of connector P4. A sixth circuit node is provided on the line between pin 16 and resistor R16. A line from the sixth circuit node is connected to pin 4 of connector P4. A seventh circuit node is provided on the line between the sixth circuit node and pin 4 of connector P4. A line from pin 11 of optocoupler chip U5 is connected to pin 3 of connector CN1 after being connected in series with resistor R18. The base of transistor Q5 is connected, and the line from the collector of transistor Q5 is connected to pin 13 of optocoupler chip U5. The line from the emitter of transistor Q5 is connected in series with resistor R19 and then connected to pin 3 of connector P4. There is an eighth circuit node on the line between resistor R18 and the base of transistor Q5. There is a ninth circuit node on the line between the emitter of transistor Q5 and resistor R19. The line from the eighth circuit node is connected to the base of transistor Q5. The line from the collector of transistor Q5 is connected to the ninth circuit node. The emitter of transistor Q5 is grounded. There is a tenth circuit node on the line between resistor R19 and pin 3 of connector P4. The line from the tenth circuit node is connected in series with resistor R21 and diode D11 and then connected to the seventh circuit node.

[0032] In this embodiment, the first optocoupler chip U1 and the first optocoupler chip U5 can be ACPL-332J-500E chips. This chip integrates protection functions, mainly including: VCE saturation detection, undervoltage lockout (UVLO) fault feedback, active Miller clamping, etc., providing comprehensive protection for the IGBT drive circuit. Other components, such as... Figure 9 As shown, it will not be elaborated further here.

[0033] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be covered within the scope of the claims and specification of the present invention.

Claims

1. A power supply for an ozone generator, characterized in that, The ozone generator power supply includes a high-voltage power generation device and a control device; The high-voltage power generating device is used to convert the three-phase AC power provided by the power grid into double-peak high-voltage power, and to transmit the generated double-peak high-voltage power to the discharge unit of the ozone generator. The control device is connected to the high-voltage electric generator and is used to detect and control the operation of the high-voltage electric generator.

2. The ozone generator power supply according to claim 1, characterized in that, The high-voltage power generation device includes a rectifier circuit, an inverter circuit, a step-up transformer, and an ozone generator load. The rectifier circuit is used to convert the three-phase alternating current supplied by the power grid into direct current. The inverter circuit is connected to the rectifier circuit and is used to perform single-phase full-bridge inversion on the DC power output by the rectifier circuit, converting it into single-phase AC power with adjustable duty cycle and frequency that matches the load electrical parameters of the ozone generator. The step-up transformer is connected to the inverter circuit and is used to step up the single-phase AC power output by the inverter circuit. The ozone generator load is connected to the step-up transformer and is used to resonate with the high voltage generated by the step-up transformer to generate the double-peak high voltage required for air to discharge and ionize ozone through the dielectric barrier, and to deliver the generated double-peak high voltage to the discharge unit.

3. The ozone generator power supply according to claim 2, characterized in that, The control device includes a control board and a drive board; The control board is connected to the rectifier circuit, and the drive board is connected to the control board and the inverter circuit.

4. The ozone generator power supply according to claim 3, characterized in that, The control board is equipped with a main control circuit, a DC voltage sampling circuit, an analog quantity sampling circuit, a relay output circuit, a PWM pulse circuit, a 485 communication circuit, and a digital quantity input circuit. The DC voltage sampling circuit, analog sampling circuit, relay output circuit, PWM pulse circuit, 485 communication circuit, and digital input circuit are respectively connected to the main control circuit.

5. The ozone generator power supply according to claim 4, characterized in that, The main control circuit includes a main control chip U1; The DC voltage sampling circuit includes a first DC voltage sampling circuit, a second DC voltage sampling circuit, and a third DC voltage sampling circuit. The first DC voltage sampling circuit includes an operational amplifier U4B. The non-inverting input terminal of the operational amplifier U4B is connected to pin 1 of connector P7 after being connected in series with resistors R47, R46, R104 and R103. The inverting input terminal is connected to pin 2 of connector P7 after being connected in series with resistors R69, R68, R108 and R107. The output terminal is connected to pin 15 of the main control chip U1 after being connected in series with resistor R58. The second DC voltage sampling circuit includes an operational amplifier U3A. The non-inverting input terminal of the operational amplifier U3A is connected to pin 1 of connector P8 after being connected in series with resistors R12, R20, R98 and R97. The inverting input terminal is connected to pin 2 of connector P8 after being connected in series with resistors R19, R18, R102 and R101. The output terminal is connected to pin 20 of the main control chip U1 after being connected in series with resistor R14. The third DC voltage sampling circuit includes an operational amplifier U3B. The non-inverting input terminal of the operational amplifier U3B is connected to pin 1 of connector P9 after being connected in series with resistors R44, R42, R106, and R105. The inverting input terminal is connected to pin 2 of connector P9 after being connected in series with resistors R67, R66, R110, and R109. The output terminal is connected to pin 22 of the main control chip U1 after being connected in series with resistor R57.

6. The ozone generator power supply according to claim 5, characterized in that, The analog signal sampling circuit includes a first analog signal sampling circuit, a second analog signal sampling circuit, and a third analog signal sampling circuit, wherein: The first analog sampling circuit includes an operational amplifier U5A. The non-inverting input terminal of the operational amplifier U5A is connected to pin 5 of connector CN2 via a series resistor R51, the inverting input terminal is connected to pin 6 of connector CN2 via a series resistor R71, and the output terminal is connected to pin 14 of the main control chip U1 via a series resistor R62. The second analog sampling circuit includes an operational amplifier U6A. The non-inverting input terminal of the operational amplifier U6A is connected to pin 3 of connector CN2 via a series resistor R13, the inverting input terminal is connected to pin 4 of connector CN2 via a series resistor R26, and the output terminal is connected to pin 11 of the main control chip U1 via a series resistor R17. The third analog sampling circuit includes an operational amplifier U6B. The non-inverting input terminal of the operational amplifier U6B is connected to pin 1 of connector CN2 via a series resistor R54, the inverting input terminal is connected to pin 2 of connector CN2 via a series resistor R73, and the output terminal is connected to pin 10 of the main control chip U1 via a series resistor R64.

7. The ozone generator power supply according to claim 6, characterized in that, The digital input circuit includes a first digital input circuit, a second digital input circuit, a third digital input circuit, a fourth digital input circuit, and a fifth digital input circuit, wherein: The first digital input circuit includes an optocoupler OP6. The line from pin 4 of the optocoupler OP6 is connected to pin 56 of the main control chip U1 after being connected in series with resistor R53. The line from pin 3 is grounded. The line from pin 1 is connected to pin 1 of connector P10 after being connected in series with resistor R5 and resistor R3. The line from pin 2 is connected to the drain of field-effect transistor Q4. The source of field-effect transistor Q4 is grounded. The gate of field-effect transistor Q4 is connected to pin 1 of connector P10. The second digital input circuit includes an optocoupler OP3. The line from pin 4 of the optocoupler OP3 is connected to pin 55 of the main control chip U1 after being connected in series with resistor R50. The line from pin 3 is grounded. The line from pin 1 is connected to pin 2 of connector P10 after being connected in series with resistors R9 and R6. The line from pin 2 is connected to the drain of field-effect transistor Q5. The source of field-effect transistor Q5 is grounded. The gate of field-effect transistor Q5 is connected to pin 2 of connector P10. The third digital input circuit includes an optocoupler OP5. The line from pin 4 of the optocoupler OP5 is connected to pin 54 of the main control chip U1 after being connected in series with resistor R52. The line from pin 3 is grounded. The line from pin 1 is connected to pin 3 of connector P10 after being connected in series with resistors R11 and R10. The line from pin 2 is connected to the drain of field-effect transistor Q6. The source of field-effect transistor Q6 is grounded. The gate of field-effect transistor Q6 is connected to pin 3 of connector P10. The fourth digital input circuit includes an optocoupler OP8. The line from pin 4 of the optocoupler OP8 is connected to pin 53 of the main control chip U1 after being connected in series with resistor R70. The line from pin 3 is grounded. The line from pin 1 is connected to pin 1 of connector P11 after being connected in series with resistor R21 and resistor R15. The line from pin 2 is connected to the drain of field-effect transistor Q7. The source of field-effect transistor Q7 is grounded. The gate of field-effect transistor Q7 is connected to pin 1 of connector P11. The fifth digital input circuit includes an optocoupler OP7. The line from pin 4 of the optocoupler OP7 is connected to pin 50 of the main control chip U1 after being connected in series with resistor R61. The line from pin 3 is grounded. The line from pin 1 is connected to pin 2 of connector P11 after being connected in series with resistors R23 and R16. The line from pin 2 is connected to the drain of field-effect transistor Q8. The source of field-effect transistor Q8 is grounded. The gate of field-effect transistor Q8 is connected to pin 2 of connector P11.

8. The ozone generator power supply according to claim 6, characterized in that, The relay output circuit includes a first relay output circuit, a second relay output circuit, and a third relay output circuit, wherein: The first relay output circuit includes a packaged chip Q1. The line leading out of the drain D of the packaged chip Q1 is connected to the anode of the diode D5. The line leading out of the cathode of the diode D5 is connected to pin 4 of the relay K1. The line leading out of pin 1 of the relay K1 is connected to the drain D of the packaged chip Q1. The line leading out of pin 2 of the relay K1 is connected to pin 2 of the connector P2. The line leading out of the gate of the packaged chip Q1 is connected to pin 38 of the main control chip U1 after being connected in series with resistor R43. The drain of the packaged chip Q1 is grounded. The second relay output circuit includes a packaged chip Q2. The line leading out from the drain D of the packaged chip Q2 is connected to the anode of the diode D6. The line leading out from the cathode of the diode D6 is connected to pin 4 of the relay K2. The line leading out from pin 1 of the relay K2 is connected to the drain D of the packaged chip Q2. The line leading out from pin 2 of the relay K2 is connected to pin 2 of the connector P3. The line leading out from the gate of the packaged chip Q2 is connected to pin 37 of the main control chip U1 after being connected in series with resistor R37. The drain of the packaged chip Q2 is grounded. The third relay output circuit includes a packaged chip Q3. The line leading out of the drain D of the packaged chip Q3 is connected to the anode of the diode D7. The line leading out of the cathode of the diode D7 is connected to pin 4 of the relay K3. The line leading out of pin 1 of the relay K3 is connected to the drain D of the packaged chip Q3. The line leading out of pin 2 of the relay K3 is connected to pin 2 of the connector P4. The line leading out of the gate of the packaged chip Q3 is connected to pin 33 of the main control chip U1 after being connected in series with a resistor R38. The drain of the packaged chip Q3 is grounded.

9. The ozone generator power supply according to claim 3, characterized in that, The driver board is provided with a first driving circuit and a second driving circuit, wherein: The first driving circuit includes a first optocoupler chip U1. A line from pin 3 of the optocoupler chip U1 is connected to pin 1 of connector CN1. A line from pin 7, connected in series with resistor R6, is connected to pin 2 of connector CN1. A resistor R1 is provided on a line from pin 16. The other end of resistor R1 is connected to the cathode of diode D1. The anode of diode D1 is connected to the anode of diode D2. The cathode of diode D2 is connected to pin 1 of connector P3. A first circuit node is provided on the line between pin 16 and resistor R1. A line from the first circuit node is connected to pin 4 of connector P3. A second circuit node is provided on the line between the first circuit node and pin 4 of connector P3. A line from pin 11 of the optocoupler chip U1, connected in series with resistor R3, is connected to a transistor... The base of transistor Q1 is connected, and the line from the collector of transistor Q1 is connected to pin 13 of optocoupler chip U1. The line from the emitter of transistor Q1 is connected in series with resistor R4 and then connected to pin 3 of connector P3. A third circuit node is provided on the line between resistor R3 and the base of transistor Q1. A fourth circuit node is provided on the line between the emitter of transistor Q1 and resistor R4. The line from the third circuit node is connected to the base of transistor Q2. The line from the collector of transistor Q2 is connected to the fourth circuit node. The emitter of transistor Q2 is grounded. A fifth circuit node is provided on the line between resistor R4 and pin 3 of connector P3. The line from the fifth circuit node is connected in series with resistor R15 and diode D10 and then connected to the second circuit node. The second driving circuit includes a second optocoupler chip U5. A line from pin 3 of the optocoupler chip U5 is connected to pin 1 of connector CN1. A line from pin 7 is connected to pin 3 of connector CN1 after being connected in series with resistor R7. A resistor R16 is provided on a line from pin 16, and the other end of resistor R16 is connected to the cathode of diode D7. The anode of diode D7 is connected to the anode of diode D8. The cathode of diode D8 is connected to pin 1 of connector P4. A sixth circuit node is provided on the line between pin 16 and resistor R16. A line from the sixth circuit node is connected to pin 4 of connector P4. A seventh circuit node is provided on the line between the sixth circuit node and pin 4 of connector P4. A line from pin 11 of the optocoupler chip U5 is connected to a transistor after being connected in series with resistor R18. The base of transistor Q5 is connected, and the line from the collector of transistor Q5 is connected to pin 13 of optocoupler chip U5. The line from the emitter of transistor Q5 is connected in series with resistor R19 and then connected to pin 3 of connector P4. An eighth circuit node is provided on the line between resistor R18 and the base of transistor Q5. A ninth circuit node is provided on the line between the emitter of transistor Q5 and resistor R19. The line from the eighth circuit node is connected to the base of transistor Q5. The line from the collector of transistor Q5 is connected to the ninth circuit node. The emitter of transistor Q5 is grounded. A tenth circuit node is provided on the line between resistor R19 and pin 3 of connector P4. The line from the tenth circuit node is connected in series with resistor R21 and diode D11 and then connected to the seventh circuit node.

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