Single-stage sepic power converter with power factor correction

Abstract

An isolated SEPIC converter is provided with a power factor correction inductor coupled between an output node of a diode bridge and a terminal of a power switch transistor. When the power switch transistor is cycled off, the power factor correction inductor conducts a demagnetization current through a primary winding of a transformer to charge a bulk capacitor.

Description

Technical Field

[0001] This application relates to a switching power converter, and more particularly, to a single-ended primary inductor converter (SEPIC) power converter with power factor correction. Background Technology

[0002] Battery charging and power management via AC / DC switching power converters are fundamental components of systems with rechargeable batteries. A crucial factor for a switching power converter is its power factor, which is the ratio of its active power to its apparent (complex) power. The power factor decreases when the AC / DC switching power converter acts as a reactive load (inductive or capacitive) on the AC power supply. In this case, the apparent power increases, which involves undesirable power oscillations between the AC power supply and the AC / DC switching power converter. Therefore, for AC / DC switching power converters with higher output power, the power factor is regulated so that relatively high-output-power AC / DC switching power converters must meet their power factor thresholds.

[0003] To achieve a relatively high power factor in an AC / DC switching power converter, its input voltage and input current should be in phase. When an AC / DC switching power converter presents a purely resistive load to an AC power supply, the input voltage and input current are in phase. However, AC / DC switching power converters typically present a reactive load to an AC power supply. For example, the input impedance of a flyback converter without any power factor correction is largely capacitive, and therefore will have an unsatisfactory power factor. To improve the power factor, a boost power factor correction stage can be inserted between the rectified AC power supply and the flyback converter, thus forming a two-stage architecture. However, a two-stage architecture increases cost, so a single-stage isolated (AC-to-DC) switching power converter is desired. For example, a single-stage flyback converter can use peak current or constant on-time methods for power factor correction. However, these single-stage power factor correction (PFC) techniques result in relatively high output voltage ripple. Therefore, there is a need in the art for a single-stage isolated switching power converter with power factor correction without relatively high output voltage ripple. Summary of the Invention

[0004] According to one aspect of this disclosure, an isolated switching power converter is provided, comprising: an input node for receiving a rectified input voltage; a transformer including a first primary winding having a first terminal coupled to the input node; a power switching transistor coupled to a second terminal of the primary winding; and a power factor correction inductor coupled between the input node and the second terminal of the first primary winding.

[0005] According to another aspect of this disclosure, a method of operating an isolated switch power converter is provided, comprising the following actions: turning on a power switching transistor to magnetize a power factor correction inductor and the primary winding of a transformer; and demagnetizing the power factor correction inductor in response to turning off the power switching transistor to conduct a demagnetizing current from the power factor correction inductor and through the primary winding to charge a large-capacity capacitor.

[0006] According to another aspect of this disclosure, a controller for an isolated SEPIC converter is provided, comprising: an input node for receiving a rectified input voltage; a main transformer including a first primary winding having a first terminal coupled to the input node; a power switching transistor coupled to a second terminal of the primary winding; a current sensing resistor coupled between ground and the power switching transistor; a power factor correction inductor coupled between the input node and the drain of the power switching transistor; a current sensor configured to sense a power factor correction current conducted by the power factor correction inductor to provide a power factor correction current measurement; and a controller configured to sense a voltage across the current sensing resistor to determine a combined current conducted by the power switching transistor, the controller further configured to subtract the power factor correction current measurement from the combined current to determine a primary winding current conducted by the first primary winding.

[0007] Other devices, apparatuses, systems, methods, features, and advantages of the present invention will be apparent to those skilled in the art upon studying the following figures and detailed embodiments. All such additional devices, apparatuses, systems, methods, features, and advantages are included within this specification, within the scope of the invention, and protected by the appended claims. Attached Figure Description

[0008] Throughout the diagram, the same reference numerals denote corresponding parts across different views.

[0009] Figure 1 The diagram illustrates a typical isolated SEPIC.

[0010] Figure 2 An isolated SEPIC according to one aspect of this disclosure is illustrated.

[0011] Figure 3 The illustration shows a method according to one aspect of this disclosure. Figure 2 Modifications to the isolated SEPIC to reduce the voltage of large-capacity capacitors.

[0012] Figure 4A The illustration shows one aspect of the present disclosure. Figure 3 Some of the operating waveforms of the isolated SEPIC are based on cutting-edge technology.

[0013] Figure 4B The illustration shows one aspect of the present disclosure. Figure 3 Some falling-edge based operating waveforms of the isolated SEPIC.

[0014] Figure 5 It is a graph of power factor correction inductor switch-on time compensation based on the voltage of a large-capacity capacitor, according to one aspect of this disclosure.

[0015] Figure 6A The illustration shows a portion of an isolated SEPIC in which the power factor correction inductor switch is directly coupled to ground, according to one aspect of the present disclosure.

[0016] Figure 6B The illustration shows a portion of an isolated SEPIC according to one aspect of the present disclosure, wherein the power factor correction inductor switch is coupled to ground via a dedicated sensing resistor.

[0017] Figure 7 The figure illustrates a graph of rectified AC input voltage, rectified and filtered AC input voltage, and power factor correction inductor switch on-time compensation at the zero crossover of the rectified and filtered AC input voltage, according to one aspect of the present disclosure.

[0018] Figure 8 The illustration shows an isolated SEPIC according to one aspect of the present disclosure, comprising an auxiliary winding connected in series with an auxiliary switching transistor and a zero-voltage switching capacitor for zero-voltage switching control of a power switching transistor.

[0019] Figure 9 The illustration shows a portion of an isolated SEPIC according to one aspect of the present disclosure, in which a current-sensing transformer is used to sense the current of a power factor correction inductor.

[0020] Figure 10 The flowchart illustrates the operation method of the SEPIC switching power converter.

[0021] The embodiments of this disclosure and their advantages can be best understood by referring to the following detailed description. It should be understood that the same reference numerals are used to identify one or more of the same elements shown in the drawings. Detailed Implementation

[0022] Figure 1The diagram illustrates an example of a prior art single-stage isolated switching power converter 100 with power factor correction. A bridge rectifier 105 rectifies an AC power supply 110 to produce a rectified sinusoidal input voltage (Vin) at input node 115. A power factor correction (PFC) inductor (LPFC) is coupled between input node 115 and an internal node 120, which in turn is coupled to the anode of diode D1. A large-capacity capacitor Cbulk is coupled between the cathode of diode D1 and ground. Similarly, the primary winding W1 of a transformer T (note that transformer T acts as a pair of coupled inductors) is coupled between the cathode of diode D1 and the drain of power switching transistor M1. The source of power switching transistor M1 is grounded through a sensing resistor Rsense. Internal node 120 is also coupled to the anode of diode D2. The cathode of diode D2 is coupled to the drain of power switching transistor M1.

[0023] When controller U1 turns on power switching transistor M1, both diodes D1 and D2 become forward biased and thus conduct. A magnetizing current then occurs across the power factor correction inductor. Similarly, when power switching transistor M1 conducts, a magnetizing current occurs across the primary winding W1's magnetizing inductance Lm. When power switching transistor M1 turns off, the drain of power switching transistor M1 rises to equal the sum of n*Vout and the voltage of the large-capacity capacitor. Therefore, when power switching transistor M1 turns off, diode D2 is reverse biased and does not conduct. To demagnetize the power factor correction inductor, the anode of diode D1 rises to equal the voltage of the large-capacity capacitor (ignoring any threshold voltage drop across diode D1). Therefore, in response to the power switching transistor turning off, the demagnetizing voltage difference across the power factor correction inductor is the difference between the voltage of the large-capacity capacitor and the input voltage Vin. Demagnetization maintains the voltage of the large-capacity capacitor.

[0024] When the power switching transistor M1 is conducting, the output diode D3, coupled between the secondary winding W2 and the output node for the output voltage Vout, is reverse biased. However, when the power switching transistor M1 is off, the output diode D3 conducts the secondary winding current to charge the output capacitor Cout with the output voltage. Therefore, with respect to the cycle of the power switching transistor M1, the secondary side of the switching power converter 100 thus functions similarly to a flyback converter.

[0025] For the switching power converter 100, operation in discontinuous conduction mode, where both the secondary winding current and the power factor correction inductor are demagnetized to zero current, is advantageous. In contrast, in continuous conduction mode, both the secondary winding current and the power factor correction inductor current can increase. While maintaining discontinuous conduction mode is desirable, it should be noted that the demagnetizing voltage of the power factor correction inductor is merely the difference between the voltage of the large-capacity capacitor and the input voltage. Therefore, the switching power converter 100 may struggle to deliver sufficient output power while maintaining discontinuous conduction mode operation.

[0026] Although not typically described in this way, it can be seen that the switching power converter 100 is used as a SEPIC. In contrast, as... Figure 2 The single-stage switching power converter 200 shown also functions as a SEPIC, enabling stronger demagnetization of the power factor correction inductor. Therefore, while providing increased output power, it is also advantageous to maintain discontinuous conduction operation. As similarly discussed for the switching power converter 100, a bridge rectifier 205 rectifies the AC source 210 to generate a rectified sinusoidal input voltage (Vin) at input node 215 in the switching power converter 200. A power factor correction inductor (LPFC) is coupled between input node 215 and the anode of diode D2, which has a cathode coupled to the drain of power switching transistor M1. Input node 215 is also coupled to the anode of diode D1, which has a cathode coupled to the primary winding W1 of transformer T (it should be noted that since the primary and secondary currents do not conduct simultaneously, transformer T effectively functions as a pair of coupled inductors). A bulk capacitor (Cbulk) is coupled between the cathode of diode D1 and ground. The controller U1 drives the gate voltage of the power switching transistor M1 to control whether the transistor M1 is turned on or off. For example, the controller U1 can monitor the voltage across the sense resistor Rsense coupled between the source of the power switching transistor M1 and ground to turn off the power switching transistor M1 when the desired peak current is achieved.

[0027] When power switching transistor M1 is on, both diodes D1 and D2 are forward biased, while output diode D3, coupled between the secondary winding W2 and the output node for the output voltage Vout, is reverse biased. Therefore, with power switching transistor M1 conducting, a magnetizing current occurs in the power factor correction inductor, and another magnetizing current occurs in the primary winding W1. When power switching transistor M1 is off, the power factor correction inductor demagnetizes through diode D2 and the conduction of winding W1 to charge the large-capacity capacitor. When power switching transistor M1 is off, the secondary winding current is then formed not only by the flyback current generated by the magnetizing inductance across the primary winding (e.g., multiplied by the N:1 turns ratio between the primary and secondary windings) but also by the forward current conducted by the power factor correction inductor (e.g., multiplied by the turns ratio). Therefore, the demagnetizing voltage of the power factor correction inductor is not just the voltage of the large-capacity capacitor, but the sum of the voltage of the large-capacity capacitor and n*Vout. In this way, despite providing relatively high output power, the power factor correction inductor can be more strongly demagnetized to enhance its ability to maintain discontinuous conduction operating modes.

[0028] The arrangement of the power factor correction inductor between input node 215 and the anode of diode D2 can also reduce the power factor correction inductor current during the off-time of power switching transistor M1. Additionally, the drain-source voltage (Vds spike) across power switching transistor M1 also decreases during off-time, allowing for a less robust (and therefore less expensive) implementation of power switching transistor M1. For example, in one implementation of switching power converter 200, power switching transistor M1 may have a 650V rating. In contrast, switching power converter 100 may need to operate in continuous conduction mode to provide sufficient output power. In continuous conduction mode, the primary winding current becomes increasingly higher, and the Vds spike also becomes increasingly higher, necessitating a more robust (and therefore more expensive) voltage rating for power switching transistor M1 in switching power converter 100, such as an 800V rating.

[0029] While the switching power converter 200 advantageously simplifies the implementation of discontinuous conduction operation, the voltage of large-capacity capacitors can become relatively high (e.g., up to 450V), requiring a more robust (and therefore more expensive) implementation of large-capacity capacitors. Figure 3 The switching power converter 300 is shown; the switching power converter 200 can be modified to reduce the voltage of large-capacity capacitors. For clarity of illustration, Figure 3The AC input source and bridge rectifier are not shown, but they will be arranged as discussed for switching converter 200 to drive input node 315 with the rectified input voltage Vin. The power factor correction inductor LPFC is now coupled not only between input node 315 (which can also be represented as the output node of a diode bridge) and the anode of diode D2, but also between input node 315 and the drain of NMOS power factor correction inductor transistor M2, which has a source coupled to ground via a sensing resistor Rsense. The cathode of diode D2 is coupled to auxiliary winding P2, which is coupled to the drain of power switching transistor M1. Input node 315 is coupled to the drain of power switching transistor M1 via diode D1 and primary winding W1. The large-capacity capacitor, secondary winding W2, output diode D3, and output capacitor Cout are arranged as discussed for switching power converter 200.

[0030] If power switching transistor M1 is on while transistor M2 is off, the voltage across the auxiliary winding P2 is opposite to the input voltage, which would otherwise be applied across the power factor correction inductor. Therefore, the magnetizing current through the power factor correction inductor is reduced, which in turn limits the increase in voltage across the large capacitor when power switching transistor M1 is off. Thus, during low-load cycles, circulating power switching transistor M1 while transistor M2 remains off is useful for preventing excessive voltage increases across the large capacitor. In this way, the large capacitor can maintain a relatively inexpensive voltage rating (e.g., 400V or lower) to reduce manufacturing costs. If transistor M2 is cyclically on while power switching transistor M1 is on, the magnetizing current through the power factor correction inductor is maximized because it is charged with the input voltage Vin (minus the sense resistor voltage). In contrast, when power switching transistor M1 is on and transistor M2 is off, the power factor correction inductor is charged only with the input voltage Vin minus the auxiliary winding voltage. The ringing that occurs with respect to the power factor correction inductor voltage during the zero-crossing period of transistor M2 in the AC input voltage is also useful. In particular, if the ringing causes the lower terminal voltage of the power factor correction inductor to become overly negative, the body diode of transistor M2 will conduct and clamp this voltage.

[0031] The cycle of transistor M2 can be controlled using either rising edge alignment or falling edge alignment. Figure 4AThe diagram shows some example operating waveforms of the rising edge alignment control method for transistor M2. At time t0, power switching transistor M1 is turned on. Therefore, the gate voltage of power switching transistor M1 has a rising edge at time t0 (rising from ground to the supply voltage). The turn-on time / rising edge of the gate voltage of transistor M2 is substantially coordinated with the rising edge of the gate voltage of power switching transistor M1 at time t0, but with a slight delay to avoid voltage and / or current spikes. At time t1, the gate voltage of transistor M2 has a falling edge (discharging to ground). Finally, the gate voltage of power switching transistor M1 has a falling edge at time t2. Since both power switching transistors M1 and M2 are turned on, the sense resistor voltage Vsense rises at a relatively steep rate from time t0 to time t1. From time t1 to time t2, only power switching transistor M1 is turned on, which causes the Vsense voltage to rise more slowly. When the Vsense voltage at time t2 indicates that the desired peak primary winding current has been achieved, controller U1 cyclically turns off power switching transistor M1.

[0032] exist Figure 4B The diagram illustrates some example operating waveforms of the falling edge aligned control method. At time t0, power switching transistor M1 is turned on. Therefore, the gate voltage of power switching transistor M1 has a rising edge at time t0 (rising from ground to the supply voltage). At time t2, controller U1 senses that the desired peak primary winding current has been reached via the Vsense voltage, and therefore controller U1 turns off power switching transistor M1. Therefore, the gate voltage of power switching transistor M1 has a falling edge at time t2 (discharging to ground). The turn-off time of transistor M2 is substantially the same as that of power switching transistor M1. Therefore, controller U1 discharges the gate voltage of transistor M2 at time t2 (causing a falling edge). At time t1, after time t0 but before time t2, the gate voltage of transistor M2 has a rising edge to turn on transistor M2. Since only power switching transistor M1 is turned on during the time from time t0 to time t1, the sense resistor voltage Vsense rises at a relatively low rate from time t0 to time t1. From time t1 to time t2, both power switching transistors M1 and M2 are turned on, causing the Vsense voltage to rise more rapidly. When the Vsense voltage at time t2 indicates that the desired peak primary winding current has been achieved, the controller U1 cycles off power switching transistor M1.

[0033] Regardless of whether the control method is based on the rising edge or the falling edge, controller U1 needs to determine an appropriate on-time for each cycle of transistor M2 (assuming it is not a light-load cycle in which the cycle of transistor M2 is suppressed). In one implementation, the on-time (M2_on) of transistor M2 can be proportional to the on-time (M1_on) of power switching transistor M1 by a scaling constant k, such that M2_on = k * M1_on. Furthermore, the scaling constant k can be determined by comparing the voltage of the large-capacity capacitor with the threshold voltage (vbulk_reg_th). For example, as... Figure 5 As shown, the proportional constant can be equal to 1 as long as the voltage of the large-capacity capacitor (Vbulk) is less than the threshold voltage. If the voltage of the large-capacity capacitor rises above the overvoltage threshold (Vbulk_ovp_th), the proportional constant is zero. Within the range where Vbulk is greater than Vbulk_reg_th but less than Vbulk_ovp_th, the proportional constant decreases linearly according to the ratio (Vbulk - Vbulk_ovp_th) / dvbulk, where dvbulk equals Vbulk_ovp_th - Vbulk_reg_th.

[0034] Referring again to the switching power converter 300, it should be noted that the current conducted through transistor M2 will be added to the current conducted through the sense resistor Rsense. Since output voltage regulation is based on the assumption that the peak primary winding current is proportional to the sense resistor voltage Vsense, this can potentially impair power factor correction and output voltage regulation. Therefore, as... Figure 6A The switching power converter 600 is shown, and the switching power converter 300 can be modified. For clarity, in... Figure 6A Only diode D2, auxiliary winding P2, transistor M2, power switching transistor M1, and sense resistor Rsense are illustrated. The remaining components of the switching power converter 600 can be arranged as discussed for the switching power converter 300. In the switching power converter 600, the source of transistor M2 is directly coupled to ground, rather than through the sense resistor. Therefore, the sense resistor voltage Vsense will depend only on the primary winding current in the switching power converter 600.

[0035] Although the sense resistor voltage Vsense in the switching power converter 600 depends only on the primary winding current, it may be beneficial to monitor the current conducted by transistor M2 to detect faults such as overcurrent conditions. Therefore, as Figure 6BThe switching power converter 605 is shown, and the switching power converter 600 can be modified. In the switching power converter 605, the source of transistor M2 is coupled to ground via a switching transistor sense resistor RsM2. The resistance of the sense resistor RsM2 can be significantly smaller than the resistance of the sense resistor Rs, such that during normal operation (fault-free), the voltage across the sense resistor RsM2 is much smaller than the sense resistor voltage Vsense. However, if a fault occurs, such as a partial short circuit in the power factor correction inductor causing excessive current to flow through transistor M2, the voltage across the sense resistor RsM2 may exceed the sense resistor voltage Vsense. This increase in voltage causes the diode D4 coupled between the source of transistor M2 and the power switching transistor M1 to become forward biased, triggering an overcurrent fault such as that sensed by the controller U1 through the Isense pin or terminal.

[0036] Referring again to AC source 210, it should be noted that the relatively high frequency switching of power switching transistor M1 can pollute the AC line with switching noise. Therefore, an X capacitor (not shown) is typically coupled between AC source 210 and bridge diode 205 to prevent switching noise from affecting AC source 210. If the switching power converter is decoupled from AC source 210, the X capacitor can be charged with a relatively high voltage. Therefore, it is also routine to monitor whether the switching power converter has been decoupled from AC source 210 so that the X capacitor can discharge accordingly. This monitoring of the AC line voltage can be performed by low-pass filtering a full-wave rectified version of the AC line voltage to better detect zero crossings in the AC voltage cycle. It should be noted that the power factor correction inductor current may resonate at these zero crossings. The on-time (M2_on) of transistor M2 can then be compensated (increased) during the zero crossing so that the power factor correction inductor current increases accordingly, and thus reduces the effect of resonance that would otherwise occur. Now refer to Figure 7Regarding the filtered and rectified AC line voltage 700 monitored by a low-pass filter (e.g., an infinite impulse response (IIR) filter), advantageous compensation for the M2 on-time is shown. For comparison, an unfiltered and rectified AC line voltage 705 is also shown. Controller U1 can monitor the filtered and rectified AC line voltage 700 to determine when the filtered and rectified AC line voltage 700 drops below a first high-to-low threshold voltage (Vac_th1_h21) as it approaches zero crossover time. As the filtered and rectified AC line voltage 700 continues to drop below the first high-to-low threshold voltage, controller U1 can increase the M2 on-time until the filtered and rectified AC line voltage 700 drops below a second high-to-low threshold voltage (VAC_th2_h21). At this point, the M2 on-time remains at this maximum compensation value when passing zero crossover. Then, the filtered and rectified AC line voltage 700 begins to rise until it passes the first low-to-high threshold voltage (Vac_th1_l2h). Then, when the filtered and rectified AC line voltage 700 reaches a second low-to-high threshold voltage (Vac_th2_l2h) that is greater than the first low-to-high threshold voltage, the compensation gradually decreases until it reaches zero.

[0037] The zero-voltage switching control of the power switching transistor M1 can advantageously enhance the switching power converter architecture disclosed herein. Figure 8An example switching power converter 800 with zero-voltage switching is shown. An auxiliary winding P3 is magnetically coupled to the primary winding P1, auxiliary winding P2, and secondary winding S. The auxiliary winding P3 is connected in series with a capacitor Czvs and an auxiliary switching transistor M3. A controller U1 controls the switching of transistor M2, auxiliary switching transistor M3, and power switching transistor M1, although it will be understood that separate controllers for the switching of these transistors can be used in alternative implementations. An advantageous adaptive control method for the switching of auxiliary switching transistor M3 is disclosed in U.S. Patent No. 11,437,916, the contents of which are incorporated herein by reference in their entirety. In a flyback topology, the adaptive control of the on-time (Ton auxflyback) of the auxiliary switching transistor depends on the primary winding magnetizing inductance, the parasitic capacitance of the power switching transistor M1, and the ratio Vin / (N*Vout), where N is the turns ratio. Based on these factors, the dependence of the auxiliary switch turn-on time on the magnetizing inductance and parasitic capacitance can be expressed as Ton aux flyback = A*Trst / Ton*(B*Tring+C), where Trill is the resonant period of the drain voltage of the power switching transistor after transformer reset (Trst), and A, B, and C are coefficients that can be solved using conventional differential equation techniques. There is a dead time (Twdg flyback) between the cyclic turn-off of the auxiliary switching transistor and the turn-on of the power switching transistor M1, which can be expressed as Twdg flyback = (D+E*Tring / Ton auxflyback)*(F*Tring+G), where D, E, and F are also coefficients that can be solved using conventional differential equation techniques. However, these equations apply to zero-voltage switching in flyback topologies. Aside from the additional inductance and capacitance from the power factor correction inductor, transistor M2, diode D2, and winding P2, the control of the auxiliary switching transistor M3 in the switching power converter 800 can follow the same principles as discussed in U.S. Patent No. 11,437,916. However, such factors can be addressed using appropriate scaling constants (coefficients) and configurable offsets (such as via programmable resistors). Therefore, the on-time (Ton auxiliary SEPIC) of the auxiliary switching transistor M3 can be expressed as Ton auxiliary SEPIC = (Tonaux flyback) * coefficient + offset.Similarly, the dead time (Twdg SEPIC) between the cyclic turn-off of auxiliary switching transistor M3 and the cyclic turn-on of power switching transistor M1 can be expressed as Twdg SEPIC = (Twdg flyback) * coefficient + offset (it should be noted that the coefficient and offset used to calculate Ton auxiliary SEPIC can be independent of the coefficient and offset used to calculate Twdg SEPIC, or they can be the same depending on the implementation). Using the resulting zero-voltage switching control of power switching transistor M1, the cyclic losses from transistor M2 and the switching losses from power switching transistor M1 can be advantageously reduced.

[0038] Referring again to the rectified AC input voltage, the switching power converter 800 includes a pair of diodes D6 and D5 for its rectification. A low-pass filter 805 (which can be incorporated into the controller U1) low-pass filters the resulting rectified AC input voltage to produce a filtered and rectified AC input voltage. The controller U1 processes this filtered and rectified AC input voltage to determine whether low-to-high threshold voltages Vac_th1_h21 and Vac_th2_h21 are satisfied as the filtered and rectified AC input voltage decreases toward a zero crossover. Similarly, the controller U1 can process the filtered and rectified AC input voltage to determine whether low-to-high threshold voltages Vac_th1_12h and Vac_th2_12h are satisfied as the filtered and rectified AC input voltage increases after a zero crossover. Based on these threshold voltages, the controller U1 can then compensate for the on-time of transistor M2, as per [reference to...]. Figure 7 The subject of discussion.

[0039] Referring again to the switching power converter 200, it should be noted that the peak current conducted through the sense resistor Rsense is a combination of the peak primary winding current and the current conducted by the power factor correction inductor. This same combination occurs in the switching power converter 300 when transistor M2 cycles on while power switching transistor M1 is on. Conventional control methods for the cycling of power switching transistor M1 in flyback topologies assume that the peak current conducted by the sense resistor Rsense is the same as the peak primary winding current. However, this is no longer true in the SEPIC 200 and SEPIC 300. Figure 9 The SEPIC switching power converter 900 is illustrated, in which the contribution of the power factor correction inductor current to the peak current sensed at the sensing resistor Rsense can be determined by a current sensor. In the SEPIC 900, a current sensing transformer T1 is used to sense the power factor correction inductor current, but it will be understood that other types of current sensors, such as Hall effect sensors, can be used in alternative implementations. Figure 9For clarity, the AC input source and bridge rectifier are not shown, but they will be arranged as discussed for the switching power converter 200 to drive input node 915 with the rectified input voltage Vin. A power factor correction inductor (LPFC) is coupled between input node 915 (which can also be represented as the output node of a diode bridge) and the first winding N3 of current sensing transformer T1. Winding N3 is further coupled to the anode of diode D2, which has a cathode coupled to the drain of power switching transistor Q1 via auxiliary winding P2. A large-capacity capacitor, secondary winding W2, output diode D3 (not shown), and output capacitor Cout (not shown) are arranged as discussed for the switching power converter 200. Alternatively, the output diode D3 can be replaced by a synchronous rectifier switch.

[0040] The current through the second winding N4 of the current-sensing transformer T1 is rectified by diode D5, which has an anode coupled to ground and a cathode coupled to the first terminal of winding N4. The second terminal of winding N4 is grounded through resistor R1. The current Ict conducted through winding N4 is equal to the turns ratio N4 / N3 multiplied by the power factor correction inductor current (IPFC), such that Ict equals (N4 / N3)*IPFC, which is equal to Nct*IPFC (Nct equals the turns ratio N4 / N3). The voltage at the second terminal of winding N4 is equal to the product of the current Ict and the resistance of resistor R1. This voltage across resistor R1 is divided by a voltage divider formed by the series combination of resistors R2 and R3 to form a current-sensing voltage (Vcs_PFC), which is equal to the ratio R3 / (R2+R3) multiplied by the voltage across resistor R1 Ict*R1. Therefore, the current sensing voltage Vcs_PFC is proportional to the power factor correction inductor current IPFC through a proportionality constant Kr equal to R1*R3*Nct / (R2+R3).

[0041] Therefore, controller U1 can use any suitable conventional control algorithm to control the cycling of power switching transistor M1 by sensing the voltage of the sense resistor Rsense, subtracting the contribution of the peak power factor correction inductor current sensed by the current sense voltage Vcs_PFC, and obtaining the current IPFC by dividing the current sense voltage Vcs_PFC by the proportionality constant Kr. The resulting control of the SEPIC switching power converter 900 is very advantageous. For example, if the input voltage Vin at input node 915 is always lower than the voltage Vbulk on the large-capacity capacitor Vbulk, the constant current mode CCM can be eliminated. In addition, the drain-source voltage (Vds) spikes of the power switching transistor are advantageously controlled.

[0042] Now about Figure 10The flowchart discusses the operation of the SEPIC switching power converter 900. This method includes action 1000: turning on a power switching transistor to magnetize the primary winding of a power factor correction inductor and a transformer, causing a power factor correction current to conduct through the power factor correction inductor, a primary winding current to conduct through the primary winding, and a combined current equal to the sum of the power factor correction current and the primary winding current to conduct through the power switching transistor. The conduction of power switching transistor M1 in the SEPIC switching power converter 900, resulting in a combined current conducting through power switching transistor M1 (and thus through the sensing resistor Rsense), is an example of action 1000. The method also includes action 1005, which involves sensing the power factor correction current via a current sensor coupled to the power factor correction inductor to provide a power factor correction current measurement. Sensing the power factor correction current through a current sensing transformer T1 is an example of action 1005, but it should be noted that a Hall effect sensor or another suitable current sensor can be used to perform action 1005. The method also includes action 1010, which involves sensing the combined current to provide a combined current measurement. Sensing the voltage across the sensing resistor is an example of action 1010. Finally, the method includes action 1015: subtracting the power factor correction measurement from the combined current measurement to provide a primary winding current measurement, wherein the power switching transistor is turned off in response to the primary winding current measurement being equal to the peak primary winding current threshold. Subtraction via controller U1 in the SEPIC converter 900 is an example of action 1015.

[0043] Those skilled in the art will now recognize that many modifications, substitutions, and variations can be made to the materials, apparatus, configuration, and methods of use of the devices of this disclosure without departing from the scope of this disclosure. Therefore, the scope of this disclosure should not be limited to the specific embodiments described herein, as they are merely examples, but should be fully proportionate to the scope of the appended claims and their functional equivalents.

Claims

1. An isolated switching power converter, comprising: Input node, which is used to receive rectified input voltage from AC power supply; A transformer comprising a first primary winding having a first terminal coupled to the input node; A power switching transistor coupled to the second terminal of the primary winding; as well as A power factor correction inductor is coupled between the input node and the second terminal of the first primary winding.

2. The isolated switching power converter according to claim 1, further comprising: A first diode has an anode coupled to the input node and a cathode coupled to a first terminal of the primary winding; as well as The second diode has an anode coupled to the power factor correction inductor and a cathode coupled to a second terminal of the primary winding.

3. The isolated switching power converter according to claim 1, further comprising: A large-capacity capacitor is coupled between the first terminal of the primary winding and ground.

4. The isolated switching power converter according to claim 3, wherein, The transformer includes a second primary winding coupled between the power factor correction inductor and the power switching transistor.

5. The isolated switching power converter according to claim 4, further comprising: A power factor correction inductor transistor coupled between the power factor correction inductor and the primary side ground.

6. The isolated switching power converter according to claim 1, wherein, The transformer further includes a secondary winding, and the switching power converter further includes: An output diode having an anode coupled to a first terminal of the secondary winding; and An output capacitor is coupled between the secondary-side ground and the cathode of the output diode.

7. A method for an isolated switching power converter, comprising: Turn on the power switching transistor to magnetize the power factor correction primary winding of inductors and transformers; as well as In response to turning off the power switching transistor, the power factor correction inductor is demagnetized to conduct a demagnetizing current from the power factor correction inductor and through the primary winding to charge the large-capacity capacitor.

8. The isolated switching power converter method according to claim 7, wherein, The power switching transistor is turned on during its on-time, and the method further includes: The power factor correction inductor transistor coupled between the power factor correction inductor and ground is turned on for at least a portion of the power switching transistor's on-time.

9. The isolated switching power converter method according to claim 8, wherein, The power factor correction inductor transistor is turned on substantially simultaneously with the power switching transistor.

10. The isolated switching power converter method according to claim 8, further comprising: The power factor correction inductor transistor is turned off substantially simultaneously with the power switch transistor.

11. The isolated switching power converter method according to claim 8, further comprising: Determine whether the voltage of the large-capacity capacitor of the switching power converter exceeds the overvoltage threshold voltage; as well as In response to the large-capacity capacitor voltage exceeding the overvoltage threshold voltage, the cycling of the power factor correction inductor transistor is suppressed.

12. The isolated switching power converter method according to claim 11, further comprising: In response to the large-capacity capacitor voltage exceeding the adjustment threshold voltage while being less than the overvoltage threshold voltage, the on-time of the power factor correction inductor transistor is reduced.

13. The isolated switching power converter method according to claim 7, further comprising: Before the power switching transistor is turned on, an auxiliary switching transistor is turned on during the on-time. This auxiliary switching transistor is coupled to the auxiliary winding of the transformer and to a zero-voltage switching capacitor for the auxiliary switching transistor, wherein when the power switching transistor is turned on, there is essentially zero voltage across the power switching transistor.

14. The isolated switching power converter method according to claim 8, further comprising: The rectified AC input voltage is filtered to produce a filtered and rectified AC input voltage. When the filtered and rectified AC input voltage decreases toward zero crossing, the on-time of the power factor correction inductor transistor is increased in response to the filtered and rectified AC input voltage falling below a first threshold voltage. as well as After the filtered and rectified AC input voltage increases beyond the zero crossover, in response to the filtered and rectified AC input voltage rising above the second threshold voltage, the on-time of the power factor correction inductor transistor is reduced.

15. The isolated switching power converter method according to claim 7, wherein, Turning on the power switching transistor to magnetize the power factor correction inductor and the primary winding of the transformer includes conducting a power factor correction current through the power factor correction inductor, conducting a primary winding current through the primary winding, and conducting a combined current equal to the sum of the power factor correction current and the primary winding current through the power switching transistor, the method further comprising: The power factor correction current is sensed through a current sensor coupled to the power factor correction inductor to provide a power factor correction current measurement. Sensing the combined current to provide a combined current measurement; and The power factor correction current measurement is subtracted from the combined current measurement to provide a primary winding current measurement, wherein the power switching transistor is turned off in response to the primary winding current measurement being equal to a peak primary winding current threshold.

16. The isolated switching power converter method according to claim 15, wherein, Sensing the combined current includes sensing the voltage across a sensing resistor connected in series with the power switching transistor.

17. An isolated SEPIC converter, comprising: Input node, which is used to receive the rectified input voltage; The main transformer includes a first primary winding having a first terminal coupled to the input node; A power switching transistor coupled to the second terminal of the primary winding; A current-sensing resistor is coupled between ground and the power switching transistor; A power factor correction inductor is coupled between the input node and the drain of the power switching transistor; A current sensor is configured to sense the power factor correction current conducted by the power factor correction inductor to provide a power factor correction current measurement. as well as A controller is configured to sense the voltage across the current sensing resistor to determine the combined current conducted by the power switching transistor, and the controller is also configured to subtract the power factor correction current measurement from the combined current to determine the primary winding current conducted by the first primary winding.

18. The isolated SEPIC converter of claim 17, further comprising: First diode; as well as An auxiliary winding, coupled between the cathode of the first diode and the drain of the power switching transistor, wherein the current sensor includes: A current sensing transformer having a primary winding coupled between the input node and the anode of the first diode; A first resistor, which is connected in series with the secondary winding of the current sensing transformer; and A voltage divider is used to divide the voltage across the first resistor to provide a voltage division, wherein the controller is also configured to sense the power factor correction current by sensing the voltage division.

19. The isolated SEPIC converter of claim 18, further comprising: The second diode is configured to rectify the current conducted by the secondary winding of the current sensing transformer.

20. The isolated SEPIC converter of claim 19, further comprising: A third diode has an anode coupled to the input node and a cathode coupled to the primary winding; as well as A large-capacity capacitor is coupled between the first terminal of the primary winding and ground.

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