Anti-cracking structure of multi-layer substrate

Abstract

The present application provides a kind of anti-cracking structure for preventing the cracking of slit portion and mounting hole formed in multilayer substrate.The anti-cracking structure of slit (110) formed in FPC substrate (100) with multilayer structure includes conductor pattern (120A, 120B) formed close to the base (112) of slit (110), and the conductor pattern (120A, 120B) is formed in all layers of wiring layer (W1, W2, W3, W4) of FPC substrate (100).Therefore, compared with the anti-cracking structure of the prior art, the strength of anti-cracking can be improved.

Description

Technical Field

[0001] This invention relates to a multilayer substrate having multiple wiring layers stacked with an insulating layer between them, and particularly to a crack-resistant structure consisting of grooves and mounting holes formed on the multilayer substrate. Background Technology

[0002] Micro-LEDs capable of directly displaying images from light-emitting diodes have been developed, and the mounting of micro-LEDs on flexible film types has been investigated. As a substrate for the film type, slit holes or similar features are formed on a representative flexible printed circuit board (hereinafter referred to as an FPC substrate) to facilitate bending or to mount the substrate. For example, Patent Document 1 discloses an FPC substrate in which a reinforcing conductor pattern is formed in the groove portion to prevent damage to the wiring pattern even when cracking occurs.

[0003] Existing technical documents Patent documents Patent Document 1: Japanese Patent Application Publication No. 2010-74101 Summary of the Invention

[0004] The problem that the invention aims to solve The film substrate mainly uses insulating layers such as PI (polyimide), PET (polyethylene terephthalate) or PC (polycarbonate) with a thickness of less than 100μm. The FPC substrate is made by stacking a conductor layer on such an insulating layer.

[0005] Figure 1 This illustrates an example of a conventional FPC substrate. As described above, the FPC has a slit 12 formed on the substrate 10 to facilitate bending. The planar shape of the slit portion is not rectangular but has a circle or radius (R). As disclosed in Patent Document 1, a circular conductor pattern 20 for reinforcement is formed close to the base of the slit 12. Such a method is generally used as a construction to prevent cracking of the slit portion, but the following problems exist.

[0006] 1. The slit section is prone to breaking off from its base due to stretching or snagging.

[0007] 2. As disclosed in Patent Document 1, even if an arc-shaped or U-shaped reinforcing conductor pattern 20 is provided to make it difficult to break in the slit portion, its effect is weaker in a single conductor pattern 20.

[0008] 3. When the conductor pattern 20 used for slit and crack reinforcement is a movable part, the conductor pattern 20 is more prone to cracking than the membrane material due to bending.

[0009] 4. Cracks develop from the slit portion, and when they reach the reinforcing conductor pattern 20, the FPC substrate is prone to breakage.

[0010] The purpose of this invention is to solve such conventional problems and provide a crack-resistant structure for multilayer substrates with higher strength than conventional ones.

[0011] Methods for solving problems The anti-cracking structure of the present invention is an anti-cracking structure of a multilayer substrate having multiple wiring layers stacked with an insulating layer between them. The anti-cracking structure includes an anti-cracking conductor pattern formed close to a slit or hole formed in the multilayer substrate. The conductor pattern is formed in at least two wiring layers of the multilayer substrate.

[0012] Invention Effects According to the present invention, since a conductor pattern for crack prevention is formed on at least two wiring layers, the strength of the crack prevention structure can be improved compared with the past. Attached Figure Description

[0013] Figure 1 This is a schematic plan view illustrating a slit portion formed on an existing FPC substrate and a reinforcing conductor pattern.

[0014] Figure 2 (A) is a schematic top view of the FPC substrate according to the first embodiment of the present invention. Figure 2 (B) is its schematic cross-sectional view.

[0015] Figure 3 This diagram shows a conventional FPC substrate used as a comparative example. Figure 3 (A) is a schematic top view of the FPC substrate. Figure 3 (B) is a schematic cross-sectional view of its AA line.

[0016] Figure 4 (A) is a schematic top view of the FPC substrate according to the second embodiment of the present invention. Figure 4 (B) is its schematic cross-sectional view.

[0017] Figure 5 (A) is a schematic top view of the FPC substrate according to the third embodiment of the present invention. Figure 5 (B) is its schematic cross-sectional view.

[0018] Figure 6 (A) is a schematic top view of the FPC substrate according to the fourth embodiment of the present invention. Figure 6 (B) is its schematic cross-sectional view.

[0019] Figure 7 (A) is a schematic top view of the FPC substrate according to the fifth embodiment of the present invention. Figure 7 (B) is its schematic cross-sectional view.

[0020] Figure 8(A) is a schematic top view of the FPC substrate according to the sixth embodiment of the present invention. Figure 8 (B) is its schematic cross-sectional view.

[0021] Figure 9 (A) and (B) are schematic top views of the FPC substrate according to the seventh embodiment of the present invention. Figure 9 (C) is its schematic cross-sectional view.

[0022] Symbol Explanation 100~100F: FPC substrate 110 narrow slit 112 base 120A, 120B, 120C, 120D conductor patterns Insulation layers 130, 132, 134, 136, and 138 140 through hole 200 round holes 210A and 210B conductor patterns Detailed Implementation

[0023] This invention relates to a multilayer substrate with multiple wiring layers stacked between insulating layers, and particularly to a crack-resistant structure consisting of slits or mounting holes formed on a flexible multilayer substrate. Light-emitting elements such as micro LEDs, circuit elements, semiconductor packages, etc., are mounted on the multilayer substrate. It should be noted that the accompanying drawings referenced in the following description include exaggerated displays for ease of understanding of the invention and do not directly represent the shape or proportions of actual products.

[0024] [Example] Figure 2 (A) is a schematic top view of the FPC substrate according to the first embodiment of the present invention. Figure 2 (B) is a schematic cross-sectional view of its AA line. For example... Figure 2 As shown in (A), a slit 110 is formed at the location of the FPC substrate 100. The slit 110 has, for example, an elongated shape, which imparts flexibility to the FPC substrate 100, allowing the FPC substrate 100 to be bent through the slit 110. The position, number, shape, size, etc., of the slits 110 formed on the substrate 100 are arbitrary and not particularly limited.

[0025] The base 112 of the slit 110 has a circular or R-shaped planar shape. Additionally, two conductor patterns 120A and 120B for crack prevention are formed near the base 112 of the slit 110. Conductor pattern 120A is closer to the base 112, and conductor pattern 120B is further away. Conductor pattern 120B is formed at a certain distance from conductor pattern 120A. Conductor pattern 120A does not necessarily need to have the same shape as conductor pattern 120B, but both have an arcuate or curved shape that mimics the circular or R-shaped shape of the base 112 of the slit 110.

[0026] FPC such as Figure 2 As shown in (B), the substrate 100 has a multilayer structure with multiple wiring layers stacked between insulating layers. The example in the figure shows a multilayer structure including four wiring layers W1, W2, W3, and W4, and five insulating layers 130 and 132 formed above and below these layers. Figure 2 In the cross-sectional view of (B), for ease of explanation, the wiring layers are shown in the gap between the insulation layer and the insulation layer. However, it should be noted that in reality, the layers of the insulation layer are sealed together by means of adhesive.

[0027] In this embodiment, the two conductor patterns 120A and 120B used for crack prevention are formed at the same location in each of the wiring layers W1, W2, W3, and W4 of the multilayer structure (the distance from the base of the slit is constant). The two conductor patterns 120A and 120B are formed simultaneously, for example, when the wiring layers W1, W2, W3, and W4 are formed.

[0028] The manufacturing method of the FPC substrate is not particularly limited. For example, a base film layer 130 is prepared on which wiring layers W2 and W3 are formed on the top and bottom. The base film 130 is, for example, a flexible film such as polyimide or a transparent film with light transmittance. In addition, on the top and bottom surfaces of the base film 130, as wiring layers W2 and W3, a conductor film such as copper foil is formed over the entire surface, for example. Such a conductor film is patterned using a subtractive etching process to form wiring patterns on the wiring layers W2 and W3. When forming the wiring pattern, the conductor film is simultaneously patterned with residual conductor patterns 120A and 120B for preventing cracking.

[0029] Next, a cover layer (insulating layer) 132, on which the wiring layer W1 is formed, and a cover layer (insulating layer) 134, on which the wiring layer W4 is formed, are bonded together above and below the base film layer 130 using an adhesive. While the wiring patterns are formed on the wiring layers W1 and W4, conductor patterns 120A and 120B for crack prevention are simultaneously formed. Next, the cover layer (insulating layer) 136 is bonded together with an adhesive to cover the wiring layer W1, and the cover layer (insulating layer) 138 is bonded together with an adhesive to cover the wiring layer W4.

[0030] Figure 3 (A) is a schematic top view of a conventional FPC substrate. Figure 3 (B) is a schematic cross-sectional view of its AA line, with the same reference numerals used for structures identical to those in the first embodiment. In the conventional FPC substrate 10, a crack-resistant conductor pattern 120A is formed on a wiring layer W1. In contrast, in this embodiment, the crack-resistant conductor patterns 120A and 120B are formed on all layers of wiring layers W1 to W4, thus improving the crack-resistant strength compared to conventional crack-resistant structures.

[0031] Next, a second embodiment of the present invention will be described. Figure 4 (A) is a schematic top view of the FPC substrate of the second embodiment. Figure 4 (B) is a schematic cross-sectional view thereof, with the same reference numerals used for structures identical to those in the first embodiment. In the second embodiment, unlike the first embodiment, a single anti-cracking conductor pattern 120A is formed at the same location in each of the wiring layers W1, W2, W3, and W4 of the FPC substrate 100A.

[0032] According to the second embodiment, when the circuit pattern is dense and the space for forming the conductor pattern for crack prevention is limited, by setting the conductor pattern 120A in the same location of all wiring layers, a strong structure that prevents cracking from both the surface and back of the substrate can be provided.

[0033] Next, the third embodiment of the present invention will be described. Figure 5 (A) is a schematic top view of the FPC substrate of the third embodiment. Figure 5 (B) is a schematic cross-sectional view thereof, with the same reference numerals used for structures identical to those in the first embodiment. In the third embodiment, unlike the first and second embodiments, single anti-cracking conductor patterns 120A, 120B, 120C, and 120D are formed on each wiring layer W1, W2, W3, and W4 of the FPC substrate 100B at positions gradually moving away from the base 112 of the slit 110. The conductor patterns 120A, 120B, 120C, and 120D can all be of the same shape, or they can decrease in size as they move away from the base 112 of the slit 110.

[0034] According to the third embodiment, by changing the position of the anti-cracking conductor patterns 120A, 120B, 120C, and 120D for each wiring layer, it is possible to provide a structure that prevents sudden avoidance from the slit portion when stress is applied to the FPC substrate 100B.

[0035] Next, the fourth embodiment of the present invention will be described. Figure 6 (A) is a schematic top view of the FPC substrate of the fourth embodiment. Figure 6(B) is a schematic cross-sectional view. In the FPC substrate 100C of the fourth embodiment, a through-hole 140 is formed between conductor patterns 120A and 120B. The through-hole 140 is formed at the same location on the base film 130 and the capping layers 132, 134, 136, and 138. The planar shape of the through-hole 140 is not particularly limited, but it is preferable to have an arc shape that mimics the planar shape of conductor patterns 120A and 120B.

[0036] According to the fourth embodiment, by forming a through hole 140 throughout the insulating layer between the two conductor patterns 120A and 120B, even if part (A) of the slit 110 cracks, the development of cracking can be suppressed by the through hole 140, and the crack-resistant structure of part (B) can be maintained.

[0037] Next, the fifth embodiment of the present invention will be described. Figure 7 (A) is a schematic top view of the FPC substrate of the fifth embodiment. Figure 7 (B) is a schematic cross-sectional view thereof, with the same reference numerals used for structures identical to those in the fourth embodiment. In the fifth embodiment, through holes 140 are formed in the base film 130 and the capping layers 136 and 138, but unlike the fourth embodiment, through holes 140 are not formed in the capping layers 132 and 134.

[0038] According to the fifth embodiment, a structure can be provided that prevents cracking from the outermost layer of the back surface of the FPC substrate 100D and gives the substrate elasticity. The position and layers of the through-hole 140 can be arbitrarily set according to the thickness of the base film, the cover layer, the number of insulating layers, etc. For example, the through-hole may not be formed in the base film, but in the cover layers 136 and 138, or the through-hole may be formed only in the base film.

[0039] Next, the sixth embodiment of the present invention will be described. Figure 8 (A) is a schematic top view of the FPC substrate of the sixth embodiment. Figure 8 (B) is a schematic cross-sectional view thereof. In the sixth embodiment, the conductor pattern for crack prevention is also used as an alignment mark when bonding the insulating layer (cover layer). In the case of a multilayer substrate, alignment marks for bonding the insulating layer are usually provided in the working area outside the substrate, but in this embodiment, a structure is provided in which the conductor pattern for crack prevention is also used as an alignment mark, and the alignment mark is provided inside the substrate.

[0040] Wiring layer W1 is formed on cover layer 132, and wiring layer W4 is formed on cover layer 134, and they are bonded to base film 130. For example, the conductor pattern 120A of wiring layer W2 formed on base film 130 is used as an alignment mark for bonding pattern 120A formed on cover layer 134. In addition, the conductor pattern 120C of wiring layer W2 formed on base film 130 is used as an alignment mark for bonding pattern 120C formed on cover layer 132.

[0041] Thus, according to this embodiment, by using the conductor pattern as an alignment mark, the process of forming alignment marks in the working area outside the substrate can be eliminated, preventing cracking of the FPC substrate and simplifying the manufacturing process of the FPC substrate.

[0042] Next, the seventh embodiment of the present invention will be described. Figure 9 (A) and (B) are schematic top views of the FPC substrate of the seventh embodiment. Figure 9 (C) is a schematic cross-sectional view thereof. In the first to sixth embodiments, anti-cracking structures for the slit portion are illustrated, but in the seventh embodiment, anti-cracking structures for mounting circular holes and elliptical holes formed on the FPC substrate are illustrated.

[0043] like Figure 9 As shown in (A), a circular hole 200 for mounting the FPC substrate 100F to a housing or the like is formed. For example, the FPC substrate 100F is fixed to the housing, casing, or the like by screws inserted into the circular hole 200.

[0044] In the FPC substrate 100F of this embodiment, two concentric circular conductor patterns 210A and 210B are formed on the outer periphery of the circular hole 200. The two conductor patterns 210A and 210B are formed on all layers of wiring layers W1, W2, W3, and W4 in the same manner as in the first embodiment.

[0045] In addition, Figure 9 In the example shown in (B), the inner conductor pattern 210A is not a continuous pattern, but is composed of four separate arc-shaped patterns. Similarly, the outer conductor pattern 210B is also not a continuous pattern, but is composed of four separate arc-shaped patterns. Furthermore, the separated portions of the inner conductor pattern 210A and the outer conductor pattern 210B are not aligned radially; that is, the separated portions of conductor pattern 210A are covered by the pattern of conductor pattern 210B. Therefore, the entire omnidirectional area of ​​the hole 200 is substantially covered by conductor patterns 210A and 210B, making it difficult for cracks to develop.

[0046] The conductor patterns 210A and 210B are not limited to those described above. For example, as in the second embodiment, either conductor pattern 210A or 210B can be formed at the same location in wiring layers W1, W2, W3, and W4. Alternatively, as in the third embodiment, the position of conductor patterns 210A / 210B can be changed for each of the wiring layers W1, W2, W3, and W4. Furthermore, the widths of conductor patterns 210A and 210B do not necessarily have to be the same; one can be larger than the other. Regarding elliptical holes, although not illustrated here, similar to the circular hole 200, elliptical conductor patterns mimicking the shape of an elliptical hole can be formed in all layers of the wiring layers.

[0047] In the above embodiments, an FPC substrate with wiring layers W1 to W4 stacked between insulating layers is illustrated. However, the number of stacked wiring layers is arbitrary and can be 5 or more, or 3 or less. Furthermore, the shape of the conductor pattern for preventing cracking can be appropriately determined based on the shape of the slits and holes formed in the multilayer substrate.

[0048] As explained above, this embodiment achieves the following effects.

[0049] 1. It can prevent the base of the slit from easily breaking due to stretching, hooking, etc.

[0050] 2. By setting multiple layers and multiple arch-shaped or U-shaped anti-cracking patterns, it can be made less prone to cracking.

[0051] 3. The slits or anti-cracking patterns are located in the movable parts, so that even if the pattern cracks due to bending, it can prevent further cracking.

[0052] 4. Cracking develops from the outer shape, and even if it reaches the pattern, it can easily continue to crack or prevent breakage.

[0053] The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to specific embodiments. Various modifications and alterations can be made within the scope of the spirit of the invention as described in the claims.

Claims

1. A crack-resistant structure, It is a crack-resistant structure for a multilayer substrate with multiple wiring layers stacked between insulating layers. The anti-cracking structure includes a conductor pattern for anti-cracking formed close to a slit or hole formed in a multilayer substrate. The conductor pattern is formed on at least two wiring layers of the multilayer substrate.

2. The crack-resistant structure according to claim 1, wherein, The conductor pattern is formed in each of the wiring layers.

3. The crack-resistant structure according to claim 1, wherein, The conductor pattern is formed at different locations on each of the multiple wiring layers.

4. The crack-resistant structure according to claim 1, wherein, The conductor patterns are formed separately in multiple ways on the same wiring layer.

5. The crack-resistant structure according to claim 4, wherein, Through holes are formed in the insulating layer between the separated conductor patterns.

6. The crack-resistant structure according to claim 4, wherein, Through holes are formed in all or part of the plurality of insulating layers between the separated conductor patterns.

7. The crack-resistant structure according to claim 1, wherein, The conductor pattern also serves as an alignment mark for bonding the insulating layer.

Images