A dynamic random memory cell and array

Abstract

The application discloses a dynamic random memory unit and array, and belongs to the technical field of semiconductor memory. The application forms a memory unit by using a vertical ring gate write transistor based on an oxide semiconductor and a silicon-based read transistor, and integrates the memory unit into a memory array in a mode of sharing a source area of the read transistor, and the area overhead of the application is about 6F 2 , which effectively reduces the unit area overhead and improves the integration density of the memory array.

Description

Technical Field

[0001] This invention belongs to the field of micro-nano electronics technology, specifically relating to a dynamic random access memory cell and its array based on oxide transistors and silicon transistors. Background Technology

[0002] Oxide-semiconductor (OSB)-based dynamic random access memory (DRAM) effectively addresses the miniaturization challenges faced by traditional DRAM. This cell features a 2TOC structure, consisting of a write transistor and a read transistor. The write transistor utilizes an OSB transistor with extremely low off-state current as the cell's gate transistor, enabling extremely long hold times even when using only the read transistor's gate capacitance as the storage capacitor. Simultaneously, the charge information stored at the read transistor's gate (represented by the read transistor's gate voltage) can be amplified by the read transistor, reflected in its drain current, and read out through the circuit module, avoiding the low read signal problem caused by the traditional DRAM charge-sharing read mechanism. In existing 2TOC structures, the read transistor often uses an OSB transistor, resulting in low read current and slow cell read speed. Furthermore, the simple planar 2TOC integration method will bring 20F... 2 The area overhead is not conducive to the implementation of high-density dynamic random access arrays. Summary of the Invention

[0003] This invention aims to provide a dynamic random access memory (DRAM) cell and array. The invention utilizes a vertical ring gate write transistor based on oxide semiconductors and a silicon-based read transistor to form memory cells, and integrates these cells into a memory array by sharing the read transistor source region. This invention effectively improves the read speed of the cells and reduces the area overhead of the cells.

[0004] The technical solution of the present invention is as follows:

[0005] A dynamic random access memory (DRAM) cell includes a substrate, write transistors, and read transistors. Specifically, a read transistor gate structure is provided on the substrate, the read transistor gate structure being composed of a read transistor gate dielectric layer and a memory node layer stacked from bottom to top. Read transistor source regions and read transistor drain regions are provided on the substrate on both sides of the read transistor gate structure. A read bit line layer is provided above the read transistor drain region; a read word line layer is provided above the read transistor source region; and a signal line stack is provided above the read transistor gate structure, read bit line layer, and read word line layer, the signal line stack consisting of an isolation layer from bottom to top. The system comprises a write bit line layer and an isolation layer stacked together. Vias are etched perpendicularly to the signal line stack, with the vias located above the storage node layer. A write transistor gate structure is filled within these vias, which consists of a write transistor gate dielectric layer enclosing a write transistor active layer from the outside in. A write bit line layer is positioned above the write transistor gate structure. An isolation layer is positioned above the write bit line layer and the signal line stack. Vias are etched perpendicularly to the isolation layer and the signal line stack, with the vias located above the read bit line layer. Read bit line layer material is filled within these vias, and a read bit line layer is positioned above the vias.

[0006] Furthermore, the read word line layer, read bit line layer, write word line layer, and write bit line layer are made of Ti, TiN, Ta, TaN, Al, AlN, W, Cu, Pt, Mo, Ni, ITO, or heavily doped polycrystalline silicon conductor materials.

[0007] Furthermore, the source and drain regions of the read transistor are prepared by doping a silicon substrate with N, P, As, B, Ga, In, or a combination of the above elements.

[0008] Furthermore, the active layer of the write transistor is a single-layer or multi-layer ZnO, IGZO, IAZO, ITO composite oxide semiconductor material thin film.

[0009] Furthermore, the gate dielectric layer of the write transistor and read transistor is composed of a single-layer or multi-layer composite material thin film, including SiO2. x AlO x HfO x TaO x ZrO x wait.

[0010] Furthermore, the storage node layer material is a conductor material or a semiconductor material, including Ti, TiN, Ta, TaN, Al, AlN, W, Cu, Pt, Mo, Ni, ZnO, IGZO, IAZO, ITO, polycrystalline silicon, etc.

[0011] Furthermore, the thickness of the thin film materials for the read transistor active layer, write transistor active layer, gate dielectric layer, and storage node layer is 5nm-1000nm.

[0012] The present invention also provides a dynamic random access memory array, which is composed of periodically arranged basic unit groups. Each basic unit group consists of two dynamic random access memory cells. The two read transistors of each basic unit group are symmetrically distributed and share the same read transistor source region. The basic unit groups are isolated by isolation slots. The read bit lines and write bit lines of all cells in the same column of the array are connected along the column direction of the array. The read word lines and write word lines of all cells in the same row of the array are connected along the row direction of the array.

[0013] The present invention has the following advantages:

[0014] 1. This invention uses silicon-based read transistors, which can improve the read current and read speed of 2T0C structure dynamic random access memory.

[0015] 2. The present invention can use an array integration method with a shared read transistor source region, which can effectively reduce the area overhead of the memory cell and increase the integration density of the memory array. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the dynamic random access memory cell of the present invention, wherein (a) is a front view and (b) is a side view, wherein: 1-substrate; 2-drain region of read transistor; 3-gate dielectric layer of read transistor; 4-read bit line layer; 5-isolation layer; 6-write word line layer; 7-write bit line layer; 8-read word line layer; 9-source region of read transistor; 10-memory node layer; 11-dielectric layer of write transistor; 12-active layer of write transistor;

[0017] Figure 2 This is a circuit diagram of the dynamic random access memory cell of the present invention;

[0018] Figures 3-6 This is a schematic diagram of the operation of the dynamic random access memory (DRAM) cell of the present invention, wherein (a) is a front view and (b) is a side view; Figure 3 This is a schematic diagram of the operation of writing data "1" in this invention; Figure 4 This is a schematic diagram illustrating the storage of data after writing the data "1" in this invention; Figure 5 This is a schematic diagram of the data reading operation "1" of the present invention; Figure 6 This is a schematic diagram illustrating the data reading operation "0" of the present invention;

[0019] Figure 7 This is a top view of the 4×2 array of the present invention; two adjacent memory cells share the source terminal of the read transistor to form a cell group, and the array is composed of the basic cell groups arranged periodically.

[0020] Figure 8 for Figures 1-8 Legend of the diagram. Detailed Implementation

[0021] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0022] It should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the scope of the claims.

[0023] like Figure 1 As shown, the dynamic random access memory (DRAM) cell of the present invention includes a substrate, a write transistor, and a read transistor. Specifically, a DRAM cell includes a substrate, a write transistor, and a read transistor. The structure specifically includes a read transistor gate structure on the substrate, wherein the read transistor gate structure is composed of a read transistor gate dielectric layer and a memory node layer stacked from bottom to top. Read transistor source regions and read transistor drain regions are provided on the substrate on both sides of the read transistor gate structure. A read bit line layer is provided above the read transistor drain region; a read word line layer is provided above the read transistor source region; and a signal layer is provided above the read transistor gate structure, the read bit line layer, and the read word line layer. The signal line stack consists of an isolation layer, a write word line layer, and another isolation layer stacked from bottom to top. Vias are etched vertically into the signal line stack, located above the storage node layer. Write transistor gate structures are filled within these vias, which are composed of a write transistor gate dielectric layer enclosing a write transistor active layer from the outside in. A write bit line layer is positioned above the write transistor gate structure. An isolation layer is positioned above the write bit line layer and the signal line stack. Vias are etched vertically into the isolation layer and the signal line stack, located above the read word line layer. Read word line layer material is filled within these vias, and a read word line layer is positioned above the vias. Figure 2 As shown, the dynamic random access memory cell of the present invention has a 2T0C structure, as follows: Figure 3 As shown, taking writing data "1" as an example, applying a high-level write word line turns on the channel of the write transistor (marked by the dashed box), forming a conductive path between the write bit line and the memory node layer. Current flows from the high-level write bit line through the turned-on read transistor channel to the memory node, positively charging the memory node layer and realizing the operation of writing "1". Figure 4 As shown, after the write operation of data "1" is completed, the write word line voltage is pulled low, the write transistor is turned off, and the conductive path between the write bit line and the memory node layer is closed. No current can be generated between the memory node layer and the write word line, allowing positive charges to be stored in the capacitance formed by the memory node layer, thus achieving information storage. Figure 5 As shown, if the storage voltage is high (storing data "1"), when a voltage is applied between the read bit line and the read word line, the active layer of the read transistor will form a conductive path at the dashed box, and current will flow through the read bit line. For example... Figure 6As shown, if the storage voltage is low (storing data "0"), when a voltage is applied between the read bit line and the read word line, no conductive path will be formed at the dashed box, and there will be no current in the read bit line; the magnitude of the current on the read bit line indicates the voltage stored in the cell, and reading this current will enable the information to be read out.

[0024] like Figure 7 As shown, the present invention also provides a dynamic random access memory (DRAM) array, in which two adjacent memory cells form a basic cell group. Within each basic cell group, two read transistors are symmetrically distributed and share the same read transistor source region. The basic cell groups are isolated by isolation trenches. The array is composed of periodically arranged basic cell groups. The read bit lines and write bit lines of all cells in the same column of the array are connected along the column direction; the read word lines and write word lines of all cells in the same row of the array are connected along the row direction.

[0025] The area overhead of this invention is approximately 6F. 2 Where F is the process feature dimension, which is the area occupied by the traditional 2T0C planar unit, 20F. 2 Compared to other methods, this significantly reduces area overhead and increases array integration density.

[0026] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the scope of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A dynamic random access memory cell, comprising a substrate, a write transistor, and a read transistor, characterized in that, A read transistor gate structure is provided on the substrate. The read transistor gate structure is composed of a read transistor gate dielectric layer and a storage node layer stacked from bottom to top. Read transistor source regions and read transistor drain regions are provided on the substrate on both sides of the read transistor gate structure. A read bit line layer is provided above the read transistor drain region. A read word line layer is provided above the read transistor source region. A signal line stack is provided above the read transistor gate structure, read bit line layer, and read word line layer. This signal line stack is composed of an isolation layer, a write word line layer, and an isolation layer stacked from bottom to top. A via is etched vertically in the stacked layers. The via is located above the storage node layer. A write transistor gate structure is filled within the via. The write transistor gate structure consists of a write transistor gate dielectric layer surrounding a write transistor active layer from the outside in. A write bit line layer is provided above the write transistor gate structure. An isolation layer is provided above the stacked layers of write bit lines and signal lines. A via is etched vertically in the stacked layers of isolation and signal lines. The via is located above the read word line layer. The via is filled with read word line layer material. A read word line layer is provided above the via.

2. The dynamic random access memory unit as described in claim 1, characterized in that, The materials of the read line layer, read bit line layer, write line layer, and write bit line layer are Ti, TiN, Ta, TaN, Al, AlN, W, Cu, Pt, Mo, Ni, ITO, and heavily doped polycrystalline silicon conductor materials.

3. The dynamic random access memory unit as described in claim 1, characterized in that, The source and drain regions of the read transistor are silicon substrates doped with N, P, As, B, Ga, In, or a combination of the above elements.

4. The dynamic random access memory unit as described in claim 1, characterized in that, The active layer of the write transistor is a single-layer or multi-layer ZnO, IGZO, IAZO, or ITO composite oxide semiconductor material thin film.

5. The dynamic random access memory unit as described in claim 1, characterized in that, The write transistor gate dielectric layer and the read transistor gate dielectric layer are composed of a single layer or multiple layers of SiO2. x AlO x HfO x TaO x ZrO x Composite material thin films.

6. The dynamic random access memory unit as described in claim 1, characterized in that, The storage node layer material is Ti, TiN, Ta, TaN, Al, AlN, W, Cu, Pt, Mo, Ni, ZnO, IGZO, IAZO, ITO, or polycrystalline silicon.

7. The dynamic random access memory unit as described in claim 1, characterized in that, The thickness range of the thin films of the read transistor active layer, write transistor active layer, gate dielectric layer, and storage node layer is 5nm-1000nm.

8. A dynamic random access memory array, characterized in that, The array is composed of periodically arranged basic unit groups, each basic unit group consisting of two dynamic random access memory (DRAM) cells as described in claim 1. The two read transistors of the basic unit group are symmetrically distributed and share the same read transistor source region. The basic unit groups are isolated by isolation slots. The read bit lines and write bit lines of all cells in the same column of the array are connected along the column direction of the array; the read word lines and write word lines of all cells in the same row of the array are connected along the row direction of the array.

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