Semiconductor device

Abstract

Disclosed is a semiconductor device. The semiconductor device includes: a substrate; a plurality of semiconductor patterns on the substrate and extending in a first direction parallel to an upper surface of the substrate, wherein the plurality of semiconductor patterns are spaced apart in a third direction perpendicular to the upper surface of the substrate; a bit line extending in the third direction and electrically connected to a first end of each of the plurality of semiconductor patterns, a plurality of word lines on the plurality of semiconductor patterns and extending in a second direction parallel to the upper surface of the substrate, wherein the second direction intersects the first direction; a plurality of first electrodes extending in the first direction and spaced apart in the third direction, wherein each of the plurality of first electrodes has a first end electrically connected to a second end of a corresponding semiconductor pattern of the plurality of semiconductor patterns; and a support extending in the third direction and covering the second end of each of the plurality of first electrodes.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0194666, filed with the Korean Intellectual Property Office on December 23, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor devices. Background Technology

[0003] Technologies are being developed to increase the integration density of semiconductor devices. For two-dimensional semiconductor memory devices, integration density is primarily determined by the area occupied by a single memory cell, and this aspect of integration density can be affected by the level of fine patterning technology.

[0004] However, the integration density of two-dimensional semiconductor devices is constantly increasing but still limited due to the expensive equipment required for fine patterning techniques. Therefore, three-dimensional semiconductor devices with memory cells arranged in three dimensions have been proposed. Summary of the Invention

[0005] Some aspects of this disclosure provide semiconductor devices with improved reliability.

[0006] Some aspects of this disclosure provide semiconductor devices that exhibit reduced structural deformation.

[0007] A semiconductor device according to some embodiments of the present disclosure includes: a substrate; a plurality of semiconductor patterns extending on the substrate in a first direction parallel to an upper surface of the substrate, wherein the plurality of semiconductor patterns are spaced apart in a third direction perpendicular to the upper surface of the substrate; bit lines extending in a third direction and electrically connected to a first end of each of the plurality of semiconductor patterns; a plurality of word lines extending on the plurality of semiconductor patterns in a second direction parallel to the upper surface of the substrate, wherein the second direction intersects the first direction; a plurality of first electrodes extending in the first direction and spaced apart in a third direction, wherein each of the plurality of first electrodes has a first end electrically connected to a second end of a corresponding semiconductor pattern in the plurality of semiconductor patterns; and a support extending in a third direction and covering the second end of each of the plurality of first electrodes.

[0008] According to some embodiments of this disclosure, a semiconductor device includes: a substrate; a plurality of semiconductor patterns extending on the substrate in a first direction parallel to an upper surface of the substrate, wherein the plurality of semiconductor patterns are spaced apart in a third direction perpendicular to the upper surface of the substrate; bit lines extending in a third direction and electrically connected to a first end of each of the plurality of semiconductor patterns; a plurality of word lines extending on the plurality of semiconductor patterns in a second direction parallel to the upper surface of the substrate, wherein the second direction intersects the first direction; a plurality of first electrodes having a rod shape and extending in the first direction, wherein each of the plurality of first electrodes has a first end electrically connected to a second end of a corresponding semiconductor pattern in the plurality of semiconductor patterns; a support extending in a third direction and contacting a second end of each of the plurality of first electrodes; a second electrode on the plurality of first electrodes and the support; and a dielectric film between the plurality of first electrodes and the second electrode.

[0009] According to some embodiments of this disclosure, a semiconductor device includes: a substrate; a plurality of semiconductor patterns extending on the substrate in a first direction parallel to an upper surface of the substrate, wherein the plurality of semiconductor patterns are spaced apart in a third direction perpendicular to the upper surface of the substrate; bit lines extending in a third direction and electrically connected to a first end of each of the plurality of semiconductor patterns; a plurality of word lines extending on the semiconductor patterns in a second direction parallel to the upper surface of the substrate, wherein the second direction intersects the first direction; a plurality of first electrodes extending in the first direction and having a cylindrical shape with a hollow portion, wherein each of the plurality of first electrodes has a first end electrically connected to a second end of a corresponding semiconductor pattern among the plurality of semiconductor patterns; a support extending in a third direction and covering the second end of each of the plurality of first electrodes; a second electrode on the plurality of first electrodes and the support; and a dielectric film between the plurality of first electrodes and the second electrode. Attached Figure Description

[0010] Figure 1 This is a perspective view schematically illustrating an example of a semiconductor device.

[0011] Figure 2 This is a cross-sectional view of an example of a semiconductor device.

[0012] Figure 3 yes Figure 2 A magnified view of region A.

[0013] Figure 4 This is a plan view of a portion of an example of a semiconductor device.

[0014] Figure 5 This is a side view of a portion of an example of a semiconductor device.

[0015] Figures 6 to 23 This is a diagram illustrating an example of a method for manufacturing a semiconductor device.

[0016] Figure 24 This is a plan view of a portion of an example of a semiconductor device.

[0017] Figure 25 This is a side view of a portion of an example of a semiconductor device.

[0018] Figure 26 This is a plan view of a portion of an example of a semiconductor device.

[0019] Figure 27 This is a side view of a portion of an example of a semiconductor device.

[0020] Figures 28 to 30 This is a side view of a portion of an example of a semiconductor device. Detailed Implementation

[0021] For clarity, parts irrelevant to the description have been omitted, and throughout the specification, the same reference numerals are used for the same or similar components.

[0022] Furthermore, for ease of illustration, the size and thickness of each component shown in the accompanying drawings may be arbitrarily depicted. In the drawings, the thickness of layers, films, plates, regions, etc., may be exaggerated for clarity.

[0023] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly on" another element, there are no intermediate elements present. Furthermore, in the specification, the terms "on" or "above" indicate placement on or below the object portion, and do not necessarily indicate placement on the upper side of the object portion based on the direction of gravity.

[0024] Furthermore, unless explicitly stated otherwise, the words “include” and their variations shall be understood to imply inclusion of the stated elements but not exclusion of any other elements.

[0025] Furthermore, throughout the instruction manual, the phrase "in a plan view" or "on a plane" indicates viewing a portion of the object from the top, and the phrase "in a sectional view" or "on a section" indicates viewing a section formed by vertically cutting the portion of the object from the side.

[0026] Figure 1 This is a perspective view schematically illustrating an example of a semiconductor device. Figure 2 This is a cross-sectional view of a semiconductor device.

[0027] like Figures 1 to 2As shown, the semiconductor device may include a substrate 100, a bit line BL, a semiconductor pattern SP, and a word line WL.

[0028] For ease of explanation, Figure 1 A bit line BL, a word line WL, a semiconductor pattern SP, and a data storage element DS are shown, and one or more insulating layers that may exist are omitted.

[0029] The substrate 100 may be, for example, a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate 100 may have a shape extending in a first direction DR1 and a second direction DR2. Here, the second direction DR2 may be a direction intersecting the first direction DR1. For example, the first direction DR1 and the second direction DR2 may be orthogonal to each other. For example, the first direction DR1 and the second direction DR2 may be directions parallel to the upper surface of the substrate 100 (e.g., a lateral direction). Additional peripheral circuitry, in addition to the peripheral circuitry shown, may be disposed on the substrate 100.

[0030] A bit line BL extending along a third direction DR3 may be disposed on the upper surface of the substrate 100. The bit line BL may have a shape extending along the third direction DR3, which is perpendicular to the upper surface of the substrate 100. Here, the third direction DR3 may be a direction intersecting with the first direction DR1 and the second direction DR2. For example, the second direction DR2 and the third direction DR3 may be orthogonal to each other. The third direction DR3 and the first direction DR1 may be orthogonal to each other. For example, the third direction DR3 may be a direction perpendicular to the upper surface of the substrate 100 (e.g., a vertical direction).

[0031] Bit line BL may include a conductive material. The conductive material may be, for example, a doped semiconductor material (such as doped silicon (doped Si) or doped germanium (doped Ge)), a conductive metal nitride (such as titanium nitride (TiN) or tantalum nitride (TaN)), a metal (such as tungsten (W), titanium (Ti), or tantalum (Ta)), and a metal semiconductor compound (such as tungsten silicide (WSi)). x ), cobalt silicide (CoSi) x ) or titanium silicide (TiSi) x One of them.

[0032] exist Figure 1 and Figure 2 In this configuration, a bit line BL is arranged on the substrate 100, but the number of bit lines BL is not limited to this. For example, multiple bit lines BL can be arranged on the substrate 100 at intervals from each other in the first direction DR1 and the second direction DR2.

[0033] A semiconductor pattern SP may be disposed on a substrate 100. The semiconductor pattern SP may have a shape extending in a first direction DR1. For example, the semiconductor pattern SP may have a strip shape extending in the first direction DR1.

[0034] A semiconductor pattern SP may be connected (e.g., electrically connected) to a bit line BL. One end of the semiconductor pattern SP may be connected to (e.g., in contact with) the bit line BL. The semiconductor pattern SP may be arranged to penetrate the first insulating layer 210. For example, one end of the semiconductor pattern SP may be covered by the bit line BL. However, the relative arrangement is not limited to this. For example, one end of the semiconductor pattern SP may be in contact with one side of the bit line BL.

[0035] For example, the semiconductor pattern SP may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe).

[0036] The device may include multiple semiconductor patterns SP. Each semiconductor pattern SP may include a channel region, a first impurity region, and a second impurity region. The first and second impurity regions may represent regions of the semiconductor pattern SP that are doped with impurities. The first and second impurity regions may have n-type or p-type conductivity types.

[0037] One end of the semiconductor pattern SP may be connected to the bit line BL (e.g., in contact with the bit line BL). The semiconductor pattern SP may be connected to the bit line BL such that the semiconductor pattern SP partially protrudes inside the bit line BL, but the arrangement is not limited to this. For example, the side surface of one end of the semiconductor pattern SP may not protrude into the bit line BL, and may be in contact with the side surface of the bit line BL.

[0038] The other end of the semiconductor pattern SP can be connected (e.g., electrically connected) to the data storage element DS. For example, a first impurity region of the semiconductor pattern SP can be connected to the bit line BL, and a second impurity region of the semiconductor pattern SP can be connected to the data storage element DS. A channel region can be located between the first impurity region and the second impurity region.

[0039] Multiple semiconductor patterns SP can be arranged on the substrate 100, and the multiple semiconductor patterns SP can be stacked to be spaced apart from each other along a third direction DR3. For example, multiple semiconductor patterns SP connected to a bit line BL can be arranged to be spaced apart from each other along a third direction DR3. In addition, multiple semiconductor patterns SP can be arranged to be spaced apart from each other along corresponding bit lines BL that are "arranged to be spaced apart from each other in a first direction DR1 and a second direction DR2".

[0040] Word lines WL can be arranged on a semiconductor pattern SP. Word lines WL can have a shape extending along a second direction DR2. For example, word lines WL can have a strip shape extending along the second direction.

[0041] For example, word lines WL can be arranged as part of a semiconductor pattern SP. However, the arrangement is not limited to this, and for example, a pair of word lines can be arranged above and below the semiconductor pattern SP, respectively. Multiple word lines WL can be arranged on the substrate 100, and multiple word lines WL can be stacked while being spaced apart from each other on a third-direction DR3.

[0042] The word line (WL) may include a conductive material. The conductive material can be any of a semiconductor material, a conductive metal nitride, a metal, or a metal semiconductor compound.

[0043] The semiconductor device may include a first insulating layer 210, a gate insulating pattern 220, a second insulating layer 230, a first spacer 242, a second spacer 244, and an interlayer insulating layer 250.

[0044] The first insulating layer 210 may be placed on one side of the bit line BL. The first insulating layer 210 may be placed between the bit line BL and the first spacer 242. In addition, the first insulating layer 210 may be located between the bit line BL and the interlayer insulating layer 250.

[0045] The gate insulating pattern 220 may be placed between the word line WL and the semiconductor pattern SP. The semiconductor pattern SP and the word line WL may be arranged to be spaced apart on the third direction DR3, with the gate insulating pattern 220 positioned between them. The gate insulating pattern 220 may also be disposed between the first spacer 242 and the semiconductor pattern SP. The gate insulating pattern 220 may also be disposed between the word line WL and the second spacer 244. For example, the gate insulating pattern 220 may have an "L" shape in the cross-section on the first direction DR1 and the third direction DR3, but the shape is not limited to this.

[0046] The gate insulating pattern 220 may include an insulating material. The gate insulating pattern 220 may include a silicon oxide film, a silicon oxynitride film, a high-k dielectric film having a higher dielectric constant than the silicon oxide film, or combinations thereof. Here, the high-k dielectric film may be made of a metal oxide or a metal oxide nitride. For example, high-k dielectric films that can be used as the gate insulating pattern 220 may include, but are not limited to: hafnium oxide (HfO2), silicon hafnium oxide (HfSiO), silicon hafnium oxynitride (HfSiON), tantalum hafnium oxide (HfTaO), titanium hafnium oxide (HfTiO), zirconium hafnium oxide (HfZrO), zirconium oxide (ZrO2), aluminum oxide (Al2O3), or combinations thereof.

[0047] The second insulating layer 230 may be located between the second spacer 244 and the semiconductor pattern SP. The second insulating layer 230 may be disposed between the second spacer 244 and the data storage element DS. For example, the second insulating layer 230 may have an "L" shape in the cross-section on the first direction DR1 and the third direction DR3, but is not limited thereto.

[0048] A first spacer 242 may be disposed between a word line WL and a bit line BL. The first spacer 242 may have a shape surrounding the portion of the semiconductor pattern SP between the word line WL and the bit line BL. The first spacer 242 may be located between a first insulating layer 210 and the word line WL.

[0049] The second spacer 244 may be disposed between the word line WL and the data storage element DS. For example, the first spacer 242 and the second spacer 244 may be disposed on both sides (or opposite sides) of the word line WL. The second spacer 244 may have a shape that surrounds the portion of the semiconductor pattern SP between the word line WL and the data storage element DS. The second spacer 244 may be disposed between the second insulating layer 230 and the interlayer insulating layer 250.

[0050] The first insulating layer 210, the second insulating layer 230, the first spacer 242, and the second spacer 244 may comprise insulating materials. The first insulating layer 210, the second insulating layer 230, the first spacer 242, and the second spacer 244 may comprise the same insulating material. Optionally, at least one of the first insulating layer 210, the second insulating layer 230, the first spacer 242, and the second spacer 244 may comprise other insulating materials different from those of the first insulating layer 210, the second insulating layer 230, the first spacer 242, and the second spacer 244. For example, the first insulating layer 210, the second insulating layer 230, the first spacer 242, and the second spacer 244 may include, but are not limited to, at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON). The first insulating layer 210, the second insulating layer 230, the first spacer 242, and the second spacer 244 may be formed simultaneously or individually.

[0051] Interlayer insulating layer 250 may be placed between semiconductor patterns SP (e.g., between adjacent semiconductor patterns SP). Multiple semiconductor patterns SP may be arranged to be spaced apart on a third-direction DR3, and interlayer insulating layer 250 may be arranged between pairs of multiple semiconductor patterns SP spaced apart on the third-direction DR3.

[0052] Interlayer insulation layer 250 may be disposed above word lines WL. Interlayer insulation layer 250 may be disposed above first spacer 242. Interlayer insulation layer 250 may be disposed between word lines WL. For example, multiple word lines WL may be arranged to be spaced apart on a third direction DR3, and interlayer insulation layer 250 may be disposed between pairs of multiple word lines WL spaced apart on the third direction DR3. Interlayer insulation layer 250 may be located between second spacer 244 and bit line BL. Interlayer insulation layer 250 may be disposed between second spacer 244 and first insulation layer 210. One side of interlayer insulation layer 250 may contact first insulation layer 210, and the other side of interlayer insulation layer 250 may contact second spacer 244.

[0053] The interlayer insulation layer 250 may include an insulating material. For example, the interlayer insulation layer 250 may include, but is not limited to, at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON).

[0054] A silicide layer SC may be disposed between the first electrode 310 and the semiconductor pattern SP. The silicide layer SC may be located at the other end of the semiconductor pattern SP. The silicide layer SC serves to reduce the contact resistance between the first electrode 310 and the semiconductor pattern SP. The silicide layer SC may include a silicon metal compound. The silicide layer SC may include, for example, a compound in which silicon (Si) is bonded to at least one of titanium (Ti), cobalt (Co), and nickel (Ni). The silicide layer SC may include, for example, titanium silicide (TiSi). x ).

[0055] The semiconductor device may include a data storage element DS and a support 400. The data storage element DS may be connected (e.g., electrically connected) to a semiconductor pattern SP. The other end of the semiconductor pattern SP may be connected (e.g., electrically connected) to the data storage element DS. The data storage element DS may include a first electrode 310, a dielectric film 320, and a second electrode 330.

[0056] The first electrode 310 may be connected to the other end of the semiconductor pattern SP. One end of the first electrode 310 may be connected to the semiconductor pattern SP. The first electrode 310 may have a shape extending in the first direction DR1. The first electrode 310 may have a strip shape, rod shape, or column shape extending in the first direction DR1, but is not limited thereto. For example, the first electrode 310 may have a hollow-center cylindrical shape. The first electrode 310 may be positioned at substantially the same vertical height as the semiconductor pattern SP. The first electrode 310 may be aligned parallel to the semiconductor pattern SP along the first direction DR1. The width of the first electrode 310 in the second direction DR2 or the third direction DR3 may be substantially the same as the width of the semiconductor pattern SP in the second direction DR2 or the third direction DR3, but is not limited thereto. For example, the width of the first electrode 310 in the second direction DR2 or the third direction DR3 may be different from the width of the semiconductor pattern SP in the second direction DR2 or the third direction DR3.

[0057] The first electrode 310 may include a conductive material. The first electrode 310 may include, for example, metallic materials (such as titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), aluminum (Al), platinum (Pt), iridium (Ir), or ruthenium (Ru)), conductive metal nitrides (such as titanium nitride (TiN), molybdenum nitride (MoN), vanadium nitride (VN), niobium nitride (NbN), or tantalum nitride (TaN)), and conductive metal oxides (such as ruthenium oxide (RuO)). x ), Iridium oxide (IrO), Indium tin oxide (ITO), Molybdenum oxide (MoO) x ) and vanadium oxide (VO) x At least one of doped semiconductor materials (such as doped silicon (doped Si) or doped germanium (doped Ge)).

[0058] A support member 400 may be mounted on a substrate 100. The support member 400 may have a shape extending along a third-direction DR3. The support member 400 may function to support a first electrode 310. The support member 400 may be connected to (e.g., in contact with) the other end of the first electrode 310. The support member 400 may cover the other end of the first electrode 310. One side of the support member 400 may contact the other side of the first electrode 310. The support member 400 may be connected to (e.g., in contact with) a plurality of first electrodes 310 stacked on the third-direction DR3.

[0059] The support member 400 may be arranged parallel to the bit line BL. The support member 400 may be positioned so as not to overlap with the first electrode 310 in the second direction DR2 and the third direction DR3. For example, the support member 400 may not be located in the space between the plurality of first electrodes 310. The support member 400 may be positioned to overlap with the central region of the first electrode 310 in the second direction DR2 along the first direction DR1, but is not limited thereto.

[0060] The support 400 may include an insulating material. For example, the support 400 may include, but is not limited to, at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON).

[0061] A dielectric film 320 may be disposed on the first electrode 310 and the support member 400. The dielectric film 320 may cover the upper and lower surfaces of the first electrode 310 and one or more side surfaces of the support member 400. For example, a side surface of the first electrode 310 may represent a surface perpendicular to the upper surface of the substrate 100. The dielectric film 320 may cover a portion of the other side of the first electrode 310. Here, the other side of the first electrode 310 may represent the surface opposite to the side of the first electrode 310a in which the first electrode 310 and the semiconductor pattern SP are connected. For example, a portion of the other side of the first electrode 310 may be covered by the support member 400, and the remaining portion may be covered by the dielectric film 320. The dielectric film 320 may be disposed between the first electrode 310 and the second electrode 330. The dielectric film 320 may be conformally disposed on the first electrode 310 and the support member 400.

[0062] The dielectric film 320 may be placed on the second insulating layer 230. The first spacer 242 and the second spacer 244 may be placed on the interlayer insulating layer 250, the second insulating layer 230 may be placed on the second spacer 244, and the dielectric film 320 may be placed on the second insulating layer 230. For example, the second spacer 244 may be placed on the side surface of the interlayer insulating layer 250.

[0063] The dielectric film 320 may include an insulating material. The dielectric film 320 may include a silicon oxide film, a silicon oxynitride film, a high-k dielectric film having a higher dielectric constant than a silicon oxide film, or a combination thereof. Here, the high-k dielectric film may be made of a metal oxide or a metal oxide nitride. For example, high-k dielectric films that can be used as dielectric film 320 may include, but are not limited to, hafnium oxide (HfO2), silicon hafnium oxide (HfSiO), silicon hafnium oxynitride (HfSiON), tantalum hafnium oxide (HfTaO), titanium hafnium oxide (HfTiO), zirconium hafnium oxide (HfZrO), zirconium oxide (ZrO2), aluminum oxide (Al2O3), or a combination thereof.

[0064] The second electrode 330 may be disposed on the dielectric film 320. The second electrode 330 may fill the space between a plurality of first electrodes 310. Data storage elements DS stacked on the third-party DR3 may share a second electrode 330.

[0065] The second electrode 330 may include a conductive material. The second electrode 330 may include, for example, metallic materials (such as titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), aluminum (Al), platinum (Pt), iridium (Ir), or ruthenium (Ru)), conductive metal nitrides (such as titanium nitride (TiN), molybdenum nitride (MoN), vanadium nitride (VN), niobium nitride (NbN), or tantalum nitride (TaN)), and conductive metal oxides (such as ruthenium oxide (RuO)). x ), Iridium oxide (IrO), Indium tin oxide (ITO), Molybdenum oxide (MoO) x ) and vanadium oxide (VO) x At least one of doped semiconductor materials (such as doped silicon (doped Si) or doped germanium (doped Ge)).

[0066] Figure 3 yes Figure 2 A magnified view of region A. Figure 4 It is a semiconductor device (e.g., Figures 1 to 2 A plan view of an example semiconductor device. Figure 5 This is a side view of a part of a semiconductor device.

[0067] Reference Figures 3 to 5 A plurality of first electrodes 310, each having a shape extending in a first direction DR1, may be arranged in parallel and spaced apart in a third direction DR3. The other side of each first electrode 310 may be connected to a support 400 (e.g., in contact with the support 400). The support 400 may have a shape extending in the third direction DR3. One support 400 may be connected to the first electrodes 310 spaced apart in the third direction DR3. The support 400 may be positioned to cover the central region of the first electrodes 310 in a second direction DR2. The width D1 of the first electrodes 310 in the second direction DR2 may be greater than the width D2 of the support 400 in the second direction DR2.

[0068] The support member 400 may be positioned so as not to overlap with the first electrode 310 along the second direction DR2 and the third direction DR3. The support member 400 may not be located in the space between the first electrodes 310. Positioning the support member 400 so as not to overlap with the first electrode 310 along the second direction DR2 and the third direction DR3 reduces the impact on the data storage capacity of the data storage element DS. However, the implementation is not limited to this, and the support member 400 may be positioned to overlap with the first electrode 310 along the second direction DR2 and / or the third direction DR3. For example, the support member 400 may be positioned between adjacent first electrodes 310 of a plurality of first electrodes 310.

[0069] The dielectric film 320 may be disposed on the first electrode 310 and the support 400. The dielectric film 320 may be conformally disposed on the first electrode 310 and the support 400. The second electrode 330 may be disposed on the dielectric film 320. The second electrode 330 may fill the space between the plurality of first electrodes 310.

[0070] The second electrode 330 may cover the first electrode 310, the support 400, and the dielectric film 320 disposed on the first electrode 310 and the support 400. The second electrode 330 may fill the space between the plurality of first electrodes 310. For example, the second electrode 330 may fill the space between the plurality of first electrodes 310 in the second direction DR2 and the third direction DR3.

[0071] Figures 6 to 23 It is used to explain the process of manufacturing semiconductor devices (e.g., Figures 1 to 5 An example diagram illustrating a method for using a semiconductor device.

[0072] Reference Figures 6 to 8 First electrodes 310, having a shape extending in a first direction DR1, can be stacked while being spaced apart from each other in a third direction DR3. A first mask pattern 341 and a second mask pattern 342 can be placed between the plurality of first electrodes 310. The first mask pattern 341 can fill the space between the plurality of first electrodes 310, and the second mask pattern 342 can be conformally arranged on a side surface of the first mask pattern 341. The plurality of first electrodes 310 can be arranged in a shape that penetrates the first mask pattern 341 and the second mask pattern 342 in the first direction DR1. The other side of the first electrode 310 can be exposed to the outside. The second mask pattern 342 can have one side exposed to the outside. Through the second mask pattern 342, the first mask pattern 341 may not be exposed to the outside. The positions of the first mask pattern 341 and the second mask pattern 342 are examples and can be changed in various ways as needed.

[0073] The first mask pattern 341 and the second mask pattern 342 may include insulating materials. For example, the first mask pattern 341 and the second mask pattern 342 may include, but are not limited to, at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON). The first mask pattern 341 and the second mask pattern 342 may include different materials. For example, the first mask pattern 341 may include silicon oxide (SiO), and the second mask pattern 342 may include silicon nitride (SiN).

[0074] Next, refer to Figures 9 to 11 A third mask pattern 343 may be formed to contact the second mask pattern 342 and the first electrode 310. The third mask pattern 343 may have a shape extending in the second direction DR2 and the third direction DR3. The third mask pattern 343 may cover the exposed side surface of the first electrode 310 and the second mask pattern 342. The third mask pattern 343 may be formed not to overlap with the plurality of first electrodes 310 along the second direction DR2 and the third direction DR3. However, the arrangement is not limited to this, and a portion of the third mask pattern 343 may be arranged to overlap with the plurality of first electrodes 310 along the second direction DR2 and / or the third direction DR3. For example, in some embodiments, the third mask pattern 343 may be disposed between the plurality of first electrodes 310.

[0075] The third mask pattern 343 may include an insulating material. For example, the third mask pattern 343 may include, but is not limited to, at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon oxynitride (SiON).

[0076] Next, refer to Figures 12 to 14 A portion of the third mask pattern 343 can be removed to form a trench TRC. The trench TRC may have a shape extending on the third direction DR3.

[0077] The trench TRC can be formed to expose the central region of the first electrode 310 along the second direction DR2. For example, the central region of the first electrode 310 along the second direction DR2 can be exposed by the trench TRC. However, the location of the trench TRC is not limited to this and can be changed in various ways. A portion of the second mask pattern 342 can be exposed by the trench TRC. The trench TRC can be formed to overlap with at least a portion of the first electrode 310 along the first direction DR1. The trench TRC can be formed not to overlap with the first electrode 310 along the second direction DR2 and the third direction DR3. However, the implementation is not limited to this, and the trench TRC can be arranged to overlap with the first electrode 310 along the second direction DR2 and / or the third direction DR3. For example, the trench TRC can be located between multiple first electrodes 310.

[0078] For example, an etching process can be used to form the trench TRC. The etching process can be either dry etching or wet etching, but is not limited to these, and can be performed in a variety of ways.

[0079] Next, refer to Figures 15 to 17 A support member 400 can be formed within the trench TRC. The support member 400 may have a shape extending in a third direction DR3.

[0080] The support member 400 may be formed to contact the central region of the first electrode 310 in the second direction DR2. However, the position of the support member 400 is not limited to this and can be changed in various ways. The support member 400 may cover the side surfaces of the plurality of first electrodes 310 stacked on the third direction DR3. A portion of the second mask pattern 342 may contact the support member 400. The support member 400 may be covered by a third mask pattern 343. The support member 400 may be formed to overlap at least a portion of the first electrode 310 along the first direction DR1. The support member 400 may be formed not to overlap with the first electrode 310 along the second direction DR2 and the third direction DR3. However, the implementation is not limited to this, and the support member 400 may be positioned to overlap with the first electrode 310 along the second direction DR2 and / or the third direction DR3. For example, the support member 400 may be positioned between adjacent first electrodes 310 of the plurality of first electrodes 310.

[0081] The support member 400 may include an insulating material. The support member 400 may include a material different from the third mask pattern 343.

[0082] Next, refer to Figures 18 to 20 The third mask pattern 343 can be removed. When the third mask pattern 343 is removed, the support member 400 can be exposed to the outside. Furthermore, because the third mask pattern 343 is removed, a portion of the side surface of the first electrode 310 can be exposed. For example, the remaining portion of the side surface of the first electrode 310, excluding the portion in contact with the support member 400, can be exposed. Because the third mask pattern 343 is removed, a portion of the second mask pattern 342 can be exposed to the outside.

[0083] For example, an etching process can be performed to remove the third mask pattern 343. The etching process can utilize dry etching and / or wet etching methods, but is not limited to these, and can be varied in a variety of ways.

[0084] Next, refer to Figures 21 to 23The first mask pattern 341 and the second mask pattern 342 can be removed. Since the first mask pattern 341 and the second mask pattern 342 are removed, the first electrode 310 can be exposed to the outside. For example, the upper and lower surfaces of the first electrode 310 can be exposed to the outside. Furthermore, the surfaces of the first electrode 310 covered by the first mask pattern 341 and the second mask pattern 342 can be exposed to the outside. For example, the surfaces of the first electrode 310 covered by the first mask pattern 341 and the second mask pattern 342 can be surfaces extending in the first direction DR1.

[0085] For example, the first mask pattern 341 may include silicon oxide (SiO), and the second mask pattern 342 may include silicon nitride (SiN). The support 400 may include the same material as the second mask pattern 342. Furthermore, for example, the width of the support 400 may be reduced to some extent during the process of removing the first mask pattern 341 and the second mask pattern 342.

[0086] Even if the first mask pattern 341 and the second mask pattern 342 are removed, the support member 400 is still connected to (e.g., in contact with) the plurality of first electrodes 310, so that the first electrodes 310 can be supported. Therefore, the first electrodes 310 can be prevented from bending in the third direction DR3 by external forces (such as gravity).

[0087] When the support member 400 is configured not to overlap with the plurality of first electrodes 310 along the second direction DR2 and the third direction DR3, the impact on data storage performance in the data storage element DS can be reduced by ensuring the overlap area of ​​the first electrodes 310 and the second electrodes 330. However, the arrangement is not limited to this, and the support member 400 may overlap with the plurality of first electrodes 310 along the second direction DR2 and / or the third direction DR3. In this case, the support member 400's support capability for the plurality of first electrodes 310 can also be improved.

[0088] For example, an etching process can be used to remove the first mask pattern 341 and the second mask pattern 342. The etching process can be a dry etching process and / or a wet etching process, but is not limited to this, and can be performed in a variety of ways.

[0089] Figure 24 and Figure 25 These are a plan view and a side view, respectively, illustrating another example of a semiconductor device. Unless the context otherwise indicates or implies, the semiconductor device may have the same characteristics as... Figures 1 to 5 The characteristics of the semiconductor device are matched or similar.

[0090] Reference Figure 24 and Figure 25The support member 400 may be arranged to overlap at least a portion of the first electrode 310 along the first direction DR1. A support member 400 may be arranged to overlap simultaneously along the first direction DR1 with a pair of first electrodes 310 spaced apart along the second direction DR2 (e.g., adjacent first electrodes 310 along the second direction DR2). The support member 400 may be arranged to overlap along the space between the first direction DR1 and the plurality of first electrodes 310 spaced apart along the second direction DR2. In some embodiments, when a support member 400 is arranged to overlap simultaneously along the first direction DR1 with a pair of first electrodes 310 spaced apart along the second direction DR2, the central region (e.g., the center) of the first electrode 310 in the second direction DR2 may not contact the support member 400.

[0091] The width D2 of the support member 400 in the second direction DR2 may be greater than the space D3 in the second direction DR2 between a pair of adjacent first electrodes 310 at substantially the same height in the second direction DR3. The width D2 of the support member 400 in the second direction DR2 may be less than the width D1 of the first electrodes 310 in the second direction DR2.

[0092] For example, the support 400 may be positioned so that it does not overlap with the first electrode 310 along the second direction DR2 and the third direction DR3. However, the arrangement is not limited to this, and the support 400 may be positioned to overlap with the first electrode 310 along the second direction DR2 and / or the third direction DR3. For example, the support 400 may be positioned between a plurality of first electrodes 310.

[0093] Figure 26 and Figure 27 These are a plan view and a side view, respectively, illustrating another example of a semiconductor device. Unless the context otherwise indicates or implies, the semiconductor device may have the same characteristics as... Figures 1 to 5 The characteristics of the semiconductor device are matched or similar.

[0094] Reference Figure 26 and Figure 27 The support member 400 can be arranged to be spatially stacked between a plurality of first electrodes 310 spaced apart along the first direction DR1 and the second direction DR2. Furthermore, the support member 400 can be arranged to be stacked along the first direction DR1 and the central region (e.g., center) of the first electrodes 310 in the second direction DR2. For example, the support member 400 can be placed at a location where it is stacked between a pair of first electrodes 310 spaced apart along the first direction DR1 and the second direction DR2, and the support member 400 can be placed at a location where it is stacked along the first direction DR1 and the central region (e.g., center) of the first electrodes 310 in the second direction DR2.

[0095] The width D2 of the support member 400 in the second direction DR2 can vary depending on the position, but is not limited thereto. That is, the width D2 of the support member 400 in the second direction DR2 can be substantially the same, regardless of the position.

[0096] For example, the support member 400 may be positioned on the second direction DR2 and the third direction DR3 without overlapping the first electrode 310. However, it is not limited to this; the support member 400 may be positioned on the second direction DR2 and the third direction DR3 overlapping the first electrode 310. That is, the support member 400 may be positioned between a plurality of first electrodes 310.

[0097] Figures 28 to 30 This is a diagram illustrating another example of a semiconductor device. Unless the context otherwise indicates or implies, a semiconductor device may have the same characteristics as... Figures 1 to 5 The characteristics of the semiconductor device are matched or similar.

[0098] Reference Figures 28 to 30 The first electrode 310 may extend in the first direction DR1 and has a cylindrical shape with a hollow portion.

[0099] The first electrode 310 may include a vertical portion extending in a third direction DR3 and a horizontal portion extending from the vertical portion in a first direction DR1. The vertical portion of the first electrode 310 may be connected to a semiconductor pattern SP. The vertical portion of the first electrode 310 covers a side surface of the semiconductor pattern SP and may extend in the third direction DR3. The horizontal portion of the first electrode 310 may extend from the vertical portion of the first electrode 310 away from the bit line BL in the first direction DR1. The horizontal portion of the first electrode 310 may have a hollow prism shape.

[0100] The second electrode 330 can be inserted into and surrounded by the first electrode 310. The second electrode 330 can be inserted into the internal space of the cylindrical first electrode 310. Multiple layers of data storage elements DS stacked on the third-direction DR3 can share a single second electrode 330.

[0101] The end of the horizontal portion of the first electrode 310 can be supported by the support member 400. The support member 400 can contact the dielectric film 320. Even when the first electrode 310 has a cylindrical shape, the end of the horizontal portion of the first electrode 310 can be supported by the support member 400.

[0102] While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of the claims. Specific features described in the context of individual embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a specific combination, in some cases, one or more features from the combination may be removed from the combination, and the combination may involve sub-combinations or variations thereof.

[0103] Although examples have been described in detail above, the scope of this disclosure is not limited thereto, and various modifications and improvements made by those skilled in the art also fall within the scope of this disclosure.

Claims

1. A semiconductor device, comprising: Base; Multiple semiconductor patterns are on a substrate and extend in a first direction parallel to the upper surface of the substrate, wherein the multiple semiconductor patterns are spaced apart in a third direction perpendicular to the upper surface of the substrate. Bit lines extend upward in a third direction and are electrically connected to a first end of each of the plurality of semiconductor patterns; Multiple word lines extend on the multiple semiconductor patterns and in a second direction parallel to the upper surface of the substrate, wherein the second direction intersects the first direction; A plurality of first electrodes extending in a first direction and spaced apart in a third direction, wherein each of the plurality of first electrodes has a first end electrically connected to a second end of a corresponding semiconductor pattern in the plurality of semiconductor patterns; and A support extends upward on a third party and covers the second end of each of the plurality of first electrodes.

2. The semiconductor device of claim 1, wherein, The side surface of the support member contacts the side surface of each of the plurality of first electrodes at the second end of the first electrode.

3. The semiconductor device as claimed in claim 1, wherein, The support is stacked along the first direction at the center of each of the plurality of first electrodes in the second direction.

4. The semiconductor device of claim 1, wherein, The width of the support member in the second direction is greater than the distance between one of the plurality of first electrodes and another first electrode in the second direction, wherein the other first electrode is spaced apart from the one of the plurality of first electrodes in the second direction.

5. The semiconductor device of claim 4, wherein, The support member is stacked along a first direction with one of the plurality of first electrodes and the other first electrode.

6. The semiconductor device according to any one of claims 1 to 5, further comprising: The second electrode, on the plurality of first electrodes, and A dielectric film is placed between the second electrode and the plurality of first electrodes.

7. The semiconductor device according to any one of claims 1 to 5, wherein, The width of the support in the second direction is smaller than the width of each of the plurality of first electrodes in the second direction.

8. The semiconductor device according to any one of claims 1 to 5, further comprising: A silicide layer is placed between each of the plurality of first electrodes and a corresponding semiconductor pattern in the plurality of semiconductor patterns.

9. The semiconductor device according to any one of claims 1 to 5, wherein, Each of the plurality of semiconductor patterns and the corresponding first electrode of the plurality of first electrodes electrically connected to the semiconductor pattern are arranged at the same height in a third direction and aligned parallel to each other in a first direction.

10. The semiconductor device according to any one of claims 1 to 5, wherein, The support member is not superimposed on the plurality of first electrodes along the second direction and the third direction.

11. A semiconductor device, comprising: Base; Multiple semiconductor patterns are on a substrate and extend in a first direction parallel to the upper surface of the substrate, wherein the multiple semiconductor patterns are spaced apart in a third direction perpendicular to the upper surface of the substrate. Bit lines extend upward in a third direction and are electrically connected to a first end of each of the plurality of semiconductor patterns; Multiple word lines extend on the multiple semiconductor patterns and in a second direction parallel to the upper surface of the substrate, wherein the second direction intersects the first direction; A plurality of first electrodes having a rod shape, a strip shape, or a column shape and extending in a first direction, wherein each of the plurality of first electrodes has a first end electrically connected to a second end of a corresponding semiconductor pattern in the plurality of semiconductor patterns; A support member extends upward in a third party and contacts the second end of each of the plurality of first electrodes; A second electrode is located on the plurality of first electrodes and the support; and A dielectric film is placed between the second electrode and the plurality of first electrodes.

12. The semiconductor device of claim 11, wherein, The dielectric film is located between the support and the second electrode.

13. The semiconductor device of claim 11, wherein, The support is stacked along the first direction with the center of each of the plurality of first electrodes in the second direction.

14. The semiconductor device of claim 11, wherein, The support member is stacked along a first direction with one of the plurality of first electrodes and another first electrode spaced apart from the one of the plurality of first electrodes in a second direction.

15. The semiconductor device of claim 11, wherein, The width of the support in the second direction is smaller than the width of each of the plurality of first electrodes in the second direction.

16. A semiconductor device, comprising: Base; Multiple semiconductor patterns are on a substrate and extend in a first direction parallel to the upper surface of the substrate, wherein the multiple semiconductor patterns are spaced apart in a third direction perpendicular to the upper surface of the substrate. Bit lines extend upward in a third direction and are electrically connected to a first end of each of the plurality of semiconductor patterns; Multiple word lines extend on a semiconductor pattern in a second direction parallel to the upper surface of the substrate, wherein the second direction intersects the first direction; A plurality of first electrodes extend in a first direction and have a cylindrical shape with a hollow portion, wherein each of the plurality of first electrodes has a first end electrically connected to a second end of a corresponding semiconductor pattern in the plurality of semiconductor patterns; A support member extends upward on a third party and covers the second end of each of the plurality of first electrodes; A second electrode is located on the plurality of first electrodes and the support; and A dielectric film is placed between the second electrode and the plurality of first electrodes.

17. The semiconductor device of claim 16, wherein, The side surface of the support member contacts the side surface of each of the plurality of first electrodes at the second end of the first electrode.

18. The semiconductor device of claim 16, wherein, The support is stacked along the first direction at the center of each of the plurality of first electrodes in the second direction.

19. The semiconductor device of claim 16, wherein, The support member is stacked along a first direction with one of the plurality of first electrodes and another first electrode spaced apart from the one of the plurality of first electrodes in a second direction.

20. The semiconductor device of claim 16, wherein, The width of the support in the second direction is smaller than the width of each of the plurality of first electrodes in the second direction.

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