Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure relates to the field of semiconductor, and provides a semiconductor structure and a preparation method thereof. The semiconductor structure comprises: a plurality of semiconductor layers, the plurality of semiconductor layers are arranged in mirror symmetry in a first horizontal direction, each semiconductor layer comprises a first source-drain region, a channel region and a second source-drain region arranged in sequence along the first horizontal direction; a plurality of bit line structures arranged in a second direction and a second horizontal direction respectively, and coupled to the first source-drain regions of the plurality of semiconductor layers respectively; a plurality of word line structures arranged in the first direction and the second horizontal direction respectively, and located on the channel regions; the first direction is one of the second horizontal direction intersecting the first horizontal direction or a vertical direction, and the second direction is the other one of the second horizontal direction and the vertical direction; the word line structure comprises a first tunneling layer, a charge trapping layer, a second tunneling layer and a control layer arranged in sequence, and the first tunneling layer is located between the channel region and the charge trapping layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] With the continuous development of integrated circuit technology and processes, the feature size of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) is constantly shrinking in order to improve the integration density of integrated circuits. Currently, 3D chips have become the industry's preferred solution to address the contradiction between increasing transistor density and the high cost of advanced process miniaturization. Whether in chip manufacturing or packaging, whether in logic chips or memory, high-end applications are all shifting towards 3D.

[0003] Consequently, 3D NOR flash memory technology emerged, promising to redefine the future of non-volatile memory by offering significant improvements over traditional 2D NOR flash memory. NOR flash memory in 3D NOR flash memory technology is mainly divided into serial and parallel types. Serial NOR flash memory is characterized by simpler interfaces, thinner profiles, lower power consumption, and lower overall system cost. Compared to NAND, NOR has higher costs, smaller capacity, and slower write speeds, and is mainly used for small-capacity code storage in feature phones, televisions, set-top boxes, USB keys, etc.

[0004] Currently, 3D NOR flash memory technology is in its early stages and faces many challenges, such as forming a vertical stacking structure based on conventional 2D NOR flash design, and achieving size reduction (increased integration) and low cost while ensuring the safety of 3D NOR flash. Summary of the Invention

[0005] This disclosure provides a semiconductor structure and a method for fabricating the same, which at least helps to improve the integration level of the semiconductor structure.

[0006] This disclosure provides a semiconductor structure comprising: a plurality of semiconductor layers, arranged at intervals in a first horizontal direction, a second horizontal direction, and a vertical direction, wherein the plurality of semiconductor layers in the first horizontal direction are arranged alternately in a mirror-symmetrical manner, and each semiconductor layer includes a first source-drain region, a channel region, and a second source-drain region sequentially arranged along the first horizontal direction; a plurality of bit line structures, arranged at intervals in a second direction and a second horizontal direction, the bit line structures extending along the first direction and respectively coupled to the first source-drain regions of the plurality of semiconductor layers; and a plurality of word line structures, arranged at intervals in the first direction and the second horizontal direction, the word line structures extending along the second direction and located on the channel region; wherein the first direction is either a second horizontal direction intersecting the first horizontal direction or a vertical direction, and the second direction is the other of the second horizontal direction and the vertical direction; the word line structure includes a first tunneling layer, a charge trapping layer, a second tunneling layer, and a control layer sequentially disposed therefrom, the first tunneling layer being located between the channel region and the charge trapping layer.

[0007] Optionally, at least one of the first tunneling layer and the second tunneling layer may be made of silicon oxide.

[0008] Optionally, multiple connection structures are arranged at intervals between each other in the first direction and the second horizontal direction, the connection structures extend along the first direction, and the connection structures are coupled to the second source and drain regions of multiple semiconductor layers.

[0009] Optionally, the connection structure is coupled to the second source / drain regions of a plurality of semiconductor layers that are mirror-symmetrical along the first horizontal direction.

[0010] Optionally, the connection structure and the bit line structure are mirror-symmetrical along the axis of the semiconductor layer.

[0011] Optionally, the charge trapping layer includes a silicon nitride layer, a silicon-rich silicon nitride layer, or a composite layer composed of silicon nitride and a high-k dielectric material; the high-k dielectric material includes aluminum oxide or hafnium oxide.

[0012] Optionally, the word line structure surrounds the channel region.

[0013] This disclosure also provides a method for fabricating a semiconductor structure, comprising: forming a plurality of semiconductor layers, which are arranged at intervals in a first horizontal direction, a second horizontal direction, and a vertical direction, wherein the plurality of semiconductor layers in the first horizontal direction are arranged alternately in a mirror-symmetrical manner, and each semiconductor layer includes a first source-drain region, a channel region, and a second source-drain region arranged sequentially along the first horizontal direction; forming a plurality of bit line structures, which are arranged at intervals in a second direction and a second horizontal direction, wherein the bit line structures extend along a first direction and are respectively coupled to the first source-drain regions of the plurality of semiconductor layers; forming a plurality of word line structures, which are arranged at intervals in the first direction and a second horizontal direction, wherein the word line structures extend along the second direction and are located on the channel region; wherein the first direction is one of a second horizontal direction or a vertical direction intersecting the first horizontal direction, and the second direction is the other of the second horizontal direction and the vertical direction; the word line structure includes a first tunneling layer, a charge trapping layer, a second tunneling layer, and a control layer arranged sequentially, wherein the first tunneling layer is located between the channel region and the charge trapping layer.

[0014] Optionally, the process steps for forming the word line structure include: providing a substrate; forming a stacked semiconductor layer and a first sacrificial layer on the substrate; patterning the semiconductor layer and the first sacrificial layer to form a first groove; removing the first sacrificial layer along the first groove and removing a portion of the width of the semiconductor layer; sequentially forming a first tunneling layer, a second sacrificial layer, a second tunneling layer, a connection film, and a word line isolation layer between adjacent semiconductor layers; patterning the semiconductor layer to form a second groove, the second groove not overlapping the first groove; removing the second sacrificial layer to form a charge trapping layer, the connection film serving as a control layer.

[0015] Optionally, the connecting film is located on the inner wall of the first groove, the second groove exposes the side of the connecting film, and the connecting film is etched along the second groove to form two spaced control layers.

[0016] The technical solution provided in this disclosure has at least the following advantages: The semiconductor structure disclosed herein expands the memory array directly from a two-dimensional plane to a three-dimensional space by stacking multiple semiconductor layers, i.e., a 3D stacked structure. This achieves a number of memory cells that are multiples of the number of stacked layers within the same planar area. Multiple semiconductor layers are arranged alternately in a mirror-symmetrical manner along the first horizontal direction. This mirror-symmetrical alternation allows adjacent layers to share source-drain contacts or bit lines, reducing unnecessary isolation space and thus saving chip area. The bit line structure extends vertically and directly couples to the first source-drain regions of each layer, achieving vertical interconnection. This allows bit lines, which originally occupied a large area in the plane, to be moved vertically, avoiding complex peripheral circuit wiring that would otherwise occupy array area. The word line structure surrounds the channel region, i.e., a gate-all-around (GAA) structure is adopted. Compared to planar transistors, GAA (Gate-All-Around) can better control the channel and effectively suppress short-channel effects. With word lines extending horizontally and bit lines extending vertically, the semiconductor structure forms a layout resembling a three-dimensional intersecting matrix. Each memory cell is located at the intersection of the word line and the bit line. This array layout is regular and compact, thus enabling extremely high integration density. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A top view of a semiconductor structure provided in an embodiment of this disclosure; Figure 2 for Figure 1 A sectional view along section A1-A2; Figure 3 A circuit diagram of a semiconductor structure provided in one embodiment of this disclosure; Figure 4 A top view of another semiconductor structure provided in an embodiment of this disclosure; Figure 5 A top view of a semiconductor structure corresponding to a substrate is provided in a method for fabricating a semiconductor structure according to an embodiment of this disclosure; Figure 6 for Figure 5 A sectional view along section A1-A2; Figure 7This is a top view of a semiconductor structure corresponding to the formation of a second trench in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure. Figure 8 for Figure 7 A sectional view along section A1-A2; Figure 9 This is a cross-sectional view of a semiconductor structure corresponding to the formation of a first groove in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; Figure 10 This is a cross-sectional view of a semiconductor structure corresponding to the removal of the first sacrificial layer in a method for fabricating a semiconductor structure according to an embodiment of this disclosure; Figure 11 A cross-sectional view of a semiconductor structure corresponding to the formation of a first tunneling film in a method for fabricating a semiconductor structure according to an embodiment of this disclosure; Figure 12 This is a cross-sectional view of a semiconductor structure corresponding to the formation of a second sacrificial layer in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure. Figure 13 This is a cross-sectional view of a semiconductor structure corresponding to the formation of a connecting film in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; Figure 14 This is a cross-sectional view of a semiconductor structure corresponding to the formation of a fourth sacrificial layer in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; Figure 15 A cross-sectional view of a semiconductor structure corresponding to the removal of the second sacrificial layer located in the first groove in a method for fabricating a semiconductor structure according to an embodiment of this disclosure; Figure 16 This is a cross-sectional view of a semiconductor structure corresponding to the formation of a fifth sacrificial layer in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; Figure 17 A cross-sectional view of a semiconductor structure corresponding to the first tunneling film after removing the first groove in a method for fabricating a semiconductor structure according to an embodiment of this disclosure; Figure 18 This is a cross-sectional view of a semiconductor structure corresponding to a bit line structure formed in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure. Figure 19 This is a cross-sectional view of a semiconductor structure corresponding to the formation of the sixth sacrificial layer in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; Figure 20 A cross-sectional view of the semiconductor structure corresponding to the formation of the second groove in a method for fabricating a semiconductor structure according to an embodiment of this disclosure; Figure 21This is a cross-sectional view of a semiconductor structure corresponding to a control layer in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; Figure 22 This is a cross-sectional view of a semiconductor structure corresponding to the formation of a charge trap layer in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure; Figure 23 This is a cross-sectional view of a semiconductor structure corresponding to the formation of the sixth isolation layer in a method for fabricating a semiconductor structure according to an embodiment of this disclosure.

[0019] Explanation of reference numerals in the attached figures: 100. Substrate; 101. Semiconductor layer; 102. First sacrificial layer; 103. Second isolation layer; 104. First isolation layer; 105. Third isolation layer; 106. Second filler layer; 107. Third filler layer; 108. First trench; 109. First tunneling film; 110. Word line structure; 111. First tunneling layer; 112. Charge trap layer; 113. Second tunneling layer; 114. Second sacrificial layer; 115. Third sacrificial layer; 116. Connector film; 117. Word line isolation layer; 118. Fourth sacrificial layer; 119. Fifth sacrificial layer; 120. Bit line structure; 121. Sixth sacrificial layer; 122. Second trench; 123. Sixth isolation layer; 124. Connector structure; 129. Control layer; 201. Semiconductor layer; 210. Word line structure; 211. First tunneling layer; 212. Charge trapping layer; 213. Second tunneling layer; 217. Word line isolation layer; 220. Bit line structure; 224. Connection structure; 229. Control layer; 234. Isolation layer. Detailed Implementation

[0020] As can be seen from the background technology, the integration level of current semiconductor structures is not good.

[0021] This disclosure provides a semiconductor structure that, by configuring the architecture of the semiconductor structure, forms a 3D NOR Flash based on the concept of Slit HWL (Slit Half-Width Length) 3D DRAM architecture, thereby realizing a high-density, low-interference vertically stacked memory array.

[0022] It should be noted that the terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the exemplary implementations according to embodiments of this disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0023] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0024] In the description of the embodiments of this disclosure, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is generally based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this disclosure and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of the embodiments of this disclosure; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0025] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0026] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore should not be construed as limiting the scope of protection of this disclosure.

[0027] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0028] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: a plurality of semiconductor layers, arranged at intervals in a first horizontal direction, a second horizontal direction, and a vertical direction, wherein the plurality of semiconductor layers in the first horizontal direction are arranged alternately in a mirror-symmetrical manner, and each semiconductor layer includes a first source-drain region, a channel region, and a second source-drain region arranged sequentially along the first horizontal direction; a plurality of bit line structures, arranged at intervals in a second direction and a second horizontal direction, the bit line structures extending along the first direction and respectively coupled to the first source-drain regions of the plurality of semiconductor layers; a plurality of word line structures, arranged at intervals in the first direction and a second horizontal direction, the word line structures extending along the second direction and located on the channel region; wherein the first direction is one of a second horizontal direction intersecting the first horizontal direction or a vertical direction, and the second direction is the other of the second horizontal direction and the vertical direction; the word line structure includes a first tunneling layer, a charge trapping layer, a second tunneling layer, and a control layer arranged sequentially, the first tunneling layer being located between the channel region and the charge trapping layer.

[0029] The semiconductor structure provided in this disclosure extends the memory array from a two-dimensional plane to a three-dimensional space by stacking multiple semiconductor layers, resulting in a 3D stacked structure. This allows for a number of memory cells that are multiples of the number of stacked layers within the same planar area. Multiple semiconductor layers are arranged alternately in a mirror-symmetrical manner in the first horizontal direction. This mirror-symmetrical alternation allows adjacent layers to share source-drain contacts or bit lines, reducing unnecessary isolation space and saving chip area. The bit line structure extends vertically and directly couples to the first source-drain regions of each layer, achieving vertical interconnection. This allows bit lines, which originally occupied a large area in the plane, to be moved vertically, avoiding complex peripheral circuit wiring that would otherwise occupy array area. The word line structure surrounds the channel region, employing a gate-around-a-ring (GAA) structure. Compared to planar transistors, GAA can better control the channel and effectively suppress short-channel effects. With word lines extending horizontally and bit lines extending vertically, the semiconductor structure forms a layout resembling a three-dimensional intersecting matrix. Each memory cell is located at the intersection of the word line and the bit line. This array structure is regular and compact, enabling extremely high integration density.

[0030] The semiconductor structure provided in the above embodiments will be described in detail below with reference to the specific accompanying drawings.

[0031] Figure 1A top view of a semiconductor structure provided in an embodiment of this disclosure; Figure 2 for Figure 1 A sectional view along section A1-A2; Figure 3 A circuit diagram of a semiconductor structure provided in one embodiment of this disclosure; Figure 4 This is a top view of another semiconductor structure provided in an embodiment of the present disclosure.

[0032] It should be noted that, Figure 2 This is a semiconductor structure consisting of multiple vertically stacked transistors. The first horizontal direction is defined as the X direction, the second horizontal direction as the Y direction, and the vertical direction as the Z direction. Figure 1 and Figure 2 The first direction of the semiconductor structure is a second horizontal direction that intersects with the first horizontal direction. The second direction is a vertical direction, that is, the bit line structure extends along the second horizontal direction Y, and the word line structure extends along the vertical direction Z. Figure 4 The first direction of the semiconductor structure is a vertical direction that intersects with the first horizontal direction, and the second direction is a second horizontal direction that intersects with the first horizontal direction. That is, the bit line structure extends along the vertical direction Z, and the word line structure extends along the second horizontal direction Y.

[0033] refer to Figure 1 as well as Figure 2 The semiconductor structure includes a substrate 100, and multiple semiconductor layers 101 are stacked on the substrate 100.

[0034] In some embodiments, the material of the substrate 100 can be a semiconductor material, which may include any one of silicon, germanium, silicon carbide, or silicon germanide. The substrate 100 contains doping elements, which can be N-type or P-type doping elements. N-type doping elements can be group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As), while P-type doping elements can be group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0035] Semiconductor layer 101 is the region on the silicon wafer where active devices are fabricated, i.e., the active region. Different doping element types in the active region can form n-type or p-type active regions. The active region consists of a source region and a drain region (with the same doping type). Before interconnection, the two active regions are indistinguishable. After the circuit is connected, the source region or drain region is defined according to the direction of the current.

[0036] The semiconductor layer 101 is made of undoped or doped semiconductor materials, two-dimensional semiconductor materials, amorphous metal oxide semiconductor materials, polycrystalline metal oxide semiconductor materials, or combinations thereof. Undoped or doped semiconductor materials include single-crystal Si, polycrystalline Si, SiGe, or SiC. Two-dimensional semiconductor materials include transition metal dichalcogenides (TMDs) (such as CuS2, CuSe2, WSe2, MoS2, MoSe2, WS2, etc.) and hexagonal boron nitride (h... Metal-oxide semiconductor materials may include In3O4, graphene, carbon nanotubes (CNTs), or combinations thereof. Zn-based oxides (IZO), Zn Sn-based oxides (ZTO), In Ga-based oxides (IGO), Y At least one of Zn-based oxide (YZO) or indium gallium zinc oxide (IGZO).

[0037] In some embodiments, a plurality of semiconductor layers 101 are arranged at intervals from each other in a first horizontal direction X, a second horizontal direction Y, and a vertical direction Z.

[0038] In some embodiments, each semiconductor layer 101 includes a first source-drain region, a channel region, and a second source-drain region arranged sequentially along a first horizontal direction X. In this transistor, the first source-drain region, the channel region, and the second source-drain region all have the same doping type, meaning the transistor is a junction-less transistor. Here, "junction-less" refers to the absence of a PN junction, meaning the transistor composed of semiconductor layer 101 does not have a PN junction. The advantages of this include: firstly, it eliminates the need for additional doping of the first and second source-drain regions, thus avoiding the problem of difficult-to-control doping processes for these regions. This is especially true as transistor sizes shrink further, as additional doping of the first and second source-drain regions would make doping concentration even more difficult to control. Secondly, since the device is a junction-less transistor, it is beneficial to avoid the phenomenon of creating ultra-steep PN junctions at the nanoscale using ultra-steep source-drain concentration gradient doping processes. This avoids problems such as threshold voltage drift and increased leakage current caused by abrupt doping changes, and also helps suppress short-channel effects, allowing it to still operate at a scale of a few nanometers. Therefore, it helps to further improve the integration density and electrical performance of the semiconductor structure. It is understandable that the additional doping here refers to doping performed to make the dopant ion types in the first and second source / drain regions different from the dopant ion types in the channel region.

[0039] In some embodiments, the doping types of the first and second source-drain regions differ from those of the channel region; that is, the transistor is a junction transistor. Junction transistors can have higher current drive capability, higher input impedance, and a higher rate of change of drain current with gate voltage, thus providing controllable gate-source bias. The drain current can be controlled by changing the gate voltage. Junction transistors have high input impedance, low noise figure, and maintain a linear relationship within a certain range, thereby improving signal accuracy.

[0040] In some embodiments, the first source-drain region is one of the source region or the drain region, and the second source-drain region is the other of the source region or the drain region.

[0041] In some embodiments, the channel region includes one of nanowires, nanosheets, or fin structures. Nanowires refer to cylindrical / square pillars with small cross-sections and similar dimensions in all directions. Setting the channel region as a nanowire structure allows the word line structure 110 to surround the channel region, forming a vertically surrounding gate channel. Nanosheets are flat, elongated sheets with a width much greater than their thickness. This allows the word line structure 110 to surround the channel region while simultaneously stacking more semiconductor layers 101 vertically, forming more transistors and improving overall integration. Fin structures refer to word line structures 110 covering a portion of the channel region's surface. Specifically, for the portion of the semiconductor layer 101 near the substrate, a fin structure allows the word line structure 110 to partially enclose the channel region, suppressing short-channel effects and allowing for higher density arrangement.

[0042] It should be noted that the overall shape of the semiconductor layer 101 can be configured like the channel region, and the overall cross-section along the vertical direction can be approximately the same. For example, the cross-sections of the first source / drain region, the channel region, and the second source / drain region are all nanosheets. In other embodiments, the overall shape of the semiconductor layer 101 can be different, such as a dumbbell-shaped structure. The channel region is etched to form one of nanowires, nanosheets, or fin structures. The cross-sectional pattern size of the first source / drain region and the second source / drain region is larger to achieve a larger contact area and a smaller contact resistance.

[0043] In some embodiments, a plurality of semiconductor layers 101 are arranged alternately in a mirror-symmetric manner in a first horizontal direction X. The mirror-symmetric alternating arrangement allows adjacent layers to share source-drain contacts or bit lines, reducing unnecessary isolation space and thus saving chip area.

[0044] Bit line structure 120 is the data transmission path between the memory cell and the external circuit, responsible for reading stored information or writing new data.

[0045] Multiple bit line structures 120 are arranged at intervals in the first horizontal direction X and the second horizontal direction Y, respectively. The bit line structures 120 extend in the vertical direction Z and are coupled to the first source and drain regions of multiple semiconductor layers 101. Vertical interconnection is achieved, thereby transferring the bit lines that originally occupied a large area in the plane to the vertical direction, avoiding the need for complex peripheral circuit wiring to occupy array area.

[0046] In some embodiments, the bit line structure 120 is a metallic bit line, and the material of the bit line structure 120 can be metals such as tungsten, copper, molybdenum, and silver. Metals have low resistance, which is beneficial for improving the conductivity between the bit line structure 120 and the first source / drain region. In other embodiments, the bit line structure 120 can be a semiconductor bit line, and the material of the semiconductor bit line can be silicon, germanium, germanium-silicon, silicon carbide, or polycrystalline silicon. Furthermore, the semiconductor bit line is doped with the same type of dopant element as the first source / drain region. The dopant element can act as a charge carrier, which can improve the migration and diffusion of charge carriers between the bit line structure 120 and the first source / drain region, thus improving the conductivity between the bit line structure 120 and the first source / drain region.

[0047] The word line structure 110 is used to select a specific row of memory cells and control the turn-on / turn-off of transistors. The working principle is as follows: when a voltage is applied to the word line structure 110, the gates of all transistors in that row are activated (such as MOSFETs being turned on), connecting the bit line to the memory cell.

[0048] Multiple character line structures 110 are arranged at intervals in the vertical direction Z and the second horizontal direction Y, and the character line structures 110 extend along the second horizontal direction Y.

[0049] In some embodiments, the word line structure 110 is opposite to the channel region; the word line structure 110 serves as the gate of the semiconductor structure, and the word line surrounds the active portion to form a gate-all-around (GAA) transistor structure, which can largely solve the problems of leakage current, capacitance effect and short channel effect caused by the reduction of gate pitch size, reduce the area occupied by the word line structure 110 in the vertical direction, and help to enhance gate control performance and improve the integration of the semiconductor structure.

[0050] In some embodiments, the word line structure 110 includes a first tunneling layer 111, a charge trapping layer 112, a second tunneling layer 113, and a control layer 129 arranged sequentially, wherein the first tunneling layer 111 is located between the channel region and the charge trapping layer 112.

[0051] The first tunneling layer 111, located near the channel region, is primarily used during programming (writing): When a positive voltage is applied to the control layer 129, electrons in the channel tunnel through this thin layer via FN tunneling (Fowler-Nordheim tunneling) or channel hot electron injection, entering the charge trapping layer 112. During erasure: When a negative voltage is applied to the control layer 129, holes tunnel from the channel into the charge trapping layer 112 to neutralize electrons; or electrons are pulled back into the channel. During the erase operation, electrons in the charge trapping layer 112 are prevented from flowing back into the channel region.

[0052] In some embodiments, the material of the first tunneling layer 111 includes silicon oxide.

[0053] The charge trap layer 112 is located between the first tunneling layer 111 and the second tunneling layer 113, and mainly serves as the data storage medium. The charge trap layer 112 has a high density of defect energy levels. When electrons pass through the first tunneling layer 111, they are captured and fixed by these defects. Due to the high potential barrier of these energy levels, even after the power is turned off, the captured electrons cannot escape, thus achieving long-term data storage.

[0054] In some embodiments, the charge trapping layer 112 includes a silicon nitride layer, a silicon-rich silicon nitride layer, or a composite silicon nitride layer, wherein the composite silicon nitride layer contains alumina, hafnium oxide, or a composite layer of silicon nitride and a high-k dielectric material; the high-k material includes alumina or hafnium oxide. For example, the principle of the silicon nitride layer is that silicon nitride contains a large number of dangling bonds and defects, which are very suitable for trapping electrons.

[0055] The second tunneling layer 113 is located between the charge trapping layer 112 and the control layer 129. It mainly acts as a barrier layer: during programming, the voltage applied to the control layer 129 is very high, and the function of this layer is to prevent electrons in the charge trapping layer 112 from tunneling directly to the control layer 129.

[0056] In some embodiments, the material of the second tunneling layer 113 includes silicon oxide. The material of the second tunneling layer 113 may also be a high dielectric constant material or an alumina / silicon dioxide stack.

[0057] The control layer 129 is located on the outermost layer of the word line structure 110 and is in contact with the metal gate. The function of the control layer 129 is to receive programming, erasing, or reading voltages from the word line structure 110.

[0058] In some embodiments, the control layer 129 can be made of a metal, such as any one of tungsten, tantalum, molybdenum, titanium nitride, or tantalum nitride, forming a metal gate. Because metal gates can avoid the depletion effect of polysilicon and provide a suitable work function, they are beneficial for reducing power consumption and increasing operating speed.

[0059] In some embodiments, the bit line structure 120 extends vertically and directly couples to the first source and drain regions of each layer, while the word line structure 110 surrounds the channel region, i.e., a gate-around-around (GAA) structure is adopted. Compared to planar transistors, GAA can better control the channel and effectively suppress short-channel effects. With the word line structure 110 extending horizontally and the bit line structure 120 extending vertically, the semiconductor structure forms a layout similar to a three-dimensional intersecting dot matrix. Each memory cell is located at the intersection of the word line and the bit line. This array structure is regular and compact, thereby achieving extremely high integration density.

[0060] In some embodiments, the word line structure 110 is located on one side of the channel region and is a single-gate structure. In other embodiments, the word line structure includes two word lines, which are located on opposite sides of the channel region, forming a double-gate structure.

[0061] In some embodiments, the system further includes: a connection structure 124, arranged at intervals between each other in a first direction and a second horizontal direction, the connection structure 124 extending along the first direction, and the connection structure 124 coupling to the second source-drain regions of a plurality of semiconductor layers 101. The connection structure 124 is a source line (SL) of the semiconductor structure, which is used to provide a reference potential and current path for readout operations.

[0062] The material of the connecting structure 124 can be metals such as tungsten, copper, molybdenum, and silver.

[0063] In some embodiments, the connection structure 124 is coupled to the second source and drain regions of a plurality of semiconductor layers 101 that are mirror-symmetrical along a first horizontal direction. Thus, in a 3D array, by providing the connection structure 124 to connect the second source and drain regions of multiple sets of semiconductor layers 101 that are symmetrically arranged horizontally, the source line of a single transistor can be greatly reduced, thereby reducing the area of ​​metal contacts and improving integration density.

[0064] In some embodiments, the connection structure 124 and the bit line structure 120 are mirror-symmetrical along the axis of the semiconductor layer.

[0065] In some embodiments, the semiconductor structure further includes a sixth isolation layer 123 located on the side of the word line structure 110. A first isolation layer 104 is present on the surface of the substrate 100 and is located on the word line structure.

[0066] In some embodiments, the semiconductor structure further includes: a word line isolation layer 117, located between word line structures 110 arranged in a vertical direction. The semiconductor structure also includes: a fourth sacrificial layer 118, located on the side of the control layer 129 and between the word line isolation layer 117 and the second tunneling layer 113. The semiconductor structure further includes: a fifth sacrificial layer 119, located on the side of the charge trapping layer 112 and between the first tunneling layer 111 and the second tunneling layer 113. The semiconductor structure further includes: a sixth sacrificial layer 121, located on the surface of the first isolation layer 104.

[0067] refer to Figure 3 , Figure 3 This is a circuit diagram of a semiconductor structure, including multiple transistors, multiple bit line structures 120 (Bit0~Bit7), and multiple word line structures 110 (Word1~Word3). The drain terminals of the transistors are coupled to the bit line structures 120, and the source terminals of the transistors are coupled to the source lines. The programming mechanism is as follows: a set of word line structures 110 and bit line structures 120 are selected; a programming voltage is applied to the control layer 129 of the word line structure 110, and a first voltage is applied to the bit line structure 120. A voltage difference is formed between the word line structure 110 and the bit line structure 120, creating a strong vertical electric field between the first tunneling layer 111 and the second tunneling layer 113. The source lines are grounded or at a low voltage. The strong vertical electric field causes electrons in the channel region to tunnel through the first tunneling layer 111 via Fowler-Nordheim (FN) tunneling and enter the charge trap layer 112, where they are captured and stored. The reading mechanism involves selecting a set of word line structures 110 and bit line structures 120, applying a reading voltage to the control layer 129 of the word line structure 110, applying a bias voltage to the bit line structure 120, grounding the source line, and detecting the conduction current in the channel region. If the current is large, a "1" is read; if the current is small, a "0" is read. The erasing mechanism involves selecting a set of word line structures 110 and bit line structures 120, applying a high negative voltage to the control layer 129 of the word line structure 110, and grounding or connecting the bit line structure 120 and the source line to an intermediate potential. The electric field direction of the strong vertical electric field is reversed, and the electrons captured by the charge trap layer 112 tunnel back to the channel region or the holes neutralize with the electrons.

[0068] refer to Figure 4 , Figure 4The semiconductor structure includes: multiple semiconductor layers 201, which are arranged at intervals in a first horizontal direction X, a second horizontal direction Y, and a vertical direction Z, respectively. Each semiconductor layer 201 includes a first source-drain region, a channel region, and a second source-drain region arranged sequentially along the first horizontal direction X. The multiple semiconductor layers 201 are arranged alternately in a mirror-symmetrical manner in the first horizontal direction; multiple bit line structures 220, which are arranged at intervals in the first horizontal direction X and the vertical direction Z, respectively. The bit line structures 220 extend along the second horizontal direction Y and are respectively coupled to the first source-drain regions of the multiple semiconductor layers 201; multiple word line structures 210, which are arranged at intervals in the first horizontal direction X and the second horizontal direction Y, respectively. The word line structures 210 extend along the vertical direction Z and surround the channel region; the word line structure 210 includes a first tunneling layer 211, a charge trapping layer 212, a second tunneling layer 213, and a control layer 229 arranged sequentially. The first tunneling layer 211 is located between the channel region and the charge trapping layer 212.

[0069] It should be noted that, Figure 4 The semiconductor structure shown is Figure 2 Their semiconductor structures are basically the same, the difference lies in Figure 2 In the semiconductor structure, the bit line structure 120 extends along the vertical direction Z, and the word line structure 110 extends along the second horizontal direction Y. Figure 4 The bit line structure 220 of the semiconductor structure extends along the second horizontal direction Y, and the word line structure 210 extends along the vertical direction Z.

[0070] therefore, Figure 4 Semiconductor layer 201, word line structure 210, bit line structure 220, first tunneling layer 211, charge trapping layer 212, second tunneling layer 213, control layer 229, interconnection structure 224, word line isolation layer 217 (reference) Figure 2 The description of the semiconductor layer 101, word line structure 110, bit line structure 120, first tunneling layer 111, charge trapping layer 112, second tunneling layer 113, control layer 129, interconnection structure 124, and word line isolation layer 117.

[0071] In some embodiments, the semiconductor structure includes an isolation layer 234 for isolating transistors that are spaced apart.

[0072] In some embodiments, Figure 4 The semiconductor structure shown includes a set of transistors arranged along a first horizontal direction. In some embodiments, the semiconductor structure may include multiple sets of transistors arranged along the first horizontal direction X, with adjacent transistors exhibiting a mirror-symmetric structure. The connection structure 224 may be coupled to one set of transistors or to two mirror-symmetric sets of transistors.

[0073] The semiconductor structure provided in this disclosure extends the memory array from a two-dimensional plane to a three-dimensional space by stacking multiple semiconductor layers 201, i.e., a 3D stacked structure. This achieves a memory cell number that is multiples of the number of stacked layers within the same planar area. The multiple semiconductor layers 201 are arranged alternately in a mirror-symmetrical manner in the first horizontal direction. This mirror-symmetrical alternation allows adjacent layers to share source-drain contacts or bit lines, reducing unnecessary isolation space and thus saving chip area. The bit line structure 220 extends along the second horizontal direction and directly couples to the first source-drain regions of each layer, achieving vertical interconnection. This allows the bit lines, which originally occupied a large area in the plane, to be moved vertically, avoiding the need for complex peripheral circuit wiring to occupy array area. The word line structure 210 surrounds the channel region, i.e., it adopts a gate-around-around (GAA) structure. Compared to planar transistors, GAA can better control the channel and effectively suppress short-channel effects. With word lines extending horizontally and bit lines extending vertically, the semiconductor structure forms a layout similar to a three-dimensional intersecting matrix. Each memory cell is located at the intersection of the word line and the bit line. This array layout is regular and compact, thus enabling extremely high integration density.

[0074] According to some embodiments of this disclosure, another aspect of this disclosure also provides a method for preparing a semiconductor structure, used to prepare the semiconductor structure provided in the above embodiments, so as to... Figure 2 The semiconductor structure shown is an example, and its technical features are the same or corresponding to those in the above embodiments, and will not be described in detail here.

[0075] Figures 5-23 This is a schematic diagram of the semiconductor structure corresponding to each step in a method for preparing a semiconductor structure according to an embodiment of the present disclosure.

[0076] refer to Figures 5-10 The fabrication method includes forming a plurality of semiconductor layers 101, which are arranged at intervals in a first horizontal direction X, a second horizontal direction Y, and a vertical direction Z. Each semiconductor layer 101 includes a first source-drain region, a channel region, and a second source-drain region arranged sequentially along the first horizontal direction. The plurality of semiconductor layers 101 are arranged alternately in a mirror-symmetrical manner in the first horizontal direction.

[0077] refer to Figure 5 and Figure 6 The preparation method includes: providing a substrate 100, the surface of which has a first isolation layer 104.

[0078] The material of the first isolation layer 104 can be silicon oxide.

[0079] Continue to refer to Figure 6The preparation method includes: forming a stacked semiconductor layer 101 and a first sacrificial layer 102 on a substrate, wherein the semiconductor layer 101 and the first sacrificial layer 102 are located within a first isolation layer 104.

[0080] The material of the first sacrificial layer 102 can be germanium-silicon.

[0081] The process steps for forming semiconductor layer 101 include: (refer to...) Figure 5 A first trench is formed, and a second isolation layer 103 is filled in the first trench. The second isolation layer 103 causes the semiconductor layers 101 to be spaced apart along the second horizontal direction Y, so that the semiconductor layers 101 can be arranged spaced apart along the second horizontal direction Y in subsequent processes.

[0082] refer to Figure 6 A portion of the first sacrificial layer 102 is etched back to expose a portion of the semiconductor layer 101, which is subsequently used to form the channel region.

[0083] Reference Figure 7 and Figure 8 The fabrication method includes: forming a second trench by a patterned semiconductor layer 101 and a first sacrificial layer 102; forming a second filling layer 106 and a third filling layer 107 in the second trench, wherein the second filling layer 106 is silicon nitride and the third filling layer 107 is polysilicon.

[0084] The second trench penetrates the semiconductor layer 101 and the first sacrificial layer 102 and also penetrates a portion of the substrate.

[0085] After forming the second trench, the process further includes: forming a third isolation layer 105, which is located on the first isolation layer 104; forming a third trench, which is filled with a second filling layer 106 and a third filling layer 107, and the third trench is located between two adjacent semiconductor layers 101. The second trench located at the semiconductor layer 101 is used to form a bit line structure 120, and the third trench located between two adjacent semiconductor layers 101 is used to form a connection structure 124.

[0086] The material of the third isolation layer 105 includes silicon nitride.

[0087] refer to Figure 9 The fabrication method includes: forming a first groove 108 by a patterned semiconductor layer 101 and a first sacrificial layer 102. Specifically, this involves removing a second filling layer 106 and a third filling layer 107 located within a second trench, wherein the second trench is defined as the first groove 108.

[0088] Continue to refer to Figure 9 The preparation method also includes: removing the third isolation layer 105.

[0089] refer to Figure 10The preparation method includes: removing the first sacrificial layer 102 along the first groove 108, and removing a portion of the width of the semiconductor layer 101.

[0090] Continue to refer to Figure 10 The preparation method includes: continuing to etch along the region of the removed first sacrificial layer 102 in the second horizontal direction Y to remove part of the second isolation layer 103 until two adjacent regions in the second horizontal direction Y are penetrated.

[0091] refer to Figures 11-21 The fabrication method includes: forming a plurality of bit line structures 120, which are arranged at intervals in a first horizontal direction X and a second horizontal direction Y, and extend along a vertical direction Z, and are respectively coupled to the first source and drain regions of a plurality of semiconductor layers 101; forming a plurality of word line structures 110, which are arranged at intervals in a vertical direction Z and a second horizontal direction Y, and extend along a second horizontal direction Y, and surround a channel region; the word line structure 110 includes a first tunneling layer 111, a charge trapping layer 112, a second tunneling layer 113 and a control layer 129 arranged sequentially, wherein the first tunneling layer 111 is located between the channel region and the charge trapping layer 112.

[0092] refer to Figures 11-13 The preparation method includes: sequentially forming a first tunneling layer 111, a second sacrificial layer 114, a second tunneling layer 113, a connection film, and a word line isolation layer between adjacent semiconductor layers.

[0093] refer to Figure 11 The preparation method includes forming a first tunneling film 109 on the outer wall surface of the first groove 108, the semiconductor layer 101, and the outer wall surface of the first isolation layer 104.

[0094] refer to Figure 12 The preparation method includes: forming a second sacrificial layer 114 and a third sacrificial layer 115 sequentially on the surface of the first tunneling membrane 109, wherein the third sacrificial layer 115 is located on the surface of the second sacrificial layer 114.

[0095] refer to Figure 13 The preparation method includes: forming a connecting film 116 and a word line isolation layer 117.

[0096] Continue to refer to Figure 13 The preparation method includes: etching back the connecting film 116.

[0097] refer to Figure 14 The preparation method includes: forming a fourth sacrificial layer 118, which is located between the third sacrificial layer 115 and the word line isolation layer 117, and is located on the side of the connecting film 116.

[0098] Continue to refer to Figure 14 The preparation method includes: removing the third sacrificial layer 115 located in the first groove 108 to expose the side of the second sacrificial layer 114.

[0099] refer to Figure 15 The preparation method includes: removing the second sacrificial layer 114 located in the first groove 108 and etching back a portion of the width of the second sacrificial layer 114.

[0100] refer to Figure 16 The preparation method includes: forming a fifth sacrificial layer 119, which is located on the side of the second sacrificial layer 114 and on the side of the first tunneling membrane 109.

[0101] refer to Figure 17 The preparation method includes: removing the first tunneling film 109 and the fifth sacrificial layer 119 located in the first groove 108, so that the side of the semiconductor layer 101 is exposed.

[0102] refer to Figure 18 The fabrication method includes: forming a plurality of bit line structures 120, wherein the bit line structures 120 extend along the vertical direction Z and are respectively coupled to the first source and drain regions of a plurality of semiconductor layers 101.

[0103] refer to Figure 19 The preparation method includes: forming a sixth sacrificial layer 121, wherein the sixth sacrificial layer 121 is located on the surface of the first isolation layer 104.

[0104] Continue to refer to Figure 19 The fabrication method includes: removing the second filling layer 106 and the third filling layer 107 in the third trench, and continuing to etch based on the region of the third trench until the other end of the semiconductor layer 101 is near or exposed.

[0105] refer to Figure 20 The fabrication method includes: patterning a semiconductor layer 101 and a first isolation layer 104 to form a second groove 122, wherein the second groove 122 does not overlap with the first groove 108. The side of the second groove 122 exposes the side of the first tunneling film 109.

[0106] refer to Figure 21 The preparation method includes: the connecting film 116 is located on the inner wall surface of the first groove 108, the second groove 122 exposes the side surface of the connecting film 116, and the connecting film 116 is etched along the second groove 122 to form two spaced control layers 129.

[0107] Continue to refer to Figure 21 as well as Figure 22 The preparation method includes: etching the first tunneling film 109 along the second groove 122 to form a first tunneling layer 111 and a second tunneling layer 113.

[0108] Continue to refer to Figure 21 The preparation method includes: removing the second sacrificial layer 114.

[0109] refer to Figure 22 The preparation method includes: forming a charge trapping layer 112 and a connecting film 116 as a control layer 129.

[0110] refer to Figure 23 The preparation method includes: forming a sixth isolation layer 123, wherein the sixth isolation layer 123 is located on the side of the word line structure 110.

[0111] refer to Figure 2 The preparation method includes: forming a connection structure 124, which is arranged at intervals with each other in a first direction and a second horizontal direction, the connection structure 124 is located in a second groove 122, and the connection structure 124 is coupled to the second source and drain regions of a plurality of semiconductor layers 101.

[0112] Accordingly, according to some embodiments of the present disclosure, another aspect of the present disclosure also provides an electronic device, including a processing device and a storage device, wherein the storage device includes a semiconductor structure as described in any one of the above embodiments or a semiconductor structure prepared by the method described in any one of the above embodiments.

[0113] The processing device can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0114] Storage devices can be used to store computer programs and / or modules. Processing devices implement various functions of electronic devices by running or executing computer programs and / or modules stored in the storage devices and by accessing data stored in the storage devices. Storage devices can primarily include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a function, etc.; the data storage area may store data created based on the use of the terminal device, etc. Furthermore, storage devices may include high-speed random access memory, and may also include non-volatile memory, such as hard disks, RAM, plug-in hard disks, smart media cards (SMC), secure digital cards (SD cards), flash cards, at least one disk storage device, flash memory device, or other volatile solid-state storage devices.

[0115] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Multiple semiconductor layers are arranged at intervals in a first horizontal direction, a second horizontal direction, and a vertical direction, wherein the multiple semiconductor layers in the first horizontal direction are arranged alternately in a mirror-symmetrical manner, and each semiconductor layer includes a first source-drain region, a channel region, and a second source-drain region arranged sequentially along the first horizontal direction. Multiple bit line structures are arranged at intervals in a second direction and a second horizontal direction, respectively. The bit line structures extend along a first direction and are respectively coupled to the first source and drain regions of multiple semiconductor layers. Multiple character line structures are arranged at intervals in the first direction and the second horizontal direction, respectively. The character line structures extend along the second direction and are located on the channel area. The first direction is either a second horizontal direction or a vertical direction that intersects the first horizontal direction, and the second direction is either the second horizontal direction or the vertical direction. The word line structure includes a first tunneling layer, a charge trapping layer, a second tunneling layer, and a control layer arranged sequentially, wherein the first tunneling layer is located between the channel region and the charge trapping layer.

2. The semiconductor structure according to claim 1, characterized in that, The material of at least one of the first tunneling layer and the second tunneling layer includes silicon oxide.

3. The semiconductor structure according to claim 1, characterized in that, Also includes: Multiple connection structures are arranged at intervals in the first direction and the second horizontal direction, respectively. The connection structures extend along the first direction and are coupled to the second source and drain regions of the multiple semiconductor layers.

4. The semiconductor structure according to claim 3, characterized in that, The connection structure is coupled to the second source / drain regions of a plurality of semiconductor layers that are mirror-symmetrical along the first horizontal direction.

5. The semiconductor structure according to claim 4, characterized in that, The connection structure and the bit line structure are mirror-symmetrical along the axis of the semiconductor layer.

6. The semiconductor structure according to claim 1, characterized in that, The charge trapping layer includes a silicon nitride layer, a silicon-rich silicon nitride layer, or a composite layer composed of silicon nitride and a high-k dielectric material; the high-k dielectric material includes aluminum oxide or hafnium oxide.

7. The semiconductor structure according to claim 1, characterized in that, The word line structure surrounds the channel area.

8. A method for fabricating a semiconductor structure, characterized in that, include: Multiple semiconductor layers are formed and arranged at intervals in a first horizontal direction, a second horizontal direction, and a vertical direction, wherein the multiple semiconductor layers in the first horizontal direction are arranged alternately in a mirror-symmetrical manner, and each semiconductor layer includes a first source-drain region, a channel region, and a second source-drain region arranged sequentially along the first horizontal direction. Multiple bit line structures are formed and arranged at intervals between each other in the second direction and the second horizontal direction. The bit line structures extend along the first direction and are respectively coupled to the first source and drain regions of multiple semiconductor layers. Multiple word line structures are formed and arranged at intervals in the first direction and the second horizontal direction, respectively. The word line structures extend along the second direction and are located on the channel region. The first direction is either a second horizontal direction or a vertical direction that intersects the first horizontal direction, and the second direction is either the second horizontal direction or the vertical direction. The word line structure includes a first tunneling layer, a charge trapping layer, a second tunneling layer, and a control layer arranged sequentially. The first tunneling layer is located between the channel region and the charge trapping layer.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The process steps for forming the word line structure include: providing a substrate; forming a stacked semiconductor layer and a first sacrificial layer on the substrate; patterning the semiconductor layer and the first sacrificial layer to form a first groove; removing the first sacrificial layer along the first groove and removing a portion of the width of the semiconductor layer; sequentially forming a first tunneling layer, a second sacrificial layer, a second tunneling layer, a connection film, and a word line isolation layer between adjacent semiconductor layers; patterning the semiconductor layer to form a second groove, the second groove not overlapping the first groove; removing the second sacrificial layer to form a charge trapping layer, the connection film serving as a control layer.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The connecting membrane is located on the inner wall of the first groove, and the second groove exposes the side of the connecting membrane. The connecting membrane is etched along the second groove to form two spaced control layers.

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