Semiconductor structure and method of fabricating the same

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a semiconductor structure and a manufacturing method thereof, wherein the manufacturing method of the semiconductor structure comprises the following steps: providing a substrate; forming a plurality of semiconductor channels arranged in an array along a first direction and a second direction on the substrate; forming a plurality of bit lines extending along the first direction, the bit lines being in the substrate, and each bit line being electrically connected with the plurality of semiconductor channels arranged along the first direction; forming a plurality of word lines extending along the second direction, each word line wrapping around part of side surfaces of the plurality of semiconductor channels arranged along the second direction, wherein, along the first direction, two adjacent word lines are arranged at intervals in a direction perpendicular to the surface of the substrate; and forming a sidewall conductive layer, the sidewall conductive layer being located above one of the two adjacent word lines, and the sidewall conductive layer being arranged in the same layer as the other one of the two adjacent word lines. The semiconductor structure can reduce the coupling effect between adjacent word lines.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and particularly to semiconductor structures and methods of fabrication thereof. Background Technology

[0002] As the integration density of dynamic memory continues to increase, while researching the arrangement of transistors in dynamic memory array structures and how to reduce the size of individual functional devices in dynamic memory array structures, it is also necessary to improve the electrical performance of small-sized functional devices.

[0003] When using a vertical gate-all-around (GAA) transistor structure as a dynamic memory select transistor (access transistor), its area can reach 4F. 2 (F: the minimum feature size that can be obtained under given process conditions), in principle, higher density efficiency can be achieved.

[0004] However, there is currently a problem of strong coupling effect between adjacent character lines. Summary of the Invention

[0005] This disclosure provides a semiconductor structure and a method for fabricating the same, which can at least reduce the coupling effect between adjacent word lines.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate; forming a plurality of semiconductor channels arranged in an array along a first direction and a second direction on the substrate; forming a plurality of bit lines extending along the first direction, the bit lines being located within the substrate, and each bit line being electrically connected to the plurality of semiconductor channels arranged along the first direction; forming a plurality of word lines extending along the second direction, each word line wrapping around a portion of the side surface of the plurality of semiconductor channels arranged along the second direction, wherein two adjacent word lines in the first direction are spaced apart in a direction perpendicular to the surface of the substrate; forming a sidewall conductive layer, the sidewall conductive layer being located above one of the two adjacent word lines, and the sidewall conductive layer being disposed in the same layer as the other of the two adjacent word lines.

[0007] In some embodiments, the plurality of semiconductor channels includes: a plurality of first channel groups, each of the first channel groups including a plurality of first semiconductor channels arranged along a second direction; a plurality of second channel groups, each of the second channel groups including a plurality of second semiconductor channels arranged along the second direction, and the plurality of first channel groups and the plurality of second channel groups are alternately arranged in the first direction; the plurality of word lines includes: a plurality of first word lines extending along the second direction, each first word line wrapping around a portion of the side surface of a semiconductor channel in a column of the first channel groups; a plurality of second word lines extending along the second direction, each second word line wrapping around a portion of the side surface of a semiconductor channel in a column of the second channel groups, and the distance between the bottom surface of the second word line and the substrate surface is greater than the distance between the bottom surface of the first word line and the substrate surface; forming the plurality of word lines includes: forming the first word lines; and forming the second word lines.

[0008] In some embodiments, forming the first word line includes: forming a first groove that exposes a portion of the sidewall of the first semiconductor channel; forming a first initial word line that fills the first groove; and etching back the first initial word line, leaving the remaining first initial word line as the first word line.

[0009] In some embodiments, forming the first groove includes: forming a first sidewall layer that covers sidewalls of the semiconductor channel spaced along the first direction; forming a mask layer that covers the second semiconductor channel and the first sidewall layer located on the sidewall of the second semiconductor channel; and patterning the first sidewall layer with the mask layer as a mask to form the first groove.

[0010] In some embodiments, the second word line and the sidewall conductive layer are formed simultaneously. Forming the second word line and the sidewall conductive layer includes: forming a first capping layer located on the top surface of the first word line; forming a first isolation layer located between adjacent semiconductor channels, with the top surface of the first isolation layer higher than the top surface of the first word line; forming a second sidewall layer covering the sidewall of the first capping layer and the sidewall of the second semiconductor channel; forming a second isolation layer located on the top surface of the first isolation layer, with one sidewall of the second isolation layer contacting the second sidewall layer covering the sidewall of the first capping layer, and the other sidewall contacting the second sidewall layer of the sidewall of the second semiconductor channel; etching back the second sidewall layer to form a second groove; forming the second word line and the sidewall conductive layer, wherein the second word line and the sidewall conductive layer are located in different second grooves.

[0011] In some embodiments, after forming the second letter line, the method further includes forming a second cover layer located on the top surface of the second letter line.

[0012] In some embodiments, the character line that is closer to the substrate surface among two adjacent character lines in the first direction is defined as the lower character line, and the character line that is farther from the substrate surface among two adjacent character lines is defined as the upper character line. The bottom surface of the upper character line is located on the side of the top surface of the lower character line away from the substrate surface. During the formation of the character line, the distance between the top surface of the lower character line and the bottom surface of the upper character line is controlled to be greater than or equal to 3nm and less than or equal to 10nm.

[0013] In some embodiments, the semiconductor channel includes a first doped region, a channel region, and a second doped region arranged in sequence, wherein the first doped region is electrically connected to the bit line, and the first doped region, the channel region, and the second doped region have the same doping type.

[0014] In some embodiments, forming the plurality of semiconductor channels arranged in an array along the first direction and the second direction on the substrate includes: patterning the substrate to form a plurality of initial semiconductor channels spaced apart along the second direction; and patterning the plurality of initial semiconductor channels to form the plurality of semiconductor channels spaced apart along both the first direction and the second direction.

[0015] In some embodiments, the semiconductor channel is made of silicon, and the plurality of bit lines are formed using a silicon metallization process.

[0016] According to some embodiments of this disclosure, another aspect of this disclosure provides a semiconductor structure, including: a substrate and a plurality of semiconductor channels arranged in an array along a first direction and a second direction on the substrate; a plurality of bit lines extending along the first direction, the bit lines being located within the substrate, and each bit line being electrically connected to the plurality of semiconductor channels arranged along the first direction; a plurality of word lines extending along the second direction, each word line wrapping around a portion of the side surface of the plurality of semiconductor channels arranged along the second direction, wherein, along the first direction, two adjacent word lines are spaced apart in a direction perpendicular to the surface of the substrate; a sidewall conductive layer, the sidewall conductive layer being located above one of two adjacent word lines, and the sidewall conductive layer being disposed in the same layer as the other of the two adjacent word lines.

[0017] In some embodiments, the plurality of semiconductor channels include: a plurality of first channel groups, each of the first channel groups including a plurality of first semiconductor channels arranged along a second direction; a plurality of second channel groups, each of the second channel groups including a plurality of second semiconductor channels arranged along the second direction, and the plurality of first channel groups and the plurality of second channel groups are alternately arranged in the first direction; the plurality of word lines include: a plurality of first word lines extending along the second direction, each first word line wrapping around a portion of the side surface of a semiconductor channel in a column of the first channel group; a plurality of second word lines extending along the second direction, each second word line wrapping around a portion of the side surface of a semiconductor channel in a column of the second channel group, and the distance between the bottom surface of the second word line and the substrate surface is greater than the distance between the bottom surface of the first word line and the substrate surface.

[0018] In some embodiments, the bottom surface of each of the first character lines is flush with the top surface of each of the first character lines; the bottom surface of each of the second character lines is flush with the top surface of each of the second character lines.

[0019] In some embodiments, the multiple first word lines are made of the same material; the multiple second word lines are made of the same material.

[0020] In some embodiments, the first letter line and the second letter line are made of different materials.

[0021] In some embodiments, the semiconductor structure further includes: a first capping layer located on the top surface of the first word line; a second capping layer located on the top surface of the second word line; and a sidewall conductive layer disposed in the same layer as the second word line and located on the side of the first capping layer, wherein the material of the sidewall conductive layer is the same as the conductive material in the second word line.

[0022] In some embodiments, the semiconductor structure further includes: a first isolation layer located between adjacent first word lines and second word lines, the top surface of the first isolation layer being higher than the top surface of the first word lines; and a second isolation layer located on the top surface of the first isolation layer, and also located on the side of the second word lines and the side of the second capping layer.

[0023] In some embodiments, the character line that is closer to the base surface among two adjacent character lines in the first direction is defined as the lower character line, and the character line that is farther from the base surface among two adjacent character lines is defined as the upper character line, wherein the bottom surface of the upper character line is located on the side of the top surface of the lower character line away from the base surface.

[0024] In some embodiments, in a direction perpendicular to the substrate surface, the distance between the top surface of the lower character line and the bottom surface of the upper character line is greater than or equal to 3 nm and less than or equal to 10 nm.

[0025] In some embodiments, each of the letter lines has the same size in a direction perpendicular to the substrate surface.

[0026] The technical solution provided by the embodiments of this disclosure has at least the following advantages: by arranging adjacent word lines at intervals in a direction perpendicular to the substrate surface, the spacing between adjacent word lines is increased, thereby reducing the coupling effect between adjacent word lines; and by setting word lines to wrap around the sides of multiple semiconductor channel layers arranged along the second direction to form a fully surrounding gate transistor structure, the formation of a sidewall conductive layer can play a shielding role. Attached Figure Description

[0027] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A top view of a semiconductor structure provided in an embodiment of this disclosure;

[0029] Figures 2 to 16 This is a schematic diagram of the structure corresponding to each step of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0030] Figure 17 A cross-sectional view of a semiconductor structure is provided as an embodiment of this disclosure. Detailed Implementation

[0031] As the background technology shows, with the continuous miniaturization of integration, the distance between adjacent word lines is becoming smaller and smaller. When the distance between adjacent word lines is small enough, when one word line is turned on for cell selection, the adjacent word lines will also be turned on due to the small distance between them. This may lead to signal transmission errors or even read / write failures. The effect of one word line affecting another word line is called the coupling effect between word lines.

[0032] This disclosure provides a method for fabricating a semiconductor structure. After forming a substrate, semiconductor channels, and bit lines, the spacing between adjacent word lines can be increased by arranging them at intervals in a direction perpendicular to the substrate surface. Correspondingly, the increased spacing between word lines improves the insulation performance between adjacent word lines, thereby improving the coupling effect between adjacent word lines. Furthermore, the provision of a sidewall conductive layer can also achieve a shielding effect, thereby improving the reliability of the semiconductor structure.

[0033] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0034] refer to Figure 1 and Figure 2 , Figure 1 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure. Figure 2 A semiconductor structure fabrication method provided in this disclosure embodiment is as follows: Figure 1 Cross-sectional views along the AA, BB, CC and DD directions.

[0035] refer to Figure 1 The system provides a substrate 100; a plurality of semiconductor channels 110 arranged in an array along a first direction X and a second direction Y are formed on the substrate 100; a plurality of bit lines 120 extending along the first direction X are formed, the bit lines 120 are located within the substrate 100, and each bit line 120 is electrically connected to the plurality of semiconductor channels 110 arranged along the first direction X; a plurality of word lines 130 extending along the second direction Y are formed, each word line 130 wraps around a portion of the side surface of the plurality of semiconductor channels 110 arranged along the second direction Y, wherein, along the first direction X, two adjacent word lines 130 are spaced apart in a direction perpendicular to the surface of the substrate 100.

[0036] Understandable Figure 1 This is a top view of the semiconductor structure. In the top view, adjacent word lines 130 are not shown to be spaced apart in the direction perpendicular to the surface of the substrate 100. However, in reality, two adjacent word lines 130 are spaced apart in the direction perpendicular to the surface of the substrate 100.

[0037] For example, refer to Figure 2 A substrate 100 is provided. In some embodiments, the material type of the substrate 100 can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanide, gallium arsenide, or gallium arsenide indium, etc.

[0038] refer to Figure 3 and Figure 4 , Figure 3 and Figure 4 A method for fabricating a semiconductor structure provided in this disclosure embodiment Figure 2 A cross-sectional view of the basic manufacturing steps.

[0039] refer to Figure 3 and Figure 4 Multiple semiconductor channels 110 are arranged in an array along the first direction X and the second direction Y.

[0040] For example, refer to Figure 3 It includes: a patterned substrate 100 to form a plurality of initial semiconductor channels 111 spaced apart along a second direction.

[0041] In some embodiments, an initial semiconductor channel 111 can be formed by forming a mask on the surface of the substrate 100 and then patterning the substrate 100 by etching the mask.

[0042] In some embodiments, after forming the initial semiconductor channels 111, the grooves between the initial semiconductor channels 111 are filled to form an isolation structure 101, for example, an oxide may be used for filling. The isolation structure 101 may be referred to as a shallow trench isolation structure (STI).

[0043] refer to Figure 4 A plurality of initial semiconductor channels 111 are graphically represented to form a plurality of semiconductor channels 110 arranged at intervals along a first direction and a second direction, respectively.

[0044] In some embodiments, the semiconductor channel 110 can be formed by self-aligned double patterning (SADP) technology, which can make the formed semiconductor channel 110 more precise.

[0045] In some embodiments, after forming the initial semiconductor channel 111, a first mask layer 140 is formed on the top surface of the initial semiconductor channel 111, and the initial semiconductor channel 111 is etched downward along the first mask layer 140 to form semiconductor channels 110 spaced apart along both the first direction X and the second direction Y. For example, the first mask layer 140 is an oxide layer, which can be formed by depositing oxide on the top surface of the semiconductor channel 110 or by oxidizing part of the top surface of the semiconductor channel 110.

[0046] Semiconductor channel 110 includes a first doped region 112, a channel region 113, and a second doped region 114 arranged sequentially, with the first doped region 112 electrically connected to a bit line. For example, after forming semiconductor channel 110, it can be ion-doped to form the first doped region 112, channel region 113, and second doped region 114, with the doped ions being of the same type. By doping semiconductor channel 110 with the same type of ions, a junctionless transistor can be formed. A junctionless transistor is one in which the doped ions in the first doped region 112, channel region 113, and second doped region 114 are of the same type, for example, all doped ions are N-type ions. Furthermore, the doped ions in the first doped region 112, channel region 113, and second doped region 114 can be the same. Here, "junctionless" refers to the absence of a PN junction, meaning that the transistor formed by semiconductor channel 110 does not contain a PN junction. Because the device is a junctionless transistor, it avoids the phenomenon of fabricating ultra-steep PN junctions at the nanoscale using ultra-steep source-drain concentration gradient doping processes. This avoids problems such as threshold voltage drift and increased leakage current caused by abrupt doping changes, and also helps suppress short-channel effects, allowing it to operate at a scale of several nanometers. Therefore, it contributes to further improving the integration density and electrical performance of the semiconductor structure. It can be understood that the additional doping here refers to doping performed to ensure that the dopant ion types of the first doped region 112 and the second doped region 114 are different from the dopant ion types of the channel region 113.

[0047] In some embodiments, the first doped region 112 (i.e., the portion of the semiconductor channel 110 corresponding to the formation of the first doped region 112) can be ion implanted using a high-energy method, thereby increasing the ion concentration of the first doped region 112; then, the channel region 113 and the second doped region 114 (i.e., the portions of the semiconductor channel 110 corresponding to the formation of the channel region 113 and the second doped region 114) can be ion implanted using a low-energy method, thereby increasing the concentration of the channel region 113 and the second doped region 114; then, the concentration of the second doped region 114 can be increased by ion implanting the second doped region 114 (the portion of the semiconductor channel 110 corresponding to the formation of the second doped region 114), thereby increasing the concentration of the second doped region 114.

[0048] It should be noted that the substrate 100 may also be doped before the semiconductor channel 110 is formed, so that after the semiconductor channel 110 is formed, the semiconductor channel 110 has a first doped region 112, a channel region 113 and a second doped region 114 arranged in sequence.

[0049] In some embodiments, in a direction perpendicular to the base 100, the length of the channel region 113 is greater than or equal to the sum of the lengths of adjacent word lines, that is, the top surface of the channel region 113 is higher than or flush with the top surface of the word line above it, and the bottom surface of the channel region 113 is lower than or flush with the bottom surface of the word line below it.

[0050] refer to Figure 5 Multiple bit lines 120 extending along the first direction X are formed. The bit lines 120 are located within the substrate 100, and each bit line 120 is electrically connected to multiple semiconductor channels 110 arranged along the first direction X.

[0051] In some embodiments, a first sidewall layer 150 is formed on the sidewall of the first mask layer 140 and the semiconductor channel 110 before the bit line 120 is formed. By forming the first sidewall layer 150, the semiconductor channel 110 can be prevented from being affected when the bit line 120 is formed subsequently.

[0052] In some embodiments, the semiconductor channel material is silicon, and multiple bit lines 120 are formed using a silicon metallization process. For example, the method for forming the bit lines 120 may include: forming a metal layer (not shown in the figure), the metal layer filling the spaces between adjacent semiconductor channels 110 and the metal layers being spaced apart along a second direction; performing a first rapid thermal annealing process, a cleaning process (removing unreacted metal layers), and a second rapid thermal annealing process on the metal layer to form a metal silicide within the substrate 100, the metal silicide serving as the bit lines 120. That is, the bit lines 120 are formed using a metal silicide process. This metal silicide process can reduce the contact resistance of the bit lines 120 and reduce defects between the bit lines 120 and the substrate 100, thereby improving the performance of the semiconductor structure.

[0053] refer to Figures 6 to 15 , Figures 6 to 15 A method for fabricating a semiconductor structure provided in this disclosure embodiment Figure 5 A structural diagram of the basic production steps.

[0054] For example, the plurality of semiconductor channels 110 includes: a plurality of first channel groups, each of which includes a plurality of first semiconductor channels arranged along a second direction; a plurality of second channel groups, each of which includes a plurality of second semiconductor channels arranged along a second direction, and the plurality of first channel groups and the plurality of second channel groups are alternately arranged in a first direction; the plurality of word lines 130 includes: a plurality of first word lines 131 extending along a second direction, each first word line 131 wrapping around a portion of the side surface of a semiconductor channel 110 in a column of first channel groups; a plurality of second word lines 132 extending along a second direction, each second word line 132 wrapping around a portion of the side surface of a semiconductor channel 110 in a column of second channel groups, and the distance between the bottom surface of the second word line 132 and the surface of the substrate 100 is greater than the distance between the bottom surface of the first word line 131 and the surface of the substrate 100; forming the plurality of word lines 130 includes: forming the first word lines 131; and forming the second word lines 132.

[0055] By forming spaced-apart first word lines 131 and second word lines 132, the coupling effect between adjacent word lines 130 can be reduced. Forming spaced-apart first word lines 131 and second word lines 132 also increases the spacing between adjacent word lines 130 (i.e., adjacent first word lines 131 and / or adjacent second word lines 132) that are directly opposite each other in the same plane. Increasing the spacing between adjacent word lines 130 that are directly opposite each other in the same plane reduces the coupling effect between them, thereby preventing the activation of one word line 130 from causing the activation of the other word line 130, thus increasing the reliability of the semiconductor structure.

[0056] For example, refer to Figures 6 to 10 The step of forming the first word line 131 may include: forming a first groove 180, the first groove 180 exposing a portion of the side surface of the first semiconductor channel; forming a first initial word line 133, the first initial word line 133 filling the first groove 180; patterning the first initial word line 133, the remaining first initial word line 133 serving as the first word line 131. By first filling the first groove 180 to form the first initial word line 133, and then patterning to form the first word line 131, the top surface height of the formed first word line 131 can be better controlled, thereby avoiding the impact of insufficient space left for the sidewall conductive layer on the performance of the sidewall conductive layer.

[0057] For example, refer to Figures 6 to 8The step of forming the first groove 180 includes: forming a first sidewall layer 150, the first sidewall layer 150 covering the sidewalls of the semiconductor channel 110 spaced along a first direction; forming a mask layer 170, the mask layer 170 covering the second semiconductor channel and the first sidewall layer 150 located on the sidewall of the second semiconductor channel; and patterning the first sidewall layer 150 with the mask layer 170 as a mask to form the first groove 180.

[0058] For example, refer to Figure 6 After forming the first sidewall layer 150, the process also includes forming a first filler layer 160 between the first sidewall layers 150. The material of the first sidewall layer 150 can be an oxide, such as silicon oxide, and the material of the first filler layer 160 can be a nitride, such as silicon nitride.

[0059] In some embodiments, the process of forming the first filling layer 160 further includes forming a first initial filling layer, which also covers the top surface of the semiconductor channel 110. Part of the first initial filling layer is removed by chemical mechanical polishing (CMP) to expose the top surface of the semiconductor channel 110, and the remaining first initial filling layer serves as the first filling layer 160.

[0060] refer to Figure 7 A mask layer 170 is formed, which provides a process basis for the subsequent formation of the first groove. The mask layer 170 can protect the space used to form the second character line, and provides a process basis for the subsequent formation of the spaced first character line and second character line.

[0061] In other embodiments, the mask layer may only cover the first semiconductor channel and the first sidewall layer of the first semiconductor channel sidewall. This application does not limit the position of the mask layer; it is sufficient for the mask layer to cover the top surface of the same channel group and the first sidewall layer of the channel group sidewall.

[0062] refer to Figure 8 The first groove 180 is formed. After the first groove 180 is formed, the mask layer 170 is removed. The first groove 180 does not expose the top surface of the bit line 120. That is, during the process of graphicizing the first sidewall layer 150, a part of the first sidewall layer 150 is retained, thereby avoiding the subsequent connection between the first word line and the bit line 120.

[0063] refer to Figure 9 The process includes forming a first initial word line 133. Before forming the first initial word line 133, a first gate oxide layer 190 is also formed. By forming the first gate oxide layer 190, the first initial word line 133 can be prevented from directly contacting the substrate 100.

[0064] In some embodiments, the first gate oxide layer 190 may be formed by thermally oxidizing a portion of the semiconductor channel 110. Oxidation provides space for the formation of the first initial word line 133, meaning the formed first gate oxide layer 190 does not completely occupy the first recess 180 (see reference). Figure 8 This allows for the increase of the volume of the first initial word line 133, thereby reducing its resistance and improving the performance of the semiconductor structure. Alternatively, the first gate oxide layer 190 can be formed by deposition.

[0065] In some embodiments, during the formation of the first initial word line 133, the first initial word line 133 may cover the top surface of the first filler layer 160. Therefore, CMP can be used to make the top surface of the first initial word line 133 flush with the top surface of the first filler layer 160. The material of the first initial word line 133 can be titanium nitride or tungsten, etc.

[0066] refer to Figure 10 The first initial character line 131 is formed. Part of the first initial character line 133 can be removed by etching back the first initial character line 133, leaving the remaining first initial character line 133 (see reference). Figure 9 ) as the first character line 131.

[0067] refer to Figures 11 to 15 Simultaneously, a second word line 132 and a sidewall conductive layer 240 are formed. Forming a second word line 132 spaced from the first word line 131 reduces the coupling between adjacent word lines. Forming the sidewall conductive layer 240 provides shielding, thereby improving the performance of the semiconductor structure.

[0068] For example, refer to Figure 11 The steps of forming the second word line 132 and the sidewall conductive layer 240 may include: forming a first capping layer 200, the first capping layer 200 being located on the top surface of the first word line 131, the first capping layer 200 serving as a protective layer for the first word line 131, and covering the first word line 131 with the first capping layer 200 thereby preventing subsequent processes from affecting the first word line 131, thus improving the reliability of the semiconductor structure.

[0069] The steps of forming the first capping layer 200 may include: forming a first initial capping layer, the first initial capping layer also covering the top surface of the first gate oxide layer 190, removing part of the first initial capping layer by CMP until the top surface of the first gate oxide layer 190 is exposed, and the remaining first initial capping layer is the first capping layer 200.

[0070] In some embodiments, the material of the first cover layer 200 may be an insulating material such as silicon oxynitride.

[0071] refer to Figure 12 A first isolation layer 161 is formed, which is located between adjacent semiconductor channels 110, and the top surface of the first isolation layer 161 is higher than the top surface of the first word line 131. In some embodiments, a portion of the patterned fill layer 160 can be removed, and the remaining fill layer 160 serves as the first isolation layer 161. The formation of the first isolation layer 161 provides a process basis for the subsequent formation of the second word line.

[0072] The method for patterning the fill layer 160 can be through wet etching.

[0073] In some embodiments, after patterning the fill layer 160, the process may further include removing the first gate oxide layer 190 located on the top surface of the semiconductor channel 110. The method for removing a portion of the first gate oxide layer 190 may be by wet etching.

[0074] refer to Figure 13 A second sidewall layer 210 is formed, which covers the sidewalls of the first capping layer 200 and the sidewalls of the second semiconductor channel. By forming the second sidewall layer 210, and subsequently removing the second sidewall layer 210, space can be provided for forming the second word line 132.

[0075] The method for forming the second sidewall layer 210 may be to first form the second initial sidewall layer by depositing oxide on the sidewall of the first capping layer 200, the sidewall of the second semiconductor channel and the top surface of the first isolation layer 161, and then etch back part of the second initial sidewall layer to expose the top surface of the first isolation layer 161, with the remaining second initial sidewall layer serving as the second sidewall layer 210.

[0076] refer to Figure 14 This forms a second isolation layer 220, which is located on the top surface of the first isolation layer 161, and one sidewall of the second isolation layer 220 is connected to a second sidewall layer 210 that covers the sidewall of the first cover layer 200 (see reference). Figure 13 ) contact, the other sidewall is in contact with the second sidewall layer 210 of the second semiconductor channel sidewall (reference) Figure 13 Contact; back etching of the second sidewall layer 210 (reference) Figure 13 ), to form the second groove 181.

[0077] The step of forming the second isolation layer 220 may include: forming a second initial isolation layer, the second initial isolation layer also covering the top surface of the semiconductor channel 110, and removing part of the second initial isolation layer by CMP to expose the top surface of the semiconductor channel 110.

[0078] Etching back the second sidewall layer 210 (reference) Figure 13The method can be wet etching. It is understood that the materials of the first gate oxide layer 190 and the second sidewall layer 210 can be the same. During the wet etching of the second sidewall layer 210, a portion of the first gate oxide layer 190 is also etched. However, the density of the first gate oxide layer 190 is greater than that of the second sidewall layer 210, therefore their etching rates are different; that is, the etching rate of the first gate oxide layer 190 is less than the etching rate of the second sidewall layer 210. Therefore, when patterning the second sidewall layer 210 (refer to...),... Figure 13 During the process, the depth of the second gate oxide layer 230 removed is less than the depth of the second sidewall layer 210 removed.

[0079] Through graphical representation of the second sidewall layer 210 (reference) Figure 13 This provides space for the subsequent formation of the second word line and the sidewall conductive layer. The second isolation layer 220 can separate the second word line and the sidewall conductive layer, thereby preventing the second word line from being electrically connected to the sidewall conductive layer. The sidewall conductive layer can shield the second word line to reduce the coupling effect between adjacent second word lines.

[0080] refer to Figure 15 A second word line 132 is formed within a second recess 181. In the same step, a sidewall conductive layer 240 is formed. The sidewall conductive layer 240 and the second word line 132 are located in different second recesses 181 (e.g., adjacent second recesses). The material of the sidewall conductive layer 240 is the same as that of the second word line 132, for example, both can be titanium nitride. By forming a second word line 132 spaced from the first word line 131, the spacing between adjacent word lines 130 can be increased while ensuring the normal operation of the semiconductor structure. This reduces the coupling effect between the first word line 131 and the second word line 132, thereby improving the reliability of the semiconductor structure. Furthermore, the sidewall conductive layer 240 can serve as a shielding layer, further improving the performance of the semiconductor structure.

[0081] The sidewall conductive layer 240 is located above one of the two adjacent word lines 130, and the sidewall conductive layer 240 is disposed in the same layer as the other of the two adjacent word lines 130. In other words, the sidewall conductive layer 240 is located on the outer periphery of at least one word line 130 and is disposed directly opposite to the word line 130.

[0082] In some embodiments, the step of forming the second word line 132 and the sidewall conductive layer 240 may further include: forming a second initial word line and an initial sidewall conductive layer, wherein the second initial word line and the initial sidewall conductive layer fill different second grooves 181, and the second initial word line and the initial sidewall conductive layer are also located on the semiconductor channel 110; then removing part of the second initial word line and the initial sidewall conductive layer by CMP and back etching, and the remaining second initial word line and the initial sidewall conductive layer serve as the second word line 132 and the sidewall conductive layer 240, wherein the second word line 132 and the sidewall conductive layer 240 are located in the second groove 181; and the second word line 132 and the sidewall conductive layer 240 of the required height can be formed by deposition followed by etching.

[0083] It is understood that the sidewall conductive layers 240 are spaced apart in the second direction, and the two sidewall conductive layers 240 are located on both sides of a second word line 132.

[0084] In some embodiments, before forming the second word line 132, the method further includes: forming a second gate oxide layer 230 by oxidizing the second groove 181 (see reference). Figure 14 The exposed semiconductor channel 110 can form a second gate oxide layer 230, which can prevent the second word line 132 from directly contacting the substrate 100. Of course, the second gate oxide layer 230 can also be formed by deposition.

[0085] It is understandable that in the graphical second sidewall layer 210 (reference) Figure 13 During the process, part of the second gate oxide layer 230 may be removed. Therefore, during the formation of the second word line 132, part of the filling material of the second word line 132 is also filled on the top surface of the second gate oxide layer 230. Subsequently, the formation of the second word line 132 also includes etching back the second word line 132. During the etching back of the second word line 132, the filling material filled on the top surface of the second gate oxide layer 230 is also removed. Therefore, a recessed hole is also formed on the top surface of the second gate oxide layer 230.

[0086] In some embodiments, the word line 130 that is closer to the surface of the substrate 100 among two adjacent word lines 130 in the first direction is defined as the lower word line, and the word line 130 that is farther from the surface of the substrate 100 among two adjacent word lines 130 is defined as the upper word line. The bottom surface of the upper word line is located on the side of the top surface of the lower word line away from the surface of the substrate 100. During the formation of the word line 130, the distance between the top surface of the lower word line and the bottom surface of the upper word line is controlled to be greater than or equal to 3nm and less than or equal to 10nm.

[0087] It should be noted that the lower word line mentioned here is equivalent to the first word line 131, and the upper word line is equivalent to the second word line 132. By setting the distance between the bottom surface of the upper word line and the top surface of the lower word line to be greater than or equal to 3nm, the distance between the upper and lower word lines can be increased, thereby improving the insulation between adjacent word lines 130, reducing the coupling effect between adjacent word lines 130, and avoiding the situation where the upper word line conducts and the lower word line conducts, thus improving the reliability of the semiconductor structure. By setting the distance between the bottom surface of the upper word line and the top surface of the lower word line to be less than or equal to 10nm, the process difficulty can be reduced.

[0088] refer to Figure 16 , Figure 16 A method for fabricating a semiconductor structure provided in this disclosure embodiment Figure 15 A cross-sectional view of the basic manufacturing steps.

[0089] In some embodiments, after forming the second word line 132, the method further includes forming a second capping layer 250. The second capping layer 250 is located on the top surface of the second word line 132, and the second capping layer 250 also fills the recesses formed on the top surface of the second gate oxide layer during the etching process of the second word line 132, so as to make the surface of the semiconductor structure flat. The second capping layer 250 can also serve as a protective layer for the second word line 132, preventing the second word line 132 from reacting with air by isolating it from the outside environment. When the semiconductor structure is affected by external forces, the second capping layer 250 can also absorb some of the stress, thereby reducing the stress effect on the second word line 132 and improving the stability of the semiconductor structure. Based on this, the top surface of the semiconductor channel 110 can be exposed by CMP.

[0090] It should be noted that, in the embodiments of this disclosure, "co-layered" means that the two membrane layers or structures are at approximately the same horizontal level relative to the substrate, with one located on one or both sides of the other, and the two are arranged approximately opposite each other; for example, the same material and the same process can be used to simultaneously form the two membrane layers or structures "co-layered".

[0091] In this embodiment of the present disclosure, after forming the substrate 100, the semiconductor channel 110 and the bit line 120, the spacing between adjacent word lines 130 can be increased by arranging them at intervals in a direction perpendicular to the surface of the substrate 100. Correspondingly, the increased spacing between word lines 130 improves the insulation performance between adjacent word lines 130, thereby improving the coupling effect between adjacent word lines 130. The sidewall conductive layer 240 can also serve as a shielding effect, thereby improving the reliability of the semiconductor structure.

[0092] Another embodiment of this disclosure also provides a semiconductor structure, which can be formed by all or part of the above steps. The semiconductor structure provided by another embodiment of this disclosure will be described below with reference to the accompanying drawings. It should be noted that the same or corresponding parts as those in the foregoing embodiments can be referred to the corresponding descriptions of the foregoing embodiments, and will not be repeated hereafter.

[0093] refer to Figure 17 This disclosure provides a semiconductor structure comprising: a substrate 100 and a plurality of semiconductor channels 110 arranged in an array along a first direction and a second direction on the substrate 100; a plurality of bit lines 120 extending along the first direction, the bit lines 120 being located within the substrate 100, and each bit line 120 being electrically connected to the plurality of semiconductor channels 110 arranged along the first direction; a plurality of word lines 130 extending along the second direction, each word line 130 wrapping around a portion of the side surface of the plurality of semiconductor channels 110 arranged along the second direction, wherein two adjacent word lines 130 in the first direction are spaced apart in a direction perpendicular to the surface of the substrate 100; and a sidewall conductive layer 240 located above one of the two adjacent word lines 130, and the sidewall conductive layer 240 being disposed in the same layer as the other of the two adjacent word lines 130.

[0094] By providing word lines 130 spaced apart in a direction perpendicular to the surface of the substrate 100, the spacing between adjacent word lines 130 can be increased. Increasing the spacing between adjacent word lines 130 can improve the insulation performance of adjacent word lines 130, thereby reducing the coupling effect between adjacent word lines 130 and thus improving the reliability of the semiconductor structure. By providing a sidewall conductive layer 240, the sidewall conductive layer 240 can play a shielding role, thereby reducing the interference intensity and improving the performance and reliability of the semiconductor structure.

[0095] In some embodiments, the plurality of semiconductor channels 110 includes: a plurality of first channel groups, each of which includes a plurality of first semiconductor channels arranged along a second direction; a plurality of second channel groups, each of which includes a plurality of second semiconductor channels arranged along a second direction, and the plurality of first channel groups and the plurality of second channel groups are alternately arranged in a first direction; the plurality of word lines 130 includes: a plurality of first word lines 131 extending along a second direction, each first word line 131 wrapping around a portion of the side surface of a semiconductor channel 110 in a column of first channel groups; a plurality of second word lines 132 extending along a second direction, each second word line 132 wrapping around a portion of the side surface of a semiconductor channel 110 in a column of second channel groups, and the distance between the bottom surface of the second word line 132 and the surface of the substrate 100 is greater than the distance between the bottom surface of the first word line 131 and the surface of the substrate 100.

[0096] Adjacent word lines 130 are divided into first word lines 131 and second word lines 132. The word line 130 with a relatively higher position can be defined as the second word line 132, and the word line 130 with a relatively lower position can be defined as the first word line 131. By arranging word lines 130 at intervals in a direction perpendicular to the substrate 100, the spacing between adjacent word lines 130 provided in this embodiment is larger than that of word lines arranged in the same layer. By arranging word lines 130 with a larger spacing, the insulation performance between word lines 130 can be increased, thereby improving the problem of coupling effect between adjacent word lines 130.

[0097] In other embodiments, the word line with a relatively higher position can be defined as the first word line, and the word line with a relatively lower position can be defined as the second word line. The embodiments of this disclosure do not limit the name of the word line, as long as the word lines are arranged at intervals in the direction perpendicular to the substrate.

[0098] In some embodiments, the bottom surface of each first character line 131 is flush with the top surface of each first character line 131; the bottom surface of each second character line 132 is flush with the top surface of each second character line 132. That is, for all first character lines 131, the projections of the first character lines 131 along the first direction coincide, and the projections of the second character lines 132 along the first direction coincide.

[0099] By setting each first word line 131 and each second word line 132 to be flush, the stability of the semiconductor structure can be improved, and adverse effects caused by the position between the first word line 131 and the second word line 132 can be avoided. Furthermore, setting each first word line 131 and each second word line 132 to be flush can also facilitate the manufacturing process.

[0100] It should be noted that "aligned" here can be considered as the top surfaces of the first character lines 131 being completely aligned, or it can be considered as the height difference between the top surfaces of the first character lines 131 being within the allowable error range. When the height difference between the top surfaces of the first character lines 131 is within the allowable error range, the first character lines 131 can also be considered to be aligned.

[0101] In some embodiments, the materials of multiple first letter lines 131 can be the same; the materials of multiple second letter lines 132 can be the same. By setting first letter lines 131 and second letter lines 132 of the same material, the types of materials in the process can be reduced, which facilitates the control of the entire process.

[0102] In other embodiments, the materials of the multiple first letter lines may be different, and the materials of the multiple second letter lines may be different.

[0103] In some embodiments, the materials of the first word line 131 and the second word line 132 may be different. By setting the materials of the first word line 131 and the second word line 132 to be different, it is easier to locate which step or which material caused the problem during subsequent failure analysis. Furthermore, different materials can be selected based on the relative position of the first word line 131 and the second word line 132. For example, if the relative position of the first word line 131 is lower, the path required for subsequent electrical signal transmission with the capacitor structure is longer. Therefore, by setting the material of the first word line 131 to have better conductivity, the long conduction path can be compensated for, thereby improving the performance of the semiconductor structure.

[0104] In some other embodiments, the first word line and the second word line may be made of the same material. This disclosure does not limit the materials of the first word line and the second word line, as long as they meet the performance requirements of the semiconductor structure.

[0105] In some embodiments, among adjacent word lines 130 in the first direction X, the word line 130 that is closer to the surface of the substrate 100 is defined as the lower word line, and the word line 130 that is farther from the surface of the substrate 100 is defined as the upper word line. The bottom surface of the upper word line is located on the side of the top surface of the lower word line that is away from the surface of the substrate 100. By setting upper and lower word lines, the spacing between word lines can be increased, thereby increasing the insulation performance between adjacent word lines and further improving the reliability of the semiconductor structure.

[0106] It should be noted that the lower character line mentioned here is equivalent to the first character line 131, and the upper character line is equivalent to the second character line 132.

[0107] In some embodiments, in a direction perpendicular to the surface of the substrate 100, the distance between the top surface of the lower word line and the bottom surface of the upper word line is greater than or equal to 3 nm and less than or equal to 10 nm. By setting the distance between the bottom surface of the upper word line and the top surface of the lower word line to be greater than or equal to 3 nm, the distance between the upper and lower word lines can be increased, thereby improving the insulation between adjacent word lines 130 and preventing the lower word line from being conductive due to the upper word line, thus improving the reliability of the semiconductor structure; by setting the distance between the bottom surface of the upper word line and the top surface of the lower word line to be less than or equal to 10 nm, the process difficulty can be reduced.

[0108] In some embodiments, the semiconductor structure may further include: a first capping layer 200 located on the top surface of the first word line 131; a second capping layer 250 located on the top surface of the second word line 132; and a sidewall conductive layer 240 disposed in the same layer as the second word line 132 and located on the side of the first capping layer 200, wherein the material of the sidewall conductive layer 240 is the same as the conductive material in the second word line 132.

[0109] The first capping layer 200 can serve as a protective layer for the first word line 131. By setting the first capping layer 200, it can absorb some of the stress when the semiconductor structure is subjected to stress, thereby reducing the stress on the first word line 131. In addition, the first capping layer 200 can also prevent other process steps from affecting the first word line 131 during the forming process. The second capping layer 250 can serve as a protective layer for the second word line 132. The second capping layer 250 can also be used to fill in the semiconductor structure, thereby forming a semiconductor structure with a better morphology.

[0110] In some embodiments, the semiconductor structure may further include: a first isolation layer 161, the first isolation layer 161 being located between adjacent first word lines 131 and second word lines 132, the top surface of the first isolation layer 161 being higher than the top surface of the first word lines 131; and a second isolation layer 220, the second isolation layer 220 being located on the top surface of the first isolation layer 161, and also located on the side surface of the second word lines 132 and the side surface of the second capping layer 250.

[0111] The second word line 132 and the sidewall conductive layer 240 can be separated by the first isolation layer 161 and the second isolation layer 220, thereby avoiding electrical connection between the second word line 132 and the sidewall conductive layer 240. When the second word line 132 is electrically connected to the sidewall conductive layer 240, the poor coupling effect between adjacent word lines 130 is improved.

[0112] In some embodiments, each word line 130 has the same dimensions in the direction perpendicular to the surface of the substrate 100. Here, the dimensions refer to the thickness of the word line 130. In other words, by setting word lines 130 of the same thickness, the difference between adjacent word lines 130 can be reduced, thereby improving the reliability of the semiconductor structure.

[0113] In some embodiments, the semiconductor structure further includes: a first sidewall layer 150 covering the sidewalls of the semiconductor channel 110 spaced along a first direction; a first gate oxide layer 190 located between the first capping layer 200 and the semiconductor channel 110; and a second gate oxide layer 230 located on the sidewalls of the semiconductor channel 110.

[0114] This embodiment of the disclosure forms a GAA structure by providing multiple word lines 130 extending along the second direction and the word lines 130 wrapping around multiple semiconductor channels 110 arranged along the second direction. By setting adjacent word lines 130 to be spaced apart in a direction perpendicular to the surface of the substrate 100, the insulation performance between adjacent word lines 130 can be increased, thereby reducing the coupling effect between adjacent word lines 130. The sidewall conductive layer 240 can also serve as a shielding layer, further improving the performance of the semiconductor structure.

[0115] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method of fabricating a semiconductor structure, the method comprising: include: Provide a base; A plurality of semiconductor channels are formed on the substrate in an array arranged along a first direction and a second direction; Multiple bit lines are formed extending along the first direction, the bit lines are located within the substrate, and each bit line is electrically connected to a plurality of semiconductor channels arranged along the first direction. Multiple word lines are formed extending along the second direction, each word line wrapping around a portion of the side surface of a plurality of semiconductor channels arranged along the second direction, wherein two adjacent word lines in the first direction are spaced apart in a direction perpendicular to the substrate surface and their orthographic projections on the substrate surface do not overlap. A sidewall conductive layer is formed above one of the two adjacent word lines, and the sidewall conductive layer is disposed in the same layer as the other of the two adjacent word lines. The sidewall conductive layer and any two of the three components formed by the two adjacent word lines are insulated from each other.

2. The method of fabricating a semiconductor structure of claim 1, wherein, The plurality of semiconductor channels include: a plurality of first channel groups, each of the first channel groups including a plurality of first semiconductor channels arranged along a second direction; a plurality of second channel groups, each of the second channel groups including a plurality of second semiconductor channels arranged along the second direction, and the plurality of first channel groups and the plurality of second channel groups are alternately arranged in the first direction; the plurality of word lines include: a plurality of first word lines extending along the second direction, each first word line wrapping around a portion of the side surface of a semiconductor channel in a column of the first channel groups; a plurality of second word lines extending along the second direction, each second word line wrapping around a portion of the side surface of a semiconductor channel in a column of the second channel groups, and the distance between the bottom surface of the second word line and the substrate surface is greater than the distance between the bottom surface of the first word line and the substrate surface; forming the plurality of word lines includes: forming the first word lines; and forming the second word lines.

3. The method of fabricating a semiconductor structure of claim 2, wherein, The formation of the first character line includes: A first groove is formed, the first groove exposing a portion of the side surface of the first semiconductor channel; A first initial character line is formed, and the first initial character line fills the first groove; The first initial word line is etched back, and the remaining first initial word line is used as the first word line.

4. The method of fabricating a semiconductor structure of claim 3, wherein, Forming the first groove includes: A first sidewall layer is formed, which covers the sidewalls of the semiconductor channel spaced along the first direction; A mask layer is formed, the mask layer covering the second semiconductor channel and the first sidewall layer located on the sidewall of the second semiconductor channel; The first sidewall layer is patterned using the mask layer as a mask to form the first groove.

5. The method of fabricating a semiconductor structure of claim 3, wherein, The second word line and the sidewall conductive layer are formed simultaneously; Forming the second word line and the sidewall conductive layer includes: A first cover layer is formed, which is located on the top surface of the first letter line; A first isolation layer is formed, the first isolation layer is located between adjacent semiconductor channels, and the top surface of the first isolation layer is higher than the top surface of the first word line; A second sidewall layer is formed, which covers the sidewall of the first capping layer and the sidewall of the second semiconductor channel; A second isolation layer is formed, the second isolation layer is located on the top surface of the first isolation layer, and one sidewall of the second isolation layer is in contact with the second sidewall layer covering the sidewall of the first capping layer, and the other sidewall is in contact with the second sidewall layer of the second semiconductor channel sidewall. The second sidewall layer is etched back to form the second groove; The second word line and the sidewall conductive layer are formed, and the second word line and the sidewall conductive layer are located in different second grooves.

6. The method of fabricating a semiconductor structure of claim 2, wherein, After forming the second letter line, the process further includes forming a second cover layer, which is located on the top surface of the second letter line.

7. The method of fabricating a semiconductor structure of claim 1, wherein, The character line that is closer to the substrate surface among two adjacent character lines in the first direction is defined as the lower character line, and the character line that is farther from the substrate surface among two adjacent character lines is defined as the upper character line. The bottom surface of the upper character line is located on the side of the top surface of the lower character line away from the substrate surface. During the formation of the character line, the distance between the top surface of the lower character line and the bottom surface of the upper character line is controlled to be greater than or equal to 3nm and less than or equal to 10nm.

8. The method of fabricating a semiconductor structure of claim 1, wherein, The semiconductor channel includes a first doped region, a channel region, and a second doped region arranged in sequence. The first doped region is electrically connected to the bit line, and the first doped region, the channel region, and the second doped region have the same doping type.

9. The method of fabricating a semiconductor structure of claim 1, wherein, Forming the plurality of semiconductor channels arranged in an array along the first direction and the second direction on the substrate includes: patterning the substrate to form a plurality of initial semiconductor channels spaced apart along the second direction; The plurality of initial semiconductor channels are graphically represented to form the plurality of semiconductor channels spaced apart along both the first and second directions.

10. The method of fabricating a semiconductor structure of claim 1, wherein, The semiconductor channel is made of silicon, and the multiple bit lines are formed using a silicon metallization process.

11. A semiconductor structure, characterized by include: A substrate and a plurality of semiconductor channels arranged in an array along a first direction and a second direction on the substrate; Multiple bit lines extending along the first direction, the bit lines being located within the substrate, and each bit line being electrically connected to a plurality of semiconductor channels arranged along the first direction; Multiple word lines extending along the second direction, each word line wrapping around a portion of the side surface of a plurality of semiconductor channels arranged along the second direction, wherein two adjacent word lines in the first direction are spaced apart in a direction perpendicular to the substrate surface and their orthographic projections on the substrate surface do not overlap. A sidewall conductive layer is located above one of the two adjacent word lines, and the sidewall conductive layer is disposed in the same layer as the other of the two adjacent word lines. The sidewall conductive layer and any two of the three components formed by the two adjacent word lines are insulated from each other.

12. The semiconductor structure of claim 11, wherein, The plurality of semiconductor channels include: Multiple first channel groups, each column of the first channel group including multiple first semiconductor channels arranged along the second direction; multiple second channel groups, each column of the second channel group including multiple second semiconductor channels arranged along the second direction, and the multiple first channel groups and the multiple second channel groups are arranged alternately in the first direction; The multiple character lines include: Multiple first word lines extending along the second direction, each first word line wrapping around a portion of the side surface of the semiconductor channel in a column of the first channel group; Multiple second word lines extending along the second direction, each second word line wrapping around a portion of the side surface of the semiconductor channel in a column of the second channel group, and the distance between the bottom surface of the second word line and the substrate surface is greater than the distance between the bottom surface of the first word line and the substrate surface.

13. The semiconductor structure of claim 12, wherein, The bottom surface of each of the first character lines is flush with the top surface of each of the first character lines; the bottom surface of each of the second character lines is flush with the top surface of each of the second character lines.

14. The semiconductor structure of claim 12, wherein, Multiple first-line characters are made of the same material; multiple second-line characters are made of the same material.

15. The semiconductor structure of claim 12, wherein, The first letter line and the second letter line are made of different materials.

16. The semiconductor structure of claim 12, wherein, Also includes: The first cover layer is located on the top surface of the first letter line; The second cover layer is located on the top surface of the second letter line; The sidewall conductive layer is disposed in the same layer as the second letter line and is located on the side of the first cover layer. The material of the sidewall conductive layer is the same as the conductive material in the second letter line.

17. The semiconductor structure of claim 16, wherein, The semiconductor structure further includes: a first isolation layer located between adjacent first word lines and second word lines, the top surface of the first isolation layer being higher than the top surface of the first word lines; and a second isolation layer located on the top surface of the first isolation layer, and also located on the side of the second word lines and the side of the second capping layer.

18. The semiconductor structure of claim 11, wherein, The character line that is closer to the base surface among two adjacent character lines in the first direction is defined as the lower character line, and the character line that is farther from the base surface among two adjacent character lines is defined as the upper character line. The bottom surface of the upper character line is located on the side of the top surface of the lower character line away from the base surface.

19. The semiconductor structure of claim 18, wherein, In a direction perpendicular to the substrate surface, the distance between the top surface of the lower character line and the bottom surface of the upper character line is greater than or equal to 3nm and less than or equal to 10nm.

20. The semiconductor structure according to claim 11, characterized in that, In the direction perpendicular to the surface of the substrate, each of the word lines has the same size.

Images