Semiconductor structure and method of manufacturing the same, electronic device

Abstract

The present disclosure provides a semiconductor structure and a manufacturing method thereof, and an electronic device, wherein the semiconductor structure comprises: a memory array, the memory array comprising: a plurality of transistor groups, each transistor group comprising: a plurality of semiconductor layers arranged in a vertical direction; the semiconductor layer comprising a first source / drain region, a channel region and a second source / drain region arranged in a first direction; the first source / drain region having an upper surface, a lower surface and a side surface at a first end portion away from the channel region; a plurality of gate layers respectively covering the channel regions of the plurality of semiconductor layers; a bit line contact layer extending in the vertical direction, the bit line contact layer at least surrounding the upper surface, the lower surface and the side surface of the first end portion; a bit line layer extending in the vertical direction and conformally covering the surface of the bit line contact layer, wherein the bit line layer has a shape adapted to the bit line contact layer towards the surface of the bit line contact layer, and the bit line layer is electrically connected to the plurality of first source / drain regions through the bit line contact layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its manufacturing method, and an electronic device. Background Technology

[0002] With technological advancements, semiconductor devices are continuously evolving towards miniaturization and higher integration. Dynamic Random Access Memory (DRAM), as an important semiconductor device, can be used to store data or programs for data processing in electronic devices. However, many problems still exist in the actual manufacturing process of DRAM that urgently need improvement. Summary of the Invention

[0003] This disclosure provides a semiconductor structure, including: The storage array includes: A plurality of transistor groups, each of the transistor groups comprising: a plurality of semiconductor layers spaced apart in a vertical direction; each of the semiconductor layers comprising a first source / drain region, a channel region, and a second source / drain region arranged along a first direction; the first source / drain region having opposing upper and lower surfaces, opposing left and right surfaces, and a side surface located between the upper, lower, left, and right surfaces at a first end away from the channel region; Multiple gate layers, each covering the channel region of the multiple semiconductor layers; Bit line contact layer, extending in a vertical direction, the bit line contact layer at least surrounds the upper surface, the lower surface and the side surface of the first end; A bitline layer extends vertically and conformally covers the surface of the bitline contact layer, wherein the surface of the bitline layer facing the bitline contact layer has a shape adapted to the bitline contact layer, and the bitline layer is electrically connected to a plurality of first source / drain regions through the bitline contact layer.

[0004] In some embodiments, the bit line contact layer also surrounds the left and right surfaces of the first end.

[0005] In some embodiments, the bit line contact layer comprises a metal silicide material, wherein the metal silicide material comprises at least one of titanium silicide or molybdenum silicide.

[0006] In some embodiments, in the bit line contact layer, the material covering the portion of the side surface of the first end is a metal silicide material, and the material covering the portions of the upper and lower surfaces of the first end includes a semiconductor material.

[0007] In some embodiments, the bit line contact layer includes a plurality of first sub-parts, a plurality of second sub-parts, and a plurality of third sub-parts connected sequentially along a vertical direction; wherein... The first sub-part directly covers at least the upper surface, the lower surface, and the side surface of the first end; the second sub-part is located between adjacent first sub-parts in a vertical direction, and at least part of the third sub-part is sandwiched between adjacent first sub-parts and second sub-parts in a vertical direction. In the first direction, the first sub-part, the third sub-part, and the second sub-part are arranged sequentially in a direction close to the bit line layer, away from the sidewall of the bit line layer, so that the bit line contact layer away from the sidewall of the bit line layer is serrated.

[0008] In some embodiments, the storage array further includes: Multiple data storage elements are located along the first direction on one side of the multiple semiconductor layers away from the bit line layer, and are electrically connected to the second source / drain regions of the multiple semiconductor layers one by one.

[0009] In some embodiments, the semiconductor structure further includes: The first interconnect layer is located on the memory array in a vertical direction; A CMOS chip is located vertically on the side of the first interconnect layer opposite to the memory array and is bonded to the first interconnect layer. The second interconnect layer is located vertically on the side of the CMOS chip facing away from the memory array.

[0010] This disclosure also provides a method for manufacturing a semiconductor structure, including: Provide a second substrate; A memory array is formed on the second substrate; forming the memory array includes: A plurality of stacked layers are formed on the second substrate, each stacked layer including a plurality of initial semiconductor layers spaced apart in a vertical direction, each initial semiconductor layer including at least a first sub-segment, the first sub-segment including a first source / drain region, a channel region and a second source / drain region arranged along a first direction, the first source / drain region having a first end away from the channel region; the first direction is parallel to the surface of the second substrate; An isolation structure is formed, the isolation structure being at least partially located between the plurality of initial semiconductor layers, and a plurality of gate layers are formed within the isolation structure, the plurality of gate layers respectively covering the plurality of channel regions of the stacked layers; An opening is formed on one side of the stacked layer in the first direction, and a portion of the isolation structure is removed from the opening to expose at least the opposing upper and lower surfaces of the first end, as well as the side surface located between the upper and lower surfaces. A bit line contact layer is formed, the bit line contact layer extending in a vertical direction and at least surrounding the upper surface, the lower surface and the side surface of a plurality of first ends of the stacked layer; A bitline layer is formed, which extends vertically and conformally covers the surface of the bitline contact layer, wherein the surface of the bitline layer facing the bitline contact layer has a shape adapted to the bitline contact layer, and the bitline layer is electrically connected to a plurality of first source / drain regions through the bitline contact layer.

[0011] In some embodiments, forming the isolation structure includes: A plurality of first sublayers, a plurality of second sublayers, and a third sublayer are formed; wherein, the first sublayers are located vertically between adjacent first sub-segments and spaced apart from the first sub-segments; the plurality of second sublayers respectively surround the first source / drain regions and channel regions of the plurality of initial semiconductor layers, and the gate layer covers a portion of the second sublayers surrounding the channel regions; a portion of the third sublayers are located vertically between adjacent first sublayers and surround the portion of the second sublayers not covered by the gate layer, the third sublayers also cover the side surface of the first end, as well as the sidewalls of the first and second sublayers, and the opening exposes the third sublayer.

[0012] In some embodiments, removing a portion of the isolation structure from the opening side includes: A portion of the third sublayer is removed laterally from the opening to expose the side surface of the first end and the sidewalls of the first and second sublayers facing the opening, and a portion of the third sublayer is further removed laterally from the opening to form a first gap, at least a portion of which is sandwiched vertically between adjacent first and second sublayers. A portion of the first sublayer and a portion of the second sublayer are removed from the side of the opening to form a second gap and a third gap communicating with the first gap, respectively. The third gap exposes at least the upper and lower surfaces of the first end. The bit line contact layer also covers the remaining sidewall of the isolation structure facing the opening, and the depths of the third gap, the first gap, and the second gap decrease sequentially in the first direction, so that the sidewall of the bit line contact layer away from the bit line layer in the first direction is serrated.

[0013] In some embodiments, forming the bit line contact layer includes: An initial semiconductor material layer is formed, which conformally covers the inner wall of the opening, as well as the surface of the isolation structure and the first end that is exposed; A portion of the initial semiconductor material layer is removed to form a semiconductor material layer having a predetermined thickness, the semiconductor material layer extending in a vertical direction and at least surrounding the upper surface, the lower surface, and the side surface of a plurality of first ends of the stacked layer; A metal layer is formed, which conformally covers the inner wall of the opening and the surface of the semiconductor material layer; Perform a thermal annealing process to convert at least a portion of the semiconductor material layer and a portion of the metal layer into a metal semiconductor compound material; Remove the metal layer that has not been converted into the metal semiconductor compound material to form the bit line contact layer.

[0014] In some embodiments, the initial semiconductor layer further includes a second sub-segment connected to a second source / drain region of the first sub-segment; forming the memory array further includes: The second sub-segment of the initial semiconductor layer is removed, and the remaining initial semiconductor layer constitutes a semiconductor layer; Multiple data storage elements are formed, wherein the data storage elements are located along the first direction on the side of the semiconductor layer away from the bit line layer, and are electrically connected to the second source / drain regions of the multiple semiconductor layers in a one-to-one correspondence.

[0015] In some embodiments, after forming the storage array, the method further includes: A first interconnect layer is formed, which is located in the vertical direction on the side of the memory array opposite to the second substrate; A CMOS chip is provided and the CMOS chip is bonded to the first interconnect layer, wherein the CMOS chip is located on the side of the first interconnect layer opposite to the memory array in a vertical direction; A second interconnect layer is formed, which is located vertically on the side of the CMOS chip opposite to the memory array.

[0016] In some embodiments, after forming the second interconnect layer, the method further includes: Remove the second substrate; A first substrate is formed on the side of the storage array away from the first interconnect layer, and the material of the first substrate includes an insulating material.

[0017] This disclosure also provides an electronic device, including: a processing device; and a storage device electrically connected to the processing device, the storage device including the semiconductor structure provided in any of the above embodiments.

[0018] In this embodiment of the present disclosure, the formed bit line contact layer at least surrounds the upper surface, lower surface and side surface of the first end, and the bit line contact layer extends continuously in the vertical direction. The surface of the bit line layer facing the bit line contact layer has a shape adapted to the bit line contact layer, which increases the contact area between the bit line layer and the bit line contact layer, thereby reducing the contact resistance between the bit line layer and the bit line contact layer and improving the performance of the semiconductor structure.

[0019] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification and the drawings. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the semiconductor structure provided in some embodiments of the present disclosure; Figure 2 This is a top view schematic diagram of multiple transistor groups provided in some embodiments of the present disclosure; Figure 3 A partial structural diagram of a storage array provided in some embodiments of this disclosure; Figure 4 for Figure 3 A partially enlarged view of the structure shown; Figure 5 Some embodiments of this disclosure follow Figure 3 A schematic diagram of a partial cross-sectional structure taken from line A1A2 in the diagram; Figure 6 This is a schematic diagram of the semiconductor structure provided in some other embodiments of the present disclosure; Figure 7 A partial structural schematic diagram of a storage array provided for other embodiments of this disclosure; Figure 8 for Figure 7 A partially enlarged view of the structure shown in the image; Figure 9 For other embodiments of this disclosure along Figure 7 A schematic diagram of a partial cross-sectional structure taken from line A1A2 in the diagram; Figure 10 A flowchart illustrating a method for forming a memory array on a second substrate according to some embodiments of this disclosure; Figure 11 Schematic diagram of a partial structure of a semiconductor structure during the manufacturing process, provided for some embodiments of this disclosure. Figure 1 ; Figure 12 Schematic diagram of a partial structure of a semiconductor structure during the manufacturing process, provided for some embodiments of this disclosure. Figure 2 ; Figure 13 Schematic diagram of a partial structure of a semiconductor structure during the manufacturing process, provided for some embodiments of this disclosure. Figure 3 ; Figure 14 Schematic diagram of a partial structure of a semiconductor structure during the manufacturing process, provided for some embodiments of this disclosure. Figure 4 ; Figure 15 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 3 Schematic diagram of the local cross-sectional structure taken by line A1A2 in the middle Figure 5 ; Figure 16 Schematic diagram of a partial structure of a semiconductor structure during the manufacturing process, provided for some embodiments of this disclosure. Figure 6 ; Figure 17 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 3 Schematic diagram of the local cross-sectional structure taken by line A1A2 in the middle Figure 7 ; Figure 18 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 3 Schematic diagram of the local cross-sectional structure taken by line A1A2 in the middle Figure 8 ; Figure 19 Schematic diagram of a partial structure of a semiconductor structure during the manufacturing process, provided for some embodiments of this disclosure. Figure 9 ; Figure 20 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 3 Schematic diagram of the local cross-sectional structure taken by line A1A2 in the middle Figure 10 ; Figure 21 Schematic diagram of a partial structure of a semiconductor structure during the manufacturing process, provided for some embodiments of this disclosure. Figure 10 one; Figure 22 Schematic diagram of a partial structure of a semiconductor structure during the manufacturing process, provided for some embodiments of this disclosure. Figure 10 two; Figure 23 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 3 Schematic diagram of the local cross-sectional structure taken by line A1A2 in the middle Figure 10 three; Figure 24 Schematic diagram of a partial structure of a semiconductor structure during the manufacturing process, provided for some embodiments of this disclosure. Figure 10 Four; Figure 25 for Figure 24 A partial magnification of the structure shown Figure 10 five; Figure 26 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 3 Schematic diagram of the local cross-sectional structure taken by line A1A2 in the middle Figure 10 six; Figure 27 Schematic diagram of a partial structure of a semiconductor structure during the manufacturing process, provided for some embodiments of this disclosure. Figure 10 seven; Figure 28 Schematic diagram of a partial structure of a semiconductor structure during the manufacturing process, provided for some embodiments of this disclosure. Figure 10 eight; Figure 29 Schematic diagram of a partial structure of a semiconductor structure during the manufacturing process, provided for some embodiments of this disclosure. Figure 10 Nine; Figure 30 Schematic diagram of a partial structure of a semiconductor structure during the manufacturing process, provided for some embodiments of this disclosure. Figure 2 ten; Figure 31 for Figure 30 A partial magnification of the structure shown Figure 2 eleven; Figure 32 The semiconductor structure provided for some embodiments of this disclosure is manufactured along... Figure 3 Schematic diagram of the local cross-sectional structure taken by line A1A2 in the middle Figure 2 twelve; Figure 33 Schematic diagram of a partial structure of a semiconductor structure during the manufacturing process, provided for some embodiments of this disclosure. Figure 2 Thirteen; Figure 34 Schematic diagram of a partial structure of a semiconductor structure during the manufacturing process, provided for some embodiments of this disclosure. Figure 2 fourteen; Figure 35 Schematic diagram of the semiconductor structure provided in some embodiments of this disclosure during the manufacturing process Figure 2 fifteen; Figure 36 Schematic diagram of a partial structure of a semiconductor structure during the manufacturing process, provided for other embodiments of this disclosure. Figure 2 sixteen; Figure 37 for Figure 36A partial magnification of the structure shown Figure 2 Seventeen; Figure 38 The semiconductor structures provided for other embodiments of this disclosure follow the manufacturing process along Figure 7 Schematic diagram of the local cross-sectional structure taken by line A1A2 in the middle Figure 2 eighteen; Figure 39 Schematic diagram of a partial structure of a semiconductor structure during the manufacturing process, provided for other embodiments of this disclosure. Figure 2 nineteen; Figure 40 Schematic diagram of a partial structure of a semiconductor structure during the manufacturing process, provided for other embodiments of this disclosure. Figure 3 ten; Figure 41 Schematic diagram of the semiconductor structure during the manufacturing process provided for other embodiments of this disclosure. Figure 3 eleven; Figure 42 This is a structural block diagram of an electronic device provided in some embodiments of the present disclosure. Detailed Implementation

[0022] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0023] In semiconductor structures, such as Dynamic Random Access Memory (DRAM), a three-dimensional stacked DRAM architecture is typically employed to further increase memory cell density. In the manufacturing process of three-dimensional DRAM with horizontal memory cells, the bit line contact layer is formed as follows: First, the ends of horizontally extending silicon pillars are trimmed to form horizontally extending trenches; then, polysilicon material is backfilled into the horizontal trenches as the bit line contact layer. However, the contact area between the bit line contact layer formed in this way and the horizontal silicon pillars is small. The polysilicon material itself has high resistivity, and voids and other defects are easily generated when backfilling polysilicon material into the horizontal trenches, further deteriorating the resistance of the bit line contact layer.

[0024] Based on this, the technical solution of the present disclosure is proposed. In the embodiments of the present disclosure, the formed bit line contact layer at least surrounds the upper surface, lower surface and side surface of the first end, and the bit line contact layer extends continuously in the vertical direction. The surface of the bit line layer facing the bit line contact layer has a shape adapted to the bit line contact layer, which increases the contact area between the bit line layer and the bit line contact layer, thereby reducing the contact resistance between the bit line layer and the bit line contact layer and improving the performance of the semiconductor structure.

[0025] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0026] The semiconductor structure provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings.

[0027] like Figures 1 to 5 As shown, the semiconductor structure includes a memory array 200, which includes multiple transistor groups 30a. Each transistor group 30a includes multiple semiconductor layers 11 spaced apart in a vertical direction. Each semiconductor layer 11 includes a first source / drain region 111, a channel region 112, and a second source / drain region 113 arranged along a first direction. The first source / drain region 111 has opposing upper surfaces W1 and lower surfaces W2, opposing left surfaces W3 and right surfaces W4 at a first end D1 away from the channel region 112, and a second source / drain region W4 located on the upper surface W1, lower surface W2, and left surface W4. The first end D1 has a side surface W5 between the right surface W4 and the right surface W5; a plurality of gate layers 16, each covering a channel region 112 of a plurality of semiconductor layers 11; a bit line contact layer 19 extending in a vertical direction, the bit line contact layer 19 at least surrounding the upper surface W1, lower surface W2 and side surface W5 of the first end D1; a bit line layer BL extending in a vertical direction and conformally covering the surface of the bit line contact layer 19, wherein the surface of the bit line layer BL facing the bit line contact layer 19 has a shape adapted to the bit line contact layer 19, and the bit line layer BL is electrically connected to a plurality of first source / drain regions 111 through the bit line contact layer 19.

[0028] The semiconductor structure provided in this disclosure can be a three-dimensional dynamic random access memory (3D-DRAM).

[0029] In some embodiments, the semiconductor structure may further include: a first substrate 10, on which the memory array 200 is located.

[0030] Here and below, the vertical direction may refer to the first substrate 10 or the second substrate 20 (see [reference]). Figure 11The surface of the first end D1 is perpendicular to the direction of the first end D1; the upper surface W1 and lower surface W2 of the first end D1 can refer to the surfaces of the first end D1 that are opposite each other in the vertical direction; the left surface W3 and right surface W4 can refer to the surfaces of the first end D1 that are opposite each other in the second direction; and the side surface W5 can refer to the surface of the first end D1 that faces the bit line layer BL along the first direction; wherein, the second direction can be oblique to or perpendicular to the first direction, and both the first direction and the second direction are parallel to the surface of the first substrate 10 or the second substrate 20.

[0031] In some embodiments, the material of the first substrate 10 includes an insulating material. In some specific embodiments, the material of the first substrate 10 may include, but is not limited to, oxides, such as silicon oxide. In the embodiments of this disclosure, by disposing the memory array 200 on the first substrate 10 having an insulating material, leakage current of the first substrate 10 can be avoided, and parasitic capacitance and signal crosstalk between the memory array 200 and the first substrate 10 can be mitigated or avoided, thereby reducing power consumption and improving the performance of the semiconductor structure.

[0032] like Figure 1 and Figure 2 As shown, in some embodiments, each transistor group 30a may include a plurality of transistors 30 distributed in a vertical direction, and each transistor 30 includes at least a semiconductor layer 11 and a gate layer 16 corresponding to a channel region 112 covering the semiconductor layer 11.

[0033] In some embodiments, a plurality of transistor groups 30a may be arranged in an array along a first direction and a second direction, and a plurality of transistor groups 30a arranged along the second direction may constitute a transistor array 30b. A plurality of transistors 30 in each transistor array 30b are arranged in an array along a vertical direction and a second direction. The memory array 200 may include a plurality of transistor arrays 30b. The plurality of transistor arrays 30b may include at least two transistor arrays 30b arranged adjacent to each other in the first direction and separated by an isolation trench T1. For a plurality of transistors 30 located on both sides of the isolation trench T1 along the first direction and adjacent to the isolation trench T1, the first source / drain region 111 of each transistor 30 is located at one end of the semiconductor layer 11 near the isolation trench T1, and the first end D1 is located at one end of the first source / drain region 111 near the isolation trench T1.

[0034] It should be noted that, Figure 2 The transistor group 30a marked in the figure includes a plurality of transistors 30 arranged in a vertical direction.

[0035] In some embodiments, the isolation trench T1 may be filled with one or more insulating materials, such as one or more low dielectric constant materials such as oxides (e.g., silicon oxide) and nitrides (e.g., silicon nitride), and may be formed by a multi-step process.

[0036] In some embodiments, each transistor array 30b may include a plurality of transistor rows spaced apart in a vertical direction, each transistor row may include a plurality of transistors 30 arranged in a second direction, and the gate layers 16 of the plurality of transistors 30 in each transistor row are interconnected in the second direction to form a word line layer WL extending in the second direction. The word line layer WL covers the region of the channel region 112 to form the gate layer 16. In some embodiments, the gate layer 16 may surround the channel region 112, and each word line layer WL may surround the channel region 112 of a plurality of semiconductor layers 11 in the second direction.

[0037] In some embodiments, the number of bit line contact layers 19 and bit line layers BL electrically connected to each transistor array 30b can be multiple. The multiple bit line contact layers 19 and multiple bit line layers BL can be arranged along the second direction. Each bit line contact layer 19 is electrically connected to the first end D1 of multiple first source / drain regions 111 of a transistor group 30a. Each bit line layer BL is electrically connected to multiple first source / drain regions 111 of a transistor group 30a through the bit line contact layer 19.

[0038] like Figure 3 and Figure 4 As shown, in some embodiments, the memory array 200 may further include an isolation structure 15, which is located at least between a plurality of semiconductor layers 11, and the word line layer WL is located within the isolation structure 15.

[0039] In some embodiments, the isolation structure 15 may include: a plurality of first sub-layers 151, a plurality of second sub-layers 152, and a third sub-layer 153; wherein, the first sub-layers 151 may be located between adjacent semiconductor layers 11 in a vertical direction and extend continuously in a second direction; the second sub-layers 152 may surround the channel region 112 and the portion of the first source / drain region 111 of the semiconductor layer 11 except for the first end D1, and the portion of the second sub-layer 152 surrounding the channel region 112 is sandwiched between the gate layer 16 and the channel region 112 and may serve as the gate oxide layer of the transistor 30; the portion of the third sub-layer 153 may be located between adjacent first sub-layers 151 in a vertical direction and surround the second source / drain region 113 of the semiconductor layer 11 and the portion of the second sub-layer 152 that does not cover the channel region 112.

[0040] In some embodiments, the first sublayer 151 and the second sublayer 152 may be made of the same material, which may include, but is not limited to, oxides (e.g., silicon oxide). The third sublayer 153 may be made of a material that has a greater etching selectivity than the materials of the first sublayer 151 and the second sublayer 152, such as a nitride (including silicon nitride). In some embodiments, the thickness of the first sublayer 151 may be greater than the thickness of the second sublayer 152.

[0041] In some embodiments, a portion of the sidewalls of the isolation structure 15 (including a first sublayer 151, a second sublayer 152, and a third sublayer 153) are recessed inward in a first direction relative to the side surface W5 of the first end D1, so as to expose at least the upper surface W1, the lower surface W2, and the side surface W5 of the first end D1. The bit line contact layer 19 at least covers the sidewalls of the isolation structure 15 that are recessed inward relative to the side surface W5, and the upper surface W1, the lower surface W2, and the side surface W5 of the first end D1 exposed by the isolation structure 15. In some embodiments, the third sublayer 153 also covers the portion of the sidewalls of the first sublayer 151 and the second sublayer 152 facing the isolation trench T1 that are not covered by the bit line contact layer 19.

[0042] In this embodiment of the present disclosure, the bit line contact layer 19 at least surrounds the upper surface W1, the lower surface W2 and the side surface W5 of the first end D1, that is, the bit line contact layer 19 at least partially surrounds the outer surface of the first end D1, thereby increasing the contact area between the bit line contact layer 19 and the first source / drain region 111, reducing the contact resistance between the bit line contact layer 19 and the first source / drain region 111, and improving the performance of the semiconductor structure.

[0043] Meanwhile, in this embodiment, the bit line contact layer 19 extends continuously in the vertical direction, and the surface of the bit line layer BL facing the bit line contact layer 19 has a shape adapted to the bit line contact layer 19, thereby increasing the contact area between the bit line layer BL and the bit line contact layer 19.

[0044] like Figure 5 As shown, in some other embodiments of this disclosure, the isolation structure 15 also exposes the left surface W3 and the right surface W4 of the first end D1, and the bit line contact layer 19 also surrounds the left surface W3 and the right surface W4 of the first end D1, that is, the bit line contact layer 19 completely surrounds the outer surface of the first end D1, thereby further increasing the contact area between the bit line contact layer 19 and the first source / drain region 111.

[0045] like Figure 4 and Figure 5 As shown, in some embodiments, the bit line contact layer 19 may include a plurality of first sub-parts 191, a plurality of second sub-parts 192, and a plurality of third sub-parts 193 connected sequentially in a vertical direction; wherein, the first sub-parts 191 at least directly cover the upper surface W1, lower surface W2, and side surface W5 of the first end D1; the second sub-parts 192 are located between adjacent first sub-parts 191 in a vertical direction, and at least part of the third sub-parts 193 are sandwiched between adjacent first sub-parts 191 and second sub-parts 192 in a vertical direction; wherein, the first sub-parts 191, second sub-parts 192, and third sub-parts 193 may respectively cover the sidewalls of the opposite side surfaces W5 of the second sub-layer 152, the first sub-layer 151, and the third sub-layer 153 that are recessed inward in a first direction.

[0046] In some embodiments, where the isolation structure 15 also exposes the left surface W3 and right surface W4 of the first end D1, the first sub-part 191 also directly covers the left surface W3 and right surface W4 of the first end D1, and the third sub-part 193 surrounds the portion of the first sub-part 191.

[0047] In some embodiments, the distance by which the partial sidewalls of the second sublayer 152, the third sublayer 153, and the first sublayer 151 are recessed inward relative to the side surface W5 in the first direction decreases sequentially, so that the sidewalls of the isolation structure 15 recessed inward relative to the side surface W5 in the first direction are serrated. This results in the first sub-part 191, the third sub-part 193, and the second sub-part 192 being arranged in the direction close to the bit line layer BL, away from the sidewalls of the bit line layer BL, and the sidewalls of the bit line contact layer 19 being serrated away from the bit line layer BL.

[0048] like Figure 3 and Figure 4 As shown, in some embodiments, when the sidewall of the bit line contact layer 19 away from the bit line layer BL is serrated, the sidewall of the bit line contact layer 19 facing the bit line layer BL can also be serrated, thus further increasing the contact area between the bit line layer BL and the bit line contact layer 19.

[0049] like Figure 3 As shown, in some embodiments, the material of the bit line contact layer 19 includes a metal semiconductor compound material 19a; wherein, the metal semiconductor compound material 19a may include one or more of metal silicide material 19b, metal germanide material, metal silicon germanide material, etc., for example, metal silicide material 19b; wherein, the metal silicide material 19b may include one or more of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide or platinum silicide, for example, titanium silicide and / or molybdenum silicide.

[0050] In this embodiment of the disclosure, the material of the bit line contact layer 19 includes a metal semiconductor compound material 19a. The metal semiconductor compound material 19a has a smaller resistance, thereby reducing the resistance of the bit line contact layer 19 and further reducing the contact resistance between the bit line contact layer 19 and the first end D1, as well as the contact resistance between the bit line layer BL and the bit line contact layer 19.

[0051] In other embodiments of this disclosure, the material of the bit line contact layer 19 may include polycrystalline silicon in addition to the metal silicide material 19b. For example... Figures 6 to 8As shown, by way of example, in the bit line contact layer 19, the material covering the side surface W5 of the first end D1 is a metal silicide material 19b, and the material covering the upper surface W1 and lower surface W2 of the first end D1 may include a polysilicon layer 18, for example, it may be entirely polysilicon layer 18, or it may be a mixed material including polysilicon layer 18 and metal silicide material 19b.

[0052] In some embodiments, in the second sub-section 192 and the third sub-section 193, the portion near the bit line layer BL includes a metal silicide material 19b, and the portion near the isolation structure 15 includes a polysilicon layer 18.

[0053] like Figure 9 As shown, in some other embodiments, when the bit line contact layer 19 also covers the left surface W3 and the right surface W4 of the first end D1, the material of the portion of the bit line contact layer 19 covering the left surface W3 and the right surface W4 of the first end D1 may also include the polysilicon layer 18 described above.

[0054] It is worth noting that the metal silicide material 19b in the bit line contact layer 19 is formed by depositing a thin initial semiconductor material layer on the exposed surface of the first source / drain region 111, etching back the initial semiconductor material layer to form a semiconductor material layer, followed by conformal deposition of a metal layer and thermal annealing. The thickness of the semiconductor material layer retained after etching back ensures that the semiconductor material layer surrounding the side surface W5 of the first source / drain region 111 is completely consumed during the formation of the metal silicide material 19b, forming a single-crystal silicon semiconductor layer 11-metal silicide material 19b contact, which is an ohmic contact formed by an enclosed structure with low contact resistance of the bit line. Furthermore, the high thermal conductivity of the metal silicide material 19b / single-crystal silicon semiconductor layer 11 interface helps to improve the self-heating effect of the transistor.

[0055] In some embodiments of this disclosure, the semiconductor material layer is made of polycrystalline silicon. A thin layer of polycrystalline silicon is formed by a deposition process, and the polycrystalline silicon is used as a silicon source to react with the metal layer to form a metal silicide material 19b. Compared with forming single-crystal silicon or silicon-germanium by epitaxial growth process, and compared with forming metal silicide directly on the surface of semiconductor layer 11, this process is easier to control and can provide better interface characteristics, thereby reducing contact defects.

[0056] In some embodiments of this disclosure, by controlling the thickness of the semiconductor material layer and the metal layer, as well as the annealing conditions, a portion of the semiconductor material layer covering the upper surface W1 and the lower surface W2 of the first end D1 can be retained after the thermal annealing process. The portion of the semiconductor material layer covering the upper surface W1 and the lower surface W2 of the first end D1 includes a polysilicon layer 18. The retained polysilicon layer 18 can serve as a diffusion barrier layer and an interface stabilizing layer to prevent metal penetration. The retained polysilicon layer 18 can act as a barrier to prevent excessive diffusion of metal atoms (such as Ni and Co) in the metal silicide material 19b during subsequent high-temperature processes, thus protecting the gate oxide layer. On the other hand, the polysilicon layer 18 can improve thermal stability: for metal silicide materials 19b with relatively poor thermal stability, such as NiSi, retaining a portion of the polysilicon layer 18 as a buffer layer can suppress the agglomeration or transformation to a high-resistivity phase (such as NiSi2) of the metal silicide material 19b during subsequent thermal annealing processes, thereby maintaining stable contact resistance. Furthermore, the polysilicon layer 18 can optimize electrical contact and resistance, forming a gradient contact structure. The metal silicide material 19b / polysilicon layer 18 / semiconductor layer 11 (including monocrystalline silicon or other underlying materials) can form a contact structure with gradually changing resistance. The metal silicide material 19b provides the lowest sheet resistance, and the polysilicon layer 18, as an intermediate layer, can optimize contact resistance.

[0057] In some embodiments of this disclosure, retaining a portion of the polysilicon layer 18 during the formation of the metal silicide material 19b can reduce the sensitivity of these process parameters, expand the process window, and improve production stability and yield.

[0058] like Figure 1 , Figure 3 , Figure 4 as well as Figures 6 to 8 As shown, in some embodiments, the memory array 200 may further include: a plurality of data storage elements 21 located along a first direction on one side of the plurality of semiconductor layers 11 away from the bit line layer BL, and electrically connected to the second source / drain regions 113 of the plurality of semiconductor layers 11 in a one-to-one correspondence.

[0059] In some embodiments, the data storage element 21 may include a capacitor structure, which may include a single-sided capacitor structure, a double-sided capacitor structure, etc.

[0060] In some embodiments, a transistor 30 and a data storage element 21 electrically connected to the transistor 30 can constitute a storage unit for storing data.

[0061] In some embodiments, the semiconductor structure may further include: a first isolation layer 13 and a second isolation layer 14 (see...) Figure 15In the vertical direction, multiple data storage elements 21 are separated by a first isolation layer 13, and in the second direction, multiple data storage elements 21 are separated by a second isolation layer 14. The third sub-layer 153 may also cover the sidewalls of the first isolation layer 13 and the second isolation layer 14 near the semiconductor layer 11.

[0062] like Figure 1 and Figure 6 As shown, in some embodiments, the semiconductor structure may further include: The first interconnect layer 31 is located on the side of the memory array 200 opposite to the first substrate 10 in the vertical direction; The CMOS chip 32 is located vertically on the side of the first interconnect layer 31 opposite to the memory array 200, and is bonded to the first interconnect layer 31. The second interconnect layer 33 is located vertically on the side of the CMOS chip away from the memory array 200.

[0063] In some embodiments, the first interconnect layer 31 may include a first dielectric layer 311 and a first interconnect structure 312 located within the first dielectric layer 311. The first interconnect structure 312 may be electrically connected to the memory array 200, and the first interconnect layer 31 and the CMOS chip may be connected by fusion bonding.

[0064] In some embodiments, the second interconnect layer 33 may include a second dielectric layer 331 and a second interconnect structure 332 located within the second dielectric layer 331, the second interconnect structure 332 being electrically connected to the CMOS chip.

[0065] In some embodiments, the semiconductor structure may further include: a conductive via 34 penetrating the CMOS chip 32 and electrically connecting the first interconnect structure 312 and the second interconnect structure 332. The conductive via 34 can be used to realize a direct vertical interconnect between the first interconnect structure 312 and the second interconnect structure 332, thereby realizing an electrical interconnect between the memory array 200 and the CMOS chip 32. The CMOS chip 32 can be used to control and drive the memory array 200 to complete read, write, and erase operations.

[0066] In some embodiments, the semiconductor structure may further include: a plurality of pads 35 located on the side of the second interconnect layer 33 opposite to the CMOS chip 32, wherein the second interconnect layer 33 can be electrically connected to an external system (such as package pins, other chips) through the pads 35, thereby realizing global interconnection between the CMOS chip 32 and the external system.

[0067] This disclosure also provides a method for manufacturing a semiconductor structure, the method comprising: Step S101: Provide a second substrate; Step S102: Form a memory array on the second substrate.

[0068] like Figure 10 As shown, a memory array is formed on a second substrate, including: Step S1021: Form a plurality of stacked layers on the second substrate. Each stacked layer includes a plurality of initial semiconductor layers spaced apart in a vertical direction. Each initial semiconductor layer includes at least a first sub-segment. The first sub-segment includes a first source / drain region, a channel region, and a second source / drain region arranged along a first direction. The first source / drain region has a first end away from the channel region. The first direction is parallel to the surface of the second substrate. Step S1022: Form an isolation structure, the isolation structure being at least partially located between multiple initial semiconductor layers, and forming multiple gate layers within the isolation structure, the multiple gate layers respectively covering multiple channel regions of the stacked layers; Step S1023: An opening is formed on one side of the stacked layer in the first direction, and a portion of the isolation structure is removed from the side of the opening to expose at least the opposing upper and lower surfaces of the first end, as well as the side surface located between the upper and lower surfaces. Step S1024: Form a bit line contact layer, which extends in a vertical direction and at least surrounds the upper surface, lower surface and side surface of a plurality of first ends of the stacked layer. Step S1025: Form a bit line layer. The bit line layer extends vertically and conformally covers the surface of the bit line contact layer. The surface of the bit line layer facing the bit line contact layer has a shape adapted to the bit line contact layer. The bit line layer is electrically connected to a plurality of first source / drain regions through the bit line contact layer.

[0069] The manufacturing method of the semiconductor structure provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings.

[0070] First, execute step S101, as follows: Figure 11 As shown, a second substrate 20 is provided.

[0071] In some embodiments, the material of the second substrate 20 may be a semiconductor material, which may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In some embodiments, the second substrate 20 may be a silicon substrate, which may be doped or undoped.

[0072] Next, proceed to step S102, as follows: Figures 12 to 34 As shown, a memory array 200 is formed on the second substrate 20.

[0073] The method for forming a memory array 200 on a second substrate 20 provided in this disclosure will be further described in detail below with reference to the accompanying drawings.

[0074] First, execute step S1021, as follows: Figure 12 as well as Figure 14 and Figure 15 As shown, a plurality of stacked layers ST are formed on the second substrate 20. Each stacked layer ST includes a plurality of initial semiconductor layers 11b arranged at intervals in a vertical direction. Each initial semiconductor layer 11b includes at least a first sub-segment L1. The first sub-segment L1 includes a first source / drain region 111, a channel region 112, and a second source / drain region 113 arranged along a first direction. The first source / drain region 111 has a first end D1 away from the channel region 112. The first direction is parallel to the surface of the second substrate 20.

[0075] Specifically, multiple stacked layers ST can be formed using the following method: First, as... Figure 12 As shown, a stacked material layer STa is formed on the second substrate 20. The stacked material layer STa includes a plurality of first material layers 11a and a plurality of second material layers 12a that are stacked alternately in a vertical manner. Next, as Figure 14 and Figure 15 As shown, a patterned stacked material layer STa forms a plurality of stacked structures STb extending along a first direction; the second direction is perpendicular or oblique to the first direction and parallel to the surface of the second substrate 20; the first material layer 11a in the stacked structure STb constitutes an initial semiconductor layer 11b, and the plurality of initial semiconductor layers 11b arranged in a vertical direction in a stacked structure STb constitute a stacked layer ST.

[0076] In some embodiments, the material of the first material layer 11a may include a semiconductor material, such as single-crystal silicon; the material of the second material layer 12a may be a material with a larger etching selectivity than the first material layer 11a, and the material of the second material layer 12a may include a semiconductor material, such as silicon germanium.

[0077] In some embodiments, an epitaxial process can be used to form the stacked material layer STa. However, this is not the only possibility; other deposition processes can also be used to form the stacked material layer STa.

[0078] like Figure 12 As shown, in some embodiments, the stacked material layer STa may include a first region 101 and a second region 102 arranged along a first direction. For example... Figure 13As shown, in some embodiments, when the material of the second material layer 12a includes a semiconductor material, the second material layer 12a located in the second region 102 may be removed before the patterned stacked material layer STa to form a first void K1, and a first isolation layer 13 is formed in the first void K1. Thus, the second material layer 12a located in the second region 102 can be replaced with the first isolation layer 13.

[0079] See you again Figure 12 In some embodiments, before forming the first isolation layer 13, the method may further include: thinning the first material layer 11a located in the second region 102 from the first gap K1 to expand the first gap K1 in the vertical direction to increase the isolation effect between adjacent first material layers 11a.

[0080] See you again Figure 14 and Figure 15 In some embodiments, multiple stacked structures STb can be arranged at intervals along the second direction, and a second isolation layer 14 can be formed between adjacent stacked structures STb along the second direction. Multiple stacked structures STb arranged along the second direction can be a stack group STc.

[0081] In some embodiments, in the step of patterning the stacked material layer STa, an isolation trench T1 can be formed in the first region 101 that penetrates the stacked material layer STa. The number of stacked groups STc can be multiple. The multiple stacked groups STc include at least two stacked groups STc located on both sides of the isolation trench T1 along the first direction and adjacent to the isolation trench T1. Each stacked group STc spans the first region 101 and the second region 102 along the first direction.

[0082] like Figure 14 As shown, in some embodiments, the portion of the initial semiconductor layer 11b located in the first region 101 can be used as the first sub-segment L1. The first source / drain region 111, the channel region 112, and the second source / drain region 113 of each initial semiconductor layer 11b are distributed sequentially along a direction parallel to the first direction and away from the isolation trench T1. The first end D1 is located at the end of the first source / drain region 111 near the isolation trench T1.

[0083] like Figure 14 and Figure 15 As shown, in some embodiments, the first end D1 may include an upper surface W1 and a lower surface W2 that are opposite each other in a vertical direction, a left surface W3 and a right surface W4 that are opposite each other in a second direction, and a side surface W5 located between the upper surface W1, the lower surface W2, the left surface W3 and the right surface W4.

[0084] In some embodiments, the initial semiconductor layer 11b may further include a second sub-segment L2 connected to the second source / drain region 113 of the first sub-segment L1. Specifically, the portion of the initial semiconductor layer 11b located in the second region 102 may serve as the second sub-segment L2, with adjacent second sub-segments L2 separated by a first isolation layer 13 in the vertical direction.

[0085] In some embodiments, the materials of the first isolation layer 13 and the second isolation layer 14 may include, but are not limited to, oxides, such as silicon oxide.

[0086] Next, proceed to step S1022, as follows: Figure 19 and Figure 20 As shown, an isolation structure 15 is formed, which is at least partially located between a plurality of initial semiconductor layers 11b, and a plurality of gate layers 16 are formed within the isolation structure 15, which respectively cover a plurality of channel regions 112 of the stacked layer ST.

[0087] like Figure 16 and Figure 17 As shown, in some embodiments, before forming the isolation structure 15 and the gate layer 16, the method may further include: removing the remaining second material layer 12a from the isolation trench T1 to form a second void K2 between adjacent first segments L1.

[0088] See you again Figure 16 and Figure 17 In some embodiments, after forming the second gap K2 and before forming the isolation structure 15 and the gate layer 16, the method may further include: thinning the first segment L1 from the second gap K2 to expand the first gap K1 in a vertical direction to facilitate the subsequent formation of the isolation structure 15 and the gate layer 16 within the first gap K1. In some embodiments, the thickness of the thinned first segment L1 is less than the thickness of the second segment L2.

[0089] Next, as Figure 18 As shown, in some embodiments, after thinning the first segment L1, the second isolation layer 14 located in the first region 101 can also be removed to form a third gap K3. The second gap K2 and the third gap K3 are connected to each other to expose the multiple first segments L1 of the multiple stacked layers ST arranged along the second direction.

[0090] See you again Figure 19 and Figure 20In some embodiments, forming an isolation structure 15 may include forming a plurality of first sub-layers 151, a plurality of second sub-layers 152, and a third sub-layer 153; wherein the first sub-layers 151 are located vertically between adjacent first sub-segments L1 and spaced apart from the first sub-segments L1; the plurality of second sub-layers 152 respectively surround the first source / drain regions 111 and channel regions 112 of the plurality of initial semiconductor layers 11b, and the gate layer 16 covers a portion of the second sub-layers 152 surrounding the channel regions 112; a portion of the third sub-layers 153 are located vertically between adjacent first sub-layers 151 and surround the portion of the second sub-layers 152 not covered by the gate layer 16, and the third sub-layers 153 also cover the side surface W5 of the first end D1, as well as the sidewalls of the first sub-layers 151 and the second sub-layers 152 facing the isolation trench T1.

[0091] In some embodiments, the plurality of stacked layers ST spaced apart along the second direction may include a plurality of initial semiconductor rows spaced apart along the vertical direction. Each initial semiconductor row includes a plurality of initial semiconductor layers 11b spaced apart along the second direction. The gate layers 16 of the plurality of initial semiconductor layers 11b in each initial semiconductor row may be interconnected with each other along the second direction to form a word line layer WL extending along the second direction (see [link to documentation]). Figure 2 The area of ​​the channel region 112 covered by the word line layer WL constitutes the gate layer 16. In some embodiments, the gate layer 16 may surround the channel region 112, and each word line layer WL may surround the channel region 112 of a plurality of semiconductor layers 11 along a second direction.

[0092] In some embodiments, a portion of the second sublayer 152 surrounding the channel region 112 is sandwiched between the gate layer 16 and the channel region 112, and can serve as a gate oxide layer.

[0093] In some embodiments, the first sublayer 151 may extend continuously along the second direction, the word line layer WL may be sandwiched between adjacent first sublayers 151 in the vertical direction, and a portion of the third sublayer 153 may surround a plurality of second source / drain regions 113 and cover the sidewalls of the first isolation layer 13 and the second isolation layer 14 near the second source / drain region 113, as well as the bottom surface of the isolation trench T1.

[0094] In some embodiments, a second sublayer 152 can be formed by performing an oxidation process on the surfaces of the channel region 112 and the first source / drain region 111, and the materials of the first sublayer 151 and the second sublayer 152 can be the same, including but not limited to oxides (e.g., silicon oxide). In some embodiments, the thickness of the first sublayer 151 can be greater than the thickness of the second sublayer 152.

[0095] In some embodiments, the material of the third sublayer 153 may be a material that has a greater etching selectivity than the materials of the first sublayer 151 and the second sublayer 152, such as a nitride (including silicon nitride).

[0096] See you again Figure 19 In some embodiments, after forming the isolation structure 15 and the gate layer 16, the method may further include forming a first fill layer 171, which covers the third sub-layer 153 and fills the isolation trench T1.

[0097] Next, proceed to step S1023, as follows: Figures 21 to 26 As shown, an opening T2 is formed on one side of the stacked layer ST in the first direction, and a portion of the isolation structure 15 is removed from the opening T2 to expose at least the opposing upper surface W1 and lower surface W2 of the first end D1, and the side surface W5 located between the upper surface W1 and the lower surface W2.

[0098] See you again Figure 21 In some embodiments, the first filling layer 171 may be etched to form a plurality of openings T2 within the first filling layer 171, the plurality of openings T2 being spaced apart in the isolation trench T1 along a second direction, and the sidewalls of the openings T2 in the first direction exposing the third sublayer 153.

[0099] See you again Figures 22 to 26 In some embodiments, removing a portion of the isolation structure 15 from the opening T2 side may include: A portion of the third sublayer 153 is removed laterally from opening T2 to expose the side surface W5 of the first end D1, as well as the sidewalls of the first sublayer 151 and the second sublayer 152 facing opening T2. A further portion of the third sublayer 153 is removed laterally from opening T2 to form a first gap S1, at least a portion of which is vertically sandwiched between adjacent first sublayers 151 and 152 (e.g., ...). Figures 22 to 23 ); A portion of the first sublayer 151 and a portion of the second sublayer 152 are removed laterally from the opening T2 to form a second gap S2 and a third gap S3 communicating with the first gap S1, respectively. The third gap S3 exposes at least the upper surface W1 and the lower surface W2 of the first end D1, and the depths of the third gap S3, the first gap S1, and the second gap S2 decrease sequentially in the first direction (e.g., ...). Figures 24 to 26 ).

[0100] In some embodiments, since the thickness of the first sublayer 151 is greater than the thickness of the second sublayer 152, the etching rate of the second sublayer 152 is faster and the depth of the third gap S3 formed is greater during the step of laterally removing a portion of the first sublayer 151 and a portion of the second sublayer 152.

[0101] In some embodiments, the size of the opening T2 in the second direction may be larger than the size of the first end D1 in the second direction, and the projection of the first end D1 in the first direction may fall within the projection range of the opening T2 in the first direction. In the step of removing part of the isolation structure 15, part of the third sub-layer 153 and part of the second sub-layer 152 located on both sides of the first end D1 along the second direction are also removed, so that the formed third gap S3 also exposes the left surface W3 and the right surface W4 of the first end D1, and the first gap S1 surrounds part of the third gap S3.

[0102] Next, proceed to step S1024, as follows: Figures 27 to 32 As shown, a bit line contact layer 19 is formed, which extends in a vertical direction and at least surrounds the upper surface W1, lower surface W2 and side surface W5 of a plurality of first ends D1 of the stacked layer ST.

[0103] Specifically, forming the bit line contact layer 19 may include: An initial semiconductor material layer 181a is formed, which conformally covers the inner wall of the opening T2, as well as the exposed surfaces of the isolation structure 15 and the first end D1 (e.g., Figure 27 ); A portion of the initial semiconductor material layer 181a is removed to form a semiconductor material layer 181 with a predetermined thickness. The semiconductor material layer 181 extends in a vertical direction and at least surrounds the upper surface W1, lower surface W2, and side surface W5 of a plurality of first ends D1 of the stacked layer ST (e.g., Figure 28 ); A metal layer 182 is formed, which conformally covers the inner wall of the opening T2 and the surface of the semiconductor material layer 181 (e.g., Figure 29 ); A thermal annealing process is performed to convert at least a portion of the semiconductor material layer 181 and a portion of the metal layer 182 into a metal-semiconductor compound material 19a, and the metal layer 182 that has not been converted into the metal-semiconductor compound material 19a is removed to form a bit line contact layer 19 (e.g., Figures 30 to 32 ).

[0104] In this embodiment of the present disclosure, by etching the isolation structure 15, the sidewalls of the first sub-layer 151, the second sub-layer 152 and the third sub-layer 153 are recessed inward along the first direction relative to each other on the side surface W5, thereby forming a first gap S1, a second gap S2 and a third gap S3 that expose the first end D1. The initial semiconductor material layer 181a and the metal layer 182 fill at least part of the first gap S1, the second gap S2 and the third gap S3, thereby expanding the filling space of the initial semiconductor material layer 181a and the metal layer 182 and thus improving the filling quality.

[0105] like Figure 31 and Figure 32 As shown, in some embodiments, the bit line contact layer 19 may include a plurality of first sub-parts 191, a plurality of second sub-parts 192, and a plurality of third sub-parts 193 connected sequentially in a vertical direction; wherein, in the bit line contact layer 19, the portion located in the third gap S3 and the portion covering the side surface W5 can be used as the first sub-part 191, the portion located in the second gap S2 can be used as the second sub-part 192, and the portion located in the first gap S1 can be used as the third sub-part 193. The first sub-part 191 at least directly covers the upper surface W1, lower surface W2, and side surface W5 of the first end D1; the second sub-part 192 is located between adjacent first sub-parts 191 in a vertical direction, and at least a portion of the third sub-part 193 is sandwiched between adjacent first sub-parts 191 and second sub-parts 192 in a vertical direction, and the first sub-part 191, second sub-part 192, and third sub-part 193 respectively cover the sidewalls of the opposite side surface W5 of the second sub-layer 152, the first sub-layer 151, and the third sub-layer 153 that are recessed inward in a first direction.

[0106] In this embodiment of the present disclosure, the third gap S3 exposes at least the upper surface W1 and the lower surface W2 of the first end D1, the first sub-part 191 directly covers at least the upper surface W1, the lower surface W2 and the side surface W5 of the first end D1, and the bit line contact layer 19 surrounds at least the upper surface W1, the lower surface W2 and the side surface W5 of the first end D1, that is, the bit line contact layer 19 at least partially surrounds the outer surface of the first end D1, thereby increasing the contact area between the bit line contact layer 19 and the first source / drain region 111 and reducing the contact resistance between the bit line contact layer 19 and the first source / drain region 111.

[0107] like Figure 32 As shown, in some embodiments, when the third gap S3 also exposes the left surface W3 and right surface W4 of the first end D1, the first sub-part 191 also directly covers the left surface W3 and right surface W4 of the first end D1, the third sub-part 193 surrounds part of the first sub-part 191, and the bit line contact layer 19 also surrounds the left surface W3 and right surface W4 of the first end D1, that is, the bit line contact layer 19 completely surrounds the outer surface of the first end D1, thus further increasing the contact area between the bit line contact layer 19 and the first source / drain region 111.

[0108] In some embodiments, the depths of the third gap S3, the first gap S1, and the second gap S2 decrease sequentially in the first direction, and the distances by which the partial sidewalls of the second sub-layer 152, the third sub-layer 153, and the first sub-layer 151 are recessed inward relative to the side surface W5 in the first direction decrease sequentially. The sidewalls of the first sub-part 191, the third sub-part 193, and the second sub-part 192 are arranged sequentially in the direction close to the bit line layer BL, away from the sidewalls of the bit line contact layer BL, so that the sidewalls of the bit line contact layer 19 away from the isolation trench T1 in the first direction are serrated.

[0109] In some embodiments, when the sidewall of the bit line contact layer 19 facing away from the isolation trench T1 is serrated, the sidewall of the bit line contact layer 19 facing the isolation trench T1 may also be serrated.

[0110] In some embodiments, the material of the semiconductor material layer 181 may include semiconductor materials such as silicon, germanium, and silicon-germanium. For example, the semiconductor material layer 181 may include a polycrystalline silicon layer 18. The material of the metal layer 182 may include one or more of cobalt, nickel, molybdenum, titanium, tungsten, tantalum, and platinum, such as titanium and / or molybdenum. The metal semiconductor compound material 19a may include one or more of metal silicide material 19b, metal germanide material, and metal silicon-germanium material, such as metal silicide material 19b. The metal silicide material 19b may include one or more of cobalt silicide, nickel silicide, molybdenum silicide, titanium silicide, tungsten silicide, tantalum silicide, or platinum silicide, such as titanium silicide and / or molybdenum silicide.

[0111] In this embodiment of the disclosure, the material of the bit line contact layer 19 includes a metal semiconductor compound material 19a (e.g., a metal silicide material 19b). The metal semiconductor compound material 19a has a lower resistance, thereby reducing the resistance of the bit line contact layer 19 and improving the performance of the semiconductor structure.

[0112] In other embodiments of this disclosure, the material of the bit line contact layer 19 may include polycrystalline silicon in addition to the metal silicide material 19b. For example... Figures 36 to 38 As shown, by way of example, in the bit line contact layer 19, the material covering the side surface W5 of the first end D1 is a metal silicide material 19b, and the material covering the upper surface W1 and lower surface W2 of the first end D1 may include a polysilicon layer 18, for example, it may be entirely polysilicon layer 18, or it may be a mixed material including polysilicon layer 18 and metal silicide material 19b.

[0113] In some embodiments, in the second sub-part 192 and the third sub-part 193, the portion near the opening T2 includes a metal silicide material 19b, and the portion near the isolation structure 15 may include a polysilicon layer 18.

[0114] like Figure 38 As shown, in some other embodiments, when the bit line contact layer 19 also covers the left surface W3 and the right surface W4 of the first end D1, the material of the portion of the bit line contact layer 19 covering the left surface W3 and the right surface W4 of the first end D1 may also include the polysilicon layer 18 described above, in order to increase the applicability of different scenarios.

[0115] In this embodiment of the disclosure, the metal silicide material 19b in the bit line contact layer 19 is formed by depositing a thin initial semiconductor material layer 181a on the exposed surface of the first source / drain region 111, and then etching back the initial semiconductor material layer 181a to form a semiconductor material layer 181 (e.g., a polysilicon layer 18). Afterwards, a metal layer 182 is deposited using conformal deposition, and then thermally annealed to form the metal silicide material 19b.

[0116] In this embodiment, a thin polycrystalline silicon layer 18 is formed by deposition process, and the polycrystalline silicon layer 18 is used as a silicon source to react with the metal layer 182 to form a metal silicide material 19b. Compared with forming single crystal silicon or silicon-germanium by epitaxial growth process, and compared with forming metal silicide directly on the surface of semiconductor layer 11, this process is easier to control and can provide better interface characteristics, thereby reducing contact defects.

[0117] In some embodiments, the initial semiconductor material layer 181a and the metal layer 182 can be formed by one or more thin film deposition processes. The thin film deposition process can include chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. For example, atomic layer deposition process can be used to obtain the initial semiconductor material layer 181a and the metal layer 182 with good conformability.

[0118] In some embodiments, the thickness of the semiconductor material layer 181 and the metal layer 182, as well as the annealing conditions, can be controlled so that after the thermal annealing process, at least the portion of the semiconductor material layer 181 covering the side surface W5 of the first end D1 is completely consumed when forming the metal silicide material 19b. The metal silicide material 19b directly contacts the first end D1 of the monocrystalline silicon to form a semiconductor layer-metal silicide layer contact of the monocrystalline silicon, which is an ohmic contact formed by an enclosed structure with low contact resistance of the bit line. Furthermore, the high thermal conductivity of the metal silicide / monocrystalline silicon interface helps to improve the self-heating effect of the transistor.

[0119] In some embodiments, by controlling the thickness of the semiconductor material layer 181 and the metal layer 182, as well as the annealing conditions, a portion of the semiconductor material layer 181 covering the upper surface W1 and lower surface W2 of the first end D1 can be retained after the thermal annealing process. This portion of the semiconductor material layer 181 covering the upper surface W1 and lower surface W2 of the first end D1 includes a polysilicon layer 18. The polysilicon layer 18 can serve as a diffusion barrier layer and an interface stabilizing layer to prevent metal penetration. The retained polysilicon layer 18 can act as a barrier to prevent excessive diffusion of metal atoms (such as Ni or Co) in the metal silicide material 19b during subsequent high-temperature processes, protecting the gate oxide layer. Furthermore, for metal silicide materials 19b with relatively poor thermal stability, such as NiSi, retaining a portion of the polysilicon layer 18 as a buffer layer can suppress agglomeration or transformation to a high-resistivity phase (such as NiSi2) in the metal silicide material 19b during subsequent thermal annealing processes, thereby maintaining stable contact resistance.

[0120] In some embodiments of this disclosure, the polysilicon layer 18 can optimize electrical contact and resistance, forming a gradient contact structure. The metal silicide material 19b, the polysilicon layer 18, and the semiconductor layer 11 (including monocrystalline silicon or other underlying materials) can constitute a contact structure with gradually changing resistance. The metal silicide material 19b provides the lowest sheet resistance, and the polysilicon layer 18, as an intermediate layer, can optimize contact resistance. Retaining a portion of the polysilicon layer 18 during the formation of the metal silicide material 19b can reduce the sensitivity of these process parameters, expand the process window, and improve production stability and yield.

[0121] Next, in step S1025, as follows: Figure 33 As shown, a bit line layer BL is formed, which extends in the vertical direction and conformally covers the surface of the bit line contact layer 19. The surface of the bit line layer BL facing the bit line contact layer 19 has a shape adapted to the bit line contact layer 19. The bit line layer BL is electrically connected to a plurality of first source / drain regions 111 through the bit line contact layer 19.

[0122] In some embodiments, there may be multiple bit line layers BL, which are arranged along a second direction, and each bit line layer BL is electrically connected to multiple first source / drain regions 111 of a stacked layer ST.

[0123] In this embodiment, the bit line contact layer 19 extends continuously in the vertical direction, and the surface of the bit line layer BL facing the bit line contact layer 19 has a shape adapted to the bit line contact layer 19. In this way, the contact area between the bit line layer BL and the bit line contact layer 19 is increased, and the contact resistance between the bit line layer BL and the bit line contact layer 19 is reduced. At the same time, the material of the bit line contact layer 19 includes a metal semiconductor compound material 19a to reduce the contact resistance between the bit line layer BL and the bit line contact layer 19.

[0124] In some embodiments, the surface of the bit line contact layer 19 facing away from the bit line layer BL in the first direction is serrated, and the surface of the bit line contact layer 19 facing the bit line layer BL in the first direction can also be serrated, thereby further increasing the contact area between the bit line layer BL and the bit line contact layer 19.

[0125] See you again Figure 33 In some embodiments, after the bit line layer BL is formed, a second filling layer 172 may also be formed within the opening T2.

[0126] Next, as Figure 34 As shown, in some embodiments, forming the storage array 200 may further include: The second segment L2 of the initial semiconductor layer 11b is removed, and the remaining initial semiconductor layer 11b constitutes the semiconductor layer 11. Multiple data storage elements 21 are formed. The data storage elements 21 are located on the side of the semiconductor layer 11 away from the bit line layer BL along the first direction, and are electrically connected to the second source / drain regions 113 of the multiple semiconductor layers 11 in a one-to-one correspondence.

[0127] In some embodiments, the data storage element 21 may include a capacitor structure, which may include a single-sided capacitor structure, a double-sided capacitor structure, etc.

[0128] In some embodiments, in the vertical direction, a plurality of data storage elements 21 are spaced apart by a first isolation layer 13, and in the second direction, a plurality of data storage elements 21 are spaced apart by a second isolation layer 14.

[0129] In some embodiments, a semiconductor layer 11, a gate layer 16 covering a channel region 112 of the semiconductor layer 11, and a portion of a second sublayer 152 sandwiched between the gate layer 16 and the channel region 112 can constitute a transistor 30, and a transistor 30 and a data storage element 21 electrically connected thereto can constitute a storage cell for storing data.

[0130] Next, as Figure 35 As shown, in some embodiments, after forming the storage array 200, the method may further include: A first interconnect layer 31 is formed, which is located on the side of the memory array 200 opposite to the second substrate 20 along the vertical direction; A CMOS chip 32 is provided and bonded to a first interconnect layer 31. The CMOS chip 32 is located on the side of the first interconnect layer 31 opposite to the memory array 200 in the vertical direction. A second interconnect layer 33 is formed, which is located on the side of the CMOS chip 32 opposite to the memory array 200 in the vertical direction.

[0131] In some embodiments, the first interconnect layer 31 may include a first dielectric layer 311 and a first interconnect structure 312 located within the first dielectric layer 311. The first interconnect structure 312 may be electrically connected to the memory array 200, and the first interconnect layer 31 and the CMOS chip are connected by fused bonding.

[0132] In some embodiments, the second interconnect layer 33 may include a second dielectric layer 331 and a second interconnect structure 332 located within the second dielectric layer 331, the second interconnect structure 332 being electrically connected to the CMOS chip.

[0133] In some embodiments, a conductive via 34 may be formed through the CMOS chip 32 and electrically connected to the first interconnect structure 312 and the second interconnect structure 332. The conductive via 34 may be used to realize a direct vertical interconnect between the first interconnect structure 312 and the second interconnect structure 332, thereby realizing an electrical interconnect between the memory array 200 and the CMOS chip 32. The CMOS chip 32 may be used to control and drive the memory array 200 to complete read, write, and erase operations.

[0134] In some embodiments, a plurality of pads 35 may be formed on the surface of the second interconnect layer 33 away from the CMOS chip 32. The second interconnect layer 33 can be electrically connected to external systems (such as package pins, other chips) through the pads 35, thereby realizing global interconnection between the CMOS chip 32 and external systems.

[0135] Next, as Figure 1 As shown, after forming the second interconnect layer 33, the method may further include: removing the second substrate 20; forming a first substrate 10 on the side of the memory array 200 away from the first interconnect layer 31, wherein the material of the first substrate 10 includes an insulating material.

[0136] Specifically, the second substrate 20 can be removed by performing a thinning process from the side of the second substrate 20 away from the memory array 200. In some embodiments, when the isolation trench T1 and the first filling layer 171, the second filling layer 172 or the third sublayer 153 located in the isolation trench T1 extend into the second substrate 20, in the step of removing the second substrate 20, a portion of the first filling layer 171, a portion of the second filling layer 172 or a portion of the third sublayer 153 are also removed.

[0137] In some embodiments, the second substrate 20 may be damaged during the step of forming the memory array 200, thereby forming a leakage channel in the second substrate 20; by replacing the second substrate 20 with a first substrate 10 having an insulating material, leakage of the first substrate 10 can be avoided, and parasitic capacitance and signal crosstalk between the memory array 200 and the first substrate 10 can be mitigated or avoided, and power consumption can be reduced and the performance of the semiconductor structure can be improved.

[0138] In some embodiments, the material of the first substrate 10 may include, but is not limited to, oxides, such as silicon oxide.

[0139] In some embodiments, where the bit line contact layer 19 comprises a metal silicide material 19b and a polysilicon layer 18, it is possible to Figures 36 to 38 Based on the semiconductor structure shown, the steps of forming the bit line layer BL and the second fill layer 172 are continued to form, as shown. Figure 39 The structure shown.

[0140] Next, as Figure 40 As shown, the second segment L2 of the initial semiconductor layer 11b can be removed to form a semiconductor layer 11, and a plurality of data storage elements 21 can be formed that are electrically connected to the second source / drain regions 113 of the plurality of semiconductor layers 11 in a one-to-one correspondence.

[0141] Next, as Figure 41 As shown, it can execute with Figure 35 Similar steps are taken: first, a first interconnect layer 31 is formed on the memory array 200; then, a CMOS chip 32 is provided and bonded to the first interconnect layer 31; and then, a second interconnect layer 33 is formed on the CMOS chip 32.

[0142] Next, the second substrate 20 can be removed, and a first substrate 10 can be formed on the side of the memory array 200 opposite to the first interconnect layer 31, forming as shown in the diagram. Figures 6 to 9 The semiconductor structure shown.

[0143] like Figure 42As shown, this disclosure also provides an electronic device 1 with storage function. The electronic device 1 includes a processing device 2 and a storage device 3 electrically connected to the processing device 2. The storage device 3 includes the aforementioned... Figures 1 to 9 The semiconductor structure 4 is described in the document. The electronic device 1 can be a terminal device, such as a personal computer, mobile phone, tablet computer, consumer electronics (e.g., smart home appliances, autonomous vehicles, smart wearable products such as smartwatches and smart bracelets), virtual reality (VR) devices, augmented reality (AR) devices, or a server, data center, etc. The storage device 3 can be, for example, dynamic random access memory (DRAM). The storage function in the electronic device 1 can be implemented through these storage devices 3.

[0144] In some embodiments, the processing device 2 and the memory device 3 can be two independent chips forming a separate memory. In other embodiments, the memory device 3 and the processing device 2 can also be integrated into the same chip to form an embedded memory. This electronic device 1 is similar to the one described above. Figures 1 to 9 The described semiconductor structure 4 can solve the same technical problem and achieve the same expected results.

[0145] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: The storage array includes: A plurality of transistor groups, each of the transistor groups comprising: a plurality of semiconductor layers spaced apart in a vertical direction; each of the semiconductor layers comprising a first source / drain region, a channel region, and a second source / drain region arranged along a first direction; the first source / drain region having opposing upper and lower surfaces, opposing left and right surfaces, and a side surface located between the upper, lower, left, and right surfaces at a first end away from the channel region; Multiple gate layers, each covering the channel region of the multiple semiconductor layers; Bit line contact layer, extending in a vertical direction, the bit line contact layer at least surrounds the upper surface, the lower surface and the side surface of the first end; A bitline layer extends vertically and conformally covers the surface of the bitline contact layer, wherein the surface of the bitline layer facing the bitline contact layer has a shape adapted to the bitline contact layer, and the bitline layer is electrically connected to a plurality of first source / drain regions through the bitline contact layer.

2. The semiconductor structure according to claim 1, characterized in that, The bit line contact layer also surrounds the left and right surfaces of the first end.

3. The semiconductor structure according to claim 1 or 2, characterized in that, The bit line contact layer comprises a metal silicide material, which includes at least one of titanium silicide or molybdenum silicide.

4. The semiconductor structure according to claim 1 or 2, characterized in that, In the bit line contact layer, the material covering the side surface of the first end is a metal silicide material, and the material covering the upper and lower surfaces of the first end includes a semiconductor material.

5. The semiconductor structure according to claim 1, characterized in that, The bit line contact layer includes a plurality of first sub-parts, a plurality of second sub-parts, and a plurality of third sub-parts connected sequentially along a vertical direction; wherein... The first sub-part directly covers at least the upper surface, the lower surface, and the side surface of the first end; the second sub-part is located between adjacent first sub-parts in a vertical direction, and at least part of the third sub-part is sandwiched between adjacent first sub-parts and second sub-parts in a vertical direction. In the first direction, the first sub-part, the third sub-part, and the second sub-part are arranged sequentially in a direction close to the bit line layer, away from the sidewall of the bit line layer, so that the bit line contact layer away from the sidewall of the bit line layer is serrated.

6. The semiconductor structure according to claim 1, characterized in that, The storage array also includes: Multiple data storage elements are located along the first direction on one side of the multiple semiconductor layers away from the bit line layer, and are electrically connected to the second source / drain regions of the multiple semiconductor layers one by one.

7. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: The first interconnect layer is located on the memory array in a vertical direction; A CMOS chip is located vertically on the side of the first interconnect layer opposite to the memory array and is bonded to the first interconnect layer. The second interconnect layer is located vertically on the side of the CMOS chip facing away from the memory array.

8. A method for manufacturing a semiconductor structure, characterized in that, include: Provide a second substrate; A memory array is formed on the second substrate; Forming the storage array includes: A plurality of stacked layers are formed on the second substrate, each stacked layer including a plurality of initial semiconductor layers spaced apart in a vertical direction, each initial semiconductor layer including at least a first sub-segment, the first sub-segment including a first source / drain region, a channel region and a second source / drain region arranged along a first direction, the first source / drain region having a first end away from the channel region; the first direction is parallel to the surface of the second substrate; An isolation structure is formed, the isolation structure being at least partially located between the plurality of initial semiconductor layers, and a plurality of gate layers are formed within the isolation structure, the plurality of gate layers respectively covering the plurality of channel regions of the stacked layers; An opening is formed on one side of the stacked layer in the first direction, and a portion of the isolation structure is removed from the opening to expose at least the opposing upper and lower surfaces of the first end, as well as the side surface located between the upper and lower surfaces. A bit line contact layer is formed, the bit line contact layer extending in a vertical direction and at least surrounding the upper surface, the lower surface and the side surface of a plurality of first ends of the stacked layer; A bitline layer is formed, which extends vertically and conformally covers the surface of the bitline contact layer, wherein the surface of the bitline layer facing the bitline contact layer has a shape adapted to the bitline contact layer, and the bitline layer is electrically connected to a plurality of first source / drain regions through the bitline contact layer.

9. The manufacturing method according to claim 8, characterized in that, Forming the isolation structure includes: A plurality of first sublayers, a plurality of second sublayers, and a third sublayer are formed; wherein, the first sublayers are located vertically between adjacent first sub-segments and spaced apart from the first sub-segments; the plurality of second sublayers respectively surround the first source / drain regions and channel regions of the plurality of initial semiconductor layers, and the gate layer covers a portion of the second sublayers surrounding the channel regions; a portion of the third sublayers are located vertically between adjacent first sublayers and surround the portion of the second sublayers not covered by the gate layer, the third sublayers also cover the side surface of the first end, as well as the sidewalls of the first and second sublayers, and the opening exposes the third sublayer.

10. The manufacturing method according to claim 9, characterized in that, Removing a portion of the isolation structure from the side of the opening includes: A portion of the third sublayer is removed laterally from the opening to expose the side surface of the first end and the sidewalls of the first and second sublayers facing the opening, and a portion of the third sublayer is further removed laterally from the opening to form a first gap, at least a portion of which is sandwiched vertically between adjacent first and second sublayers. A portion of the first sublayer and a portion of the second sublayer are removed from the side of the opening to form a second gap and a third gap communicating with the first gap, respectively. The third gap exposes at least the upper and lower surfaces of the first end. The bit line contact layer also covers the remaining sidewall of the isolation structure facing the opening, and the depths of the third gap, the first gap, and the second gap decrease sequentially in the first direction, so that the sidewall of the bit line contact layer away from the bit line layer in the first direction is serrated.

11. The manufacturing method according to claim 8, characterized in that, Forming the bit line contact layer includes: An initial semiconductor material layer is formed, which conformally covers the inner wall of the opening, as well as the surface of the isolation structure and the first end that is exposed; A portion of the initial semiconductor material layer is removed to form a semiconductor material layer having a predetermined thickness, the semiconductor material layer extending in a vertical direction and at least surrounding the upper surface, the lower surface, and the side surface of a plurality of first ends of the stacked layer; A metal layer is formed, which conformally covers the inner wall of the opening and the surface of the semiconductor material layer; Perform a thermal annealing process to convert at least a portion of the semiconductor material layer and a portion of the metal layer into a metal semiconductor compound material; Remove the metal layer that has not been converted into the metal semiconductor compound material to form the bit line contact layer.

12. The manufacturing method according to claim 8, characterized in that, The initial semiconductor layer further includes a second sub-segment connected to the second source / drain region of the first sub-segment; Forming the storage array further includes: The second sub-segment of the initial semiconductor layer is removed, and the remaining initial semiconductor layer constitutes a semiconductor layer; Multiple data storage elements are formed, wherein the data storage elements are located along the first direction on the side of the semiconductor layer away from the bit line layer, and are electrically connected to the second source / drain regions of the multiple semiconductor layers in a one-to-one correspondence.

13. The manufacturing method according to claim 8, characterized in that, After forming the storage array, the method further includes: A first interconnect layer is formed, which is located in the vertical direction on the side of the memory array opposite to the second substrate; A CMOS chip is provided and the CMOS chip is bonded to the first interconnect layer, wherein the CMOS chip is located on the side of the first interconnect layer opposite to the memory array in a vertical direction; A second interconnect layer is formed, which is located vertically on the side of the CMOS chip opposite to the memory array.

14. The manufacturing method according to claim 13, characterized in that, After forming the second interconnect layer, the method further includes: Remove the second substrate; A first substrate is formed on the side of the storage array away from the first interconnect layer, and the material of the first substrate includes an insulating material.

15. An electronic device, characterized in that, include: Processing devices; And a memory device electrically connected to the processing device, the memory device comprising the semiconductor structure of any one of claims 1 to 7.

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