Semiconductor device and data storage system including the same

Abstract

A semiconductor device and a data storage system including the same are provided. The semiconductor device includes a first substrate structure including a substrate and a circuit element, and a second substrate structure on the first substrate structure, wherein the second substrate structure includes gate electrodes stacked in a first direction, interlayer insulating layers stacked alternately with the gate electrodes, channel structures extending into the gate electrodes and each including a channel layer and a channel dielectric layer on a side surface of the channel layer, and source structures on the channel structures and including a horizontal region and a contact region extending from the horizontal region and contacting the channel layer, wherein the contact region extends into a portion of the channel dielectric layer of each of the channel structures, and a lower surface of the contact region contacts the channel structures and the interlayer insulating layers.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and data storage systems that include semiconductor devices. Background Technology

[0002] In data storage systems that include data storage, semiconductor devices capable of storing large amounts of data are desired. Therefore, methods for increasing the data storage capacity of semiconductor devices have been investigated. For example, as one method for increasing the data storage capacity of semiconductor devices, semiconductor devices comprising three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells have been proposed. Summary of the Invention

[0003] One aspect of this disclosure is to provide semiconductor devices with improved reliability and mass production yield.

[0004] One aspect of this disclosure is to provide a data storage system including semiconductor devices with improved reliability and mass production yield.

[0005] A semiconductor device according to an example embodiment includes: a first substrate structure, the first substrate structure including a substrate, circuit elements on the substrate, a first interconnect structure on the circuit elements, and a first bonding pad on the first interconnect structure; and a second substrate structure located on the first substrate structure, wherein the second substrate structure includes: gate electrodes spaced apart from each other and stacked in a first direction perpendicular to the upper surface of the substrate; an interlayer insulating layer alternately stacked with the gate electrodes; a channel structure extending into the gate electrodes and extending in the first direction, and including a channel layer and a channel dielectric layer located on a side surface of the channel layer; and an upper insulating layer located on the channel structure. The upper end and the interlayer insulating layer; a source structure located on the upper insulating layer, the source structure including a horizontal region and a contact region, the horizontal region extending in a second direction parallel to the upper surface of the first substrate structure, the contact region extending into the upper insulating layer and a portion of each of the channel structures, extending from the horizontal region in the first direction, and contacting the channel layer of each of the channel structures; a second interconnect structure located on the gate electrode and including bit lines electrically connected to corresponding channel structures in the channel structures; and a second bonding pad located on the second interconnect structure and electrically connected to the first bonding pad, wherein a portion of the upper surface of each of the channel structures contacts the upper insulating layer.

[0006] A semiconductor device according to an example embodiment includes: a first substrate structure including a substrate and circuit elements located on the substrate; and a second substrate structure located on the first substrate structure, wherein the second substrate structure includes: gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate; an interlayer insulating layer alternately stacked with the gate electrodes; a channel structure extending into the gate electrodes and extending in the first direction, and including a channel layer and a channel dielectric layer located on a side surface of the channel layer; and a source structure located on the channel structure and including a horizontal region and a contact region, the horizontal region extending in a second direction parallel to the upper surface of the substrate, the contact region extending from the horizontal region in the first direction and contacting the channel layer, wherein the contact region extends into a portion of the channel dielectric layer of each of the channel structures, and wherein a lower surface of the contact region contacts the channel structure and the interlayer insulating layer.

[0007] A data storage system according to an example embodiment includes a semiconductor device and a controller. The semiconductor device includes a first substrate structure comprising a substrate and circuit elements located on the substrate. The semiconductor device further includes a second substrate structure including input / output pads electrically connected to corresponding circuit elements in the circuit elements. The controller is electrically connected to the semiconductor device via the input / output pads. The second substrate structure further includes: gate electrodes spaced apart from each other and stacked in a first direction perpendicular to an upper surface of the substrate; a channel structure extending into the gate electrodes and extending in the first direction, the channel structure including a channel layer and a channel dielectric layer located on a side surface of the channel layer; and a source structure located on the channel structure and including a horizontal region and a contact region. The horizontal region extends in a second direction parallel to the upper surface of the substrate, and the contact region extends from the horizontal region in the first direction and contacts the channel layer. In the upper region of each channel structure, the contact region contacts a first portion of the side surface of the channel layer and does not contact a second portion of the side surface of the channel layer.

[0008] The source structure can be connected to the channel layer through a contact region that penetrates a portion of the channel structure or extends into a portion of the channel structure, thereby providing a semiconductor device with improved reliability and batch yield, as well as a data storage system including the semiconductor device.

[0009] The advantages and effects of this application are not limited to the foregoing, and can be more easily understood in the process of describing specific exemplary embodiments of this disclosure. Attached Figure Description

[0010] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic top view of a semiconductor device according to an example embodiment; Figure 2 This is a schematic cross-sectional view of a semiconductor device according to an example embodiment; Figure 3 This is a partial enlarged view of a semiconductor device according to an example embodiment; Figure 4A , Figure 4B and Figure 4C This is a schematic partial enlarged view of a semiconductor device according to an example embodiment; Figure 5A , Figure 5B , Figure 5C and Figure 5D This is a schematic top view of a semiconductor device according to an example embodiment; Figure 6A and Figure 6B These are schematic cross-sectional views and partial enlarged views of the semiconductor device according to the example embodiment; Figure 7 This is a schematic cross-sectional view of a semiconductor device according to an example embodiment; Figure 8 This is a schematic cross-sectional view of a semiconductor device according to an example embodiment; Figure 9A and Figure 9B These are schematic top views and cross-sectional views of a semiconductor device according to an example embodiment; Figure 10A , Figure 10B , Figure 10C and Figure 10D These are schematic cross-sectional views and partial enlarged views of a semiconductor device according to an example embodiment; Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E and Figure 11F This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an example embodiment; Figure 12 This is a schematic view illustrating a data storage system including semiconductor devices according to an example embodiment; Figure 13This is a schematic perspective view of a data storage system including semiconductor devices according to an example embodiment; and Figure 14 This is a schematic cross-sectional view of a semiconductor package according to an example embodiment. Detailed Implementation

[0011] In the following description, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following, the terms “above,” “upper,” “upper surface,” “lower,” “lower,” “lower surface,” “side surface,” etc., may be understood as being based on the indications in the drawings, except that they are indicated by reference numerals and referred to separately.

[0012] To clarify this disclosure, the same elements or equivalents are referred to by the same reference numerals throughout the specification. Furthermore, because the dimensions and thicknesses of the constituent components shown in the drawings are arbitrarily given for better understanding and ease of description, this disclosure is not limited to the dimensions and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are overstated for better understanding and ease of description.

[0013] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it may be directly on the other element, or there may be intermediate elements present. In contrast, when an element is referred to as being “directly on” another element, there are no intermediate elements present. Furthermore, for ease of description, spatially relative terms such as “below,” “under,” “down,” “above,” “on top,” etc., are used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. It will be understood that, in addition to the orientation depicted in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is flipped, an element described as being “below” or “under” another element or feature will subsequently be oriented “above” the other element or feature. Thus, the term “below” can cover both above and below orientations. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0014] Additionally, unless explicitly stated otherwise, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply inclusion of the stated element but not exclusion of any other element. As used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise. The term “and / or” includes any and all combinations of one or more of the associated listed items. The term “connection” may be used herein to refer to physical and / or electrical connections, and may refer to direct or indirect physical and / or electrical connections. The term “exposed” may be used to define a relationship between a particular layer or surface, but does not require that the layer or surface be free of other elements or layers in the finished device. Components or layers described with reference to “overlapping” in a particular direction may at least partially obscure each other when viewed along a line extending in a particular direction or in a plane perpendicular to a particular direction. The terms “first,” “second,” etc., may be used herein only to distinguish one component, element, etc., from another component, element, etc.

[0015] Figure 1 This is a schematic top view of a semiconductor device according to an example embodiment.

[0016] Figure 2 This is a schematic cross-sectional view of a semiconductor device according to an example embodiment. Figure 2 It is along Figure 1 The cross-sectional view taken by the cutting line I-I'.

[0017] Figure 3 This is a partial enlarged view of a semiconductor device according to an example embodiment. Figure 3 yes Figure 2 A magnified view of region "A".

[0018] refer to Figures 1 to 3 The semiconductor device 100 includes a first substrate structure S1 and a second substrate structure S2 that are joined to each other and arranged perpendicularly (e.g., in the Z direction). The first substrate structure S1 may include a peripheral circuit region, and the second substrate structure S2 may include a memory cell region. In some example embodiments, the second substrate structure S2 may be disposed below the first substrate structure S1. Figure 1 The planar arrangement of some components of the second substrate structure S2 is shown.

[0019] The first substrate structure S1 may include a substrate 201, a source / drain region 205 and a component isolation layer 210 located within the substrate 201, a circuit element 220 disposed on the substrate 201, a peripheral region insulating layer 290, a circuit contact plug 270, a circuit interconnect 280, a first bonding passage 295, a first bonding pad 298, and a first bonding insulating layer 299.

[0020] The substrate 201 may have an upper surface extending in both the X and Y directions. An active region may be defined in the substrate 201 by a device isolation layer 210. A source / drain region 205, including impurities, may be disposed in a portion of the active region. The substrate 201 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The substrate 201 may be provided as a bulk wafer or an epitaxial layer.

[0021] Circuit element 220 may include planar transistors. Each circuit element 220 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. Source / drain regions 205 may be configured as source / drain regions on both sides of the circuit gate electrode 225 within the substrate 201.

[0022] The peripheral region insulating layer 290 may be configured to cover or at least partially overlap the circuit element 220 on the upper surface of the substrate 201. The peripheral region insulating layer 290 may include multiple insulating layers formed in different process operations. The peripheral region insulating layer 290 may be formed of an insulating material.

[0023] Circuit contact plug 270 and circuit interconnect 280 may be included in a first interconnect structure electrically connected to circuit element 220 and source / drain region 205. Circuit contact plug 270 may have a cylindrical shape, and circuit interconnect 280 may have a line shape or a straight line shape. Electrical signals may be applied to circuit element 220 through circuit contact plug 270 and circuit interconnect 280. In areas not shown, circuit contact plug 270 may also be connected to circuit gate electrode 225. Circuit interconnect 280 may be connected to circuit contact plug 270 and may be arranged in multiple layers. Circuit contact plug 270 and circuit interconnect 280 may include conductive materials, such as tungsten (W), copper (Cu), and aluminum (Al), and each of these components may also include a diffusion barrier layer. In example embodiments, the number of layers of circuit contact plug 270 and circuit interconnect 280 may vary.

[0024] The first bonding path 295, the first bonding pad 298, and the first bonding insulating layer 299 may be included in the first bonding structure and may be disposed on the uppermost circuit interconnect 280. The first bonding path 295 may have a cylindrical shape, and the first bonding pad 298 may have a circular pad shape in a plane, or a relatively short line shape or a straight line shape. The upper surface of the first bonding pad 298 may form part of the upper surface of the first substrate structure S1. The first bonding path 295 and the first bonding pad 298 may provide an electrical connection path to the second substrate structure S2. In an example embodiment, some of the first bonding pads 298 may not be connected to the circuit interconnect 280 and may only be provided for bonding. The first bonding path 295 and the first bonding pad 298 may include a conductive material, such as copper (Cu).

[0025] The first bonding insulating layer 299 may be disposed on the upper surface of the peripheral region insulating layer 290 with a predetermined thickness. The first bonding insulating layer 299 may be a layer for dielectric bonding with the second bonding insulating layer 199 of the second substrate structure S2. The first bonding insulating layer 299 may also serve as a diffusion barrier layer for the first bonding pad 298, and may include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, or SiOCN.

[0026] The second substrate structure S2 may include vertically stacked gate electrodes 130, interlayer insulating layers 120 stacked alternately with the gate electrodes 130, a channel structure CH penetrating the gate electrodes 130 or extending into the gate electrodes 130, an upper insulating layer 150 located at the upper end of the channel structure CH, a source structure 160 located on the upper insulating layer 150, and a cell region insulating layer 190. The second substrate structure S2 may also include a stud 170 located on the lower surface of the channel structure CH, a bit line 180 connected to the stud 170, a cell contact plug 182, and a cell interconnect 184, as a second interconnect structure. The second substrate structure S2 may also include a second bonding path 195, a second bonding pad 198, and a second bonding insulating layer 199, as a second bonding structure.

[0027] The gate electrodes 130 may be spaced apart and stacked in a direction perpendicular to the upper surface of the substrate 201 (e.g., in the Z direction), and may form a gate stack structure including a first stack structure GS1 and a second stack structure GS2 together with the interlayer insulating layer 120. The first stack structure GS1 and the second stack structure GS2 may be stacked vertically and may extend around the first channel structure CH1 and the second channel structure CH2, respectively. However, according to the example embodiment, the gate stack structure may be formed as a single stack structure or may include three or more stack structures.

[0028] Gate electrodes 130 may be sequentially disposed from source structure 160 and may include a lower gate electrode included in the gate of a ground select transistor, a storage gate electrode included in a plurality of memory cells, and an upper gate electrode included in the gate of a string select transistor. Here, "upper" and "lower" may refer to the state prior to the bonding of the first substrate structure S1 and the second substrate structure S2. The number of storage gate electrodes included in the memory cells may be determined according to the capacity of semiconductor device 100. According to some example embodiments, the number of upper gate electrodes and lower gate electrodes may be one to four or more, and they may have the same or different structures as the storage gate electrodes. In example embodiments, gate electrode 130 may also include gate electrode 130 disposed adjacent to the upper gate electrode and / or the lower gate electrode and included in an erase transistor for an erase operation using the gate-induced drain leakage (GIDL) phenomenon. Some gate electrodes 130, such as storage gate electrodes adjacent to the upper gate electrode and / or the lower gate electrode, may be dummy gate electrodes.

[0029] like Figure 1 As shown, the gate electrode 130 can be configured to be divided into predetermined cells in the Y direction by a partition region MS. The gate electrode 130 between a pair of partition regions MS can form a single memory block, but the range of the memory block is not limited thereto.

[0030] The gate electrode 130 may include a metallic material, such as tungsten (W). According to some example embodiments, the gate electrode 130 may include polycrystalline silicon or a metal silicide material. In example embodiments, the gate electrode 130 may also include a diffusion barrier layer and may include, for example, tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or combinations thereof.

[0031] Interlayer insulating layers 120 may be disposed between gate electrodes 130. Similar to gate electrodes 130, interlayer insulating layers 120 may also be spaced apart from each other in a direction perpendicular to the upper surface of substrate 201 and may extend in the X direction. Interlayer insulating layers 120 may include a lowermost interlayer insulating layer 120_L, an intermediate interlayer insulating layer 120_M, and an uppermost interlayer insulating layer 120_U disposed at at least one end of the first stacked structure GS1 and the second stacked structure GS2 and having relatively thick thicknesses. However, the relative thicknesses and arrangement positions of the lowermost interlayer insulating layer 120_L, the intermediate interlayer insulating layer 120_M, and the uppermost interlayer insulating layer 120_U, as well as the other interlayer insulating layers 120, may be varied differently in the example embodiment. Interlayer insulating layers 120 may include insulating materials such as silicon oxide or silicon nitride.

[0032] Each channel structure CH can form a string of memory cells and can be spaced apart from each other in rows and columns in a top view. The channel structures CH can be configured to form a grid pattern in a top view, or they can be arranged in a zigzag shape in one direction. The channel structures CH can have a column shape and can have sloping side surfaces depending on the aspect ratio, such that the width of the channel structure CH narrows as the channel structure CH approaches the source structure 160.

[0033] Each channel structure CH may have a first stacked structure GS1 and a second stacked structure GS2 that respectively penetrate the gate electrode 130 or extend into the first stacked structure GS1 and the second stacked structure GS2 of the gate electrode 130 and are connected, and may have a curved portion due to differences or variations in the width of the connection area. However, according to the example embodiment, the number of channel structures stacked in the Z direction may vary. A portion of the upper surface of each channel structure CH may contact the upper insulating layer 150, and another portion of the upper surface may contact the contact area 164 of the source structure 160.

[0034] Each channel structure CH may include a channel dielectric layer 145, a channel layer 140, and a channel buried insulating layer 147 sequentially disposed from the gate electrode 130 within a channel via, and may also include a channel pad 149 disposed at the lower end of the channel via. The channel layer 140, channel dielectric layer 145, and channel buried insulating layer 147 may be interconnected between the first channel structure CH1 and the second channel structure CH2.

[0035] The channel layer 140 may be formed in an annular shape surrounding or extending around the channel buried insulating layer 147 therein, but according to some example embodiments, it may also have a columnar shape such as a cylinder or prism without the channel buried insulating layer 147. The channel layer 140 may be physically and electrically connected to the source structure 160 via its upper end. The channel layer 140 may include a semiconductor material such as polycrystalline silicon or monocrystalline silicon. In some example embodiments, the channel layer 140 may include an N-type impurity doped in a region adjacent to the source structure 160. In some example embodiments, the channel layer 140 may have a reduced thickness by partially removing a region adjacent to the source structure 160.

[0036] A channel dielectric layer 145 may be disposed on the outer surface of the channel layer 140 and may be disposed between the gate electrode 130 and the channel layer 140. Although not specifically shown, the channel dielectric layer 145 may include a tunneling layer, a charge storage layer, and a barrier layer sequentially stacked from or on the channel layer 140. The tunneling layer allows charge to tunnel into the charge storage layer and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or combinations thereof. The charge storage layer may be a charge trapping layer or a floating gate conductive layer. The barrier layer may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or combinations thereof. In an example embodiment, at least a portion of the channel dielectric layer 145 may extend horizontally along the gate electrode 130.

[0037] The channel pad 149 may be disposed only on the lower end of the second channel structure CH2. The channel pad 149 may include, for example, doped polysilicon.

[0038] The separating region MS can extend in the Z direction through the first stacked structure GS1 and the second stacked structure GS2 or into the first stacked structure GS1 and the second stacked structure GS2, and can also extend in the X direction. For example... Figure 1 As shown, the separating regions MS can be configured to be parallel to each other. The separating regions MS can separate the gate electrodes 130 from each other in the Y direction. In some example embodiments, the separating regions MS may have a bend on their side surfaces along the Y direction in the top view.

[0039] Due to the high aspect ratio, the partition region MS can have a shape in which the width decreases toward the source structure 160. The partition region MS may have an air gap or a seam SE therein, but this disclosure is not limited thereto. The partition region MS may include an insulating material and may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0040] The upper insulating layer 150 may be disposed on the gate electrode 130, the channel structure CH, and the uppermost interlayer insulating layer 120_U, and may cover or at least partially overlap with the upper region including the upper end of the channel structure CH and the upper region including the upper end of the separator region MS. The upper insulating layer 150 may cover a portion of the side surface of the channel structure CH and the upper surface of the channel structure CH, or overlap with a portion of the side surface of the channel structure CH and the upper surface of the channel structure CH, and may also cover a portion of the side surface of the separator region MS and the upper surface of the separator region MS, or overlap with a portion of the side surface of the separator region MS and the upper surface of the separator region MS. In an example embodiment, the height by which the channel structure CH and the separator region MS protrude or extend into the upper insulating layer 150 and the thickness of the upper insulating layer 150 according to this height may vary. For example, the height of the channel structure CH protruding or extending into the upper insulating layer 150 may be 1000 Å or greater, for example, in the range of about 1000 Å to about 3000 Å, and the thickness of the upper insulating layer 150 may be greater than the protruding or extending height. The upper insulating layer 150 may include an insulating material, and includes, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0041] The source structure 160 may be disposed on the upper insulating layer 150 and may include a horizontally extending horizontal region 162 and a contact region 164 extending downward (e.g., in the Z direction) from the horizontal region 162 toward the channel structure CH and contacting the channel layer 140. The horizontal region 162 may have a rectangular shape in a top view and may be disposed, for example, as a single layer on multiple memory blocks. The contact region 164 may have a line shape or a straight line shape in a top view, such as... Figure 1 As shown, and in an example embodiment, the contact area 164 may have a linear or straight shape extending in the X direction. The contact area 164 may include multiple lines arranged at the same pitch as the rows of the channel structure CH. However, in some example embodiments, the contact area 164 may have a linear shape extending in the Y direction.

[0042] Contact regions 164 may have a trench shape that penetrates the upper insulating layer 150 and each channel structure CH, or extends into the portions of the upper insulating layer 150 and each channel structure CH. Contact regions 164 may include a trench region extending in one direction within the upper insulating layer 150. Each contact region 164 may protrude downwards (e.g., in the Z direction) from the lower surface of the horizontal region 162. The upper surface of the contact region 164 may be positioned at a height higher in the Z direction than the upper surface of the channel structure CH (e.g., the distance in the Z direction between the lower surface of the second substrate structure S2 and the upper surface of the contact region 164 is greater than the distance in the Z direction between the lower surface of the second substrate structure S2 and the upper surface of the channel structure CH). The horizontal region 162 and the contact region 164 may be integrally formed, but this disclosure is not limited thereto.

[0043] like Figure 3 As shown, the contact region 164 may penetrate or extend into the upper insulating layer 150, and may also penetrate or extend into the channel dielectric layer 145 of the channel structure CH to contact a portion of the upper surface of the channel layer 140 and a portion of the outer surface connected to the upper surface. The contact region 164 may not contact another portion of the upper surface of the channel layer 140 and another portion of the outer surface. In an example embodiment, the contact region 164 may not penetrate or extend into the channel layer 140, and may extend along the outer surface of the channel layer 140. Therefore, the contact region 164 may have a curved shape along the outer surface of the channel layer 140 and may have an asymmetrical shape relative to its central axis. When forming a contact trench in which the contact region 164 is disposed, such a shape can be formed by selectively etching the channel dielectric layer 145 only relative to the channel layer 140.

[0044] Contact region 164 may not be aligned linearly with channel structure CH (e.g., or may partially overlap in the Z direction), and may contact channel layer 140 on one side of channel structure CH. As an example, contact region 164 may be configured to have a central axis CA displaced or offset in the Y direction from the central axis CB of channel structure CH in the Z direction. Therefore, channel structure CH may have an asymmetrical shape relative to its central axis due to contact region 164. In some example embodiments, some contact regions 164 may be aligned with some channel structures CH, and some contact regions 164 may have a central axis displaced or offset in the Y direction from some central axes of channel structure CH. In some example embodiments, at least one channel structure CH may have a central axis displaced or offset in the Y direction from contact region 164, and with... Figure 3 It is connected to contact area 164 in the form shown.

[0045] The lower end or lower surface of contact region 164 may be disposed within the uppermost interlayer insulating layer 120_U. The lower end of contact region 164 may be spaced apart from the uppermost gate electrode 130 by a first distance D1. When the uppermost gate electrode 130 is a dummy gate electrode, the first distance D1 may be, for example, about 50 Å or greater, and when the uppermost gate electrode 130 is not a dummy gate electrode, the first distance D1 may be about 300 Å or greater, but this disclosure is not limited thereto. The lower surface of contact region 164 may contact the channel dielectric layer 145 and the uppermost interlayer insulating layer 120_U.

[0046] Contact region 164 may have a shape in which its width decreases toward the channel structure CH. A first width W1 of the upper surface of contact region 164 may be greater than a second width W2 of its lower surface. The first width W1 and the second width W2 may be greater than the thickness of the horizontal region 162, but this disclosure is not limited thereto. The first width W1 and the second width W2 may be determined within a range in which the desired thickness of the horizontal region 162 can be achieved while the contact region 164 is stably filled during the formation of the source structure 160. The height of contact region 164 may be in the range of approximately 100 nm to approximately 400 nm, for example, in the range of approximately 100 nm to approximately 300 nm, and may vary depending on the thickness of the upper insulating layer 150.

[0047] The source structure 160 may include a conductive material, such as crystalline silicon. However, in some example embodiments, the source structure 160 may include a metallic material. The horizontal region 162 and the contact region 164 may include the same material.

[0048] Because the source structure 160 includes a contact region 164 formed by a dry etching process, defects such as exposure of the seam SE of the separating region MS or breakage at the top of the channel structure CH can be prevented or suppressed during the manufacturing process of the semiconductor device 100, and the process can be easily performed. Reference will be made below. Figures 11A to 11F This will be described in more detail.

[0049] like Figure 1 As shown, the upper separating region US can extend in the X direction between adjacent separating regions MS along the Y direction. In the example embodiment, the number of upper separating regions US disposed between adjacent separating regions MS can be varied. The upper separating region US can be configured to penetrate some of the gate electrodes 130, including the lowermost gate electrode 130, or extend into some of the gate electrodes 130, including the lowermost gate electrode 130.

[0050] The upper partition region US can, for example, separate the total three gate electrodes 130 from each other in the Y direction, such as... Figure 2 As shown. The gate electrode 130 separated by the upper separating region US can be, for example, an upper gate electrode included in the gate of a string select transistor. However, in example embodiments, the number of gate electrodes 130 separated by the upper separating region US can vary. At least some of the upper separating regions US can be configured to at least partially penetrate the channel structure CH or extend into the channel structure CH. However, in some example embodiments, the upper separating regions US may not penetrate the channel structure CH or extend into the channel structure CH. The upper separating regions US can include an insulating material and include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0051] The cell region insulating layer 190 may be configured to cover the lower surface of the second stacked structure GS2 or at least partially overlap with the lower surface of the second stacked structure GS2. The cell region insulating layer 190 may include at least one insulating material, and may include at least one of, for example, silicon oxide, silicon nitride or silicon carbide, and may be formed from multiple insulating layers according to an example embodiment.

[0052] Studs 170, bit lines 180, cell contact plugs 182, and cell interconnects 184 may be included in a second interconnect structure of memory cells electrically connected to the second substrate structure S2. Studs 170 may be connected to a channel structure CH, and the channel structure CH may be electrically connected to the bit line 180. Studs 170 may have a plug shape, and bit lines 180 may have a line shape or a straight line shape extending in one direction (e.g., the Y direction). Cell interconnects 184 may be electrically connected to the bit line 180 via cell contact plugs 182. However, in the example embodiment, the number and arrangement of the contact plugs and interconnects included in the second interconnect structure may vary.

[0053] The stud 170, bit line 180, cell contact plug 182 and cell interconnect line 184 may include metals, and may include, for example, tungsten (W), copper (Cu) or aluminum (Al).

[0054] In the second bonding structure, the second bonding path 195 can be disposed below and connected to the cell interconnect 184, and the second bonding pad 198 can be connected to the second bonding path 195. The lower surface of the second bonding pad 198 can form part of the lower surface of the second substrate structure S2. The second bonding pad 198 can be bonded to and connected to the first bonding pad 298 of the first substrate structure S1, and the second bonding insulating layer 199 can be bonded to and connected to the first bonding insulating layer 299 of the first substrate structure S1. The second bonding path 195 and the second bonding pad 198 can include a conductive material, such as copper (Cu). The second bonding insulating layer 199 can include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, or SiOCN.

[0055] The first substrate structure S1 and the second substrate structure S2 can be joined by joining the first bonding pad 298 to the second bonding pad 198 and by joining the first bonding insulating layer 299 to the second bonding insulating layer 199. The joining of the first bonding pad 298 to the second bonding pad 198 can be, for example, copper (Cu) to copper (Cu) bonding, and the joining of the first bonding insulating layer 299 to the second bonding insulating layer 199 can be, for example, dielectric to dielectric bonding, such as SiCN to SiCN bonding. The first substrate structure S1 and the second substrate structure S2 can be joined by a hybrid bonding including copper (Cu) to copper (Cu) bonding and dielectric to dielectric bonding.

[0056] Figures 4A to 4C This is a schematic partial enlarged view of a semiconductor device according to an example embodiment. Figures 4A to 4C Showing with Figure 3 The corresponding area.

[0057] refer to Figure 4A In semiconductor device 100a, the contact region 164a of the source structure 160a can penetrate or extend into the upper insulating layer 150, and can penetrate or extend into portions of the channel dielectric layer 145, channel layer 140, and channel buried insulating layer 147 of the channel structure CH to contact the end of the channel layer 140 in the extending direction. Figure 3Unlike some example embodiments, contact region 164a may be configured to penetrate or extend not only into or into the channel dielectric layer 145, but also into or into portions of each layer of the channel structure CH. Contact region 164a may contact the ends of regions extending horizontally by forming the upper end of the channel layer 140 and the ends of regions extending vertically by forming the sides. The lower surface of contact region 164a may contact at least the channel layer 140 and the channel dielectric layer 145. Contact region 164a may have a shape symmetrical with respect to its central axis. In some example embodiments, contact region 164a may have a shape that is further recessed relative to the channel buried insulating layer 147.

[0058] refer to Figure 4B In semiconductor device 100b, the contact region 164b of source structure 160b may be linearly aligned with channel structure CH (e.g., or at least partially overlap in the Z direction) and may contact the entire upper surface of channel layer 140 and a portion of the outer surface extending from the upper surface. The central axis of contact region 164b may coincide with (e.g., overlap with) the central axis of channel structure CH. Contact region 164b may have a linear or straight shape extending along the center of channel structure CH in a top view. In some example embodiments, channel structure CH may have a shape symmetrical with respect to its central axis.

[0059] In some example embodiments, when the contact area 164b has a relatively small width, the contact area 164b may only contact the upper surface of the channel layer 140, and when the contact area 164b has a relatively large width, the contact area between the contact area 164b and the outer surface of the channel layer 140 increases, and the lower end of the contact area 164b may be lowered. In some example embodiments, the contact area 164b may be configured to extend into the channel structure CH by penetrating portions of the channel dielectric layer 145, the channel layer 140, and the channel buried insulating layer 147 of the channel structure CH, or extending into portions of the channel dielectric layer 145, the channel layer 140, and the channel buried insulating layer 147 of the channel structure CH, such as... Figure 4A As shown. In this way, in the example embodiments below, the contact region is described as having a structure with an etching process selectively performed relative to the channel layer 140, as in Figure 3 In example embodiments, or structures that perform etching processes without etch selectivity, such as Figure 4A As shown, however, unless otherwise described, the contact area may also have a structure depending on other circumstances.

[0060] refer to Figure 4CIn the semiconductor device 100c, the lower end or lower surface of the contact region 164c of the source structure 160c may be disposed within the upper insulating layer 150. For example, when the contact region 164c has a relatively small height or the upper insulating layer 150 has a relatively large thickness, the lower end of the contact region 164c may be disposed within the upper insulating layer 150, as described above.

[0061] In the example embodiment described above Figures 4A to 4C Example embodiments can be combined in various ways.

[0062] Figures 5A to 5D This is a schematic top view of a semiconductor device according to an example embodiment. Figures 5A to 5D Showing with Figure 1 The corresponding area.

[0063] refer to Figure 5A In the semiconductor device 100d, the contact region 164d of the source structure 160 may have a linear or straight shape extending in a zigzag manner in the X direction. The contact region 164d may be arranged in a zigzag shape on two adjacent rows of channel structures CH. However, in some example embodiments, the contact region 164d may be formed in a zigzag shape on three or more rows of channel structures CH. In some example embodiments, the contact region 164d may be arranged in a manner that is shifted or offset from the channel structures CH in one direction (e.g., in the Y direction).

[0064] refer to Figure 5B In the semiconductor device 100e, the contact region 164e of the source structure 160 may have a line shape or a straight line shape extending in an oblique direction between the X and Y directions. In example embodiments, the length and extension direction of each line of the contact region 164e may vary. In some example embodiments, the contact region 164e may be positioned in a direction that is shifted or offset from the channel structure CH in one direction (e.g., in a direction perpendicular to the extension direction).

[0065] refer to Figure 5C In semiconductor device 100f, the contact regions 164f of source structure 160 may have a line shape or a straight line shape extending in an oblique direction between the X and Y directions and intersecting each other. The contact regions 164f may be connected to each other in a grid shape or a mesh shape. The contact regions 164f may form a single layer connected to each other, but this disclosure is not limited thereto. In some example embodiments, the contact regions 164f may have a shape in which lines extending in the X and Y directions intersect each other perpendicularly. In some example embodiments, the contact regions 164f may be positioned in a direction that is shifted or offset from the channel structure CH in one direction (e.g., in a direction perpendicular to the direction of extension).

[0066] refer to Figure 5D In the semiconductor device 100g, the contact regions 164g of the source structure 160 can be respectively disposed in a circular shape on the channel structure CH. The contact regions 164g can be disposed in a shape that is shifted or offset from the channel structure CH in one direction, but this disclosure is not limited thereto. In some example embodiments, the contact regions 164g can have various shapes in a top view, such as elliptical or square.

[0067] As in Figures 5A to 5D In an example embodiment, contact areas 164d, 164e, 164f, and 164g may include areas set at the same pitch as the row and / or column pitch of the channel structure CH, or may be arranged to correspond one-to-one with the arrangement of the channel structure CH.

[0068] Figure 6A and Figure 6B These are schematic cross-sectional views and partial enlarged views of a semiconductor device according to an example embodiment. Figure 6A It shows the relationship with Figure 2 The corresponding area, and Figure 6B It shows Figure 6A A magnified view of region "B".

[0069] refer to Figure 6A and Figure 6B In the semiconductor device 100h, each channel structure CH may include an upper pad portion CH_UP at its upper end. The upper pad portion CH_UP may be a region whose width discontinuously expands from the upper end of the channel structure CH and at least partially overlaps with or is covered by the upper insulating layer 150. Therefore, the channel structure CH may have a curved portion having a shape that bends along the upper pad portion CH_UP.

[0070] The channel dielectric layer 145, channel layer 140, and channel buried insulating layer 147 of the channel structure CH can conformally extend into the upper pad portion CH_UP. In some example embodiments, a seam may exist within the channel buried insulating layer 147 in the upper pad portion CH_UP. In some example embodiments, the channel buried insulating layer 147 may not extend into the upper pad portion CH_UP, and the internal region of the upper pad portion CH_UP may be at least partially filled by the channel layer 140. The lower surface of the upper pad portion CH_UP is shown disposed within the uppermost interlayer insulating layer 120_U, but the height of the lower surface is not limited thereto. In some example embodiments, the lower surface of the upper pad portion CH_UP may be disposed at the same height as the lower surface of the upper insulating layer 150, or may be disposed within the upper insulating layer 150.

[0071] like Figure 6BAs shown, the contact region 164 of the source structure 160 can penetrate a portion of the upper pad portion CH_UP or extend into a portion of the upper pad portion CH_UP, and can extend into the uppermost interlayer insulating layer 120_U. In some example embodiments, the lower end of the contact region 164 can be positioned at a height higher than the lower surface of the upper pad portion CH_UP. In some example embodiments, the contact region 164 can penetrate only the channel dielectric layer 145 of the upper pad portion CH_UP or extend into the channel dielectric layer 145 of the upper pad portion CH_UP, and can contact the outer surface of the channel layer 140, such as... Figure 3 As in the example embodiments.

[0072] Figure 7 This is a schematic cross-sectional view of a semiconductor device according to an example embodiment.

[0073] refer to Figure 7 In semiconductor device 100i, at least one contact region 164 of source structure 160 may be configured to at least partially overlap with separator region MSi. Contact region 164 may be configured to extend partially from the upper surface of separator region MSi into or through separator region MSi, and at least partially overlap with separator region MSi in the Z direction. For example, contact region 164 may extend onto separator region MSi in a cross-sectional view. In some example embodiments, separator region MSi may not include seam SE (see [link to example]). Figure 2 ), and may include, for example, silicon.

[0074] Figure 8 This is a schematic cross-sectional view of a semiconductor device according to an example embodiment.

[0075] refer to Figure 8 The second substrate structure S2 of the semiconductor device 100j may further include a lower partition region LS. The lower partition region LS may be configured to penetrate or extend into the gate electrode 130 including the lower gate electrode, wherein the lower gate electrode forms the gate of a ground selection transistor. The lower partition region LS may, for example, partition a total of three gate electrodes 130 from each other in the Y direction. However, the number of gate electrodes 130 partitioned by the lower partition region LS may vary in the example embodiment. The lower partition region LS may be arranged in a line shape or a straight line shape extending in the X direction in a top view. In the example embodiment, the number of lower partition regions LS disposed between partition regions MS adjacent to each other along the Y direction may vary.

[0076] Each lower partition region LS may have a shape in which the width of its upper surface is greater than the width of its lower surface. The upper surface of the lower partition region LS may be in contact with the lower surface of the horizontal region 162 of the source structure 160. The lower partition region LS may include an insulating material and may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0077] Figure 9A and Figure 9B These are schematic top views and cross-sectional views of a semiconductor device according to an example embodiment. Figure 9B Show along Figure 9A The cross sections of cutting lines I-I' and II-II'.

[0078] refer to Figure 9A and Figure 9B In the semiconductor device 100k, the second substrate structure S2 may include a first region R1 and a second region R2. The second substrate structure S2 may also include a cell contact plug 275 disposed in the second region R2, a dummy vertical structure DH, and a contact insulating layer 260 extending around the side surface of the cell contact plug 275 or around the side surface of the cell contact plug 275.

[0079] The first region R1 may be a region where gate electrodes 130 are vertically stacked and a channel structure CH is disposed therein, and may also be a region where a memory cell is disposed therein. The second region R2 may be a region where gate electrodes 130 extend to different lengths and are connected to cell contact plugs 275, and may correspond to a region for electrically connecting memory cells to the first substrate structure S1. The second region R2 may be disposed at least at one end of the first region R1 in at least one direction (e.g., in the X direction).

[0080] In the second region R2, the gate electrode 130 can be configured such that the upper gate electrode 130 extends longer than the lower gate electrode 130. Each gate electrode 130 can have an end region 130P in which the lower surface of the gate electrode 130 is exposed downward (e.g., in the Z direction) from the interlayer insulating layer 120. The gate electrodes 130 can be connected to the cell contact plug 275 in the end region 130P. The gate electrode 130 can have a shape in which its thickness increases in the end region 130P.

[0081] In some embodiments, the source structure 160 may be disposed only in the first region R1 and may not extend into the second region R2. However, in some example embodiments, the source structure 160 may also extend onto the upper insulating layer 150 of the second region R2. In this case, the contact region 164 may be spaced apart from the cell contact plugs 275 and may extend between the cell contact plugs 275.

[0082] The cell contact plug 275 can penetrate or extend into the cell region insulating layer 190, and can be connected to the end region 130P of the gate electrode 130. The cell contact plug 275 can penetrate or extend into the gate electrode 130 in the end region 130P, and the upper end of the cell contact plug 275 can be disposed within the upper insulating layer 150. The cell contact plug 275 can be separated from the gate electrode 130 in the end region 130P by contacting the insulating layer 260.

[0083] The unit contact plug 275 may have a shape corresponding to the channel structure CH. Each unit contact plug 275 may include a region that penetrates or extends into the first stack structure GS1 and the second stack structure GS2, respectively. Each region may have a cylindrical shape in which its width decreases toward the upper insulating layer 150 due to the aspect ratio. Each unit contact plug 275 may have a horizontally extending shape in the end region 130P.

[0084] The upper end of the cell contact plug 275 may be covered by or at least partially overlapped with the upper insulating layer 150, and therefore, the cell contact plug 275 is not exposed and contaminated when the source structure 160 is formed. Additionally, because the upper end of the cell contact plug 275 is spaced apart from the source structure 160, heat generated during the crystallization process of the source structure 160 can be prevented or suppressed from being transferred along the cell contact plug 275 to the second interconnect structure. The cell contact plug 275 may comprise a conductive material and may comprise at least one of, for example, tungsten (W), copper (Cu), aluminum (Al), or alloys thereof.

[0085] The contact insulating layer 260 may be configured to extend around the side surface of each cell contact plug 275 on the end region 130P or around the side surface of each cell contact plug 275. The contact insulating layers 260 may be spaced apart from each other in the Z direction around each cell contact plug 275. The contact insulating layers 260 may each be disposed at a height substantially the same as the height of the gate electrode 130. The contact insulating layer 260 may include an insulating material and may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0086] A virtual vertical structure DH can form rows and columns in the second region R2 while being spaced apart from each other, such as... Figure 9AAs shown. The dummy vertical structure DH can be configured to extend, for example, in four directions around or around each cell contact plug 275. However, the arrangement shape of the dummy vertical structure DH can vary differently in the example embodiments. The dummy vertical structure DH can have a circular shape, an elliptical shape, or a similar shape in a top view. The dummy vertical structure DH can have a pillar shape that penetrates or extends into a portion of the gate electrode 130, and can have sloping side surfaces that narrow as the gate electrode 130 approaches the upper insulating layer 150 according to the aspect ratio. The dummy vertical structure DH can include an insulating material. The dummy vertical structure DH can include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0087] Figures 10A to 10D These are schematic cross-sectional views and partial enlarged views of a semiconductor device according to an example embodiment. Figure 10A Showing with Figure 2 The corresponding area, Figure 10B Show Figure 10A A magnified view of region "C", and Figure 10C and Figure 10D Showing with Figure 10B The corresponding area.

[0088] refer to Figure 10A and Figure 10B In semiconductor device 100l, source structure 160l may have the form of extending along the upper end of channel structure CH. Source structure 160l may extend conformally as a single layer along the upper end of separator region MS and the upper end of channel structure CH. Source structure 160l may contact channel layer 140 in regions where each channel structure CH is partially removed. In some embodiments, upper insulating layer 150 may be omitted (see...). Figure 2 The formation of the source structure 160l is described, and for example, after forming a patterned photoresist layer, a portion of each channel structure CH can be removed in a dry etching process, and then the source structure 160l can be formed. In some example embodiments, the source structure 160l may extend nonconformally, may have a flat upper surface, and may be set at a predetermined thickness.

[0089] refer to Figure 10CIn the semiconductor device 100m, the source structure 160m may have a form extending along the upper end of the channel structure CH, and at least a portion of the channel layer 140 on the uppermost interlayer insulating layer 120_U of the channel structure CH may be at least partially exposed by the channel dielectric layer 145 to contact the source structure 160m. On the uppermost interlayer insulating layer 120_U, the channel dielectric layer 145 may be partially removed and partially retained on the side surface of the channel layer 140 in the form of spacers. However, in example embodiments, the shape of the remaining channel dielectric layer 145 may be varied. In some example embodiments, the channel layer 140 may include a region in which a portion of the channel layer 140 is removed from or exposed by the channel dielectric layer 145, such that the thickness of the channel layer 140 is reduced.

[0090] In some embodiments, the upper insulating layer 150 may be omitted (see Figure 2 The formation of the channel structure CH is achieved, and the ends of the channel structure CH can be selectively removed relative to the channel layer 140 in a dry etching process while the ends of the channel structure CH are at least partially exposed, and then the source structure 160m can be formed.

[0091] refer to Figure 10D In the semiconductor device 100n, the source structure 160n may have a shape extending along the upper end of the channel structure CH, and on the uppermost interlayer insulating layer 120_U, the channel structure CH may have a structure in which the channel layer 140, with its upper end partially removed and exposed, contacts the source structure 160n. On the uppermost interlayer insulating layer 120_U, a portion of each of the channel dielectric layer 145, the channel layer 140, and the channel buried insulating layer 147 may be removed. In some example embodiments, the channel buried insulating layer 147 may be further removed than the channel dielectric layer 145 and may have a shape recessed downwards (e.g., in the Z direction) from its upper surface.

[0092] In some embodiments, the upper insulating layer 150 may be omitted (see Figure 2 The semiconductor device can be fabricated by removing the ends of the channel structure CH in a dry etching process that is not selective relative to the channel layer 140 while the ends of the channel structure CH are at least partially exposed, and then forming the source structure 160m.

[0093] Figures 11A to 11F This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to an example embodiment. Figures 11A to 11F Each shows with Figure 2 The corresponding area.

[0094] refer to Figure 11A The manufacturing process of the second substrate structure S2 can then begin. First, sacrificial insulating layers 118 and interlayer insulating layers 120 can be alternately stacked on the substrate 101, and then a first vertical sacrificial layer 119L and a second vertical sacrificial layer 119U can be formed.

[0095] The substrate 101 is a layer removed by subsequent processes and can be, for example, a semiconductor substrate, such as undoped silicon (Si). Sacrificial insulating layer 118 and interlayer insulating layer 120 can be alternately stacked on the substrate 101 to form an undermolded structure. The undermolded structure can be formed in a first channel structure CH1 (see...). Figure 2 At the height set by ).

[0096] The first vertical sacrificial layer 119L can be formed to penetrate the lower molding structure or extend into the lower molding structure. The first vertical sacrificial layer 119L can be formed in conjunction with... Figure 2 The first channel structure CH1 and the partition region MS are located at corresponding positions. The first vertical sacrificial layer 119L may include, for example, polysilicon, carbon-based materials, or metallic materials.

[0097] The upper molding structure can be formed on the lower molding structure in the same manner, and a second vertical sacrificial layer 119U can be formed. The second vertical sacrificial layer 119U can be formed to be connected to the first vertical sacrificial layer 119L.

[0098] refer to Figure 11B This can form a channel structure CH and an upper partition region US.

[0099] The channel structure CH can be fabricated by removing some of the first vertical sacrificial layer 119L and the second vertical sacrificial layer 119U to form a channel via, and then sequentially depositing at least a portion of the channel dielectric layer 145, the channel layer 140 and the channel buried insulating layer 147 in each channel via, removing some of the channel buried insulating layer 147 from the top and forming a channel pad 149.

[0100] The channel dielectric layer 145 can be formed to have a uniform thickness using atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes. The channel dielectric layer 145 can be formed integrally or partially in this operation, and a portion extending perpendicularly (in the Z direction) along the channel structure CH to the substrate 101 can be formed in this operation. The channel layer 140 can be formed in channel vias on the channel dielectric layer 145. The channel buried insulating layer 147 can be formed to at least partially fill the channel vias and can be formed of an insulating material. The channel pads 149 can be formed of a conductive material and can be formed, for example, polysilicon.

[0101] The upper partition region US can be formed by removing a portion of the upper molded structure from the upper surface and depositing an insulating material. The upper partition region US can be formed to at least partially penetrate or extend into a portion of the channel structure CH, but this disclosure is not limited thereto.

[0102] refer to Figure 11C The sacrificial insulating layer 118 can be removed and the gate electrode 130 can be formed.

[0103] It is possible to be with Figure 1 The first vertical sacrificial layer 119L and the second vertical sacrificial layer 119U are removed at positions corresponding to the partition region MS to form vertical holes. By removing portions of the lower and upper molded structures around the vertical holes, the vertical holes can be expanded to connect with each other, thereby forming groove-shaped openings corresponding to the partition region MS.

[0104] The sacrificial insulating layer 118, which is at least partially exposed by or through an opening, can be removed. The sacrificial insulating layer 118 can be selectively removed relative to the interlayer insulating layer 120 and the channel structure CH, for example, using wet etching.

[0105] The gate electrode 130 can be formed by depositing a conductive material in a region where the sacrificial insulating layer 118 has been removed. The conductive material may include a metal, polysilicon, or a metal silicide. In some example embodiments, a portion of the channel dielectric layer 145 may be formed prior to the formation of the gate electrode 130. Thus, a gate stack structure including a first stack structure GS1 and a second stack structure GS2 can be formed. After the gate electrode 130 is formed, an insulating material may be deposited within the opening to form a separation region MS.

[0106] refer to Figure 11D A second interconnect structure and a second bonding structure can be formed on the gate electrode 130, and the first substrate structure S1 and the second substrate structure S2 can be bonded to each other.

[0107] A cell region insulating layer 190 can be formed on the gate electrode 130 and the channel structure CH, and studs 170, bit lines 180, cell contact plugs 182, and cell interconnects 184, which are included in the second interconnect structure, can be formed sequentially. A second bonding path 195, a second bonding pad 198, and a second bonding insulating layer 199, which are included in the second bonding structure, can be formed on the second interconnect structure. Therefore, a second substrate structure S2 can be fabricated.

[0108] The first substrate structure S1 can be prepared by forming circuit elements 220, a first interconnect structure and a first bonding structure on the substrate 201.

[0109] A device isolation layer 210 can be formed in substrate 201, and a circuit gate dielectric layer 222 and a circuit gate electrode 225 can be sequentially formed on substrate 201. The device isolation layer 210 can be formed, for example, by a shallow trench isolation (STI) process. The circuit gate dielectric layer 222 and the circuit gate electrode 225 can be formed using ALD or CVD. The circuit gate dielectric layer 222 can be formed of silicon oxide, and the circuit gate electrode 225 can be formed of at least one of polysilicon or metal silicide layers, but this disclosure is not limited thereto. Next, a spacer layer 224 and an impurity region (or source / drain region 205) can be formed on the two sidewalls of the circuit gate dielectric layer 222 and the circuit gate electrode 225. According to an example embodiment, the spacer layer 224 can be formed of multiple layers. The impurity region (or source / drain region 205) can be formed by performing an ion implantation process.

[0110] The circuit contact plug 270 of the first interconnect structure and the first bonding passage 295 of the first bonding structure can be formed by forming a portion of the peripheral region insulating layer 290, etching and removing a portion thereof, and filling the removed portion at least partially with a conductive material. The circuit interconnect 280 of the first interconnect structure and the first bonding pad 298 of the first bonding structure can be formed, for example, by depositing a conductive material and then patterning the conductive material. The first bonding pad 298 can be formed such that its upper surface is at least partially exposed by or at least partially exposed through the first bonding insulating layer 299.

[0111] The peripheral region insulating layer 290 can be formed of multiple insulating layers. The peripheral region insulating layer 290 can be partially formed in each operation of forming the first interconnect structure and the first bonding structure. Through this operation, the first substrate structure S1 can be fabricated.

[0112] Next, the first substrate structure S1 and the second substrate structure S2 can be connected by bonding the first bonding pad 298 and the second bonding pad 198 via annealing and / or pressurization. Simultaneously, the first bonding insulating layer 299 and the second bonding insulating layer 199 can also be bonded. The second substrate structure S2 can be inverted on the first substrate structure S1 such that the second bonding pad 198 faces downwards, and then bonding can be performed.

[0113] refer to Figure 11E The substrate 101 can be removed from the bonding structure of the first substrate structure S1 and the second substrate structure S2.

[0114] For example, a portion of the substrate 101 can be removed from the upper surface by a polishing process such as a grinding process, and the remaining portion of the substrate 101 can be removed by an etching process such as wet etching. As the substrate 101 is removed, the upper surface of the uppermost interlayer insulating layer 120_U can be exposed, and the upper ends of the channel structure CH and the separation region MS can be at least partially exposed.

[0115] refer to Figure 11F An upper insulating layer 150 can be formed on the bonding structure of the first substrate structure S1 and the second substrate structure S2, and a contact trench SC can be formed thereon.

[0116] An upper insulating layer 150 may be deposited on the uppermost interlayer insulating layer 120_U and may at least partially cover the upper end of the channel structure CH and the upper end of the separating region MS. Contact trenches SC may be formed by an etching process (e.g., a dry etching process). Contact trenches SC may be formed by removing a portion of the upper insulating layer 150 and at least a portion of the channel dielectric layer 145 of each exposed channel structure CH, thereby exposing the channel layer 140. As an example, the etching process may be performed selectively on the channel layer 140, in which case the channel layer 140 may not be etched and its outer surface may be exposed.

[0117] exist Figure 4A Example embodiments Figure 6A and Figure 6B Example embodiments Figure 10A and Figure 10B Example embodiments and Figure 10D In the case of the example embodiment, in this operation, the etching process can be performed without selectivity on the channel layer 140, thus further removing a portion of the channel layer 140 and a portion of the channel buried insulating layer 147. Figures 10A to 10D In the case of the example embodiment, the semiconductor device can be manufactured by performing an etching process while omitting the process of forming the upper insulating layer 150.

[0118] Because the contact trench SC is formed by a dry etching process, defects can be prevented or suppressed compared to a comparative example where only the channel dielectric layer 145 is removed by a wet etching process after removing the substrate 101 from the upper end of the protrusion or extension of the channel structure CH onto the uppermost interlayer insulating layer 120_U. Furthermore, the process can be easily performed. For example, in the case of the comparative example, defects such as seams SE in the separator region MS being exposed during the process, causing material from the source structure 160 to fill the separator region MS, may occur. However, according to the exemplary embodiment, such defects can be prevented or suppressed. Figure 6A and Figure 6B In the case of the embodiment, defects such as the upper pad portion CH_UP being cut off may occur during the process of the comparative example, but according to the exemplary embodiment, such defects can be prevented. Figure 9A and Figure 9B In the case of the embodiment, during the process of the comparative example, the upper end of the cell contact plug 275 is exposed together, and there may be a problem of heat being transferred to the second interconnect structure through the cell contact plug 275 during the subsequent crystallization process for the source structure 160. However, according to the example embodiment, such a problem can be prevented or suppressed.

[0119] Next, let's refer to... Figure 2 A source structure 160 can be formed on the upper insulating layer 150.

[0120] The source structure 160 can be formed by depositing a conductive material to fill the contact trench SC and covering the upper surface of the insulating layer 150. For example, the source structure 160 can be formed by depositing amorphous silicon (Si) and then performing a crystallization process (e.g., by laser annealing). Therefore, it is possible to manufacture... Figure 2 The semiconductor device 100. In addition, an interconnect structure connected to the source structure 160 may be further formed on the source structure 160.

[0121] Figure 12 This is a schematic diagram of a data storage system including semiconductor devices according to an example embodiment.

[0122] refer to Figure 12 The data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including such a storage device. For example, the data storage system 1000 may be a solid-state drive (SSD), a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0123] Semiconductor device 1100 may be a non-volatile memory device, and may be, for example, the one referenced above. Figures 1 to 10DThe NAND flash memory device described herein. Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S located on the first structure 1100F. In an example embodiment, the first structure 1100F may be disposed close to the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including decoder circuitry 1110, page buffer 1120, and logic circuitry 1130. The second structure 1100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0124] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary depending on the example embodiment.

[0125] In the example embodiment, the upper transistors UT1 and UT2 may include string select transistors, and the lower transistors LT1 and LT2 may include ground select transistors. Gate lower lines LL1 and LL2 may be the gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be the gate electrode of the memory cell transistor MCT, and the gate upper lines UL1 and UL2 may be the gate electrodes of the upper transistors UT1 and UT2, respectively.

[0126] In an example embodiment, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 can be used for an erase operation to erase data stored in the memory cell transistor MCT by utilizing the GIDL phenomenon.

[0127] The common source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first interconnect 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second interconnect 1125 extending from the first structure 1100F to the second structure 1100S.

[0128] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by the logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via input / output interconnects 1135 extending from the first structure 1100F to the second structure 1100S.

[0129] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. According to an example embodiment, the data storage system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

[0130] Processor 1210 can control the overall operation of data storage system 1000, including controller 1200. Processor 1210 can operate according to predetermined firmware and can control NAND controller 1220 to access semiconductor device 1100. NAND controller 1220 may include NAND controller interface 1221 for handling communication with semiconductor device 1100. Through NAND controller interface 1221, control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, and data to be read from memory cell transistors (MCTs) of semiconductor device 1100 can be transmitted. Host interface 1230 provides communication functionality between data storage system 1000 and external host. When a control command is received from external host through host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0131] Figure 13 This is a schematic perspective view of a data storage system including semiconductor devices according to some example embodiments.

[0132] refer to Figure 13 A data storage system 2000 according to some example embodiments of the present disclosure may include a motherboard 2001, a controller 2002 mounted on the motherboard 2001, one or more semiconductor packages 2003 and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be interconnected with the controller 2002 via interconnect patterns 2005 formed on the motherboard 2001.

[0133] The motherboard 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In an example embodiment, the data storage system 2000 may communicate with the external host via any of the following interfaces: Universal Serial Bus (USB), Peripheral Component Interconnect Fast (PCI-Express), Serial Advanced Technology Attachment (SATA), or M-Phy for Universal Flash Memory (UFS). In an example embodiment, the data storage system 2000 may operate via power supplied from the external host via the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0134] The controller 2002 can write data to or read data from the semiconductor package 2003, and can improve the operating speed of the data storage system 2000.

[0135] DRAM 2004 can be a buffer memory to mitigate the speed difference between the semiconductor package 2003, which serves as data storage space, and an external host. DRAM 2004 included in the data storage system 2000 can also operate as a type of high-speed cache memory and can provide space for temporarily storing data during control operations on the semiconductor package 2003. When the data storage system 2000 includes DRAM 2004, in addition to the NAND controller for controlling the semiconductor package 2003, the controller 2002 may also include a DRAM controller for controlling the DRAM 2004.

[0136] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 located on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 to the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 or at least partially overlapping the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0137] The package substrate 2100 may be a printed circuit board including on-package pads 2130. Each semiconductor chip 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to... Figure 12 Input / output pads 1101. Each semiconductor chip 2200 may include a gate stack structure 3210 and a channel structure 3220. Each semiconductor chip 2200 may include the above-referenced... Figures 1 to 10D The semiconductor device described.

[0138] In an example embodiment, the connection structure 2400 may be a bonding wiring that electrically connects the input / output pads 2210 and the on-package pads 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via bonding wiring and may be electrically connected to the on-package pads 2130 of the package substrate 2100. According to the example embodiment, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a connection structure including through-silicon vias (TSVs) instead of a connection structure 2400 via bonding wiring.

[0139] In example embodiments, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In some example embodiments, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate interposer substrate, different from the motherboard 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other via interconnects formed on the interposer substrate.

[0140] Figure 14 This is a schematic cross-sectional view of a semiconductor package according to some example embodiments. Figure 14 Show Figure 13 Some example embodiments of the semiconductor package 2003 are shown, and conceptually illustrated along... Figure 13 The area cut by cleaving line Ⅲ-Ⅲ' of the semiconductor package 2003.

[0141] refer to Figure 14In the semiconductor package 2003, the package substrate 2100 can be a printed circuit board. The package substrate 2100 may include a package substrate body 2120, an upper package pad 2130 disposed on the upper surface of the package substrate body 2120, a lower package pad 2125 disposed on or exposed through the lower surface of the package substrate body 2120, and internal interconnects 2135 electrically connecting the upper pad 2130 and the lower pad 2125 within the package substrate body 2120. The upper pad 2130 can be electrically connected to a connection structure 2400. The lower pad 2125 can be connected via a conductive connection portion 2800 to, for example,... Figure 13 The interconnect pattern 2005 of the motherboard 2001 of the data storage system 2000 is shown.

[0142] Each semiconductor chip 2200a may include a semiconductor substrate 4010, a first structure 4100 located on the semiconductor substrate 4010, and a second structure 4200 bonded to the first structure 4100 in a wafer bonding manner.

[0143] The first structure 4100 may include a peripheral circuit region, which includes a peripheral interconnect 4110 and a first junction structure 4150. The second structure 4200 may include a common source line 4205, a gate stack structure 4210, a channel structure 4220 extending through or into the gate stack structure 4210, a separation region 4230, and a word line WL electrically connected to the memory channel structure 4220 and the gate stack structure 4210 (see [link to documentation]). Figure 12 The second bonding structure 4250. For example, the second bonding structure 4250 may be via a bit line 4240 electrically connected to the memory channel structure 4220 and a separate cell contact plug 275 electrically connected to the word line WL (see...). Figure 9A and Figure 9B The first junction structure 4150 of the first structure 4100 and the second junction structure 4250 of the second structure 4200 can contact and join each other. The joining portion of the first junction structure 4150 and the second junction structure 4250 can be formed of, for example, copper (Cu).

[0144] The second structure 4200 may include a source structure 160, which includes a horizontal region 162 and a contact region 164 that partially penetrates or extends into the channel structure CH from the horizontal region 162, as shown in the enlarged view. Each semiconductor chip 2200a may also include input / output pads 2210 and input / output interconnects 4265 located below the input / output pads 2210. The input / output interconnects 4265 may be electrically connected to some second bonding structure 4250.

[0145] Semiconductor chips 2200a can be electrically connected to each other via a connection structure 2400 in the form of bonding wiring. However, in an example embodiment, semiconductor chips (such as semiconductor chip 2200a) within a single semiconductor package can also be electrically connected to each other via a connection structure including through-silicon vias (TSVs).

[0146] This disclosure is not limited to the above embodiments and drawings, but is defined by the appended claims. Therefore, those skilled in the art can make various substitutions, modifications, changes, and combinations to the exemplary embodiments without departing from the scope of this disclosure as defined by the appended claims, and such substitutions, modifications, or changes should be interpreted as being included within the scope of this disclosure.

Claims

1. A semiconductor device, the semiconductor device comprising: A first substrate structure, the first substrate structure including a substrate, circuit elements located on the substrate, a first interconnect structure located on the circuit elements, and a first bonding pad located on the first interconnect structure; as well as A second substrate structure is located on the first substrate structure. The second substrate structure includes: Gate electrodes, which are spaced apart from each other and stacked in a first direction perpendicular to the upper surface of the substrate; An interlayer insulating layer, wherein the interlayer insulating layer is alternately stacked with the gate electrode; A channel structure extending into the gate electrode and extending in the first direction, and comprising a channel layer and a channel dielectric layer located on a side surface of the channel layer; An upper insulating layer, the upper insulating layer being located at the upper end of the channel structure and on the interlayer insulating layer; A source structure located on the upper insulating layer, the source structure including a horizontal region and a contact region, the horizontal region extending in a second direction parallel to the upper surface of the first substrate structure, the contact region extending into a portion of each of the channel structures and the upper insulating layer, extending from the horizontal region in the first direction, and contacting the channel layer of each of the channel structures; A second interconnect structure, the second interconnect structure being located on the gate electrode and including bit lines electrically connected to corresponding channel structures in the channel structure; and The second bonding pad is located on the second interconnect structure and is electrically connected to the first bonding pad. A portion of the upper surface of each of the channel structures is in contact with the upper insulating layer.

2. The semiconductor device according to claim 1, wherein, The width of the upper surface of the contact area in the second direction is greater than the width of the lower surface of the contact area in the second direction.

3. The semiconductor device according to claim 1, wherein, The central axis of the contact area is offset in the second direction relative to the central axis of at least one of the channel structures.

4. The semiconductor device according to claim 1, wherein, The contact area extends into the channel dielectric layer of the first channel structure in the channel structure and contacts a portion of the upper surface of the channel layer of the first channel structure and a portion of the side surface of the channel layer of the first channel structure.

5. The semiconductor device according to claim 1, wherein, The contact area extends into the channel layer of the first channel structure and the channel dielectric layer of the first channel structure, and contacts the end of the channel layer of the first channel structure.

6. The semiconductor device according to claim 1, wherein, The contact area includes a trench area that extends in the second direction and is located in the upper insulating layer.

7. The semiconductor device according to claim 1, wherein, The lower end of the contact area is located in the uppermost interlayer insulation layer of the interlayer insulation layer.

8. The semiconductor device according to claim 1, wherein, The horizontal region and the contact region are made of the same material.

9. The semiconductor device according to claim 1, in, Each of the aforementioned trench structures includes a lower portion and an upper pad portion, the upper pad portion and the lower portion having different widths in the second direction, and The contact area extends into a portion of the upper pad portion.

10. The semiconductor device according to claim 1, in, The second substrate structure further includes a lower partition region extending in the first and second directions and extending into the uppermost gate electrode of the gate electrodes. The upper surface of the lower dividing region is in contact with the horizontal region.

11. The semiconductor device according to claim 1, in, The second substrate structure includes a first region, and the first region includes the channel structure. The second substrate structure further includes a second region located on at least one side of the first region and including unit contact plugs electrically connected to the gate electrode. The source structure is located in the first region and not in the second region.

12. The semiconductor device according to claim 11, wherein, The upper insulating layer extends from the first region to the second region and at least partially overlaps with the upper end of the cell contact plug in the first direction.

13. The semiconductor device according to claim 1, in, The second substrate structure further includes a partition region extending into the gate electrode and extending in both the first and second directions, and The upper insulating layer at least partially overlaps with the upper end of the partition region in the first direction.

14. The semiconductor device according to claim 13, wherein, The contact area extends into a portion of the separating area.

15. A semiconductor device, the semiconductor device comprising: A first substrate structure, the first substrate structure including a substrate and circuit elements located on the substrate; as well as A second substrate structure is located on the first substrate structure, wherein the second substrate structure includes: Gate electrodes, which are spaced apart from each other and stacked in a first direction perpendicular to the upper surface of the substrate; An interlayer insulating layer, wherein the interlayer insulating layer is alternately stacked with the gate electrode; A channel structure extending into the gate electrode and extending in the first direction, and comprising a channel layer and a channel dielectric layer located on a side surface of the channel layer; and A source structure is located on the channel structure and includes a horizontal region and a contact region. The horizontal region extends in a second direction parallel to the upper surface of the substrate, and the contact region extends from the horizontal region in a first direction and contacts the channel layer. The contact area extends into a portion of the channel dielectric layer of each of the channel structures, and The lower surface of the contact area is in contact with the channel structure and the interlayer insulation layer.

16. The semiconductor device according to claim 15, wherein, The contact area is in contact with the channel layer on the first side of the channel structure.

17. The semiconductor device according to claim 15, wherein, The distance in the first direction between the upper surface of the contact area and the lower surface of the second substrate structure is greater than the distance in the first direction between the upper surface of the first channel structure and the lower surface of the second substrate structure in the channel structure.

18. The semiconductor device according to claim 15, wherein, Each of the aforementioned channel structures has an asymmetrical shape relative to its central axis.

19. A data storage system, the data storage system comprising: A semiconductor device, the semiconductor device including a first substrate structure, the first substrate structure including a substrate and circuit elements located on the substrate, the semiconductor device further including a second substrate structure, the second substrate structure including input / output pads electrically connected to corresponding circuit elements in the circuit elements; as well as The controller is electrically connected to the semiconductor device via the input / output pads. The second substrate structure further includes: Gate electrodes, which are spaced apart from each other and stacked in a first direction perpendicular to the upper surface of the substrate; A channel structure extending into the gate electrode and extending in the first direction, the channel structure comprising a channel layer and a channel dielectric layer located on a side surface of the channel layer; and A source structure is located on the channel structure and includes a horizontal region and a contact region. The horizontal region extends in a second direction parallel to the upper surface of the substrate, and the contact region extends from the horizontal region in a first direction and contacts the channel layer. In each of the upper regions of the channel structure, the contact region contacts a first portion of the side surface of the channel layer, but does not contact a second portion of the side surface of the channel layer.

20. The data storage system according to claim 19, wherein, The contact area extends into a portion of the channel dielectric layer of each of the channel structures.

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