TMBS device and preparation method thereof

By using a staggered distribution of deep and shallow slots and an N+ enhancement region design, the depletion region and current path of the TMBS device are optimized, solving the performance bottleneck of traditional TMBS devices in high-voltage applications. This achieves low forward conduction resistance and high current carrying capacity while maintaining fast switching characteristics.

CN122269723APending Publication Date: 2026-06-23ZHEJIANG FORSOL ENERGY
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Patent Information

Application Number
CN202610252825.5
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-03-03
Publication Date
2026-06-23

AI Technical Summary

Technical Problem

Traditional TMBS devices suffer from problems such as insufficient reverse blocking capability, large leakage current, and high forward conduction resistance in high-voltage applications, making it difficult to widely apply them in the field of power semiconductor devices.

Method used

A staggered deep and shallow trench structure is adopted, combined with N+ enhancement region, silicon oxide layer and polysilicon filling design, to form a staggered trench structure, optimize the depletion region expansion path and current transmission path, reduce forward conduction resistance, alleviate electric field concentration and reduce reverse leakage current.

Benefits of technology

Without increasing the thickness of the epitaxial layer, the forward conduction resistance and on-state loss are significantly reduced, the current carrying capacity is improved, the zero reverse recovery characteristic and fast switching speed are maintained, and the device performance is optimized.

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Abstract

The invention relates to the technical field of semiconductors, in particular to a TMBS device and a preparation method thereof.The TMBS device comprises an N + type silicon substrate, an N-type silicon epitaxy, barrier alloy and back metal, the N-type silicon epitaxy is arranged above the N + type silicon substrate, a plurality of grooves are formed in the upper portion of the N-type silicon epitaxy, and the barrier alloy is arranged on the upper portion of the N-type silicon epitaxy; the trench comprises shallow trenches and deep trenches which are uniformly spaced and distributed in a staggered manner, the side wall of each deep trench is provided with an N + enhancement region, the inner wall of the trench is provided with a silicon oxide layer, the trench is filled with conductive polycrystalline silicon, the barrier alloy is arranged above the N-type silicon epitaxy, and the back metal is arranged below the N + type silicon substrate.
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