A tmbs device and a method of manufacturing the same

Abstract

The present application relates to the technical field of semiconductor, and relates to a TMBS device and a preparation method thereof, and the present application comprises an N+ type silicon substrate, an N type silicon epitaxial layer, a barrier alloy and a back metal, the N type silicon epitaxial layer is arranged above the N+ type silicon substrate, a plurality of grooves are arranged on the upper portion of the N type silicon epitaxial layer, the grooves comprise uniformly spaced and staggered shallow grooves and deep grooves, the sidewall of the deep groove is provided with an N+ enhancement region, the inner wall of the groove is provided with a silicon oxide layer, the groove is filled with conductive polysilicon, the barrier alloy is arranged above the N type silicon epitaxial layer, and the back metal is arranged below the N+ type silicon substrate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and specifically to a TMBS device and its fabrication method. Background Technology

[0002] In power electronics systems, power diodes are crucial fundamental components, widely used in switching power supplies, frequency converters, uninterruptible power supplies (UPS), and electric vehicle drives. Their performance directly affects the efficiency, size, and reliability of the entire system. An ideal power diode should possess low forward voltage drop, fast reverse recovery speed, and high reverse breakdown voltage. Schottky barrier diodes (SBDs) are majority carrier devices that operate using the Schottky barrier formed by the metal-semiconductor contact. Because their operating principle does not involve the storage and recombination of minority carriers, they theoretically have zero reverse recovery characteristics, extremely fast switching speed, and extremely low switching losses. Simultaneously, SBDs typically have a lower forward voltage drop than PN junction diodes. However, a fundamental drawback of traditional SBDs is that their reverse blocking capability heavily depends on the doping concentration and thickness of the semiconductor drift region. To improve the breakdown voltage, a low-doped, thick epitaxial layer must be used, but this significantly increases the device's forward resistance and voltage drop, creating a contradiction. More importantly, under reverse bias, the edge of the Schottky junction generates extremely high electric field peaks due to electric field concentration, causing the actual breakdown voltage of the device to be far lower than the theoretical limit of the semiconductor material itself, and generating a large reverse leakage current. This electric field concentration effect severely limits the application of traditional SBDs in high-voltage (typically referring to withstand voltages above 200V) applications. To overcome the bottleneck of traditional SBDs in high-voltage applications, trench MOS barrier Schottky diode (TMBS) technology has emerged. TMBS devices, based on the planar structure of traditional SBDs, introduce etched trenches and gate oxide / multi-silicon structures, i.e., creating periodic trenches and mesas on the semiconductor surface. It can effectively disperse and reduce the maximum electric field intensity at the Schottky metal-semiconductor interface, alleviate the electric field concentration phenomenon, and by optimizing the shape of the depletion region, the electric field can be more uniformly distributed throughout the drift region, thus making the actual breakdown voltage of the device closer to the theoretical limit of the material. Therefore, TMBS technology enables Schottky diodes to achieve a much higher breakdown voltage than traditional SBDs by using a drift layer with a higher doping concentration at the same breakdown voltage, or by using the same drift layer parameters.

[0003] Traditional TMBS devices typically employ a right-angle trench structure, balancing forward conduction and reverse blocking capabilities through meticulous design of parameters such as trench depth, width, spacing, and mesa doping concentration. However, during reverse blocking, the depletion region fails to completely cover the mesa, resulting in poor electric field shielding and persistently high leakage current. These drawbacks limit the application of TMBS devices in the power semiconductor field. Summary of the Invention

[0004] To address the problems of the prior art, this invention provides a TMBS device and its fabrication method.

[0005] The objective of this invention can be achieved through the following technical solution: A TMBS device, comprising: an N+ type silicon substrate, an N- type silicon epitaxial layer, a barrier alloy, and a back metal, wherein the N- type silicon epitaxial layer is disposed above the N+ type silicon substrate, and a plurality of trenches are formed on the upper part of the N- type silicon epitaxial layer, the trenches including shallow trenches and deep trenches that are uniformly spaced and staggered, the sidewalls of the deep trenches are provided with N+ enhancement regions, the inner walls of the trenches are provided with silicon oxide layers, the trenches are filled with conductive polysilicon, the barrier alloy is disposed above the N- type silicon epitaxial layer, and the back metal is disposed below the N+ type silicon substrate.

[0006] In a further improvement, the thickness of the N-type silicon epitaxial layer is 6~7 μm.

[0007] In a further improvement, the inner diameter of the shallow groove is 0.57~0.63μm, and the inner diameter of the deep groove is 0.62~0.68μm; the depth of the shallow groove is 2.0~2.5μm, and the depth of the deep groove is 3.5~4.5μm; the distance between adjacent shallow and deep grooves is 0.85~0.9μm.

[0008] In a further improvement, the N+ enhancement region is formed by phosphorus ion implantation, the width of the N+ enhancement region is 0.1~0.15μm, and the junction depth of phosphorus ion implantation is 3~4μm.

[0009] In a further improvement, the thickness of the silicon oxide layer is 300~350nm, and the barrier alloy is a Ni / Pt alloy.

[0010] A method for fabricating a TMBS device includes the following steps: S1: An N-type silicon epitaxial layer is grown on the upper surface of an N+ type silicon substrate; S2: N+ type ion implantation is performed on N-type silicon epitaxy and annealing is performed to form an N+ reinforcement region that fits the sidewall of the deep trench; S3: Multiple shallow and deep trenches are etched on the upper part of the N-type silicon epitaxial layer using a step-by-step etching process. The shallow and deep trenches are staggered, and the location of the deep trenches corresponds to the area where the N+ enhancement region is located. S4: Deposit and grow a silicon oxide layer on the surface of the N-type silicon epitaxial layer and the inner wall of the trench, and remove the excess silicon oxide layer on the N-type silicon epitaxial mesa. S5: Deposit polysilicon on the surface of the silicon oxide layer to completely fill the trench, and then remove excess polysilicon from the N-type silicon epitaxial mesa to make the upper surface of the polysilicon flush with the upper surface of the N-type silicon epitaxial mesa. S6: A Schottky contact is formed by sputtering a barrier alloy onto the upper surface of the N-type silicon epitaxial layer, and an ohmic contact is formed by sputtering a backside metal onto the lower surface of the N+ type silicon substrate, thus obtaining the TMBS device. Further improvements... In a further improvement, in step S2, the window used to define the N+ enhancement region is a rounded rectangle, and the windows are arranged in an alternating pattern.

[0011] Compared with the prior art, the beneficial effects of the TMBS device and its fabrication method of the present invention are as follows: The alternating deep and shallow trench design reduces the resistance of the forward current path. Combined with the high carrier concentration in the N+ enhancement region of the deep trench sidewall, it significantly reduces the forward conduction voltage of the device. Under the same operating current, the on-state loss of the device is significantly reduced. The hierarchical structure of deep and shallow trenches allows the depletion region to expand in layers within the drift region. Combined with the electric field shielding effect of polysilicon, this alleviates the problem of electric field concentration at the edge of the Schottky junction in traditional TMBS devices, and the reverse leakage current is reduced compared to traditional right-angle trench TMBS devices. The differentiated design of deep and shallow trenches allows different depth regions of the drift region to participate in the formation of the depletion region and current transmission, solving the problem of insufficient utilization of deep space in the drift region of traditional TMBS devices, and optimizing device performance without increasing the thickness of the epitaxial layer; It is still based on the majority carrier conduction principle of the Schottky barrier, without the storage and recombination process of minority carriers, maintaining the zero reverse recovery characteristic, and the core advantages of fast switching speed and low switching loss remain unchanged. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the TMBS device in the embodiment; Figure 2 This is a schematic diagram of the TMBS device fabrication method in the embodiment. Figure 1 ; Figure 3 This is a schematic diagram of the TMBS device fabrication method in the embodiment. Figure 2 ; Figure 4 This is a schematic diagram of the TMBS device fabrication method in the embodiment. Figure 3 ; Figure 5 This is a schematic diagram of the TMBS device fabrication method in the embodiment. Figure 4; Figure 6 This is a schematic diagram of the TMBS device fabrication method in the embodiment. Figure 5 ; Figure 7 This is a schematic diagram of the TMBS device fabrication method in the embodiment. Figure 6 ; Figure 8 This example compares the positive characteristics of the TMBS device with those of a regular TMBS device. In the figure, 1 is an N+ type silicon substrate, 2 is an N- type silicon epitaxial layer, 21 is a trench, 22 is a shallow trench, 23 is a deep trench, 3 is an N+ reinforcement region, 4 is a silicon oxide layer, 5 is polysilicon, 6 is a barrier alloy, and 7 is a back metal. Detailed Implementation

[0013] In the description of this invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0014] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0015] The following is a description of the embodiments and appendices. Figures 1-8 The technical solution of the present invention will be further described below.

[0016] Example 1 A TMBS device includes: an N+ type silicon substrate 1, an N- type silicon epitaxial layer 2, a barrier alloy 6, and a back metal 7. The N- type silicon epitaxial layer 2 is disposed above the N+ type silicon substrate 1. A plurality of trenches 21 are formed on the upper part of the N- type silicon epitaxial layer 2. The trenches 21 include shallow trenches 22 and deep trenches 23 that are uniformly spaced and staggered. The sidewalls of the deep trenches 23 are provided with N+ enhancement regions 3. The inner walls of the trenches 21 are provided with silicon oxide layers 4. The trenches 21 are filled with conductive polysilicon 5. The barrier alloy 6 is disposed above the N- type silicon epitaxial layer 2, and the back metal 7 is disposed below the N+ type silicon substrate 1.

[0017] A method for fabricating a TMBS device includes the following steps: S1: An N-type silicon epitaxial layer 2 is grown on the upper surface of an N+ type silicon substrate 1; S2: N+ type ion implantation is performed on N-type silicon epitaxy 2 and annealing is performed to form N+ reinforcement region 3 that fits the sidewall of deep trench 23; the window used to define N+ reinforcement region 3 is a rounded rectangle and the windows are staggered. S3: Multiple shallow trenches 22 and deep trenches 23 are etched on the N-type silicon epitaxial layer 2 using a step-by-step etching process. The shallow trenches 22 and deep trenches 23 are staggered, and the location of the deep trenches 23 corresponds to the region where the N+ enhancement region 3 is located. S4: Deposit and grow a silicon oxide layer 4 on the surface of the N-type silicon epitaxial layer 2 and the inner wall of the trench 21, and remove the excess silicon oxide layer 4 on the mesa of the N-type silicon epitaxial layer 2. S5: Deposit polysilicon 5 on the surface of silicon oxide layer 4, so that polysilicon 5 completely fills the inside of trench 21, and then remove excess polysilicon 5 on the mesa of N-type silicon epitaxial layer 2, so that the upper surface of polysilicon 5 is flush with the upper surface of N-type silicon epitaxial layer 2. S6: A Schottky contact is formed by sputtering a barrier alloy 6 on the upper surface of the N-type silicon epitaxial layer 2, and an ohmic contact is formed by sputtering a back metal 7 on the lower surface of the N+ type silicon substrate 1, thereby obtaining the TMBS device.

[0018] To demonstrate the effectiveness of this patented design, we simulated the forward conduction characteristics of deep and shallow trench sidewall-injected TMBS and ordinary TMBS using Silvaco. The simulation results are as follows: Figure 8 As shown, the horizontal axis represents the forward conduction voltage, and the vertical axis represents the forward operating current. The curves for the deep and shallow trench devices of this invention have a steeper slope, while those for ordinary devices have a steeper slope. Both exhibit good linearity with no threshold inflection point, preserving the majority carrier conductivity characteristics of the Schottky design. Data shows that under the same forward current, the forward voltage reduction of the deep and shallow trench devices reaches 25%~30%, with a more significant advantage in high-current conditions. Under the same forward voltage, their current carrying capacity is increased by 25%~50%, and their low-voltage turn-on characteristics are also superior, directly reflecting a significant reduction in forward conduction resistance. Therefore, the core conclusion can be drawn: this deep... The structural design of the N+ reinforcement region on the sidewalls of the shallow and deep trenches significantly reduces the forward conduction resistance of the device, substantially reduces conduction losses, and improves current carrying capacity without changing the core Schottky conductivity principle of the TMBS device and retaining its excellent switching characteristics such as zero reverse recovery. This represents a breakthrough optimization of forward conduction performance. Moreover, this optimization was achieved by making reasonable trade-offs of slightly sacrificing a small amount of reverse breakdown voltage and slightly increasing reverse leakage current. The relevant parameters can also be flexibly adjusted to match different application requirements. Simulation data also provides important theoretical and data support for subsequent process development.

[0019] As shown in the figure, the principle of this invention is as follows: The core of the TMBS device in this embodiment adopts a trench structure with alternating deep and shallow trenches, and sets an N+ enhancement region on the sidewall of the deep trench. At the same time, it is combined with the silicon oxide layer, polysilicon filling and Ni / Pt barrier alloy Schottky contact design in the trench. From the three dimensions of current conduction path optimization, electric field distribution control and carrier transport efficiency improvement, it breaks through the technical bottleneck of low drift region space utilization and difficulty in balancing forward conduction and reverse blocking performance of traditional TMBS devices.

[0020] By uniformly and alternately arranging shallow and deep trenches, the depletion region expansion path and forward current transmission path of the device are redesigned. Shallow trenches can quickly form a local depletion region under reverse bias to achieve preliminary electric field shielding, while deep trenches guide the depletion region to extend deeper into the drift region, making the distribution of the depletion region in the drift region more in line with the device structure and improving the space utilization efficiency of the drift region. Taking advantage of the fact that the transmission paths of forward current and reverse leakage current do not overlap, an N+ enhancement region is set on the sidewall of the deep trench. When forward conduction is enabled, the N+ enhancement region can provide a high concentration of free electrons, which significantly reduces the resistance of current transmission. When reverse blocking is enabled, the N+ enhancement region exists only in a local area of ​​the deep trench and will not have a significant negative impact on the formation of the overall depletion region. The silicon oxide layer acts as an insulating layer to isolate the polysilicon from the semiconductor body, preventing the polysilicon from forming electrical contacts with the N-type silicon epitaxial layer and affecting the device characteristics. The filled conductive polysilicon can form an electric field shielding structure, further dispersing the electric field concentration at the edge of the Schottky junction and optimizing the reverse electric field distribution. The Ni / Pt barrier alloy on the N-type silicon epitaxial surface forms a Schottky contact, ensuring the majority carrier conductivity of the device and enabling fast switching speeds; the metal on the back of the N+ type silicon substrate forms an ohmic contact, reducing the contact resistance between the substrate and the metal and ensuring efficient current transmission.

[0021] As a further preferred embodiment, the thickness of the N-type silicon epitaxial layer 2 is 6~7μm. The depth design of the matching deep and shallow trenches ensures that the epitaxial layer thickness meets the structural requirements for deep trench extension, guaranteeing that the depletion region can fully expand within the entire epitaxial layer to achieve sufficient reverse blocking capability, while also avoiding increased forward conduction resistance due to excessive epitaxial layer thickness. Simultaneously, it matches the epitaxial layer thickness requirements of power diodes in medium- and high-voltage application scenarios.

[0022] As a further preferred embodiment, the inner diameter of the shallow groove 22 is 0.57~0.63μm, and the inner diameter of the deep groove 23 is 0.62~0.68μm; the depth of the shallow groove 22 is 2.0~2.5μm, and the depth of the deep groove 23 is 3.5~4.5μm; the distance between adjacent shallow grooves 22 and deep grooves 23 is 0.85~0.9μm.

[0023] The differentiated inner diameter design matches the functional positioning of the deep and shallow trenches. The larger inner diameter of the deep trench provides sufficient space for the N+ reinforcement zone on the sidewall, while the inner diameter of the shallow trench is adapted to the formation requirements of its shallow depletion zone. The graded design of the depth guides the depletion zone to gradually extend into the deeper part of the drift zone from the shallow trench to the deep trench, avoiding the electric field peak caused by the excessive concentration of the depletion zone at a certain depth. The uniform spacing ensures the periodicity of the trench arrangement, so that the depletion zone expands uniformly in the lateral direction, avoiding the failure of electric field shielding or the current path being too narrow in some areas due to excessively large / small trench spacing.

[0024] As a further preferred embodiment, the N+ enhancement region 3 is formed by phosphorus ion implantation, which provides a low-resistance carrier channel for forward current, significantly reducing the transmission resistance of current in the drift region and further reducing the forward conduction voltage. The width of the N+ enhancement region 3 is 0.1~0.15μm, and the junction depth of phosphorus ion implantation is 3~4μm. The size limitation allows the N+ enhancement region to be locally distributed on the sidewall of the deep trench. Under reverse bias, it will only slightly increase the leakage current in the local area and will not have a significant impact on the overall reverse leakage current of the device. At the same time, it enhances the withstand voltage capability of the non-electric field peak part in the drift region, making up for the slight sacrifice of breakdown voltage in the deep and shallow trench design and achieving a slight recovery of breakdown voltage.

[0025] As a further preferred embodiment, the thickness of the silicon oxide layer 4 is 300~350nm. If it is too thin, it cannot effectively isolate the polycrystalline silicon from the N-type silicon epitaxial layer, which is prone to leakage current. If it is too thick, it will increase the difficulty of filling the trench and may cause cracking due to film stress. The barrier alloy 6 is a Ni / Pt alloy, which can form a uniform alloy system. The Schottky barrier height can be flexibly controlled by adjusting the ratio of the two: Ni has a lower work function, which can reduce the barrier height to reduce the forward conduction voltage drop; Pt has a higher work function, which can increase the barrier height to reduce the reverse leakage current.

[0026] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A TMBS device, characterized in that, include: The structure comprises an N+ type silicon substrate 1, an N- type silicon epitaxial layer 2, a barrier alloy 6, and a back metal 7. The N- type silicon epitaxial layer 2 is disposed above the N+ type silicon substrate 1. Multiple trenches 21 are formed on the upper part of the N- type silicon epitaxial layer 2. Each trench 21 includes shallow trenches 22 and deep trenches 23 that are evenly spaced and staggered. The sidewalls of the deep trenches 23 are provided with N+ enhancement regions 3. The inner walls of the trenches 21 are provided with silicon oxide layers 4. The trenches 21 are filled with conductive polycrystalline silicon 5. The barrier alloy 6 is disposed above the N- type silicon epitaxial layer 2, and the back metal 7 is disposed below the N+ type silicon substrate 1.

2. The TMBS device according to claim 1, characterized in that, The thickness of the N-type silicon epitaxial layer 2 is 6~7 μm.

3. The TMBS device according to claim 1, characterized in that, The inner diameter of the shallow groove 22 is 0.57~0.63μm, and the inner diameter of the deep groove 23 is 0.62~0.68μm; the depth of the shallow groove 22 is 2.0~2.5μm, and the depth of the deep groove 23 is 3.5~4.5μm; the distance between adjacent shallow grooves 22 and deep grooves 23 is 0.85~0.9μm.

4. The TMBS device according to claim 1, characterized in that, The N+ enhancement region 3 is formed by phosphorus ion implantation. The width of the N+ enhancement region 3 is 0.1~0.15μm, and the junction depth of phosphorus ion implantation is 3~4μm.

5. The TMBS device according to claim 1, characterized in that, The thickness of the silicon oxide layer 4 is 300~350nm, and the barrier alloy 6 is a Ni / Pt alloy.

6. A method for fabricating a TMBS device according to any one of claims 1-5, characterized in that, Includes the following steps: S1: An N-type silicon epitaxial layer 2 is grown on the upper surface of an N+ type silicon substrate 1; S2: N+ type ion implantation is performed on N-type silicon epitaxy 2 and annealing is performed to form N+ reinforcement region 3 that fits the sidewall of deep trench 23; S3: Multiple shallow trenches 22 and deep trenches 23 are etched on the N-type silicon epitaxial layer 2 using a step-by-step etching process. The shallow trenches 22 and deep trenches 23 are staggered, and the location of the deep trenches 23 corresponds to the region where the N+ enhancement region 3 is located. S4: Deposit and grow a silicon oxide layer 4 on the surface of the N-type silicon epitaxial layer 2 and the inner wall of the trench 21, and remove the excess silicon oxide layer 4 on the mesa of the N-type silicon epitaxial layer 2. S5: Deposit polysilicon 5 on the surface of silicon oxide layer 4, so that polysilicon 5 completely fills the inside of trench 21, and then remove excess polysilicon 5 on the mesa of N-type silicon epitaxial layer 2, so that the upper surface of polysilicon 5 is flush with the upper surface of N-type silicon epitaxial layer 2. S6: A Schottky contact is formed by sputtering a barrier alloy 6 on the upper surface of the N-type silicon epitaxial layer 2, and an ohmic contact is formed by sputtering a back metal 7 on the lower surface of the N+ type silicon substrate 1, thereby obtaining the TMBS device.

7. The method for fabricating a TMBS device according to claim 6, characterized in that, In step S2, the window used to define the N+ enhancement region 3 is a rounded rectangle, and the windows are arranged in an alternating pattern.

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