Semiconductor device

Abstract

One embodiment provides a semiconductor device capable of preventing RBSOA (Reverse Bias Safe Operating Area). According to one embodiment, a semiconductor device includes a semiconductor component, a gate metal layer, a first gate electrode, and an emitter electrode. The gate metal layer includes a first portion and a second portion. The first gate electrode extends along a first direction, the first direction being from the first portion toward the second portion. The first gate electrode is connected to the gate metal layer in the first portion. The emitter electrode is provided on the semiconductor component. The emitter electrode includes a third portion and a fourth portion. The emitter electrode is electrically connected to the semiconductor component in the third portion and the fourth portion. The second portion is located between the third portion and the fourth portion in the first direction.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2024-225678, filed on December 20, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The implementation methods described herein generally relate to semiconductor devices. Background Technology

[0004] It is desirable for semiconductor devices to prevent the reduction of RBSOA (Reverse Bias Safe Operating Area). Summary of the Invention

[0005] One implementation provides a semiconductor device capable of preventing RBSOA.

[0006] According to one embodiment, a semiconductor device includes a semiconductor component, a gate metal layer, a first gate electrode, and an emitter electrode. The gate metal layer includes a first portion and a second portion. The first gate electrode extends along a first direction from the first portion toward the second portion. The first gate electrode is connected to the gate metal layer in the first portion. The emitter electrode is disposed on the semiconductor component. The emitter electrode includes a third portion and a fourth portion. The emitter electrode is electrically connected to the semiconductor component in the third and fourth portions. The second portion is located between the third and fourth portions in the first direction. Attached Figure Description

[0007] Figure 1 This is a schematic plan view showing a semiconductor device according to an embodiment.

[0008] Figure 2 This is a schematic plan view showing a semiconductor device according to an embodiment.

[0009] Figure 3 It is along Figure 2 The cross-sectional view taken from line AA.

[0010] Figure 4 It is along Figure 2 The cross-sectional view of line BB.

[0011] Figure 5 It is along Figure 2 The cross-sectional view taken from line CC.

[0012] Figure 6 This is a magnified view of the surrounding area of ​​the second part.

[0013] Figure 7 This is a schematic plan view showing a semiconductor device according to a first variation of the embodiment.

[0014] Figure 8 This is a schematic plan view showing a semiconductor device according to a first variation of the embodiment;

[0015] Figure 9 This is a schematic plan view showing a semiconductor device according to a second variation of the embodiment.

[0016] Figure 10 It is along Figure 9 The cross-sectional view taken from line HH. Detailed Implementation

[0017] Various implementation methods are described below with reference to the accompanying drawings.

[0018] The accompanying drawings are schematic and conceptual, and the relationships between the thicknesses and widths of the parts, as well as the dimensional proportions between the parts, may not be the same as the actual values. Even for the same part, the dimensions and proportions may differ in the accompanying drawings.

[0019] In the specification and drawings, components similar to those previously described or shown in the preceding drawings are marked with the same symbols, and detailed descriptions are appropriately omitted.

[0020] Figure 1 and Figure 2 This is a schematic plan view showing a semiconductor device according to an embodiment.

[0021] Figure 1 The semiconductor device 100 shown includes a semiconductor component 10M, a gate metal layer 53L including a first pad 71, a second pad 72, and an emitter electrode 52. The gate metal layer 53L includes a portion surrounding the emitter electrode 52 in the XY plane and a portion located between the emitter electrodes 52. The first pad 71 is, for example, a gate pad.

[0022] from Figure 1 The third direction D3 from the collector electrode 51 to the emitter electrode 52 (not shown) intersects with a first plane including the first direction D1 and the second direction D2. The semiconductor component 10M is located between the collector electrode 51 and the emitter electrode 52.

[0023] The second pad 72 is electrically insulated from the gate metal layer 53L. The second pad 72 is, for example, a temperature sensing pad, a multi-gate gate pad, or a current sensing pad.

[0024] The emitter electrode 52 and the gate metal layer 53L are separately disposed. The emitter electrode 52 is divided into multiple portions and provided. The gate metal layer 53L includes an outer periphery 53LA formed in a ring around the plurality of emitter electrodes 52 in the XY plane. The gate metal layer 53L includes wiring 53LB connecting the two sides of the outer periphery 53LA. Figure 1 As shown, for example, wiring 53LB extends in the Y direction and connects to the side of the outer perimeter 53LA extending in the X direction. Wiring 53LB connects to the opposite side of the outer perimeter 53LA.

[0025] When execution Figure 2 When controlling the gate potential of the gate electrodes 53 (first gate electrode 53a, second gate electrode 53b, and third gate electrode 53c), it is desirable for the gate metal layer 53L, including the wiring 53LB, to reduce the timing difference in voltage application among the multiple gate electrodes 53. Not only the outer periphery 53LA but also the wiring 53LB is connected to the gate electrode 53, and a voltage can be applied to the gate electrode 53, thus reducing the distance between the gate electrode 53 and the gate metal layer 53L.

[0026] Figure 2 It shows Figure 1 The area S1 shown.

[0027] like Figure 2 As shown, the semiconductor device 100 according to the embodiment includes a semiconductor component 10M (semiconductor substrate), a gate metal layer 53L, a first gate electrode 53a, and an emitter electrode 52.

[0028] The direction along the top surface of the semiconductor component 10M is defined as the X-axis direction. The direction along the top surface of the semiconductor component 10M and perpendicular to the X-axis direction is defined as the Y-axis direction. The direction perpendicular to both the X-axis and Y-axis directions is defined as the Z-axis direction. The X-axis direction is, for example, a first direction D1. The Y-axis direction is, for example, a second direction D2. The Z-axis direction is, for example, a third direction D3. The XY plane is, for example, a first plane.

[0029] The gate metal layer 53L includes a first portion P1 and a second portion P2. An insulator 85 is provided between the gate metal layer 53L and the semiconductor component 10M, as will be referred to later. Figure 3 As described. Insulator 85 includes insulating layer 85a and first insulating film 85b. Gate metal layer 53L is disposed on semiconductor component 10M, wherein insulating layer 85a is inserted therebetween.

[0030] A first gate electrode 53a extends along a first direction D1 from a first portion P1 toward a second portion P2. A gate metal layer 53L is electrically connected to the first gate electrode 53a in the first portion P1. The first gate electrode 53a is, for example, a gate electrode 53 embedded in a semiconductor component 10M. The first gate electrode 53a faces the semiconductor component 10M, with a first insulating film 85b inserted therebetween. For example, a transistor is formed in the semiconductor component 10M, and the conductivity of the transistor is controlled by applying a voltage to the first gate electrode 53a. The first gate electrode 53a is, for example, a trench gate electrode.

[0031] Multiple gate electrodes 53 extend in a first direction D1.

[0032] An emitter electrode 52 is disposed on the semiconductor component 10M. The emitter electrode 52 includes a third portion P3 and a fourth portion P4. The emitter electrode 52 is electrically connected to the semiconductor component 10M in the third portion P3 and the fourth portion P4. A second portion P2 is located between the third portion P3 and the fourth portion P4 in a first direction D1.

[0033] The semiconductor device 100 according to this embodiment includes a collector 51 (see...). Figure 3 ) and insulator 85. Emitter electrode 52 includes emitter contact 52C, which contacts semiconductor component 10M, as will be referred to later. Figure 4 The described emitter contact 52C includes a first emitter contact region 52a that is continuous with the third portion P3 and a second emitter contact region 52b that is continuous with the fourth portion P4.

[0034] The first insulating film 85b serves as the gate insulating film. The current flowing between the collector 51 and the emitter 52 can be controlled according to the potential of the gate electrode 53. The semiconductor device 100 is, for example, an IGBT (Insulated Gate Bipolar Transistor).

[0035] When conducting, charge carriers accumulate in the region outside the outermost first gate electrode 53a in the negative direction of the second direction D2. Considering a reference example where the emitter electrode 52 does not include the third part P3, current congestion occurs at the contacts in the active region during turn-off and when the load is short-circuited, and device damage may occur due to current congestion or latch-up.

[0036] In the semiconductor device 100 according to the embodiment, the emitter contact 52C (first emitter contact region 52a) outside the active region allows carrier discharge. This prevents the reduction of RBSOA and SCSOA (short-circuit safe operating region).

[0037] Note that the emitter contact 52C, which electrically connects the emitter electrode 52 and the semiconductor component 10M, does not necessarily extend into the semiconductor component 10M. However, it is desirable for the emitter contact 52C to extend into the semiconductor component 10M, as will be discussed later. Figure 5 As shown, this is to increase the contact area between the emitter electrode 52 and the semiconductor component 10M.

[0038] like Figure 2 As shown, the length of the third part P3 along the first direction D1 is greater than the length of the second part P2 along the first direction D1. Furthermore, the length of the third part P3 along the first direction D1 is greater than the length of the first part P1 along the first direction D1. Figure 2 As shown, the length of the first gate electrode 53a in the third part P3 in the first direction D1 is greater than the length of the first gate electrode 53a in the second part P2 in the first direction D1.

[0039] Figures 3 to 5 This is a cross-sectional view of a semiconductor device according to an embodiment.

[0040] Figure 3 It is along Figure 2 The cross-sectional view taken from line AA.

[0041] Figure 4 It is along Figure 2 The cross-sectional view of line BB.

[0042] Figure 5 It is along Figure 2 The cross-sectional view taken from line CC.

[0043] refer to Figure 3 Provide a description. Figure 3 An example of a trench gate semiconductor device is shown. This does not preclude the application of the implementation to planar gate semiconductor devices.

[0044] An insulating layer 85a is disposed on the semiconductor component 10M, the first gate electrode 53a, and the first insulating film 85b. The insulating layer 85a is inserted between the first gate electrode 53a and the emitter electrode 52.

[0045] The connecting component 60 (e.g., a metal plug) electrically connects the first portion P1 and the first gate electrode 53a. The gate metal layer 53L and the first gate electrode 53a are electrically connected via the connecting component 60.

[0046] exist Figure 3 In the example shown, in the second part P2 ( Figure 3 There is no electrical connection between (not shown in the diagram) and the first gate electrode 53a. However, for example, in the case of... Figure 3In the same AA cross section, if the second part P2 reaches the AA line, a metal plug can be formed between the second part P2 and the first gate electrode 53a.

[0047] In the first insulating film 85b, the end on the first direction D1 can be covered by a semiconductor region having a conductivity type opposite to that of the first semiconductor region 11.

[0048] The gate metal layer 53L and the emitter electrode 52 disposed on the insulating layer 85a are spaced apart from each other.

[0049] refer to Figure 4 Provide a description.

[0050] like Figure 4 As shown, emitter contact 52C contacts semiconductor component 10M. At least a portion of emitter contact 52C extends along a first direction D1. Emitter contact 52C includes a first emitter contact region 52a disposed in a third portion P3 and a second emitter contact region 52b disposed in a fourth portion P4.

[0051] Emitter contact 52C is connected to the third semiconductor region 13. Although Figure 4 A cross-section of the emitter contact 52C located on the third semiconductor region 13 is shown, but the third semiconductor region 13 and the emitter contact 52C may not be in contact with each other depending on the position of the cross-section. For example, as Figure 5 As shown, the following situation may exist: the emitter contact 52C extending into the semiconductor component 10M extends along the third direction D3 through the third semiconductor region 13, and the emitter contact 52C and the second semiconductor region 12 are in contact with each other in this cross section.

[0052] The gate metal layer 53L faces the semiconductor component 10M, with the insulating layer 85a inserted therebetween.

[0053] The semiconductor device 100 according to the embodiment includes a first emitter contact region 52a, and charge carriers can move accordingly via the first emitter contact region 52a, thereby preventing a decrease in RBSOA.

[0054] refer to Figure 5 Provide a description.

[0055] The first gate electrode 53a faces the second semiconductor region 12 of the semiconductor component 10M, wherein the first insulating film 85b is inserted therebetween. The first gate electrode 53a extends from the top of the semiconductor component 10M to the first semiconductor region 11.

[0056] Multiple first gate electrodes 53a are arranged side-by-side in the Y direction. Figure 5In a cross-section not shown, the first gate electrode 53a is, for example, via... Figure 3 The connecting component 60 shown is connected to the gate metal layer 53L.

[0057] Note that the implementation method is not limited to Figure 2 and Figure 5 The example shown, in addition to the first gate electrode 53a connected to the gate metal layer 53L, may also provide a dummy gate electrode embedded in the trench. The dummy gate electrode is electrically connected to the emitter electrode 52. The first gate electrode 53a and the dummy gate electrode are arranged cyclically in the Y direction, for example. For example, the first gate electrode 53a and the dummy gate electrode are arranged alternately in the Y direction.

[0058] Reference Figure 5 The operation of semiconductor device 100 is described. An IGBT is a type of power semiconductor device capable of high-speed switching at high power. An IGBT includes three electrodes: a gate, a collector, and an emitter. The current flowing between the collector and emitter is controlled by a voltage applied to the gate. When the voltages applied between the gate and emitter, and between the collector and emitter, are controlled, an electron-gathering channel is formed in the layer facing the gate electrode, and the IGBT turns on.

[0059] like Figure 3 As shown, the semiconductor device 100 according to the embodiment further includes a connection member 60, which includes a first connection portion 61. The first connection portion 61 is located between the first gate electrode 53a and the first portion P1. The first connection portion 61 electrically connects the first portion P1 to the first gate electrode 53a. The connection member 60 including the first connection portion 61 is, for example, a metal plug. The first connection portion 61 is, for example, a metal containing W or Al.

[0060] Refer again Figure 2 Provide a description.

[0061] The first connection part 61 is located at position 61P in the second direction D2, which intersects with the first direction D1, and is different from the first contact area position 52aP in the second direction D2 of the first emitter contact area 52a.

[0062] The gate electrode 53 of the semiconductor device 100 according to the embodiment further includes a second gate electrode 53b along a first direction D1. The direction from the second gate electrode 53b to the first gate electrode 53a is along a second direction D2. The second gate electrodes 53b are arranged side by side in the second direction D2, wherein the first gate electrode 53a is located at the end in the negative direction of the second direction D2. The connection member 60 further includes a second connection portion 62. The second connection portion 62 is between the second gate electrode 53b and the second portion P2. The second connection portion 62 electrically connects the second portion P2 to the second gate electrode 53b at the second connection portion position 62P.

[0063] The length of the first gate electrode 53a along the first direction D1 is greater than the length of the second gate electrode 53b along the first direction D1. In the third direction D3 (Z direction), at least a portion of the second gate electrode 53b overlaps with the second portion P2.

[0064] The first contact area position 52aP is located in the second direction D2 between the second connection part position 62P and the first connection part position 61P of the second connection part 62.

[0065] The direction from the first emitter contact region 52a to the second emitter contact region 52b is along a first direction D1. The second emitter contact region 52b extends, for example, along the first direction D1.

[0066] The third part P3 is located between the first part P1 and the second part P2 in the first direction D1.

[0067] The gate metal layer 53L also includes a fifth portion P5. The fifth portion P5 is continuous with the first portion P1 and the second portion P2. The direction from the fifth portion P5 to the third portion P3 intersects the first direction D1. The direction from the fifth portion P5 to the third portion P3 is along the second direction D2. The first portion P1 extends along the second direction D2, and the fifth portion P5 extends along the first direction D1. When the first portion P1 is considered to extend along the second direction D2, this includes the case where the first portion P1 is defined within a portion of the gate metal layer 53L extending along the second direction D2.

[0068] The semiconductor device 100 according to an embodiment further includes a third gate electrode 53c along a first direction D1. The direction from the third gate electrode 53c to the second gate electrode 53b is along a second direction D2. In other words, the second gate electrode 53b and the third gate electrode 53c are arranged side by side in the second direction D2. The second gate electrode 53b is located between the first gate electrode 53a and the third gate electrode 53c in the second direction D2. The third gate electrode 53c extends along the first direction D1, and the length of the third gate electrode 53c in the first direction D1 is less than the length of the first gate electrode 53a in the first direction D1.

[0069] The gate metal layer 53L also includes a sixth portion P6. The sixth portion P6 is continuous with the fifth portion P5. The direction from the sixth portion P6 to the fifth portion P5 intersects the first direction D1 (e.g., along the second direction D2). The sixth portion P6 extends, for example, along the second direction D2.

[0070] exist Figure 2 In the example shown, the length of the fifth portion P5 in the first direction D1 is greater than its length in the second direction D2. The length of the sixth portion P6 in the second direction D2 is greater than its length in the first direction D1. The first portion P1 and the fifth portion P5 form an L-shaped portion, for example, of the gate metal layer 53L. The fifth portion P5, the second portion P2, and the sixth portion P6 form a T-shaped portion, for example, of the gate metal layer 53L. The second portion P2, a portion of the fifth portion P5, and the sixth portion P6 extend along, for example, the second direction D2 and are connected to the second gate electrode 53b and the third gate electrode 53c.

[0071] The lengths of the second gate electrode 53b and the third gate electrode 53c in the first direction D1 are, for example, equal to each other, but not limited thereto.

[0072] The connecting member 60 also includes a third connecting portion 63. The third connecting portion 63 is located between the third gate electrode 53c and the sixth portion P6. Alternatively, the third connecting portion 63 may be located between the third gate electrode 53c and the fifth portion P5. The third connecting portion 63 electrically connects the fifth portion P5 to the third gate electrode 53c. The third connecting portion 63 electrically connects both the fifth portion P5 and the sixth portion P6 to the third gate electrode 53c.

[0073] The emitter electrode 52 also includes a seventh part P7. The seventh part P7 is continuous with the third part P3 and the fourth part P4. The length of the seventh part P7 in the first direction D1 is greater than the sum of the lengths of the third part P3 and the fourth part P4 in the first direction D1. The length of the seventh part P7 in the first direction D1 is equal to or greater than the sum of the lengths of the third part P3, the fourth part P4, and the second part P2 in the first direction D1. The emitter electrode 52 is electrically connected to the semiconductor component 10M in the seventh part P7. The second part P2 is located between the sixth part P6 and the seventh part P7 in the second direction D2.

[0074] Part 5 (P5), Part 2 (P2), and Part 7 (P7) are arranged sequentially in the second direction (D2). Furthermore, Part 6 (P6), Part 5 (P5), Part 2 (P2), and Part 7 (P7) are arranged sequentially in the second direction (D2).

[0075] Refer again Figure 5The semiconductor component 10M includes a first semiconductor region 11, a second semiconductor region 12, a third semiconductor region 13, and a fourth semiconductor region 14. The first semiconductor region 11 and the third semiconductor region 13 are, for example, of a first conductivity type. The second semiconductor region 12 and the fourth semiconductor region 14 are, for example, of a second conductivity type. The first conductivity type is one of n-type and p-type. The second conductivity type is the other of n-type and p-type. In this embodiment, the first conductivity type may be p-type, and the second conductivity type may be n-type.

[0076] The second semiconductor region 12 is between the first semiconductor region 11 and the emitter electrode 52. The third semiconductor region 13 is between the second semiconductor region 12 and the emitter electrode 52. The third semiconductor region 13 is electrically connected to the emitter electrode 52. The fourth semiconductor region 14 is between the first semiconductor region 11 and the collector electrode 51. The emitter contact 52C extends, for example, into the semiconductor component 10M, and the second semiconductor region 12 is electrically connected to the emitter electrode 52.

[0077] In semiconductor device 100, the concentration of a third impurity of a first conductivity type in the third semiconductor region 13 is higher than the concentration of a first impurity of a first conductivity type in the first semiconductor region 11. The first semiconductor region 11 is, for example, n - Layer 13 or n layers. The third semiconductor region 13 is, for example, n layers. + layer.

[0078] In the semiconductor device 100, the concentration of impurities of a first conductivity type in the first semiconductor region 11 is, for example, not less than 1 × 10⁻⁶. 13 cm -3 and not greater than 1×10 15 cm -3 The concentration of impurities of the first conductivity type in the third semiconductor region 13 is, for example, not less than 1 × 10⁻⁶. 18 cm -3 and not greater than 1×10 21 cm -3 The concentration of impurities of the second conductivity type in the second semiconductor region 12 is, for example, not less than 1 × 10⁻⁶. 15 cm -3 and not greater than 1×10 18 cm -3 The concentration of impurities of the second conductivity type in the fourth semiconductor region 14 is, for example, not less than 1 × 10⁻⁶. 17 cm -3 and not greater than 1×10 19 cm -3 .

[0079] In semiconductor device 100, conduction modulation occurs during conduction, and the carrier density in the first semiconductor region 11 becomes higher than the impurity concentration of the first conduction type, and for example, not less than 1 × 10⁻⁶. 16 cm -3 and not greater than 1×10 18 cm -3 .

[0080] Figure 6 This is an enlarged view of the area surrounding P2 in the second part.

[0081] The second part P2, along the second direction D2, has a first length L1 that is no less than 1 time and no more than 15 times the second length L2 between the first center E1 of the first gate electrode 53a and the second center E2 of the second gate electrode 53b in the second direction D2. The first length L1 may be no less than 1 time and no more than 12 times the second length L2. Alternatively, the first length L1 may be no less than 1 time and no more than 10 times the second length L2. When the first length L1 is less than 1 time the second length L2, the length of the second part P2 in the second direction D2 is insufficient, and there may be a second gate electrode 53b that cannot be connected to the gate metal layer 53L, or the first emitter contact region 52a may not be able to be located in the third part P3.

[0082] The length between the second part P2 and the seventh part P7 in the second direction D2 is defined as the edge length Lm. The edge length Lm is appropriately chosen such that the second part P2 and the seventh part P7 are spaced apart from each other. Since the first length L1 is not less than the second length L2, the first emitter contact region 52a and the second connection portion 62 (gate contact) can be more definitively positioned within the range of length L1 + Lm in the second direction D2. Therefore, it is desirable that the first length L1 is not less than the second length L2. When the first length L1 is not less than one time the second length L2, it is easy to achieve the formation of the first emitter contact region 52a and the second connection portion 62 (gate contact).

[0083] When the first length L1 exceeds 15 times the second length L2, the area of ​​the seventh part P7 is... Figure 2 The area that is reduced in size and cannot provide emitter contact 52C becomes too wide, which is not preferred.

[0084] The second length L2 is the sum of the width of the first gate electrode 53a (or the second gate electrode 53b) in the second direction D2 and the width L4 of the mesa M between the first gate electrode 53a and the second gate electrode 53b in the second direction D2. The second portion P2 and the mesa M overlap in the third direction D3. The first emitter contact region 52a is disposed between the semiconductor component 10M and the third portion P3 at a position where the mesa M extending along the first direction D1 extends in the negative direction of the first direction D1. When the first length L1 is less than the second length L2, it may be difficult to form a second gate electrode 53b and a mesa M in the region below the second portion P2, and have a width of the first length L1 in the second direction D2. On the other hand, when the first length L1 is greater than or equal to the second length L2, at least one second gate electrode 53b and at least one mesa M can be formed in the region below the second portion P2, and have a width of the first length L1 in the second direction D2. The formation of the first emitter contact region 52a and the formation of the second connection portion 62 (gate contact) can be easily achieved.

[0085] The distance F (interval) between the first emitter contact region 52a and the second emitter contact region 52b in the first direction D1 may not exceed 40 μm. In the semiconductor device 100 according to the embodiment, the emitter contact 52C is not located near the second portion P2, but its range is small, so the current congestion to the nearby emitter contact is small. Therefore, breakdown caused by current congestion and latch-up is reduced.

[0086] The first length L1 can be no less than 1 μm and no more than 30 μm.

[0087] The third length L3 of the second part P2 along the first direction D1 can be no less than 5μm and no more than 30μm.

[0088] The distance F between the first emitter contact region 52a and the second emitter contact region 52b can be no less than 20 μm and no more than 60 μm.

[0089] Figure 7 and Figure 8 This is a schematic plan view showing a semiconductor device according to a first variation of the embodiment. Figure 8 It shows Figure 7 The region S2 is shown.

[0090] like Figure 7 As shown, the semiconductor device 101 includes a gate metal layer 53L and an emitter electrode 52. The gate metal layer 53L includes an outer periphery 53LA surrounding the emitter electrode 52. Although Figure 7It is not shown in the figure, but the gate electrode 53 extends along the first direction D1, and the portion of the outer periphery 53LA extending along the second direction D2 is connected to the gate electrode 53.

[0091] The gate metal layer 53L includes a first portion P1, a second portion P2, a fifth portion P5, a sixth portion P6, and an eighth portion P8, as will be referred to later. Figure 8 The gate metal layer 53L includes a first pad 71. The first pad 71 includes at least a portion of a fifth portion P5, at least a portion of a sixth portion P6, and an eighth portion P8, and is, for example, a gate pad.

[0092] like Figure 8 As shown, the gate metal layer 53L also includes an eighth portion P8. The eighth portion P8 is continuous with the fifth portion P5 and the sixth portion P6. The direction from the eighth portion P8 to the fifth portion P5 intersects the first direction D1. The eighth portion P8 is positioned in the negative Y direction relative to the fifth portion P5 and in the negative X direction relative to the sixth portion P6. The portion consisting of the fifth portion P5, the sixth portion P6, and the eighth portion P8 is the first pad 71.

[0093] The gate metal layer 53L includes a first portion P1, a second portion P2, and a first pad 71. The first pad 71 is continuously disposed with respect to the first portion P1. The first pad 71 is continuously disposed with respect to the second portion P2. The first portion P1 and the second portion P2 are continuous, with the first pad 71 inserted between them. The first portion P1 is a part surrounding the outer periphery 53LA of the emitter electrode 52. The first portion P1 and the second portion P2 are located in the positive direction of the second direction D2 relative to the first pad 71. The first portion P1 extends from the first pad 71 in the positive direction of the second direction D2. The third portion P3 of the emitter electrode 52 is located in the positive direction of the second direction D2 relative to the first pad 71. The third portion P3 is located on the same side as the first portion P1 and the second portion P2 in the same direction relative to the first pad 71. In the first direction D1, the third portion P3 is located between the first portion P1 and the second portion P2.

[0094] Figure 9 This is a schematic plan view showing a semiconductor device according to a second variation of the embodiment.

[0095] Figure 10 It is along Figure 9 The cross-sectional view taken from line HH.

[0096] like Figure 9 and Figure 10As shown, the semiconductor device 102 includes a gate metal layer 53L and an emitter electrode 52. The gate metal layer 53L includes a first pad 71. The emitter electrode 52 overlaps with at least a portion of the gate metal layer 53L on a third-direction D3.

[0097] A first pad 71 is disposed on the semiconductor component 10M. The first pad 71 is electrically connected to a first portion P1 and a second portion P2. The first pad 71 is connected via an outer periphery 53LA to a wiring 53LB that includes the first portion P1 and the second portion P2. The first pad 71 is, for example, a gate pad.

[0098] The gate metal layer 53L includes a first portion P1 and a second portion P2. The first portion P1 extends along a second direction D2.

[0099] Semiconductor device 102 may include a second pad 72. The second pad 72 is disposed on semiconductor component 10M. The second pad 72 is insulated from gate metal layer 53L. The second pad 72 is, for example, a temperature sensing pad, a multi-gate gate pad, or a current sensing pad.

[0100] The gate metal layer 53L includes a fifth portion P5 connected to the first portion P1 and extending in a first direction D1. The gate metal layer 53L also includes a sixth portion P6 connected to the fifth portion P5 and the outer periphery 53LA and extending in a second direction D2. A second portion P2 is connected to the fifth portion P5 and is disposed at a position opposite to the sixth portion P6. A second pad 72 is adjacent to and insulated from both the fifth portion P5 and the sixth portion P6.

[0101] Figure 10 It shows along Figure 9 The cross-section is taken by line HH. Insulator 85 includes a second insulating film 85c and a third insulating film 85d. The second insulating film 85c is disposed on the semiconductor device 10M. Gate metal layer 53L is disposed on the second insulating film 85c. The third insulating film 85d is disposed on the gate metal layer 53L to cover the gate metal layer 53L. Emitter electrode 52 is disposed on the semiconductor device 10M and the second insulating film 85c.

[0102] The gate metal layer 53L is insulated from the semiconductor component 10M and the emitter electrode 52 by the second insulating film 85c and the third insulating film 85d. The semiconductor component 10M, the second insulating film 85c, the gate metal layer 53L, the third insulating film 85d, and a portion of the emitter electrode 52 are arranged sequentially along the third direction D3.

[0103] exist Figure 10In this configuration, the portion of the emitter electrode 52 located in the first direction D1 between the second insulating film 85c and the third insulating film 85d surrounding the first portion P1, and between the second insulating film 85c and the third insulating film 85d surrounding the second portion P2, is referred to as the third portion P3. The third portion P3 is located in the first direction D1 between the first portion P1 and the second portion P2.

[0104] Note that the configuration shown as the second variation can also be applied. Figure 7 The layout shown. That is to say, in Figure 7 In, similar to Figure 9 The wiring 53LB of the gate metal layer 53L can be disposed below the emitter electrode 52.

[0105] Semiconductor devices 100, 101 and 102 can be applied to semiconductor devices that include pads, such as temperature sensing pads, multi-gate gate pads or current sensing pads.

[0106] According to this embodiment, a semiconductor device 100 capable of preventing RBSOA reduction can be provided.

[0107] In the foregoing, exemplary embodiments of the present invention have been described with reference to specific examples. However, embodiments of the present invention are not limited to these specific examples. For example, those skilled in the art can similarly practice the present invention by appropriately selecting specific configurations of components included in a semiconductor device (e.g., semiconductor components 10M, electrodes, conductive parts, insulating parts, etc. from known technologies). Such practices are included within the scope of the present invention and achieve similar effects.

[0108] Furthermore, any two or more components of a particular example may be combined to the extent technically feasible and are included within the scope of this invention, including the scope of protection of this invention.

[0109] Furthermore, all semiconductor devices that can be made by appropriate design modifications based on the above-described semiconductor devices as embodiments of the present invention are also within the scope of the present invention, as long as they include the protected portion of the present invention.

[0110] Within the spirit of this invention, various other variations and modifications will be conceived by those skilled in the art, and it should be understood that such variations and modifications are also included within the scope of this invention.

[0111] While certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. In fact, the novel embodiments described herein can be embodied in various other forms; furthermore, various omissions, substitutions, and changes can be made to the forms of the embodiments described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover these forms or variations that fall within the scope and spirit of the invention.

Claims

1. A semiconductor device comprising: Semiconductor components; A gate metal layer, comprising a first portion and a second portion; A first gate electrode extends along a first direction from the first portion toward the second portion, and the first gate electrode is connected to the gate metal layer in the first portion; as well as An emitter electrode is disposed on the semiconductor component and includes a third portion and a fourth portion, the emitter electrode being electrically connected to the semiconductor component in the third portion and the fourth portion, and the second portion being located between the third portion and the fourth portion in the first direction.

2. The semiconductor device according to claim 1, wherein, The third part is located between the first part and the second part in the first direction.

3. The semiconductor device according to claim 1, wherein, The gate metal layer further includes a first pad disposed on the semiconductor component, and The first pad is connected to the first portion and the second portion.

4. The semiconductor device according to claim 3, wherein, The gate metal layer includes: The outer periphery surrounding the emitter electrode; and Wiring connecting the opposite sides of the outer perimeter; and The first portion and the second portion are included in the wiring.

5. The semiconductor device according to claim 3, wherein, The first portion and the second portion are continuous, the first pad is inserted between the first portion and the second portion, and the third portion is located on the same side as the first portion and the second portion relative to the first pad.

6. The semiconductor device according to claim 3, wherein, The gate metal layer faces the semiconductor component and the emitter electrode, an insulating film is inserted between the gate metal layer and the emitter electrode, and the semiconductor component, the insulating film, the gate metal layer, the insulating film and the emitter electrode are stacked in sequence.

7. The semiconductor device according to claim 1, wherein, The emitter electrode includes an emitter contact that contacts the semiconductor component. At least a portion of the emitter contact extends along the first direction, and The emitter contact includes a first emitter contact area disposed in the third part and a second emitter contact area disposed in the fourth part.

8. The semiconductor device according to claim 1, further comprising: The second gate electrode along the first direction, The first length is not less than the second length, the first length is the length of the second portion along the second direction intersecting the first direction, the second length is the length between the first center and the second center in the second direction, the first center is the center of the first gate electrode in the second direction, and the second center is the center of the second gate electrode in the second direction.

9. The semiconductor device according to claim 1, further comprising: The second gate electrode along the first direction, The direction from the second gate electrode to the first gate electrode follows a second direction that intersects with the first direction. The length of the first gate electrode along the first direction is greater than the length of the second gate electrode along the first direction.

10. The semiconductor device according to claim 1, wherein, The gate metal layer also includes a fifth part. The fifth part is continuous with the first part and the second part, and The direction from the fifth part to the third part intersects with the first direction.

11. The semiconductor device of claim 10, further comprising: Connecting components; The second gate electrode along the first direction; as well as The third gate electrode along the first direction, The first gate electrode, the second gate electrode, and the third gate electrode are arranged sequentially along a second direction intersecting the first direction. The gate metal layer also includes a sixth part. The sixth part is continuous with the fifth part. The direction from the sixth part to the fifth part intersects with the first direction. The connecting component is electrically connected to the sixth part and the third gate electrode.

12. The semiconductor device of claim 10, wherein... The first portion and the fifth portion form the L-shaped portion of the gate metal layer.

13. The semiconductor device of claim 10, wherein The gate metal layer also includes a sixth part. The fifth portion, the second portion, and the sixth portion form the T-shaped portion of the gate metal layer.

14. The semiconductor device according to claim 3, further comprising: The second pad is disposed on the semiconductor component. The second pad is insulated from the gate metal layer.

15. The semiconductor device according to claim 14, wherein, The gate metal layer also includes a fifth part. The fifth part is continuous with the first part and the second part, and The fifth portion is located between the second pad and the third portion in a second direction intersecting the first direction.

16. The semiconductor device according to claim 14, wherein, The second pad is a temperature sensing pad.

17. The semiconductor device according to claim 14, wherein, The second pad is a current sensing pad.

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