Trench shield gate device and method of forming the same

Abstract

The application provides a trench shield gate device and a forming method thereof. In the forming method, a hard mask layer is first formed on a substrate, and the material of the hard mask layer is silicon oxide; then a trench is formed, the trench extends from the top surface of the substrate to the substrate; then a shield gate and an isolation material layer are sequentially formed, the shield gate is located at the bottom of the trench, and the isolation material layer is located on the shield gate and fills the trench and extends to the hard mask layer; then a chemical mechanical polishing process is performed to stop at the top surface of the substrate; then an etching process is performed to etch part of the isolation material layer in the trench, and the remaining isolation material layer constitutes an isolation layer. In the application, the hard mask layer is a pure silicon oxide layer, and a layer of silicon nitride is not needed as an etching stop layer of the chemical mechanical polishing process, so that the falling of the silicon nitride is avoided, the short circuit of the gate and the source caused by the etching residue of the gate polysilicon is avoided, and the isolation material layer can be directly stopped on the silicon substrate, so that the poor etching uniformity of the isolation material layer is solved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a trench-type shielding gate device and a method for forming the same. Background Technology

[0002] In the gate structure of a shielded gate trench (SGT) device, source polysilicon is introduced into the gate trench as a shielding structure. In the top and bottom structure, the source polysilicon is usually located at the bottom of the polysilicon gate, and an inter-polysilicon oxide (IPO) layer is needed to isolate the source polysilicon and the polysilicon gate. The source polysilicon is usually connected to the source, and the polysilicon gate is connected to the gate. Therefore, introducing an inter-polysilicon oxide layer between the polysilicon gate and the source polysilicon can provide sufficient and effective isolation protection between the gate and the source.

[0003] High-density plasma chemical vapor deposition (HDP CVD) has rapidly become one of the mainstream processes for SGT IPO formation due to its excellent pore-filling ability, stable deposition quality, and reliable electrical characteristics.

[0004] In the HDP CVD process, physical bombardment is performed during deposition. Physical bombardment has an etching effect. After the insulating dielectric oxide layer is filled, there will be sharp corners on the film surface caused by physical bombardment. Therefore, the HDPCVD process of SGT IPO usually uses chemical mechanical polishing (CMP) to planarize the surface in order to improve the surface morphology and the uniformity of IPO within the wafer.

[0005] The trench hard mask of the HDP-CMP SGT product uses an ONO (Oxide-SiN-Oxide) structure, primarily intended to provide a stop layer in the subsequent CMP (Chemical Mechanical Polishing) process. However, after IPO wet etching, hairline-like defects were observed, which can lead to IGSS (gate-source leakage current) failure at the wafer periphery in severe cases. The HDP-CMP solution causes SIN peeling during IPO Oxide wet etching, resulting in subsequent Gate Polyetch residue and leading to GS short (gate and source short circuit). Summary of the Invention

[0006] The purpose of this invention is to provide a trench-type shielded gate device and its formation method to solve the problem that the side-penetration during wet etching of the oxide layer between polysilicon leads to silicon nitride shedding, resulting in residual polysilicon etching on the gate and thus short circuit between the gate and the source.

[0007] To solve the above-mentioned technical problems, the present invention provides a method for forming a trench-type shielding gate device, comprising:

[0008] Provide a substrate;

[0009] A patterned hard mask layer is formed, the patterned hard mask layer covering a portion of the substrate and exposing the trench definition region of the substrate, and the material of the patterned hard mask layer is silicon oxide;

[0010] A trench is formed, the trench extending from the top surface of the substrate into the substrate;

[0011] A shielding grid is formed, the shielding grid being located at the bottom of the trench;

[0012] An isolation material layer is formed on the shielding grid and fills the trench and extends to the patterned hard mask layer;

[0013] Perform a chemical mechanical polishing process to stop the process on the top surface of the substrate;

[0014] An etching process is performed to etch a portion of the isolation material layer within the trench, leaving the remaining isolation material layer as the isolation layer.

[0015] Optionally, the thickness of the patterned hard mask layer is 2,500 angstroms to 5,000 angstroms.

[0016] Optionally, the polishing solution in the chemical mechanical polishing process includes cerium oxide.

[0017] Optionally, the material of the insulating material layer is silicon oxide.

[0018] Optionally, the insulating material layer may be formed using a high-density plasma chemical vapor deposition process.

[0019] Optionally, the etching process is a wet etching process.

[0020] Optionally, prior to the step of forming the shielding grid, a field oxide layer is formed, which covers the bottom and sidewalls of the trench.

[0021] Optionally, the steps for forming the shielding barrier include:

[0022] A shielding gate material layer is formed, which is located on the field oxide layer, fills the trench, and extends to the patterned hard mask layer;

[0023] An etching process is performed to etch the shielding gate material layer to a target depth, and the remaining shielding gate material layer in the trench constitutes the shielding gate.

[0024] Optionally, the material of the shielding gate is polycrystalline silicon.

[0025] Based on the same inventive concept, the present invention provides a trench-type shielding gate device, which is prepared by the method for forming a trench-type shielding gate device described in any of the above claims.

[0026] In a method for forming a trench-type shielded gate device provided by this invention, a patterned hard mask layer is first formed on a substrate, the patterned hard mask layer being made of silicon oxide; then, a trench is formed, extending from the top surface of the substrate into the substrate; next, a shielded gate and an isolation material layer are formed sequentially, the shielded gate being located at the bottom of the trench; the isolation material layer is located on the shielded gate and fills the trench and extends onto the patterned hard mask layer; then, a chemical mechanical polishing (CMP) process is performed to stop the etching on the top surface of the substrate; then, an etching process is performed to etch part of the isolation material layer within the trench, the remaining isolation material layer constituting the isolation layer. The hard mask layer in this invention uses a pure silicon oxide layer, eliminating the need for a silicon nitride layer as an etching stop layer for the CMP process, preventing silicon nitride detachment, avoiding gate and source short circuits caused by residual polysilicon etching, and allowing the etching to stop directly on the silicon substrate, thus solving the problem of poor etching uniformity of the isolation material layer. Attached Figure Description

[0027] Figure 1 This is a flowchart of a method for forming a trench-type shielding gate device according to an embodiment of the present invention.

[0028] Figures 2 to 8 This is a structural diagram corresponding to the steps of forming a trench-type shielding gate device according to an embodiment of the present invention.

[0029] in, Figure 2 This is a schematic diagram of the substrate structure of the trench-type shielding gate device according to an embodiment of the present invention.

[0030] Figure 3 This is a schematic diagram of the structure of the trench-type shielding gate device after forming a patterned hard mask layer according to an embodiment of the present invention.

[0031] Figure 4 This is a schematic diagram of the structure of the trench-type shielding gate device after the trench is formed according to an embodiment of the present invention.

[0032] Figure 5 This is a schematic diagram of the structure of the trench-type shielding gate device after the formation of the field oxide layer according to an embodiment of the present invention.

[0033] Figure 6This is a schematic diagram of the structure of the trench-type shielding gate device after the formation of the isolation material layer according to an embodiment of the present invention.

[0034] Figure 7 This is a schematic diagram of the structure of the trench-type shielding gate device after performing a chemical mechanical polishing process according to an embodiment of the present invention.

[0035] Figure 8 This is a schematic diagram of the structure of the trench-type shielding gate device after the formation of the isolation layer according to an embodiment of the present invention.

[0036] In the picture:

[0037] 10-Substrate; 11-Patterned hard mask layer; 12-Wafer perimeter retaining ring; 13-Trench; 14-Field oxide layer; 15-Shielding gate; 16-Isolation material layer; 16a-Isolation layer. Detailed Implementation

[0038] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the present application. Repeated reference numerals may be used in the various embodiments; these repeated reference numerals are for simplicity and clarity only and do not indicate a relationship between the various embodiments.

[0039] Furthermore, in this application, spatial relationship terms such as "below," "under," "above," and "over" can be used to describe the relationship between one element and another in the accompanying drawings. In addition to the orientations shown in the drawings, these spatial relationship terms may also include different orientations of the device / structure during use (e.g., rotation of 90 degrees). The interpretation of the aforementioned spatial relationship terms should be adjusted accordingly for these different orientations.

[0040] In the description of this application, the term "connection" or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. For example, in this application, the formation of a first feature over a second feature can include direct or indirect contact between the first and second features.

[0041] In the embodiments described in this application, the term "about" or a term with an equivalent meaning can refer to a given number of values ​​that vary within, for example, 10% of the value. It is understood that for numerical values ​​not defined by terms such as "about" in this application, the numerical value may also have a certain range of fluctuation, provided that the desired technical effect of the embodiments of this application can be achieved, and the numerical values ​​described in the embodiments are merely exemplary.

[0042] Figure 1 This is a flowchart illustrating the method for forming a trench-type shielding gate device according to an embodiment of the present invention. Figure 1As shown, the present invention provides a method for forming a trench-type shielding gate device, comprising:

[0043] Step S10: Provide a substrate;

[0044] Step S20: A patterned hard mask layer is formed, the patterned hard mask layer covering a portion of the substrate and exposing the trench definition area of ​​the substrate, and the material of the patterned hard mask layer is silicon oxide;

[0045] Step S30: Forming a trench that extends from the top surface of the substrate into the substrate;

[0046] Step S40: Form a shielding grid, the shielding grid being located at the bottom of the trench;

[0047] Step S50: Form an isolation material layer, the isolation material layer being located on the shielding grid and filling the trench and extending to the patterned hard mask layer;

[0048] Step S60: Perform a chemical mechanical polishing process to stop the process on the top surface of the substrate;

[0049] Step S70: Perform an etching process to etch a portion of the isolation material layer within the trench, leaving the remaining isolation material layer as the isolation layer.

[0050] Figures 2 to 8 This is a structural diagram corresponding to the steps of forming a trench-type shielding gate device according to an embodiment of the present invention. To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the following description is provided in conjunction with the appendix to the specification. Figures 2 to 8 Specific embodiments of the present invention will be described in detail below.

[0051] Figure 2 This is a schematic diagram of the substrate structure of the trench-type shielding gate device according to an embodiment of the present invention. Figure 2 As shown, a substrate 10 is provided. The substrate 10 provides an operating platform for subsequent processes. It can be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components. It can be a bare die or a wafer processed by epitaxial growth. Specifically, the substrate 10 is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium-silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate, etc. In this embodiment, the substrate 10 is a silicon substrate.

[0052] Figure 3 This is a schematic diagram of the structure of a trench-type shielding gate device after forming a patterned hard mask layer according to an embodiment of the present invention. Figure 3As shown, a patterned hard mask layer 11 is formed, which covers a portion of the substrate 10 and exposes the substrate 10 in the trench definition region. The patterned hard mask layer 11 is made of silicon oxide. The steps of forming the patterned hard mask layer 11 include: first, forming the hard mask layer 11 to cover the substrate 10. The thickness of the hard mask layer is, for example, 2500 angstroms to 5000 angstroms. Then, photolithography and etching processes are used to pattern the hard mask layer 11 to expose the substrate 10 in the trench definition region. Before forming the trench, a wafer peripheral ring 12 is placed on the patterned hard mask layer 11. The peripheral ring 12 shields the edge of the substrate 10 to ensure the consistency of the substrate edge etching and avoid short circuits between the shield gate and the gate edge.

[0053] Figure 4 This is a schematic diagram of the structure of the trench-type shielding gate device after the trenches are formed, according to an embodiment of the present invention. Figure 4 As shown, trench 13 is formed, extending from the top surface of substrate 10 into substrate 10. Trench 13 is formed using a dry etching process. In the dry etching process, the exposed substrate 10 is etched using a patterned hard mask layer 11 as a mask to form trench 13.

[0054] Figure 5 This is a schematic diagram of the structure of a trench-type shielding gate device after the formation of a field oxide layer according to an embodiment of the present invention. Figure 5 As shown, prior to the step of forming the shielding gate, a field oxide layer 14 is formed, which covers the bottom and sidewalls of the trench 13. The field oxide layer 14 is formed using a thermal oxidation process, and the material of the field oxide layer 14 is, for example, silicon oxide. The thermal oxidation process oxidizes the bottom and sidewalls of the trench 13, which have etch interface damage, into silicon oxide to repair the interface damage of the bottom and sidewalls of the trench 13 and to serve as an insulating layer for the electrical isolation shielding gate and the trench.

[0055] Figure 6 This is a schematic diagram of the structure of the trench-type shielding gate device after the formation of the isolation material layer according to an embodiment of the present invention. Figure 6 As shown, a shielding gate 15 is formed, located at the bottom of the trench 13. The material of the shielding gate 15 is, for example, polysilicon. The steps of forming the shielding gate 15 include: first forming a shielding gate material layer, which is located on the field oxide layer 14, fills the trench 13, and extends to the patterned hard mask layer 11; then performing an etching process to etch the shielding gate material layer to a target depth, the remaining shielding gate material layer in the trench 13 constituting the shielding gate 15, the etching process being, for example, a dry etching process, and the target depth being the height of the shielding gate 15 defined according to the requirements of the trench-type shielding gate device.

[0056] Please continue to refer to this. Figure 6An isolation material layer 16 is formed on the shielding gate 15 and fills the trench 13 and extends to the patterned hard mask layer 11. The material of the isolation material layer 16 may be silicon oxide, and the isolation material layer 16 is formed by a high-density plasma chemical vapor deposition (HDP CVD) process.

[0057] Figure 7 This is a schematic diagram of the structure of the trench-type shielding gate device after undergoing a chemical mechanical polishing process according to an embodiment of the present invention. Figure 7 As shown, a chemical mechanical polishing (CMP) process is performed to stop at the top surface of substrate 10. The polishing slurry in the CMP process includes cerium oxide (CeO2). The polishing rate of cerium oxide on silicon oxide is much greater than that on silicon, therefore, the CMP process can stop at the top surface of substrate 10. If the CMP process stops on silicon oxide, the stopping time can only be controlled by the polishing duration. In other words, the CMP process cannot stop on silicon oxide, resulting in variations in the thickness of the silicon oxide on the surface. Consequently, during subsequent wet etching of the isolation material layer, the thickness range of the isolation material layer will increase, leading to poor etching uniformity. In this embodiment, the CMP process stops at the top surface of substrate 10, avoiding the problem of poor etching uniformity of the isolation material layer. Furthermore, in this embodiment, the hard mask layer uses pure silicon oxide, avoiding the problem of silicon nitride detachment during wet etching, which could cause residual polysilicon etching at the gate and lead to a short circuit between the gate and source. In this embodiment, pure silicon oxide is used as the hard mask layer, and the chemical mechanical polishing process stops at the top surface of the substrate, which improves the etching uniformity of the isolation material layer and improves the yield of the trench-type shielding gate device.

[0058] Figure 8 This is a schematic diagram of the trench-type shielding gate device after the formation of the isolation layer according to an embodiment of the present invention. Figure 8 As shown, an etching process is performed to etch a portion of the isolation material layer within the trench, leaving the remaining isolation material layer to form isolation layer 16a. The etching process is a wet etching process.

[0059] Please continue to refer to this. Figure 8 The present invention also provides a trench-type shielding gate device, which is prepared by the method for forming a trench-type shielding gate device described in any one of the above claims, comprising:

[0060] Substrate 10;

[0061] The trench extends from the top surface of the substrate 10 into the substrate;

[0062] Field oxide layer 14 covers the bottom and sidewalls of the trench;

[0063] The shielding grid 15 is located at the bottom of the trench and on the field oxide layer 14;

[0064] An isolation layer 16a is located on the shielding gate 15 and is used to isolate the shielding gate 15 from the gate that is subsequently formed.

[0065] In summary, in the method for forming a trench-type shielded gate device provided in this embodiment of the invention, a patterned hard mask layer is first formed on a substrate, the material of which is silicon oxide; then, a trench is formed, extending from the top surface of the substrate into the substrate; next, a shielded gate and an isolation material layer are formed sequentially, the shielded gate being located at the bottom of the trench; the isolation material layer is located on the shielded gate and fills the trench and extends to the patterned hard mask layer; then, a chemical mechanical polishing (CMP) process is performed to stop the etching on the top surface of the substrate; then, an etching process is performed to etch part of the isolation material layer within the trench, the remaining isolation material layer constituting the isolation layer. The hard mask layer in this invention uses a pure silicon oxide layer, eliminating the need for a silicon nitride layer as an etching stop layer for the CMP process, preventing silicon nitride detachment, avoiding gate and source short circuits caused by residual polysilicon etching, and allowing the etching to stop directly on the silicon substrate, thus solving the problem of poor etching uniformity of the isolation material layer.

[0066] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.

[0067] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for forming a trench-type shielding gate device, characterized in that, include: Provide a substrate; A patterned hard mask layer is formed, the patterned hard mask layer covering a portion of the substrate and exposing the trench definition region of the substrate, and the material of the patterned hard mask layer is silicon oxide; A trench is formed, the trench extending from the top surface of the substrate into the substrate; A shielding grid is formed, the shielding grid being located at the bottom of the trench; An isolation material layer is formed on the shielding grid, filling the trenches and extending to the patterned hard mask layer. ； Perform a chemical mechanical polishing process to stop the process on the top surface of the substrate; An etching process is performed to etch a portion of the isolation material layer within the trench, leaving the remaining isolation material layer as the isolation layer.

2. The method for forming the trench-type shielding gate device as described in claim 1, characterized in that, The thickness of the patterned hard mask layer is 2,500 to 5,000 angstroms.

3. The method for forming the trench-type shielding gate device as described in claim 1, characterized in that, The polishing solution in the chemical mechanical polishing process includes cerium oxide.

4. The method for forming the trench-type shielding gate device as described in claim 1, characterized in that, The material of the insulating material layer is silicon dioxide.

5. The method for forming the trench-type shielding gate device as described in claim 4, characterized in that, The isolation material layer is formed using a high-density plasma chemical vapor deposition process.

6. The method for forming the trench-type shielding gate device as described in claim 1, characterized in that, The etching process is a wet etching process.

7. The method for forming the trench-type shielding grid device as described in claim 1, characterized in that, Prior to the step of forming the shielding grid, a field oxide layer is formed, which covers the bottom and sidewalls of the trench.

8. The method for forming the trench-type shielding gate device as described in claim 7, characterized in that, The steps to form a shielding barrier include: A shielding gate material layer is formed, which is located on the field oxide layer, fills the trench, and extends to the patterned hard mask layer; An etching process is performed to etch the shielding gate material layer to a target depth, and the remaining shielding gate material layer in the trench constitutes the shielding gate.

9. The method for forming the trench-type shielding gate device as described in claim 8, characterized in that, The material of the shielding grid is polycrystalline silicon.

10. A trench-type shielding grid device, characterized in that, It is prepared by the method for forming a trench-type shielding gate device as described in any one of claims 1 to 9.

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