A nitride semiconductor device and a method of manufacturing the same

Abstract

This application relates to semiconductor device technology and discloses a nitride semiconductor device and its manufacturing method, including a nitride substrate, a barrier layer, a source electrode, a drain electrode, a gate structure, and a strain-adjustable dielectric layer. The barrier layer is located above the nitride substrate. The gate structure is disposed on the barrier layer between the source electrode and the drain electrode, and includes a multilayer nitride stack structure. The multilayer nitride stack structure includes at least two P-type nitride layers and at least one etch stop layer sandwiched between the P-type nitride layers. The projection of the upper P-type nitride layer onto the surface of the barrier layer is within the projection range of the lower P-type nitride layer onto the surface of the barrier layer, and the lower P-type nitride layer extends horizontally towards the drain electrode, forming a stepped structure towards the drain electrode. The strain-adjustable dielectric layer covers the surface and is used to adjust the electric field density in the gate structure region and the gate-drain region. This application can improve the problem of electric field concentration in the gate structure region and the gate-drain region.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a nitride semiconductor device and a method for manufacturing the same. Background Technology

[0002] Group III nitride semiconductor materials (such as gallium nitride, GaN) and their heterojunction structures exhibit great application potential in high-frequency and high-voltage power electronics due to their excellent properties such as wide bandgap, high critical breakdown electric field, and high electron saturation drift velocity. High electron mobility transistors (HEMTs) based on AlGaN / GaN heterojunctions can form a high-concentration, high-mobility two-dimensional electron gas (2DEG) at their interface, enabling low on-resistance and high switching speeds, making them a primary choice for power devices.

[0003] In the fabrication of HEMT devices, gate structure design and etching process control are crucial. In existing technologies, to avoid damage to the bottom AlGaN barrier layer during gate structure etching and to improve the uniformity of GaN spacer thickness, Chinese patent application CN110754001A proposes a stacked structure using a P-type GaN layer and an aluminum group III nitride etching termination layer. This structure employs a dual process of etching and non-selective etching to retain a uniformly thick GaN layer above the barrier layer. However, this approach only focuses on etching process optimization and neglects the electric field distribution in the gate-drain region during high-voltage operation, leading to the risk of electric field concentration even at high voltages.

[0004] Meanwhile, regarding the reliability issue of the gate structure in enhancement-mode HEMTs, Chinese patent application CN113728419A discloses a method to reduce the internal electric field strength of the gate structure, decrease leakage current, and increase the rated voltage of the forward gate structure by thickening the P-type gate structure layer and optimizing the impurity concentration distribution. However, this solution mainly optimizes the voltage stability of the gate structure itself and does not address the electric field modulation between the gate structure and the drain. Under high-voltage conditions, the electric field at the edge of the gate structure (especially near the drain) and the edge of the drain will still be significantly concentrated due to structural abrupt changes, which can easily lead to degradation effects such as hot carrier injection and current collapse, limiting the maximum operating voltage and long-term reliability of the device.

[0005] To balance on-resistance and electric field distribution, some solutions, such as Chinese patent application CN120730769A, attempt to set a periodic trench structure between the gate and drain. This reduces on-resistance by increasing the current path area and optimizes the electric field using trench filling materials. However, this type of solution relies on the vertical trench physical structure, resulting in limited electric field optimization. Furthermore, without incorporating strain control mechanisms, it is difficult to fundamentally alleviate the electric field concentration problem under high voltage, thus limiting the potential for improving device breakdown voltage and reliability.

[0006] In response to the aforementioned issues, group III nitride-based HEMT devices suffer from problems such as concentrated electric field in the gate-drain region, low breakdown voltage, and poor long-term reliability when operating at high voltage. There is an urgent need for a technical solution that can regulate the channel electric field distribution and synergistically optimize the gate structure and strain state to overcome the performance bottleneck of existing devices. Summary of the Invention

[0007] To address the aforementioned technical problems, this application provides a nitride semiconductor device and a method for manufacturing the same.

[0008] Firstly, the nitride semiconductor device provided in this application adopts the following technical solution: A nitride semiconductor device includes a nitride substrate; a barrier layer is located above and in contact with the nitride substrate, and a two-dimensional electron gas is formed on the contact surface; a source electrode and a drain electrode are spaced apart on the barrier layer; a gate structure is disposed on the barrier layer, located between the source electrode and the drain electrode, and includes a multilayer nitride stack structure and a metal gate electrode formed on the upper surface of the nitride stack structure; the multilayer nitride stack structure includes at least two P-type nitride layers and at least one etch stop layer sandwiched between the P-type nitride layers; in the multilayer nitride stack structure, the gate electrode is disposed between the source electrode and the drain electrode. The P-type nitride layer of the contact metal gate electrode is defined as the upper P-type nitride layer, and the P-type nitride layer of the contact barrier layer is defined as the lower P-type nitride layer. The projection of the upper P-type nitride layer onto the surface of the barrier layer is located within the projection range of the lower P-type nitride layer onto the surface of the barrier layer, and the lower P-type nitride layer extends horizontally towards the drain electrode, so that the multilayer nitride stack structure forms a stepped structure towards the drain electrode. The strain-adjusting dielectric layer covers the surface of the barrier layer between the source electrode and the drain electrode and is used to adjust the electric field density of the gate structure region and the gate-drain region.

[0009] By adopting the above technical solution, the stepped gate structure extends towards the drain side through the lower P-type nitride layer, which can smooth the structural abrupt change in the gate-drain region and weaken the electric field concentration effect. The strain-adjustable dielectric layer applies strain force through direct contact with the barrier layer to adjust the 2DEG concentration, further optimizing the electric field distribution at the edge of the gate structure and near the drain. The two work synergistically to alleviate electric field peaks, reduce hot carrier injection and current collapse, and improve the breakdown voltage and long-term reliability of the device. In addition, the etch stop layer can control the etching depth during the manufacturing process, ensuring the formation of the stepped structure while preventing damage to the barrier layer and ensuring the stability of device performance.

[0010] Optionally, the nitride semiconductor device further includes a nitride isolation layer, which is disposed between the barrier layer and the multilayer nitride stack structure and is continuously distributed along the extension direction of the barrier layer to block the diffusion of P-type doped impurities into the barrier layer.

[0011] By adopting the above technical solution, the nitride isolation layer can prevent the diffusion of doped impurities in the upper P-type nitride layer to the barrier layer, prevent the performance of the barrier layer from deteriorating, ensure the high concentration and high mobility of 2DEG, and further improve the conduction performance and stability of the device.

[0012] Optionally, the thickness d2 of the lower P-type nitride layer is less than the thickness d1 of the upper P-type nitride layer, and the average doping concentration of the lower P-type nitride layer is less than the average doping concentration of the upper P-type nitride layer.

[0013] By adopting the above technical solution, the differentiated design of thickness and doping concentration not only ensures that the upper P-type nitride layer and the metal gate electrode form a stable Schottky contact, but also reduces the impact on the channel 2DEG through the design of low doping and thin thickness of the lower layer, thus taking into account both the gate structure control capability and the device conduction performance.

[0014] Optionally, the multilayer nitride stacked structure forms a stepped structure toward the drain electrode, and the lower P-type nitride layer extends horizontally toward the source electrode side, wherein the extension length toward the drain electrode side is greater than the extension length toward the source electrode side, forming an asymmetric extension structure.

[0015] By adopting the above technical solutions, the longer extension on the drain side can smooth the structural abrupt change between the gate and drain, disperse the electric field peak, weaken the electric field concentration effect, and achieve the effect of improving the breakdown voltage; the shorter extension on the source side can smooth the structural transition of the gate-source region, alleviate interlayer stress concentration and local electric field abrupt change, and reduce the risk of device breakdown; at the same time, it will not excessively increase the equivalent resistance of the gate-source channel, thus ensuring the control of the channel by the gate structure while improving the breakdown voltage and preventing the increase of the on-resistance.

[0016] Optionally, the nitride substrate is a GaN substrate, the barrier layer is an AlGaN layer, and the band gap of the barrier layer is greater than the band gap of the nitride substrate; the etching stop layer is made of a P-type doped aluminum nitride material, which includes at least one of AlGaN, AlN, or AlInGaN.

[0017] By adopting the above technical solutions, GaN / AlGaN heterojunctions can form 2DEGs with high concentration and high mobility, ensuring low on-resistance characteristics of the devices; the etching termination layer made of aluminum nitride material has significant etching selectivity with the upper and lower P-type nitride layers, which facilitates accurate control of etching depth during manufacturing and prevents damage to the barrier layer.

[0018] Optionally, the etching termination layer is a P-type AlGaN superlattice structure, consisting of multiple alternating AlGaN thin layers, with the Al element content increasing in a gradient along the direction close to the barrier layer.

[0019] By adopting the above technical solution, the etch stop layer of this superlattice structure exhibits superior etch selectivity and structural stability. The Al content gradually increases along the direction close to the barrier layer, which not only allows the etch stop layer to achieve good lattice matching with the upper P-type nitride layer, ensuring efficient transport of P-type doped carriers, but also enhances the etch resistance of the lower region, strengthens the protective effect of etch stop, and optimizes the interface compatibility with the lower structure, further improving the reliability of the gate structure.

[0020] Optionally, the material of the strain-adjusting dielectric layer includes at least one of AlN or AlGaN, the thickness of the strain-adjusting dielectric layer is 1nm-10nm, and the thickness of the strain-adjusting dielectric layer increases in a gradient along the direction from the gate structure to the drain electrode.

[0021] By adopting the above technical solutions, strain-adjustable dielectric layers with specific materials and thickness ranges can provide suitable strain forces. The thickness gradient design can specifically enhance the electric field adjustment effect in the gate-drain region, better smooth the electric field distribution, and improve the device's withstand voltage performance.

[0022] Optionally, the source electrode and drain electrode are disposed on the upper surface of the barrier layer and are in direct contact with the barrier layer, or the source electrode and drain electrode are disposed on the upper surface of the strain-adjusting dielectric layer and are connected to the barrier layer through the strain-adjusting dielectric layer.

[0023] By adopting the above technical solution, two electrode mounting methods are supported, which can be flexibly selected according to the application scenario and performance requirements of the device, thereby improving design flexibility and process compatibility, while ensuring reliable conduction between the electrode and the barrier layer.

[0024] Optionally, the metal gate electrode forms a Schottky contact with the multilayer nitride stack structure, and the materials of the metal gate electrode, source electrode, and drain electrode include at least one of Ni, Au, or Ti.

[0025] By adopting the above technical solutions, Schottky contacts can improve the switching speed and control accuracy of the gate structure. The selected metal material has good conductivity and stability, ensuring long-term reliable connection between the electrode and the device.

[0026] Secondly, the manufacturing method of a nitride semiconductor device provided in this application adopts the following technical solution: A method for manufacturing a nitride semiconductor device includes the following steps: S1, providing a nitride substrate; S2, forming a barrier layer above the nitride substrate, such that the barrier layer contacts the nitride substrate to form a two-dimensional electron gas at the contact surface; S3, sequentially depositing multiple nitride stacks on the barrier layer, wherein the multiple nitride stacks include at least two P-type nitride layers and at least one etch stop layer sandwiched between the P-type nitride layers; S4, forming a metal gate electrode layer on the upper surface of the multiple nitride stacks, and etching the metal gate electrode layer and the multiple nitride stacks. S5. A nitride stack is formed, such that the horizontal projection size of the P-type nitride layer away from the barrier layer is smaller than that of the P-type nitride layer near the barrier layer, and the P-type nitride layer near the barrier layer extends horizontally towards the drain region to form a stepped gate structure toward the drain region; S6. A strain-adjustable dielectric layer is deposited, such that the strain-adjustable dielectric layer at least covers the gate structure region and the gate-drain region; S7. Metal is deposited and patterned to form the source electrode and the drain electrode, such that the source electrode and the drain electrode are located on opposite sides of the gate structure and are electrically connected to the barrier layer.

[0027] By adopting the above technical solution, the integration of various functional structures of the device is precisely achieved through the step-by-step formation of heterojunctions, stepped gate structures, electrodes, and strain-adjustable dielectric layers. Utilizing the etch selectivity of the etch stop layer, the stepped morphology of the gate structure stack can be controlled, preventing damage to the barrier layer. This process offers strong controllability, good compatibility with traditional nitride semiconductor manufacturing processes, and is beneficial for improving product yield and mass production capabilities.

[0028] In summary, this application includes at least one of the following beneficial technical effects: 1. To alleviate the problem of electric field concentration, the electric field distribution in the gate-drain region is optimized through the synergistic effect of the stepped gate structure and the strain-adjustable dielectric layer, thereby improving the breakdown voltage and long-term reliability of the device and reducing hot carrier injection and current collapse. 2. The structure is reasonably designed, taking into account both conduction performance and control precision. Through isolation layers, differentiated doping and thickness design, the 2DEG characteristics and gate structure control capability are guaranteed, and the overall electrical performance of the device is improved. 3. The manufacturing process is highly controllable and has good compatibility with traditional processes. It achieves precise etching with the help of an etching termination layer, reducing manufacturing difficulty and cost, which is conducive to mass production and promotion, and provides reliable device support for high-frequency and high-voltage power electronic devices. Attached Figure Description

[0029] Figure 1 This is a schematic cross-sectional view of the nitride semiconductor device provided in Embodiment 1 of this application; Figure 2 This is a schematic cross-sectional view of the nitride semiconductor device provided in Embodiment 2 of this application; Figure 3This is a schematic cross-sectional view of the nitride semiconductor device provided in Embodiment 3 of this application; Figure 4 This is a schematic cross-sectional view of the nitride semiconductor device provided in Embodiment 4 of this application; Figure 5 This is a schematic cross-sectional view of the nitride semiconductor device provided in Embodiment 5 of this application; Figure 6 This is a flowchart illustrating the manufacturing steps of a nitride semiconductor device provided in an embodiment of this application; Figure 7 In embodiment 3 of this application, corresponding to Figure 6 A schematic cross-sectional view of the initial fabrication state of the gate structure in step S3. Figure 8 In embodiment 3 of this application, corresponding to Figure 6 A schematic diagram of the cross-sectional structure of the gate structure after the initial etching in step S4. Figure 9 In embodiment 3 of this application, corresponding to Figure 6 A schematic diagram of the cross-sectional structure after the lateral etching of the metal gate electrode in step S4. Figure 10 In embodiment 3 of this application, corresponding to Figure 6 A cross-sectional schematic diagram of the formation of the stepped gate structure in step S4.

[0030] 10. Nitride substrate; 20. Barrier layer; 30. Nitride isolation layer; 40. Gate structure; 41. Lower P-type nitride layer; 42. Etch stop layer; 43. Upper P-type nitride layer; 44. Metal gate electrode; 45. Middle P-type nitride layer; 46. Lower etch stop layer; 50. Strain-adjustable dielectric layer; 61. Source electrode; 62. Drain electrode; 70. Mask layer. Detailed Implementation

[0031] The following is in conjunction with the appendix Figure 1-10 This application will be described in further detail.

[0032] In the following description, reference is made to the accompanying drawings, which constitute the illustrative portion of the embodiments of this application and illustrate specific embodiments in which this application can be implemented. For ease of explanation, directional terms such as "top," "bottom," "front," "back," "above," "below," "lateral," and "vertical" are used in the drawings. These terms are used only to indicate positional relationships and do not limit the actual orientation of components, as components in the embodiments may have different locations. It should be understood that other embodiments are possible without departing from the scope of this application, and the structure or logic may be appropriately adjusted. The following description should not be construed as restrictive.

[0033] Furthermore, although the various structures illustrated are typically approximate rectangular, actual devices may exhibit variations in shape, such as curves, rounded corners, or uneven thickness, due to differences in manufacturing processes. The straight lines and right angles in this description are merely for convenience in representing layers and technical features.

[0034] The semiconductor devices and manufacturing methods described below are preferred embodiments. Those skilled in the art will understand that modifications, including the addition or substitution of details, can be made without departing from the scope and spirit of this application. To avoid overly complex descriptions, certain specific details may be omitted, but this does not affect the substantive content of this application, which is intended to enable those skilled in the art to implement this application without excessive experimentation.

[0035] This application provides a nitride semiconductor device, including a nitride substrate 10, a barrier layer 20, a source electrode 61, a drain electrode 62, a gate structure 40, and a strain-modulated dielectric layer 50. The barrier layer 20 is located above and in contact with the nitride substrate 10, and a two-dimensional electron gas (2DEG) is formed on the contact surface. The source electrode 61 and the drain electrode 62 are spaced apart on the barrier layer 20, and the gate structure is disposed on the barrier layer 20, located between the source electrode 61 and the drain electrode 62, including a multilayer nitride stack structure and a metal gate electrode 44 formed on the upper surface of the multilayer nitride stack structure. The multilayer nitride stack structure includes at least two P-type nitride layers and at least one etch stop layer 42 sandwiched between the P-type nitride layers. In the multilayer nitride stack structure, the P-type nitride layer in contact with the metal gate electrode 44 is defined as the upper P-type nitride layer 43, and the P-type nitride layer in contact with the barrier layer 20 is defined as the lower P-type nitride layer 41. The projection of the upper P-type nitride layer 43 onto the surface of the barrier layer 20 lies within the projection range of the lower P-type nitride layer 41 onto the surface of the barrier layer 20, and the lower P-type nitride layer 41 extends horizontally toward the drain electrode 62, forming a stepped structure of the multilayer nitride stack towards the drain electrode 62. A strain-adjustable dielectric layer 50 covers the surface of the barrier layer 20 between the source electrode 61 and the drain electrode 62, and is used to adjust the electric field density of the gate structure region and the gate-drain region.

[0036] Understandably, the stepped gate structure of this application extends towards the drain side through the lower P-type nitride layer, which can smooth the structural abrupt change in the gate-drain region and weaken the electric field concentration effect. The strain-adjustable dielectric layer applies strain force through direct contact with the barrier layer to adjust the 2DEG concentration, further optimizing the electric field distribution at the edge of the gate structure and near the drain. The two work synergistically to alleviate electric field peaks, reduce hot carrier injection and current collapse, and improve the breakdown voltage and long-term reliability of the device. In addition, the etch stop layer can control the etching depth during manufacturing, ensuring the formation of the stepped structure while preventing damage to the barrier layer and ensuring the stability of device performance. Based on the above device structure design, this application provides specific embodiments.

[0037] Example 1

[0038] A nitride semiconductor device is provided, such as Figure 1 The schematic cross-sectional view shown includes a nitride substrate 10, a barrier layer 20, a source electrode 61, a drain electrode 62, a gate structure 40, and a strain-tuning dielectric layer 50. The nitride substrate 10 is a group III nitride material, such as a GaN substrate. The nitride substrate 10 includes, but is not limited to, basic structures for the device's electrical functions, such as a substrate, a nucleation layer, a buffer layer, and a channel layer (not shown in the figure). The barrier layer 20 is made of a group III nitride material, such as an AlGaN layer. The barrier layer 20 is located above and in close contact with the nitride substrate 10, and its bandgap is larger than that of the nitride substrate 10. A heterojunction is formed at the contact surface, and a two-dimensional electron gas (2DEG) is formed near the contact surface. The 2DEG has high mobility characteristics, ensuring low on-resistance characteristics of the device.

[0039] The materials used to fabricate the source electrode 61, drain electrode 62, and metal gate electrode 44 of the gate structure 40 include at least one of Ni, Au, or Ti, and the specific materials can be selected based on the electrode functional requirements, fabrication process compatibility, and device operating conditions. For example, when fabricating the metal gate electrode 44, Ni or Ti can be preferentially selected to optimize the Schottky contact characteristics and improve gate control accuracy; when fabricating the source electrode 61 and drain electrode 62, Au or Ti / Ni composite metals can be selected to reduce ohmic contact resistance and ensure current transmission efficiency.

[0040] It is understandable that Ni, Au, and Ti series metal materials are selected to prepare various electrodes. This can be achieved by relying on the excellent conductivity and chemical stability of these materials, reducing the resistance loss of the electrodes themselves, ensuring the reliability of the contact between the electrodes and adjacent functional layers, and extending the service life of the devices under high temperature and high power operating conditions.

[0041] The gate structure 40 is a P-type Schottky gate structure, consisting of a multilayer nitride stack and a metal gate electrode 44 formed on top. The upper P-type nitride layer 43 is in direct contact with the bottom of the metal gate electrode 44, forming a Schottky contact between them. Specifically, the upper P-type nitride layer 43 is P-type doped GaN, and its thickness is denoted as d1. The lower P-type nitride layer 41 is also P-type doped GaN, and its thickness is denoted as d2. The lower P-type nitride layer 41 is disposed above and in direct contact with the barrier layer 20. In this embodiment, compared to the conventional design, the thickness d2 of the lower P-type nitride layer 41 is less than the thickness d1 of the upper P-type nitride layer 43. Furthermore, the impurity doping concentrations inside the upper P-type nitride layer 43 and the lower P-type nitride layer 41 are different, with the average doping concentration of the upper P-type nitride layer 43 being greater than the average doping concentration of the lower P-type nitride layer 41.

[0042] Specifically, the upper P-type nitride layer 43, as a functional layer in direct contact with the metal gate electrode, has a relatively thick layer (larger d1) to ensure a continuous and stable Schottky contact interface with the metal gate electrode, preventing contact resistance fluctuations or Schottky barrier instability caused by an excessively thin contact layer. Simultaneously, its higher average doping concentration allows for regulation of the Schottky barrier height, enhancing the gate's ability to control the current carrying capacity of channel carriers and improving the device's switching characteristics and anti-interference capabilities. On the other hand, the lower P-type nitride layer 41 employs a low-doping, thinner layer (smaller d2) design, reducing the squeezing and scattering effect of the P-type doped region on the two-dimensional electron gas (2DEG) in the channel below. Since the acceptor properties of P-type impurities attract electron carriers in the channel, the low-doping design reduces this carrier depletion effect, while the thinner design minimizes the influence of the P-type region on the channel, thereby maximizing the retention of the 2DEG concentration and mobility in the channel and ensuring the device's on-state current density and low on-state loss performance.

[0043] Understandably, this application, through differentiated design of thickness and doping concentration, ensures a stable Schottky contact between the upper P-type nitride layer and the metal gate electrode, while reducing the impact on the channel 2DEG through the design of low doping and thin thickness of the lower layer, thus balancing gate structure control capability and device conduction performance.

[0044] The etching stop layer 42 is sandwiched between the upper P-type nitride layer 43 and the lower P-type nitride layer 41, and covers the lower P-type nitride layer 41. It is used to terminate the etching during the gate structure step patterning process. It is made of P-type doped aluminum group III nitride material, such as P-AlGaN, P-AlN or P-AlInGaN. The etching stop layer made of aluminum nitride material has significant etching selectivity with the upper and lower P-type nitride layers, which makes it easy to accurately control the etching depth during the manufacturing process and prevent damage to the barrier layer 20.

[0045] Furthermore, in another preferred embodiment of this application, the etch stop layer 42 can be configured as a P-type AlGaN superlattice structure, composed of multiple alternately grown AlGaN thin layers, with the Al element content increasing gradually along the direction close to the barrier layer 20. The etch stop layer 42 designed with a superlattice structure has superior etch selectivity and structural stability. The Al element content of the AlGaN etch stop layer 42 increases gradually along the direction close to the barrier layer 20, which not only achieves a smooth lattice transition with the upper and lower P-type GaN layers (41, 43), reducing the interface defect density between the upper P-type GaN layer 43 and the AlGaN layer 42, and providing a flat interface foundation for the upper P-type GaN layer 43 to form a stable Schottky contact with the metal gate electrode 44; but also forms an etch hard barrier layer on the high Al content side, controlling the etch depth and preventing damage to the barrier layer 20 during the etch process, while achieving lattice and bandgap connection with the barrier layer 20, improving the gate's control efficiency of the channel 2DEG.

[0046] In the stepped stacked gate structure 40, the projection of the bottom of the upper P-type nitride layer 43 onto the horizontal plane is completely surrounded by the projection of the lower P-type nitride layer 41 onto the horizontal plane. The lower P-type nitride layer 41 extends horizontally to both sides of the source electrode 61 and the drain electrode 62. The extension length to the drain electrode 62 side is greater than the extension length to the source electrode 61 side, forming an asymmetric extension structure to smooth the electric field distribution in the gate region, the gate-source region, and the gate-drain region.

[0047] Understandably, when the device is in reverse bias operation, a strong electric field is formed between the gate structure 40 and the drain electrode 62. Electric field concentration and spikes are prone to occur at the edge of the gate structure 40, becoming weak points for device breakdown. In this application, the lower P-type nitride layer 41 extends towards the drain electrode 62 to form a stepped structure. On the one hand, this widens the electric field transition region from the gate structure 40 to the drain electrode 62, dispersing the electric field energy originally concentrated at the edge of the gate structure 40 to a longer transition range. On the other hand, the stepped structure alters the equipotential line distribution in the gate-drain region, making the equipotential lines more uniform and weakening the local electric field gradient. Through these effects, electric field spikes at the edge of the gate structure 40 can be suppressed, the electric field distribution in the gate-drain region can be smoothed, tunneling and breakdown problems caused by electric field concentration can be reduced, and the stability of the device under high-voltage operating conditions can be improved.

[0048] Building upon this, this application further employs an asymmetric extension design, where the extension length of the lower P-type nitride layer 41 towards the drain electrode 62 is greater than its extension length towards the source electrode 61. The longer extension towards the drain side smooths the structural abrupt change between the gate and drain, enhances the dispersion of electric field peaks, weakens the electric field concentration effect, and improves the device breakdown voltage. The shorter extension length on the source side smooths the structural transition between the gate and source regions, alleviates interlayer stress concentration and local electric field abrupt changes, further reducing the risk of device breakdown, without excessively increasing the equivalent resistance of the gate-source channel. This improves the breakdown voltage while ensuring the gate structure 40's ability to control the channel.

[0049] A strain-adjustable dielectric layer 50 covers the gate structure 40, covering the device surface corresponding to the barrier layer 20, including the gate-drain region and the gate-source region. The source electrode 61 and the drain electrode 62 are respectively disposed above the strain-adjustable dielectric layer 50. By performing local doping treatment at specific locations in the strain-adjustable dielectric layer 50, doped conductive regions are formed, enabling the source electrode 61 and the drain electrode 62 to be electrically connected to the barrier layer 20, ensuring the normal transport of charge carriers in the device.

[0050] It should be noted that in this embodiment, after the patterning etching process is performed on the P-type Schottky gate structure 40, the lower P-type nitride layer 41 on the outside of the P-type Schottky gate structure 40 is completely etched away. In another embodiment of this application, the lower P-type nitride layer 41 on the outside of the P-type Schottky gate structure 40 can be selectively retained. The retained lower P-type nitride layer 41 can act as an additional etching barrier layer, isolating the etching process from the influence of the underlying barrier layer 20 in subsequent device fabrication processes, ensuring the structural integrity and interface performance of the barrier layer 20, and thus ensuring the stability of the concentration and mobility of the two-dimensional electron gas. Under this process scheme, the strain-adjustable dielectric layer 50 in the region outside the P-type Schottky gate structure 40 is in close contact with the retained lower P-type nitride layer 41, optimizing the interface bonding state of the device surface.

[0051] Example 2

[0052] Figure 2 The diagram shown is a cross-sectional schematic of a nitride semiconductor device according to Embodiment 2 of this application. The overall device architecture of this embodiment is similar to that of Embodiment 1, except that an independent nitride isolation layer 30 is added between the gate structure 40 and the barrier layer 20. The nitride isolation layer 30 is disposed between the barrier layer 20 and the multilayer nitride stack structure, and is continuously distributed along the extension direction of the barrier layer 20 to block the diffusion of upper P-type doped impurities into the barrier layer 20.

[0053] Specifically as follows: The gate structure 40 includes a top metal gate electrode 44, an upper P-type nitride layer 43, an etch stop layer 42, and a lower P-type nitride layer 41. The nitride isolation layer 30 is located between the lower P-type nitride layer 41 and the barrier layer 20, and is in contact with both. The nitride isolation layer 30 can prevent the diffusion of P-type doped acceptor impurities from the upper P-type nitride layer (including the upper P-type nitride layer 43 and the lower P-type nitride layer 41) into the barrier layer 20, preventing performance degradation of the barrier layer 20, ensuring a high concentration and high mobility of the two-dimensional electron gas (2DEG), and further improving the device's conduction performance and stability.

[0054] In this embodiment, during the etching process for gate patterning, the nitride isolation layer 30 in the outer region of the gate structure 40 is completely retained on the outside of the gate structure 40 and is continuously distributed along the surface of the barrier layer 20. The retained nitride isolation layer 30 can further serve as a protective layer, isolating the barrier layer 20 from the influence of subsequent processes and maintaining the structural integrity and interface performance of the barrier layer 20. The strain-adjustable dielectric layer 50, which is subsequently fabricated, is in direct contact with the nitride isolation layer 30 in the region outside the gate structure 40. In other embodiments of this application, the nitride isolation layer 30 in the outer region of the gate structure 40 can also be partially retained according to process requirements (such as device integration, compatibility with subsequent processes, etc.). The partially retained nitride isolation layer 30 can still achieve the above-mentioned protection and impurity blocking effects in the retained area, while adapting to different device fabrication process scenarios.

[0055] The preferred parameters and material settings of this embodiment are as follows: The etching stop layer 42 is made of P-type AlGaN material, with a thickness of 0.5nm–3nm; the upper P-type nitride layer 43 and the lower P-type nitride layer 41 are made of P-type GaN material, the thickness d1 of the upper P-type nitride layer 43 is greater than the thickness d2 of the lower P-type nitride layer 41, the thickness d1 of the upper P-type nitride layer 43 is set to 20nm–100nm; the thickness d2 of the lower P-type nitride layer 41 is set to 1nm–30nm. The nitride isolation layer 30 is made of undoped GaN material, with a thickness d3 set to 1nm–5nm. The thickness d4 of the strain-adjusting dielectric layer 50 ranges from 1nm to 10nm, and the material of the strain-adjusting dielectric layer includes at least one of AlN or AlGaN, specifically AlN, AlGaN, or a composite stack of AlN / AlGaN / GaN. Strain-tunable dielectric layers can compensate for residual stress generated in the gate structure region and gate-drain region during device fabrication through their own lattice characteristics and stress modulation capabilities, thus alleviating lattice defect problems caused by stress concentration. At the same time, they can regulate the stress state in the channel region, optimize the concentration and mobility of two-dimensional electron gas (2DEG), and improve the device's conduction performance and operational stability. Furthermore, the excellent insulation and chemical stability of AlN and AlGaN can also achieve passivation protection of the gate region, reducing the adverse effects of interface states and the external environment on device performance.

[0056] Example 3

[0057] Figure 3 The diagram shown is a cross-sectional schematic of a nitride-based semiconductor device according to Embodiment 3 of this application. The semiconductor device has a similar architecture to the semiconductor device in Embodiment 2, except that the structures of functional layers such as the etch stop layer 42, the lower P-type nitride layer 41, and the nitride isolation layer 30 in the gate structure 40 are adjusted accordingly, as follows: The basic components of the gate structure 40 include a metal gate electrode 44, an upper P-type nitride layer 43, an etch stop layer 42, and a lower P-type nitride layer 41 located below and in direct contact with the etch stop layer 42. Unlike the design in Embodiment 1 where the etch stop layer 42 completely covers the lower P-type nitride layer 41, in this embodiment, the etch stop layer 42 is horizontally aligned with the upper P-type nitride layer 43 and does not cover the area of ​​the lower P-type nitride layer 41 extending towards the drain electrode 62. Furthermore, in this embodiment, the nitride isolation layer 30 (undoped GaN layer) located outside the gate structure 40 is completely etched away; due to the extension effect of the etching process, a portion of the barrier layer 20 located below the removed nitride isolation layer 30 may be etched away along the device depth direction. Since the portion of the lower P-type nitride layer 41 extending towards the drain electrode 62 is not covered by the etch stop layer 42, this portion will be partially removed along with the etching process of the etch stop layer 42 (because the uncovered area in the thickness direction will be partially etched), ultimately causing the lower P-type nitride layer 41 to form a convex stepped structure. At this time, the strain-adjustable dielectric layer 50 no longer contacts the nitride isolation layer 30 in the region outside the gate structure 40, but directly contacts the barrier layer 20.

[0058] It is understood that in the device structure of this embodiment, the stress compensation effect of the strain-adjusting dielectric layer 50 itself can adjust the concentration of two-dimensional electron gas (2DEG) below the barrier layer 20 affected by etching on the outside of the gate structure 40, make up for the carrier concentration fluctuation that may be caused by the partial removal of the barrier layer 20, and ensure the stability of the conductive channel of the device; at the same time, the adjusted lower P-type nitride layer 41 can still maintain the extension characteristics towards the drain electrode 62, and in conjunction with the electric field regulation effect of the strain-adjusting dielectric layer 50, continuously smooth the electric field distribution in the gate-drain region, and ensure the withstand voltage performance of the device.

[0059] Example 4

[0060] Figure 4The diagram shown is a cross-sectional schematic of a nitride-based semiconductor device according to Embodiment 4 of this application. This embodiment has a similar architecture to the semiconductor device in Embodiment 1, the main difference being the use of a multi-step gate structure instead of the single-step gate in Embodiment 1. Furthermore, the contact methods between the source electrode, drain electrode, and barrier layer have been flexibly adjusted, as detailed below: In this embodiment, the gate structure 40 adopts a multi-step structure, which includes, from top to bottom, a metal gate electrode 44, an upper P-type nitride layer 43, an upper etch stop layer 42, a middle P-type nitride layer 45, a lower etch stop layer 46, and a lower P-type nitride layer 41. The horizontal projection range of the upper P-type nitride layer 43, the middle P-type nitride layer 45, and the lower P-type nitride layer 41 increases sequentially. The horizontal projection range of the upper P-type nitride layer 43 is smaller than that of the middle P-type nitride layer 45, and the horizontal projection range of the middle P-type nitride layer 45 is smaller than that of the lower P-type nitride layer 41. The upper etch stop layer 42 is aligned with the middle P-type nitride layer 45, and the lower etch stop layer 46 is aligned with the lower P-type nitride layer 41, forming a multi-step contour extending outward toward the drain electrode 62.

[0061] Compared to the single-step design of Example 1, the multi-step configuration of this example further widens the electric field transition path of the gate-drain region, which can more evenly disperse the electric field energy at the gate edge, suppress electric field spikes, and improve the device's withstand voltage and breakdown voltage.

[0062] It should be noted that in this embodiment, each etch stop layer is horizontally projected and aligned with the adjacent P-type nitride layer on its lower surface. In other embodiments of this application, the alignment of each etch stop layer can be flexibly adjusted. Each etch stop layer can also be horizontally projected and aligned with the adjacent P-type nitride layer on its upper surface, thereby forming a convex stepped structure in the P-type nitride layer below the etch stop layer after the gate patterning etching process. The specific alignment method can be flexibly selected according to the device voltage requirements, process accuracy, and electric field control target. This application does not impose a unique limitation on this. In addition, in other embodiments of this application, the number of stacked layers of the etch stop layer and the P-type nitride layer can be further increased according to the actual device design requirements. By adding more sets of etch stop layers and P-type nitride layers, a stepped gate structure with more stages can be constructed to further refine the electric field transition gradient of the gate-drain region and adapt to device application scenarios with higher voltage ratings and higher power densities.

[0063] Continue to refer to Figure 4In this embodiment, the source electrode 61 and the drain electrode 62 are disposed on the barrier layer 20 and are in direct contact with the barrier layer 20. Compared with the source electrode 61 and the drain electrode 62 in embodiments 1-3, which are disposed above the strain-adjusting dielectric layer 50, the electrode and the barrier layer 20 are directly connected by the strain-adjusting dielectric layer 50, which improves the stability and reliability of the electrode contact and reduces the conduction loss of the device.

[0064] It should be noted that the ohmic contact method of the source and drain electrodes in this embodiment is not limited to the multi-step gate structure of Embodiment 4. In other embodiments of this application, this direct contact scheme can be flexibly combined with various gate structure schemes in Embodiments 1-3, depending on the application scenario, on-resistance design parameters, heat dissipation requirements, fabrication process compatibility, and cost control requirements. The specific combination method can be flexibly selected according to the performance positioning and process conditions of the actual product, and this application does not impose a unique limitation on it.

[0065] Example 5

[0066] Figure 5 The diagram shown is a cross-sectional schematic of a nitride-based semiconductor device according to Embodiment 5 of this application. This embodiment has a similar architecture to the semiconductor device in Embodiment 1, the main difference being the use of a multi-step strain-adjustable dielectric layer structure, as detailed below: In this embodiment, the strain-adjusting dielectric layer 50 is entirely covered on the surface of the barrier layer 20, and its thickness range is set to 1nm–10nm. Along the extension direction from the gate structure 40 to the drain electrode 62, the thickness of the strain-adjusting dielectric layer 50 is distributed in a gradient increasing manner (for example, the thicknesses are 2nm, 4nm and 6nm respectively), forming a multi-step thickness profile.

[0067] Understandably, a strain-modulated dielectric layer with specific material and thickness range can provide appropriate strain to compensate for the lattice stress of the barrier layer 20 and ensure the concentration stability of the two-dimensional electron gas (2DEG). The design of increasing thickness gradient can specifically enhance the electric field modulation effect of the gate-drain region, more uniformly disperse the electric field energy at the gate edge, further smooth the electric field distribution, effectively suppress the formation of electric field spikes, thereby improving the device's withstand voltage and breakdown voltage.

[0068] It should be noted that the technical improvements proposed in embodiments 1 to 5 above, including adopting a single / multi-step gate structure, adding a nitride isolation layer, designing a convex P-type nitride layer, optimizing the source and drain electrode contact method, and setting a gradient thickness strain-adjustable dielectric layer, can all be flexibly combined according to the actual device performance goals and application scenarios. This allows for synergistic optimization in terms of gate-drain region electric field distribution control, voltage withstand capability improvement, and conduction loss reduction, in order to meet diverse application requirements such as high frequency, low power consumption, high voltage withstand capability, and high power.

[0069] Reference Figure 6 This application also discloses a method for manufacturing a nitride semiconductor device, including the following steps: S1, Provide nitride matrix 10; S2. A barrier layer 20 is formed above the nitride substrate 10, and the barrier layer 20 is brought into contact with the nitride substrate 10 to form a two-dimensional electron gas at the contact surface. S3. A multilayer nitride stack is sequentially deposited on the barrier layer 20, such that the multilayer nitride stack includes at least two P-type nitride layers (lower P-type nitride layer 41 and upper P-type nitride layer 43) and at least one etch stop layer 42 sandwiched between the P-type nitride layers. S4. A metal gate electrode layer is formed on the upper surface of the multilayer nitride stack. S5. The metal gate electrode layer and the multilayer nitride stack are etched so that the horizontal projection size of the P-type nitride layer away from the barrier layer 20 is smaller than the horizontal projection size of the P-type nitride layer near the barrier layer, and the P-type nitride layer near the barrier layer extends horizontally towards the drain region to form a stepped gate structure 40 towards the drain region. S5. Deposit a strain-adjusting dielectric layer 50 such that the strain-adjusting dielectric layer 50 at least covers the gate structure region and the gate-drain region; S6. Deposit and pattern the metal to form source electrode 61 and drain electrode 62, so that source electrode 61 and drain electrode 62 are located on opposite sides of gate structure 40 and electrically connected to barrier layer 20.

[0070] It is understood that the fabrication method of this application can be applied to the fabrication of nitride semiconductor devices in the foregoing embodiments. By forming heterojunctions, stepped gate structures, electrodes, and strain-adjustable dielectric layers stepwise, the integration of various functional structures of the device is achieved. Utilizing the etch selectivity of the etch stop layer, the stepped morphology of the gate structure stack can be controlled, preventing damage to the barrier layer. The process offers strong controllability and good compatibility with traditional nitride semiconductor manufacturing processes, which is beneficial for improving product yield and mass production capabilities.

[0071] To more clearly illustrate the specific implementation process of the preparation method of this application, the preparation process of the nitride semiconductor device in Example 3 will be described in detail below.

[0072] like Figure 7As shown, firstly, a nitride substrate 10, preferably made of GaN (gallium nitride), is prepared as the device base using metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). This nitride substrate 10 can be composed of multiple functional layers, such as a substrate layer providing mechanical support, a nucleation layer optimizing the crystal quality of the epitaxial layer, a buffer layer mitigating lattice mismatch and suppressing defect propagation, and a channel layer forming carrier transport channels. Subsequently, a barrier layer 20 is epitaxially grown on top of the nitride substrate 10 using the same MOCVD process. The barrier layer 20 is typically made of AlGaN or AlInN material, ensuring close contact between the barrier layer 20 and the nitride substrate 10 to form a heterojunction. High-mobility two-dimensional... Electron gas (2DEG); then, a nitride isolation layer 30 is deposited on the upper surface of the barrier layer 20 using MOCVD process. This nitride isolation layer 30 is made of undoped GaN material, which can block the diffusion of impurities from the upper P-type nitride layer to the barrier layer 20, and prevent the two-dimensional electron gas channel from being contaminated by impurities, thus reducing the mobility. On this basis, a lower P-type nitride layer 41, an etch stop layer 42, and an upper P-type nitride layer 43 are deposited sequentially to provide a basis for the formation of a multilayer nitride stack structure. The lower P-type nitride layer 41 and the upper P-type nitride layer 43 are both made of P-type GaN as the main material, while the etch stop layer 42 is made of P-type doped aluminum-containing group III nitride material (such as P-AlGaN) to provide excellent etch selectivity. like Figure 8 As shown, after deposition, a gate metal layer is prepared on the upper surface of the multilayer nitride stacked structure by electron beam evaporation or sputtering. Then, a mask layer 70 is prepared on top of it. Using the mask layer 70 as a protective layer, a dry etching process is used to pattern the gate metal layer and the upper P-type nitride layer 43 in the multilayer nitride stack, initially defining the vertical profile of the gate. Thanks to the high etching selectivity of the etching stop layer 42 (P-type doped with aluminum group III nitride material), even during the over-etching of the upper P-type nitride layer 43, the etching will stop at the etching stop layer 40. At this time, the lower P-type nitride layer 41 still maintains complete coverage, reserving the basis for the horizontal extension of the subsequent stepped structure. like Figure 9 As shown, the gate metal layer is laterally etched to form the final metal gate electrode 44. In this step, the gate metal layer, protected by the top mask layer 70, undergoes isotropic lateral etching, resulting in a structure where the horizontal dimension of the formed metal gate electrode 44 is slightly smaller than the top horizontal dimension of the upper P-type nitride layer 43. This structure can alleviate the electric field concentration phenomenon at the gate edge. like Figure 10As shown, the second photolithography and etching process is performed. First, a gate retention area (the area within the dashed box is the gate retention area) larger than the first etching area is preset. This retention area covers the metal gate electrode 44 and the upper P-type nitride layer 43, and extends additionally to both sides of the drain and source regions. A dry etching process with no selectivity for the etching stop layer 42 and the lower P-type nitride layer 41 is used to completely remove the etching stop layer 42 and the lower P-type nitride layer 41 outside the gate retention area. Since the horizontal dimension of the second etching is larger than that of the first etching, a stepped gate structure 40 extending to both sides of the drain and source regions is finally formed. The extension length of the lower P-type nitride layer 41 to the drain side is controlled to be greater than the extension length to the source side, which lengthens the electric field distribution path of the gate-drain region and reduces the electric field peak value. like Figure 3 As shown, in the second etching process, in addition to completely removing the etching stop layer 42 and the lower P-type nitride layer 41 outside the gate retention region, the undoped GaN isolation layer 30 in this region is also partially etched to align it with the lower P-type nitride layer 41. Subsequently, a strain-adjustable dielectric layer 50 is deposited to at least completely cover the gate structure region (stepped gate structure 40) and the gate-drain region, thereby adjusting the stress distribution inside the device and improving the electrical stability and reliability of the device. Finally, a metal layer is deposited and patterned. On the strain-adjustable dielectric layer 50 on the barrier layer 20, the source electrode 61 and the drain electrode 62 are formed on opposite sides of the gate structure 40, respectively, to complete the electrode interconnect structure of the device.

[0073] The device manufacturing methods of other embodiments of this application are basically the same as the main process steps described above. In actual manufacturing, they can be adapted according to the specific device structure and performance requirements. The relevant details will not be repeated here.

[0074] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A nitride semiconductor device, characterized in that, include: Nitride matrix (10); A barrier layer (20) is located above and in contact with the nitride substrate (10), and a two-dimensional electron gas is formed at the contact surface; A source electrode (61) and a drain electrode (62) are disposed on the barrier layer (20) at intervals. A gate structure (40) is disposed on the barrier layer (20) and located between the source electrode (61) and the drain electrode (62), including a multilayer nitride stack structure and a metal gate electrode (44) formed on the upper surface of the nitride stack structure. The multilayer nitride stack structure includes at least two P-type nitride layers and at least one etch stop layer (42) sandwiched between the P-type nitride layers; in the multilayer nitride stack structure, the P-type nitride layer that contacts the metal gate electrode (44) is defined as the upper P-type nitride layer (43), and the P-type nitride layer that contacts the barrier layer (20) is defined as the lower P-type nitride layer (41). The projection of the upper P-type nitride layer (43) on the surface of the barrier layer (20) is located within the projection range of the lower P-type nitride layer (41) on the surface of the barrier layer (20), and the lower P-type nitride layer (41) extends horizontally toward the drain electrode (62), so that the multilayer nitride stack structure forms a stepped structure toward the drain electrode (62); A strain-adjustable dielectric layer (50) is applied to the surface of the barrier layer (20) between the source electrode (61) and the drain electrode (62) to adjust the electric field density of the gate structure region and the gate-drain region.

2. The nitride semiconductor device according to claim 1, characterized in that, It also includes a nitride isolation layer (30), which is disposed between the barrier layer (20) and the multilayer nitride stack structure and is continuously distributed along the extension direction of the barrier layer (20) to block the diffusion of P-type doped impurities into the barrier layer (20).

3. The nitride semiconductor device according to claim 1, characterized in that, The thickness d2 of the lower P-type nitride layer (41) is less than the thickness d1 of the upper P-type nitride layer (43), and the average doping concentration of the lower P-type nitride layer (41) is less than the average doping concentration of the upper P-type nitride layer (43).

4. The nitride semiconductor device according to claim 1, characterized in that, The multilayer nitride stacked structure forms a stepped structure toward the drain electrode (62), and the lower P-type nitride layer (41) extends horizontally toward the source electrode (61) at the same time, wherein the extension length toward the drain electrode (62) is greater than the extension length toward the source electrode (61), forming an asymmetric extension structure.

5. The nitride semiconductor device according to claim 1, characterized in that, The nitride substrate (10) is a GaN substrate, the barrier layer (20) is an AlGaN layer, and the band gap of the barrier layer (20) is greater than the band gap of the nitride substrate (10); the etching termination layer (42) is made of a P-type doped aluminum nitride material, and the aluminum nitride material includes at least one of AlGaN, AlN or AlInGaN.

6. The nitride semiconductor device according to claim 5, characterized in that, The etching termination layer (42) is a P-type AlGaN superlattice structure, composed of multiple alternating AlGaN thin layers, and the Al element content increases in a gradient along the direction close to the barrier layer (20).

7. The nitride semiconductor device according to claim 1, characterized in that, The material of the strain-adjusting dielectric layer (50) includes at least one of AlN or AlGaN, the thickness of the strain-adjusting dielectric layer (50) is 1nm-10nm, and the thickness of the strain-adjusting dielectric layer (50) increases in a gradient along the direction from the gate structure (40) to the drain electrode (62).

8. The nitride semiconductor device according to claim 1, characterized in that, The source electrode (61) and the drain electrode (62) are disposed on the upper surface of the barrier layer (20) and are in direct contact with the barrier layer (20), or the source electrode (61) and the drain electrode (62) are disposed on the upper surface of the strain adjustment medium layer (50) and are connected to the barrier layer (20) through the strain adjustment medium layer (50).

9. The nitride semiconductor device according to claim 1, characterized in that, The metal gate electrode (44) forms a Schottky contact with the multilayer nitride stack structure, and the materials of the metal gate electrode (44), the source electrode (61) and the drain electrode (62) include at least one of Ni, Au or Ti.

10. A method for manufacturing a nitride semiconductor device, characterized in that, Including the following steps: S1, Provide nitride matrix (10); S2. A barrier layer (20) is formed above the nitride substrate (10) and the barrier layer (20) is brought into contact with the nitride substrate (10) to form a two-dimensional electron gas at the contact surface. S3. A multilayer nitride stack is sequentially deposited on the barrier layer (20), such that the multilayer nitride stack includes at least two P-type nitride layers and at least one etch stop layer (42) sandwiched between the P-type nitride layers. S4. A metal gate electrode layer is formed on the upper surface of the multilayer nitride stack, and the metal gate electrode layer and the multilayer nitride stack are etched so that the horizontal projection size of the P-type nitride layer away from the barrier layer (20) is smaller than the horizontal projection size of the P-type nitride layer close to the barrier layer (20), and the P-type nitride layer close to the barrier layer (20) extends horizontally towards the drain region to form a stepped gate structure (40) towards the drain region. S5. Deposit a strain-adjusting dielectric layer (50) such that the strain-adjusting dielectric layer (50) at least covers the gate structure region and the gate-drain region; S6. Deposit and pattern metal to form a source electrode (61) and a drain electrode (62), such that the source electrode (61) and the drain electrode (62) are located on opposite sides of the gate structure (40) and electrically connected to the barrier layer (20).

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