Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same are disclosed. According to embodiments, a semiconductor device can include a substrate, a buried oxide layer, a channel portion, a source / drain portion, and a gate stack. The channel portion includes a plurality of semiconductor layers stacked above the buried oxide layer spaced apart from each other, each of the plurality of semiconductor layers including a shell portion and a core portion. The shell portion is a doped region in the semiconductor layer, the shell portion having a doping type opposite to a doping type of the source / drain portion, and the shell portion is disposed between the core portion and the gate stack, and / or the shell portion encloses the core portion.

Description

Technical Field

[0001] This disclosure generally relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device comprising at least one semiconductor layer and a method for manufacturing the same. Background Technology

[0002] Gate-all-around (GAA) metal-oxide-semiconductor field-effect transistors (MOSFETs) offer excellent control over short-channel effects and enable further miniaturization of devices. However, manufacturing GAA MOSFETs is complex and costly. Summary of the Invention

[0003] In view of this, the purpose of this disclosure is at least in part to provide a semiconductor device and a method for manufacturing the same.

[0004] According to one aspect of this disclosure, a semiconductor device is provided, comprising:

[0005] Substrate;

[0006] The buried oxide layer on the substrate;

[0007] The channel portion includes at least one semiconductor layer stacked on top of the buried oxide layer at intervals from each other, each of the at least one semiconductor layer including a shell portion and a core portion;

[0008] Source / drain portion, above the buried oxygen layer and connecting the opposite ends of the channel portion; and

[0009] The grid stack intersects with the channel portion on the buried oxide layer;

[0010] The shell is a doped region in the semiconductor layer, and the doping type of the shell is opposite to that of the source / drain.

[0011] The shell portion is located between the core portion and the gate stack; and / or the shell portion surrounds the core portion.

[0012] In one embodiment, the core is of the same low-doping type as the source / drain type.

[0013] In one embodiment, the channel portion includes a plurality of semiconductor layers with a gate stack sandwiched between two adjacent semiconductor layers. The gate stack includes a gate dielectric layer and a work function layer on the gate dielectric layer, the work function layer being not connected to the source / drain portion.

[0014] In one embodiment, gate stacks are disposed on both sides of at least one semiconductor layer, and the surface layers on both sides of the at least one semiconductor layer include shell portions.

[0015] In one embodiment, each of the at least one semiconductor layer has a thickness in the range of 10 nm to 200 nm.

[0016] In one embodiment, the shell portion has a range of 1-10 nm.

[0017] In one embodiment, the channel portion includes a plurality of semiconductor layers, wherein the spacing between adjacent semiconductor layers is in the range of 20 nm to 400 nm.

[0018] In one embodiment, the width of the channel portion (including the core portion and the shell portion) between the source / drain portion is less than 3 times the interval, preferably less than 2 times the interval.

[0019] In one embodiment, each of the at least one semiconductor layer comprises Si or SiGe.

[0020] In one embodiment, the semiconductor device is configured as a plurality of semiconductor devices, the plurality of semiconductor devices including n-type semiconductor devices and p-type semiconductor devices.

[0021] Wherein, the channel portion of the n-type semiconductor device includes a p-type doped shell portion, and the work function layer is configured as n-type; and the channel portion of the p-type semiconductor device includes an n-type doped shell portion, and the work function layer is configured as p-type.

[0022] In one embodiment, the gate dielectric layer comprises HfO2, and the work function layer comprises TiN.

[0023] In another aspect, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0024] The SOI substrate is patterned (e.g., through patterning, photolithography, etching, etc.) to form a fin structure. The SOI substrate comprises a substrate, a buried oxide layer on the substrate, and alternating stacks of multiple semiconductor and oxide layers on the buried oxide layer. The multiple semiconductor and oxide layers on the SOI substrate can be formed through multiple SOI smart-cut processes. The multiple semiconductor layers have a broad range and can be Si, or other multilayer semiconductor materials (such as Ge, GaAs, III-V, etc.) or a mixture thereof. While the method of alternating stacks of multiple Si / SiGe layers is relatively well-known, it is limited to forming multiple Si semiconductor layers on the SOI substrate.

[0025] A sacrificial gate intersecting with the fin structure is formed on the SOI substrate, and a gate sidewall is formed on the sidewall of the sacrificial gate;

[0026] Source / drain portions are formed on opposite sides of the gate sidewall;

[0027] Remove the sacrificial gate to expose the alternating stack of the semiconductor layer and the oxide layer (or SiGe layer) within the space between the gate sidewalls;

[0028] The oxide layer (or SiGe layer) is selectively etched away to expose the surface of the semiconductor layer;

[0029] A doped shell is formed on the exposed surface of the semiconductor layer; and

[0030] A grid stack is formed in the space between the grid sidewalls;

[0031] The doping type of the shell is opposite to that of the source / drain.

[0032] In one embodiment, the SOI substrate is formed through a multi-smart-cut process.

[0033] In one embodiment, each of the semiconductor layers has a thickness in the range of 10 nm to 200 nm, and each of the oxide layers has a thickness in the range of 20 nm to 400 nm.

[0034] In one embodiment, a doped shell is formed in a semiconductor layer by plasma doping.

[0035] In one embodiment, the fin-shaped structure protrudes relative to the buried oxide layer, and the method further includes:

[0036] Shallow grooves are formed between the fin-shaped structures to isolate STIs.

[0037] In the selective etching, the etching rate of the oxide layer (or SiGe layer) is greater than twice the etching rate of the STI oxide.

[0038] In one embodiment, the oxide layer comprises a phosphorus-doped oxide, and the STI comprises a high-density plasma (HDP) undoped phosphorus oxide.

[0039] In one embodiment, the gate stack includes a gate dielectric layer and a work function layer on the gate dielectric layer, the work function layer not connected to the source / drain portion, and the method includes: forming an n-type doped work function layer for an n-type semiconductor device and forming a p-type work function layer for a p-type semiconductor device.

[0040] In one embodiment, each of the at least one semiconductor layer comprises Si or SiGe. Attached Figure Description

[0041] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, in which:

[0042] Figures 1 to 14(b) The illustrations schematically depict some stages in the process of manufacturing a semiconductor device according to embodiments of the present disclosure;

[0043] Figure 15 This schematically illustrates a multi-stage intelligent cutting process.

[0044] in, Figure 1 , 3(a) Figures 4(a), 5(a), 6 to 10, 11(a), 12(a), 13(a), 14(a), and 15 are cross-sectional views along line AA'.

[0045] Figure 3(b) , 4(b) Figures 5(b), 11(b), 12(b), 13(b), and 14(b) are cross-sectional views along line BB'.

[0046] Figure 2 It is a top view. Figure 2 The positions of lines AA' and BB' are shown in the diagram.

[0047] Figure 16 A schematic perspective view of a semiconductor device according to an embodiment of the present invention is shown, wherein the circled portion shows an enlarged schematic view of a portion of the channel. Detailed Implementation

[0048] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0049] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed. In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0050] According to embodiments of this disclosure, a semiconductor device is provided. Specifically, refer to... Figure 15 The perspective view shown indicates that the semiconductor device may include a channel portion and source / drain portions 1023 disposed on opposite sides of the channel portion. The channel portion may include multiple semiconductor layers 1007, 1011, wherein each semiconductor layer may include a semiconductor material such as silicon (Si), silicon germanium (SiGe), or a III-V semiconductor compound. Each semiconductor layer may have a thickness in the range of about 10 nm to about 200 nm. Each semiconductor layer includes a shell portion 1007-1, 1011-1 near the surface and a core portion. The shell portions 1007-1, 1011-1 are doped portions of the semiconductor layer, and the doping type of the shell portions 1007-1, 1011-1 is opposite to the doping type of the source / drain portions 1023. The core portion is a portion of the semiconductor layer located inside the shell portion, and is not extensively doped when the shell portion is doped. The shell portions 1007-1 and 1011-1 can have a range of approximately 1-10 nm, where range refers to the distribution range or region of doped ions, determined by the doping process. The semiconductor layers 1007 and 1011 can be intrinsic semiconductor materials or lightly doped semiconductor materials. The core portion can be the remaining portion of the semiconductor layer excluding the shell portions 1007-1 and 1011-1 in the surface layer (here, the remaining portion is located inside the semiconductor relative to the shell portion). In one embodiment, the shell portion surrounds the surface portion of the core portion.

[0051] Semiconductor layers 1007 and 1011 may be suspended relative to the substrate or the buried oxide layer 1003 on the substrate, and may extend substantially parallel to the surface of the substrate or the buried oxide layer. The individual semiconductor layers 1007 and 1011 are spaced apart from each other in a vertical direction (e.g., a direction substantially perpendicular to the surface of the substrate or the buried oxide layer), and the spacing between adjacent semiconductor layers 1007 and 1011 may be in the range of about 20 nm to about 400 nm.

[0052] The channel portion may extend in a first direction on the substrate (wafer), and the opposite ends in the first direction may be connected to the source / drain portion 1023. The width of the channel portion between the source / drain portions 1023 (i.e., the length of the channel portion in the first direction) may be less than 3 times the spacing between adjacent semiconductor layers 1007, 1011 in the plurality of semiconductor layers, preferably less than 2 times the spacing.

[0053] The gate stack can extend along a second direction that intersects (e.g., perpendicularly) a first direction on the substrate to intersect the channel portion, and thus can surround the outer periphery of the channel portion to form a gate all-around (GAA) structure. Shell portions 1007-1 and 1011-1 can be located between the gate stack and the core portion.

[0054] According to an embodiment, a plurality of semiconductor devices can be configured, including n-type semiconductor devices and p-type semiconductor devices. The shell portions 1007-1 and 1011-1 in the plurality of semiconductor layers in the channel portion of each n-type and p-type semiconductor device can respectively correspond to p-type semiconductor doped regions and n-type semiconductor doped regions. In this embodiment, the gate stack of each n-type and p-type semiconductor device can include a gate dielectric layer 1029 and a work function layer 1027 on the gate dielectric layer 1029. The work function layer 1027 can respectively correspond to n-type and p-type.

[0055] The core-shell structure or morphology of the channel portion can be used to adjust the Vt value and achieve multiple Vt values. This invention advantageously realizes multiple Vt schemes for FDSOI devices by configuring one or more shell portions and / or using doping methods, which is highly advantageous for FDSOI devices. The design of this invention allows a three-dimensional transistor structure to have multiple channel portions, each including shell portions 1007-1 and 1011-1, thereby fully utilizing the charge balance effect. Simultaneously, when conducting, the shell portions 1007-1, 1011-1 and the core portion can conduct together, enabling multi-channel devices to have multiple times the drive current. Having more than one shell portion 1007-1, 1011-1 or more than one core portion can more advantageously optimize the uniformity and consistency of the device.

[0056] In embodiments with n-type and p-type FET devices, for the n-type semiconductor device, when the absolute value of the gate voltage is less than the absolute value of the threshold voltage (positive voltage), the space charge in the core is balanced by the space charge in the case portions 1007-1 and 1011-1, resulting in complete depletion. As the absolute value of the gate voltage gradually exceeds the absolute value of the threshold voltage, the core first forms an electron accumulation mode and begins to conduct. Then, a larger gate voltage value causes the case portion to form an inversion mode and also participate in conduction. For the p-type semiconductor device, when the absolute value of the gate voltage is less than the absolute value of the threshold voltage (negative voltage), the space charge in the core is balanced by the space charge in the case portion, resulting in complete depletion. As the absolute value of the gate voltage gradually increases and exceeds the absolute value of the threshold voltage, the core first forms a hole accumulation mode and begins to conduct. Then, a larger gate voltage value causes the case portion to form an inversion mode and also participate in conduction.

[0057] In one embodiment, the semiconductor device has two semiconductor layers 1007 and 1011, which are spatially spaced apart (shown vertically in the accompanying drawings). A gate stack is disposed between the two semiconductor layers 1007 and 1011. For example, the first semiconductor layer 1007 is connected to a first gate dielectric layer, and a first work function layer and a gate conductive layer are sequentially disposed on one side of the first gate dielectric layer. The second semiconductor layer 1011 of the two semiconductor layers 1007 and 1011 is connected to a second gate dielectric layer, and a second work function layer and a gate conductive layer are sequentially disposed on one side of the second gate dielectric layer. In this embodiment, a common gate conductive layer 1031 and a first gate dielectric layer and a first work function layer corresponding to the first semiconductor layer, and a second gate dielectric layer and a second work function layer corresponding to the second semiconductor layer are disposed between the first and second semiconductor layers 1007 and 1011. The first gate dielectric layer, the second gate dielectric layer, the first and second work function layers, etc. mentioned above are only for distinguishing layers at different locations. It should be understood that they can be made of the same material and formed in the same process step, such as high-k materials (hafnium oxide), work function layers such as TiN, etc.

[0058] In one embodiment, unlike the aforementioned two-semiconductor-layer embodiment, the semiconductor device has three semiconductor layers, which are spatially spaced (vertically in the accompanying drawings). The arrangement of the first and second semiconductor layers is the same as in the previous embodiment and will not be repeated. A gate stack is disposed between the second and third semiconductor layers. The second semiconductor layer is connected to another second gate dielectric layer, and on one side of the other second gate dielectric layer, there is another second work function layer and a gate conductive layer in sequence. The third semiconductor layer is connected to a third gate dielectric layer, and on one side of the third gate dielectric layer, there is a third work function layer and a gate conductive layer in sequence. In this embodiment, a common gate conductive layer and another second gate dielectric layer and another second work function layer corresponding to the second semiconductor layer are disposed between the second and third semiconductor layers, as well as a third gate dielectric layer and a third work function layer corresponding to the third semiconductor layer. That is, in this embodiment, the two surface layers of the second semiconductor layer each include a shell portion, and the core portion of the second semiconductor layer is located between the two shell portions. This embodiment is not shown in the accompanying drawings; however, its structure can be imagined in conjunction with the aforementioned embodiments. The first gate dielectric layer, the second gate dielectric layer, the third dielectric layer, and the first, second, and third work function layers mentioned above are only used to distinguish layers at different locations. It should be understood that they are made of the same material and formed in the same process step, such as high-k material (hafnium oxide) and work function layer TiN.

[0059] According to embodiments of the present invention, the channel configuration of multiple semiconductor layers can be achieved through a three-dimensional fin structure, while a semiconductor layer can provide shells on both sides, thereby improving the compactness and performance of the device, while being compatible with current process flows.

[0060] In other embodiments, the semiconductor device may include more semiconductor layers, the arrangement of which may be configured according to the principles described herein.

[0061] In one embodiment of this aspect, the semiconductor device may include only one semiconductor layer. Based on the principles described in the above embodiments of the present invention, it is conceivable that in an embodiment including only one semiconductor layer, shell portions may be formed in the surface layers on both sides of the semiconductor layer, and the core portion may be located between the two shell portions; of course, the shell portion may be formed only in the surface layer on one side of the semiconductor layer, and the remaining part of the semiconductor layer may be the core portion.

[0062] This semiconductor device can be fabricated as follows: A silicon-on-insulator (SOI) substrate can be patterned to form a fin-shaped structure extending in a first direction on the substrate (wafer). The SOI substrate may include a substrate, a buried oxide layer on the substrate, and alternating stacks of semiconductor and oxide layers on the buried oxide layer. The SOI substrate can be formed using SOI fabrication processes such as multiple smart dicing processes.

[0063] Fin-shaped structures can protrude relative to the buried oxide layer. For the purpose of electrical isolation, shallow trench isolation (STI) can be formed between fin-shaped structures.

[0064] A sacrificial gate intersecting the fin structure can be formed on the SOI substrate. Considering the constraints of the gate stack space and the isolation between the gate stack and the source / drain portions, gate sidewalls can be formed on the sidewalls of the sacrificial gate. Additionally, inner sidewalls can also be formed. For example, the sacrificial gate and gate sidewalls can be used as etching masks to anisotropically etch the fin structure to expose the sidewalls of the semiconductor and oxide layers. By exposing the sidewalls of the oxide layer, selective etching of the oxide layer can be performed to free up space for the inner sidewalls. The inner sidewalls can then be formed in this freed-up space. Subsequently, source / drain portions can be formed on opposite sides of the gate sidewalls in a first direction.

[0065] To form the gate stack, the sacrificial gate can be removed to expose an alternating stack of semiconductor and oxide layers within the space between the gate sidewalls. Subsequently, the oxide layer can be selectively etched away to expose the surface of the semiconductor layer. In this selective etching, the etch rate of the oxide layer can be greater than twice the etch rate of the STI to avoid excessive loss of the surrounding STI oxide.

[0066] After removing the oxide layer, plasma doping can be used to dope the exposed surface of the semiconductor layer to form a shell in the semiconductor layer. The gate dielectric layer and the work function layer can be stacked sequentially in the space between the gate sidewalls to form a gate stack.

[0067] This disclosure may be presented in various forms, some of which will be described below. In the following description, the selection of various materials is discussed. The selection of materials takes into account not only their function (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation) but also etch selectivity. In the following description, the desired etch selectivity may or may not be indicated. Those skilled in the art will understand that when the following references to etching a material layer, unless it is mentioned that other layers are also etched or not shown in the figures, then such etching may be selective, and the material layer may possess etch selectivity relative to other layers exposed to the same etch formulation.

[0068] In the following embodiments, an alternating stack of multiple semiconductor layers and oxide layers is used as an example of a channel.

[0069] Figures 1 to 14(b) The illustrations schematically depict some stages in the process of manufacturing a semiconductor device according to embodiments of the present disclosure. The following description is based on a two-semiconductor-layer scenario; the manufacturing process for other numbers of semiconductor layers is similar.

[0070] like Figure 1 As shown, an SOI substrate 100 is provided. The SOI substrate 100 may include a substrate 1001, a buried oxide layer 1003 on the substrate 1001, and an alternating stack of semiconductor layers 1007 and 1011 and oxide layers 1005 and 1009 on the buried oxide layer 1003. The oxide layers 1005 and 1009 may define the location of the gate stack to be subsequently formed. In this example, two semiconductor layers 1007 and 1011 are formed, thus ultimately forming two channels in the semiconductor device. However, this disclosure is not limited to this; the number of semiconductor layers to be formed and the number of oxide layers to be formed may be determined according to the number of channels to be formed (which may be one or more).

[0071] SOI substrate 100 can be formed by, for example, SOI fabrication processes such as multiple SOI smart-cut processes.

[0072] In another embodiment, a substrate 1001 is provided, on which a buried oxide layer 1003 is formed. Semiconductor layers 1007 and 1011 and oxide layers 1005 and 1009 are alternately stacked on the buried oxide layer 1003. The semiconductor layers have a broad range and can be Si, or other multilayer semiconductor materials (such as Ge, GaAs, III-V, etc.) or a mixture thereof. The process of using alternating stacks of multilayer Si / SiGe is relatively well-known, but it is limited to forming multilayer Si semiconductor layers on an SOI substrate.

[0073] Substrate 1001 may include elemental semiconductor materials such as Si or Ge, or compound semiconductor materials such as SiGe. Here, a silicon wafer is used as an example to describe substrate 1001. Buried oxide layer 1003 may include oxides (e.g., silicon oxide). Semiconductor layers 1007 and 1011 may include elemental semiconductor materials such as Si or Ge, or compound semiconductor materials such as SiGe. Each of semiconductor layers 1007 and 1011 may have a thickness in the range of about 10 nm to about 200 nm. Each of oxide layers 1005 and 1009 may have a thickness in the range of about 20 nm to about 400 nm. The greater the thickness of oxide layers 1005 and 1009, the easier it is to remove them in a subsequent alternative gate process. To provide etching selectivity in subsequent processes, such as etching selectivity relative to buried oxide layer 1003 and the subsequently formed shallow trench isolation (STI), oxides with different etching characteristics relative to buried oxide layer 1003 and STI, such as phosphorus-doped oxides, may be included. According to other embodiments, oxide layer 1005 may also be omitted.

[0074] In one example, the semiconductor layers 1007 and 1011 in different regions of the SOI substrate 100 may include different materials. For instance, in a first region forming an n-type field-effect transistor (FET), semiconductor layers 1007 and 1011 may include Si, while in a second region forming a p-type FET, semiconductor layers 1007 and 1011 may include SiGe to optimize the carrier mobility of the n-type FET and the p-type FET, respectively. The SiGe material of semiconductor layers 1007 and 1011 in the second region can be obtained by the Ge-condensation method. The Ge-condensation method itself is well known in FDSOI (fully depleted silicon-on-insulator) processes and will not be described further here.

[0075] In another example, the lower semiconductor layer 1007 and the upper semiconductor layer 1011 on the SOI substrate 100 may include different materials. For example, FETs can be formed on the SOI substrate 100, with the lower semiconductor layer 1007 used for the lower FET and the upper semiconductor layer 1011 used for the upper FET. When the stacked FETs have different types, the semiconductor layers 1007 and 1011 may include different materials to optimize the carrier mobility of the upper and lower FETs respectively, but the process will be more complex.

[0076] Next, the SOI substrate 100 can be patterned to form the channel portion.

[0077] For example, such as Figure 2As shown, a mask such as photoresist 1013 can be formed on the SOI substrate, and the photoresist 1013 can be patterned into a form corresponding to the channel portion to be formed by photolithography. For example, in Figure 2 In the example shown, the photoresist 1013 can be in the form of a strip extending along a first direction (the horizontal direction within the plane of the paper in the figure).

[0078] For convenience, hard mask structures that may be used in the patterning process, such as hard masks in the form of stacked oxide / nitride layers, are not shown here. Furthermore, instead of being limited to examples using photoresist (+hard mask), spacer image transfer (SIT) processes can also be used. For example, sidewalls, such as nitride (e.g., silicon nitride), extending along a first direction can be formed on the SOI substrate 100 using a sidewall forming process, and these sidewalls can be used as patterning masks.

[0079] Then, as Figure 3(a) and 3(b) As shown, photoresist 1013 can be used as a mask to sequentially etch each layer using anisotropic etching, such as vertical reactive ion etching (RIE). According to an embodiment, the etching can penetrate into the substrate 1001. This forms a protruding structure (which may be referred to as a "fin structure") corresponding to the pattern of the photoresist 1013 on the substrate 1001. The photoresist 1013 can then be removed.

[0080] For electrical isolation purposes, such as Figure 4(a) and 4(b) As shown, isolation portions 1015, such as shallow trench isolation (STI), can be formed between the fin structures on the substrate 1001. For example, high-density plasma (HDP) oxide can be deposited on the substrate 1001, the deposited HDP oxide can be planarized (e.g., chemical mechanical polishing (CMP), and the planarized HDP oxide can be etched back to form the isolation portions 1015. Each semiconductor layer 1007, 1011 protrudes outward relative to the top surface of the isolation portion 1015.

[0081] After that, as Figure 5(a) and 5(b) As shown, a sacrificial gate 1017 can be formed on the SOI substrate extending along a second direction intersecting the first direction (e.g., a direction perpendicular to the plane of the paper in FIG. 5(a), or a horizontal direction within the plane of the paper in FIG. 5(b), thus intersecting the aforementioned fin structure. For example, the sacrificial gate 1017 may comprise an oxide layer and polysilicon on the oxide layer. Similarly, for convenience, a hard mask that may exist on the sacrificial gate 1017 is not shown. On the sidewalls of the sacrificial gate 1017, gate sidewalls 1019 can be formed by a sidewall forming process. For example, gate sidewalls 1019 may comprise nitrides.

[0082] like Figure 6 As shown, the sacrificial gate 1017 and gate sidewall 1019 can be used as etching masks to perform anisotropic etching, such as vertical RIE, on the semiconductor layers 1007, 1011 and oxide layers 1005, 1009. The RIE can stop at the buried oxide layer 1003. Thus, the semiconductor layers 1007, 1011 can form a channel portion self-aligned to the sacrificial gate 1017.

[0083] According to embodiments of this disclosure, an inner sidewall can also be formed.

[0084] For example, such as Figure 7 As shown, oxide layers 1005 and 1009 can be selectively etched relative to semiconductor layers 1007 and 1011, such that their sidewalls are recessed inward to a certain depth relative to the sidewall of gate sidewall 1019 or the sidewall of semiconductor layers 1007 and 1011. Preferably, the recess depths of oxide layers 1005 and 1009 are substantially the same and can be substantially equal to the thickness (in the first direction) of gate sidewall 1019, so that the subsequently formed inner sidewall can have substantially the same thickness as gate sidewall 1019.

[0085] In such a recess, an inner wall can be formed. For example... Figure 8 As shown, a dielectric material layer of a certain thickness can be formed on the substrate 1001 by, for example, deposition. The thickness of the deposited dielectric material layer is sufficient to fill the aforementioned recess. For example, the dielectric material layer may include SiC, etc. Subsequently, the deposited dielectric material layer can be etched back by, for example, a vertical RIE, to form the inner sidewall 1021. The inner sidewall 1021 may also include the same material as the gate sidewall 1019.

[0086] like Figure 8 As shown, in the first direction ( Figure 8 On the horizontal direction within the paper, the sidewalls of each semiconductor layer 1007 and 1011 are exposed.

[0087] like Figure 9 As shown, the sidewalls of the exposed semiconductor layers 1007 and 1011 serve as seeds, and source / drain portions 1023 are formed through selective epitaxial growth, for example. The source / drain portions 1023 can be formed to be in contact with the exposed sidewalls of the semiconductor layers 1007 and 1011. The source / drain portions 1023 can comprise various suitable semiconductor materials, for example, Si for n-type FETs and SiGe for p-type FETs. The source / drain portions 1023 can be doped to the desired conductivity type (n-type doping for n-type FETs and p-type doping for p-type FETs) through, for example, in-situ doping or ion implantation.

[0088] Next, an alternative gate process can be implemented.

[0089] For example, such as Figure 10 As shown, an interlayer dielectric layer 1025 can be formed on the substrate 1001. For example, the interlayer dielectric layer 1025 can be formed by depositing an oxide and then planarizing the oxide deposited by CMP. CMP can be performed up to expose the sacrificial gate 1017 inside the gate sidewall 1019.

[0090] like Figure 11(a) and 11(b) As shown, the sacrificial gate 1017 can be selectively etched away to expose the alternating stacking of semiconductor layers 1007, 1011 and oxide layers 1005, 1009 in the space between the gate sidewalls 1019. It can be seen that the sidewalls of oxide layers 1005, 1009 are exposed in the second direction (see Figure 11(b)).

[0091] After that, as Figure 12(a) and 12(b) As shown, the oxide layers 1005 and 1009 can be selectively etched to expose the surfaces of the semiconductor layers 1007 and 1011. As described above, since the oxide layers 1005 and 1009 may include phosphorus-doped oxides and the isolation portion 1015 may include HDP oxides, the etching rate of the oxide layers 1005 and 1009 during selective etching to remove them can be twice or more than the etching rate of the isolation portion 1015. Therefore, the oxide layers 1005 and 1009 can be substantially completely removed without substantially affecting the isolation portion 1015.

[0092] Next, as Figure 13(a) and 13(b) As shown, shells 1011-1 and 1011-2, and 1007-1 and 1007-2, can be formed by plasma doping on the exposed surfaces of semiconductor layers 1007 and 1011. For simplicity, in Figure 13(a) and 13(b) The diagram only schematically shows the shell portion of the surface layer of semiconductor layers 1007 and 1011, and does not represent the actual shape of the shell portion. Considering the characteristics of plasma processing, doping may also occur on other exposed surfaces, but this will not affect the subsequent processes. As shown in Figure 13(b), the shell portion can be formed within the surface layer of semiconductor layers 1007 and 1011 around the outer periphery of each semiconductor layer 1007 and 1011.

[0093] The shell is the doped portion of the semiconductor surface. For an n-type transistor, the shell is a p-type doped portion; for a p-type transistor, the shell can be an n-type doped portion. The shell has a range of 1-10 nm.

[0094] After that, as Figure 14(a) and14(b) As shown, a gate stack can be formed within the space between the gate sidewalls 1019. For example, a gate dielectric layer 1029 and a gate conductor layer 1031 can be formed sequentially to obtain the final gate stack. For example, the gate dielectric layer 1029 may include a high-k gate dielectric such as hafnium oxide (HfO2). An interface oxide layer may exist between the gate dielectric layer 1029 and the semiconductor layers 1007 and 1011. The gate conductor layer 1031 may include a work function layer and a gate electrode such as tungsten (W). The work function layer may have a suitable work function, for example, an n-type work function for an n-type FET and a p-type work function for a p-type FET.

[0095] According to embodiments, for n-type FETs and p-type FETs, semiconductor layers 1007 and 1011 can be doped (e.g., doped to p-type and n-type respectively), and corresponding work function layers can be formed (e.g., n-type work function and p-type work function respectively). The work function layer may also include an intermediate bandgap metal material. In this case, the intermediate bandgap metal material can be deposited simultaneously for n-type FETs and p-type FETs, making the method of manufacturing semiconductor devices simpler and more cost-effective.

[0096] According to other embodiments, for n-type FETs and p-type FETs, p-type doping and n-type doping can be performed respectively in their semiconductor layers 1007 and 1011 by plasma doping, as described above, and n-type and p-type work function layers can be formed with work functions in the vicinity of approximately 4.0 eV and 5.2 eV, respectively. In this way, the core in the channel can be under full depletion conditions, and the doping of the shell can be used to set the Vt value.

[0097] like Figure 14(a) and 14(b) As shown, the semiconductor device according to the embodiment may include semiconductor layers 1007, 1011 (the number may be fewer or more) including a housing, and a gate stack surrounding the semiconductor layers 1007, 1011, the gate stack including a gate dielectric layer 1029 and a gate conductor layer 1031. In the case where the oxide layer 1005 is omitted as described above, the gate stack may not extend below the lowermost semiconductor layer 1007.

[0098] Compared to conventional methods, the method for manufacturing semiconductor devices according to the embodiments is simpler and has lower costs. Furthermore, since the semiconductor layer is coated with a molybdenum disulfide coating, the semiconductor devices according to the embodiments can have improved performance.

[0099] The following will refer to Figure 15Here is a brief description of the multi-stage smart SOI dicing process. Wafer 1001 and wafer 200 can be provided. On wafer 200, an oxide layer can be formed, for example, by oxidation, and phosphorus can be implanted into a portion of this oxide layer, for example, by ion implantation or simultaneous phosphorus doping (in situ doping P). Therefore, a stack of a phosphorus-doped oxide layer 1005 and a non-phosphorus-doped buried oxide layer 1003 can be formed on wafer 200. Hydrogen ion implantation can be performed on wafer 200 to define the dicing locations therein. Wafer 200 can be bonded to wafer 1001 with the buried oxide layer 1003 facing the surface of wafer 1001. Wafer 200 is then diced, and the semiconductor layer remaining on wafer 200 is polished to form semiconductor layer 1007. Subsequently, the aforementioned smart dicing process can be performed again on the (single-bonding) SOI substrate thus formed, thereby forming a (multi-bonding) SOI substrate, for example... Figure 1 SOI substrate 100.

[0100] In addition, the work function layer includes metallic materials such as titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), titanium aluminum nitride (TiAl), zirconium aluminum nitride (ZrAl), tungsten aluminum nitride (WAl), tantalum aluminum nitride (TaAl), hafnium aluminum nitride (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto.

[0101] The semiconductor devices according to embodiments of this disclosure can be applied to various electronic devices. For example, integrated circuits (ICs) can be formed based on such semiconductor devices, and electronic devices can be constructed therefrom. Such electronic devices may also include components such as display screens that cooperate with the integrated circuits and wireless transceivers that cooperate with the integrated circuits. Examples of such electronic devices include smartphones, computers, tablet computers, wearable smart devices, artificial intelligence devices, and power banks.

[0102] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0103] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device, comprising: Substrate; The buried oxide layer on the substrate; The channel portion includes at least one semiconductor layer stacked on top of the buried oxide layer at intervals from each other, each of the at least one semiconductor layer including a shell portion and a core portion; Source / drain portion, located above the buried oxygen layer and at opposite ends of the channel portion; as well as The grid stack intersects with the channel portion on the buried oxide layer; The shell is a doped region in the semiconductor layer, and the doping type of the shell is opposite to that of the source / drain. The shell portion is located between the core portion and the gate stack; and / or the shell portion surrounds the core portion.

2. The semiconductor device of claim 1, wherein the core is of a low-doping type and has the same doping type as the source / drain.

3. The semiconductor device according to claim 1, wherein, The channel portion includes multiple semiconductor layers, with a gate stack sandwiched between two adjacent semiconductor layers. The gate stack includes a gate dielectric layer and a work function layer on the gate dielectric layer. The work function layer is not connected to the source / drain portion.

4. The semiconductor device according to claim 1, wherein, The gate stack is disposed on both sides of at least one semiconductor layer and intersects with at least one semiconductor layer, wherein the surface layers on both sides of the at least one semiconductor layer include shell portions.

5. The semiconductor device according to claim 1, wherein, Each of the at least one semiconductor layer has a thickness in the range of 10 nm to 200 nm.

6. The semiconductor device according to claim 1, wherein, The shell has a thickness of 1-10 nm.

7. The semiconductor device according to claim 1, wherein, The channel portion includes multiple semiconductor layers, and the spacing between adjacent semiconductor layers is in the range of 20 nm to 400 nm.

8. The semiconductor device according to claim 7, wherein, The width of the channel between the source and the drain is less than three times the interval, preferably less than twice the interval.

9. The semiconductor device according to claim 1, wherein, Each of the at least one semiconductor layer comprises Si or SiGe.

10. The semiconductor device according to claim 3, wherein, The semiconductor device is configured as a plurality of semiconductor devices, including n-type semiconductor devices and p-type semiconductor devices. Wherein, the channel portion of the n-type semiconductor device includes a p-type doped shell portion, and the work function layer is configured as n-type; and the channel portion of the p-type semiconductor device includes an n-type doped shell portion, and the work function layer is configured as p-type.

11. The semiconductor device according to claim 3, wherein the gate dielectric layer comprises HfO2 and the work function layer comprises TiN.

12. A method for manufacturing a semiconductor device, comprising: Patterning is performed on an SOI substrate and the alternating stacking of multiple semiconductor and oxide layers thereon to form a fin structure, wherein the SOI substrate includes a substrate and a buried oxide layer on the substrate; A sacrificial gate intersecting with the fin structure is formed on the SOI substrate, and a gate sidewall is formed on the sidewall of the sacrificial gate; Source / drain portions are formed on opposite sides of the gate sidewall; Remove the sacrificial gate to expose the alternating stack of the multilayer semiconductor layers and the oxide layers within the space between the gate sidewalls; The oxide layer is removed by selective etching to expose the surface of the semiconductor layer; A doped shell is formed on the exposed surface of the semiconductor layer; and A grid stack is formed in the space between the grid sidewalls; The doping type of the shell is opposite to that of the source / drain.

13. The method according to claim 12, wherein, The SOI substrate is formed through multiple intelligent cutting processes.

14. The method according to claim 12, wherein, Each of the semiconductor layers has a thickness in the range of 10 nm to 200 nm, and each of the oxide layers has a thickness in the range of 20 nm to 400 nm.

15. The method according to claim 12, wherein, A doped shell is formed on the surface of a semiconductor layer by plasma doping.

16. The method according to claim 12, wherein, The fin protrudes relative to the buried oxygen layer, and the method further includes: Shallow trenches are formed between the fin-shaped structures to isolate STI oxide. In the selective etching, the etching rate of the oxide layer is greater than twice the etching rate of the STI oxide.

17. The method according to claim 16, wherein, The oxide layer comprises phosphorus-doped oxide, and the STI comprises high-density plasma-undoped HDP oxide.

18. The method according to claim 12, wherein, The gate stack includes a gate dielectric layer and a work function layer on the gate dielectric layer, wherein the work function layer is not connected to the source / drain. The method includes: forming an n-type doped work function layer for an n-type semiconductor device, and forming a p-type work function layer for a p-type semiconductor device.

19. The method according to claim 12, wherein, Each of the at least one semiconductor layer comprises Si or SiGe.

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