Semiconductor device and semiconductor memory device

Abstract

A semiconductor device having excellent transistor characteristics is provided. A semiconductor device of an embodiment includes a first electrode, a second electrode, an oxide semiconductor layer provided between the first electrode and the second electrode, a gate electrode, a first insulating layer between the first electrode and the gate electrode, a second insulating layer between the gate electrode and the second electrode, and a gate insulating layer between the gate electrode, the first insulating layer, the second insulating layer, and the oxide semiconductor layer. In the case where a thickness of the gate insulating layer between the first insulating layer and the oxide semiconductor layer is a first thickness, a thickness of the gate insulating layer between the second insulating layer and the oxide semiconductor layer is a second thickness, a thickness of the gate insulating layer between a first end portion of the gate electrode on the first electrode side and the oxide semiconductor layer is a third thickness, and a thickness of the gate insulating layer between a second end portion of the gate electrode on the second electrode side and the oxide semiconductor layer is a fourth thickness, the second thickness is thicker than the first thickness, or the fourth thickness is thicker than the third thickness.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and semiconductor memory devices. Background Technology

[0002] Oxide-semiconductor transistors (OSTs) with channels formed in an oxide semiconductor layer possess excellent characteristics such as extremely low channel leakage current during turn-off. Therefore, OSTs can be used, for example, as switching transistors in memory cells of dynamic random access memory (DRAM). Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a semiconductor device with excellent transistor characteristics.

[0004] The semiconductor device of the embodiment includes: a first electrode; a second electrode; an oxide semiconductor layer disposed between the first electrode and the second electrode; a gate electrode opposite to the oxide semiconductor layer; a first insulating layer disposed between the first electrode and the gate electrode; a second insulating layer disposed between the gate electrode and the second electrode; and a gate insulating layer disposed between the gate electrode and the oxide semiconductor layer, between the first insulating layer and the oxide semiconductor layer, and between the second insulating layer and the oxide semiconductor layer, wherein in a first cross-section parallel to a first direction connecting the first electrode and the second electrode, the layer between the first insulating layer and the oxide semiconductor layer is... In the case where the thickness of the gate insulating layer at the first position in the second direction perpendicular to the first direction is set as the first thickness, the thickness of the gate insulating layer at the second position between the second insulating layer and the oxide semiconductor layer in the second direction is set as the second thickness, the thickness of the gate insulating layer at the third position between the first end of the first electrode side of the gate electrode and the oxide semiconductor layer in the second direction is set as the third thickness, and the thickness of the gate insulating layer at the fourth position between the second end of the second electrode side of the gate electrode and the oxide semiconductor layer in the second direction is set as the fourth thickness, the second thickness is thicker than the first thickness, or the fourth thickness is thicker than the third thickness. Attached Figure Description

[0005] Figure 1 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 2 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 3 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 4 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 5 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. Figure 6 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. Figure 7 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. Figure 8 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. Figure 9 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. Figure 10 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. Figure 11 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. Figure 12 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. Figure 13 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. Figure 14 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. Figure 15 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. Figure 16 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. Figure 17 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. Figure 18 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. Figure 19 This is a schematic cross-sectional view of a comparative example semiconductor device. Figure 20 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device, as shown in the comparative example. Figure 21 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device, as shown in the comparative example. Figure 22This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device, as shown in the comparative example. Figure 23 This is a schematic cross-sectional view of a semiconductor device of a first variation of the first embodiment. Figure 24 This is a schematic cross-sectional view of a semiconductor device in a second variation of the first embodiment. Figure 25 This is a schematic cross-sectional view of a semiconductor device in a third variation of the first embodiment. Figure 26 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment. Figure 27 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment. Figure 28 This is a schematic cross-sectional view of a semiconductor device in the first variation of the third embodiment. Figure 29 This is a schematic cross-sectional view of a semiconductor device in a second variation of the third embodiment. Figure 30 This is an equivalent circuit diagram of the semiconductor memory device according to the fourth embodiment. Figure 31 This is a schematic cross-sectional view of the semiconductor memory device according to the fourth embodiment. Detailed Implementation

[0006] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same or similar components will be labeled with the same reference numerals, and descriptions of components already described will sometimes be appropriately omitted.

[0007] Additionally, for convenience, terms such as “upper,” “lower,” “upper part,” or “lower part” are sometimes used in this specification. “Upper,” “lower,” “upper part,” or “lower part” are merely terms used to illustrate the relative positional relationship in the accompanying drawings, and are not terms that specify the positional relationship relative to gravity.

[0008] Qualitative and quantitative analyses of the chemical composition of components constituting semiconductor devices and semiconductor memory devices described in this specification can be performed, for example, by secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectroscopy (EDX), and Rutherford back-scattering spectroscopy (RBS). Furthermore, measurements of the thickness, inter-component distance, and crystal size of components constituting semiconductor devices and semiconductor memory devices can be performed, for example, by transmission electron microscopy (TEM). Additionally, the identification of constituent materials and the measurement of their proportions in semiconductor devices and semiconductor memory devices can be performed, for example, by X-ray photoelectron spectroscopy (XPS), hard X-ray photoelectron spectroscopy (HAXPES), and electron energy loss spectroscopy (EELS).

[0009] In this specification, "metal" is a general term for substances that exhibit metallic properties. For example, metal compounds such as metal nitrides and metal carbides that exhibit metallic properties are also included in the scope of "metal".

[0010] (First Implementation) The semiconductor device according to the first embodiment includes: a first electrode; a second electrode; an oxide semiconductor layer disposed between the first electrode and the second electrode; a gate electrode opposite to the oxide semiconductor layer; a first insulating layer disposed between the first electrode and the gate electrode; a second insulating layer disposed between the gate electrode and the second electrode; and a gate insulating layer disposed between the gate electrode and the oxide semiconductor layer, between the first insulating layer and the oxide semiconductor layer, and between the second insulating layer and the oxide semiconductor layer. In a first cross-section parallel to a first direction connecting the first electrode and the second electrode, if the thickness of the gate insulating layer at a first position between the first insulating layer and the oxide semiconductor layer in a second direction perpendicular to the first direction is set as a first thickness, the thickness of the gate insulating layer at a second position between the second insulating layer and the oxide semiconductor layer in a second direction is set as a second thickness, the thickness of the gate insulating layer at a third position between the first electrode side of the gate electrode and the oxide semiconductor layer in a second direction is set as a third thickness, and the thickness of the gate insulating layer at a fourth position between the second electrode side of the gate electrode and the oxide semiconductor layer in a second direction is set as a fourth thickness, then the second thickness is thicker than the first thickness, or the fourth thickness is thicker than the third thickness.

[0011] Figure 1 , Figure 2 , Figure 3 as well as Figure 4 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 2 yes Figure 1 AA' cross-sectional view. Figure 3 yes Figure 1 BB' cross-sectional view. Figure 4 yes Figure 1 CC' cross-sectional view.

[0012] exist Figure 1 In this context, the up-down direction is referred to as the first direction. Figure 1 In this context, the left-right direction is referred to as the second direction. The second direction is perpendicular to the first direction. The first direction is the direction connecting the lower electrode 12 and the upper electrode 14.

[0013] Figure 1 It is a cross section parallel to the first direction. Figure 1 This is an example of the first section.

[0014] The semiconductor device in the first embodiment is a transistor 100. The transistor 100 is an oxide semiconductor transistor in which a channel is formed in an oxide semiconductor. The transistor 100 is arranged such that a gate electrode surrounds the oxide semiconductor layer in which the channel is formed. The transistor 100 is a so-called Gate All Around (GAA) Transistor. The transistor 100 is a so-called vertical transistor.

[0015] Transistor 100 includes a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, a gate insulating layer 20, a first interlayer insulating layer 22, and a second interlayer insulating layer 24. The gate electrode 18 includes a first portion 18a and a second portion 18b. The first interlayer insulating layer 22 includes a third portion 22a and a fourth portion 22b. The second interlayer insulating layer 24 includes a fifth portion 24a and a sixth portion 24b.

[0016] The lower electrode 12 is an example of a first electrode. The upper electrode 14 is an example of a second electrode. The first interlayer insulating layer 22 is an example of a first insulating layer. The second interlayer insulating layer 24 is an example of a second insulating layer.

[0017] The lower electrode 12 is disposed below the oxide semiconductor layer 16. The lower electrode 12 is electrically connected to the oxide semiconductor layer 16. For example, the lower electrode 12 is connected to the oxide semiconductor layer 16. The lower electrode 12 functions as the source electrode or drain electrode of the transistor 100.

[0018] The lower electrode 12 is a conductor. The lower electrode 12 may contain, for example, an oxide conductor. The lower electrode 12 may be, for example, an oxide conductor layer.

[0019] The lower electrode 12 may contain, for example, indium (In), tin (Sn), and oxygen (O). The lower electrode 12 may contain, for example, indium tin oxide. The lower electrode 12 may be, for example, an indium tin oxide layer.

[0020] The lower electrode 12 may contain, for example, tin (Sn) and oxygen (O). The lower electrode 12 may contain, for example, tin oxide. The lower electrode 12 may be, for example, a tin oxide layer.

[0021] The lower electrode 12 may contain metal, for example. The lower electrode 12 may be a metal layer.

[0022] The lower electrode 12 may contain, for example, tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), zinc (Zn), or tantalum (Ta). The lower electrode 12 may be, for example, a tungsten layer, a molybdenum layer, a copper layer, an aluminum layer, a titanium layer, a zinc layer, or a tantalum layer.

[0023] The lower electrode 12 may also have a stacked structure of multiple conductors. For example, the lower electrode 12 is a stacked structure of an oxide conductor layer and a metal layer. For example, the surface of the lower electrode 12 on the oxide semiconductor layer 16 side is an oxide conductor layer.

[0024] The upper electrode 14 is disposed on the oxide semiconductor layer 16. The upper electrode 14 is electrically connected to the oxide semiconductor layer 16. For example, the upper electrode 14 is connected to the oxide semiconductor layer 16. The upper electrode 14 functions as the source electrode or drain electrode of the transistor 100.

[0025] The upper electrode 14 is a conductor. The upper electrode 14 may contain, for example, an oxide conductor. The upper electrode 14 may be, for example, an oxide conductor layer.

[0026] The upper electrode 14 may contain, for example, indium (In), tin (Sn), and oxygen (O). The upper electrode 14 may contain, for example, indium tin oxide. The upper electrode 14 may be, for example, an indium tin oxide layer.

[0027] The upper electrode 14 may contain, for example, tin (Sn) and oxygen (O). The upper electrode 14 may contain, for example, tin oxide. The upper electrode 14 may be, for example, a tin oxide layer.

[0028] The upper electrode 14 may contain metal, for example. The upper electrode 14 may be a metal layer.

[0029] The upper electrode 14 may contain, for example, tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), titanium (Ti), or tantalum (Ta). The upper electrode 14 may be, for example, a tungsten layer, a molybdenum layer, a copper layer, an aluminum layer, a titanium layer, or a tantalum layer.

[0030] The upper electrode 14 may also have a stacked structure of multiple conductors. For example, the upper electrode 14 may be a stacked structure of an oxide conductor layer and a metal layer. For example, the surface of the upper electrode 14 on the oxide semiconductor layer 16 side is an oxide conductor layer.

[0031] The lower electrode 12 and the upper electrode 14 are formed of the same material, for example. The lower electrode 12 and the upper electrode 14 are, for example, oxide conductors containing indium (In), tin (Sn), and oxygen (O). The lower electrode 12 and the upper electrode 14 are, for example, indium tin oxide. The lower electrode 12 and the upper electrode 14 are, for example, indium tin oxide layers.

[0032] An oxide semiconductor layer 16 is disposed between the lower electrode 12 and the upper electrode 14. The oxide semiconductor layer 16 is, for example, connected to the lower electrode 12. The oxide semiconductor layer 16 is, for example, connected to the upper electrode 14.

[0033] In the oxide semiconductor layer 16, a channel is formed that becomes a current path when the transistor 100 is turned on.

[0034] The oxide semiconductor layer 16 is an oxide semiconductor. The oxide semiconductor layer 16 is, for example, amorphous.

[0035] The oxide semiconductor layer 16, for example, contains at least one element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn), zinc (Zn), and oxygen (O). The oxide semiconductor layer 16, for example, contains indium gallium zinc oxide. The oxide semiconductor layer 16 is, for example, an indium gallium zinc oxide layer.

[0036] The oxide semiconductor layer 16 may contain, for example, at least one element selected from the group consisting of titanium (Ti), zinc (Zn), and tungsten (W) and oxygen (O). The oxide semiconductor layer 16 may contain, for example, titanium oxide, zinc oxide, or tungsten oxide. The oxide semiconductor layer 16 may be, for example, a titanium oxide layer, a zinc oxide layer, or a tungsten oxide layer.

[0037] The oxide semiconductor layer 16, for example, has a chemical composition different from that of the lower electrode 12 and the upper electrode 14.

[0038] The oxide semiconductor layer 16 contains oxygen vacancies. The oxygen vacancies in the oxide semiconductor layer 16 function as donors.

[0039] The length of the oxide semiconductor layer 16 in the first direction is, for example, 40 nm or more and 200 nm or less. The length of the oxide semiconductor layer 16 in the second direction is, for example, 10 nm or more and 100 nm or less.

[0040] The first width in the second direction of the portion of the oxide semiconductor layer 16 that is in contact with the lower electrode 12 ( Figure 1 w1) for example, the second width in the second direction of the portion of the oxide semiconductor layer 16 that is in contact with the upper electrode 14. Figure 1 The w2 in the two cases are essentially equal.

[0041] The gate electrode 18 is opposite to the oxide semiconductor layer 16. The gate electrode 18 is configured such that its position coordinate in the first direction is a value between the position coordinates in the first direction of the lower electrode 12 and the upper electrode 14, respectively.

[0042] like Figure 2 As shown, the gate electrode 18 is disposed surrounding the oxide semiconductor layer 16. The gate electrode 18 is disposed around the oxide semiconductor layer 16.

[0043] The gate electrode 18 is a conductor. The gate electrode 18 is, for example, a metal, a metal compound, or a semiconductor. The gate electrode 18 may contain, for example, tungsten (W).

[0044] The length of the gate electrode 18 in the first direction is, for example, more than 10 nm and less than 100 nm.

[0045] The gate electrode 18 includes a first portion 18a and a second portion 18b in a cross section parallel to the first direction. In the second direction, an oxide semiconductor layer 16 is disposed between the first portion 18a and the second portion 18b.

[0046] The gate electrode 18 has a first end E1 on the side of the lower electrode 12 and a second end E2 on the side of the upper electrode 14.

[0047] A gate insulating layer 20 is disposed between the gate electrode 18 and the oxide semiconductor layer 16. For example... Figure 2 As shown, the gate insulating layer 20 surrounds the oxide semiconductor layer 16. The gate insulating layer 20 is disposed between the lower electrode 12 and the upper electrode 14.

[0048] A gate insulating layer 20 is disposed between the first interlayer insulating layer 22 and the oxide semiconductor layer 16. A gate insulating layer 20 is disposed between the second interlayer insulating layer 24 and the oxide semiconductor layer 16.

[0049] The gate insulating layer 20 is, for example, connected to the lower electrode 12. The gate insulating layer 20 is, for example, connected to the upper electrode 14. The gate insulating layer 20 is, for example, separated from the lower electrode 12. The gate insulating layer 20 is, for example, separated from the upper electrode 14.

[0050] The gate insulating layer 20 is, for example, an oxide, a nitride, or an oxide oxynitride. The gate insulating layer 20 may comprise, for example, silicon oxide, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, silicon nitride, aluminum nitride, or silicon oxynitride. The gate insulating layer 20 may be, for example, a silicon oxide layer, an aluminum oxide layer, a titanium oxide layer, a tantalum oxide layer, a hafnium oxide layer, a silicon nitride layer, an aluminum nitride layer, or a silicon oxynitride layer.

[0051] The gate insulating layer 20 may also have a stacked structure, for example. The thickness of the gate insulating layer 20 is, for example, 2 nm or more and 10 nm or less.

[0052] In the first cross-section, the first position between the first interlayer insulating layer 22 and the oxide semiconductor layer 16 ( Figure 1 The thickness of the gate insulating layer 20 in the second direction of P1 is defined as the first thickness (in the first direction). Figure 1 In t1), the second position between the second interlayer insulating layer 24 and the oxide semiconductor layer 16 ( Figure 1 The thickness of the gate insulating layer 20 in the second direction of P2) is defined as the second thickness. Figure 1 t2), the first end of the lower electrode 12 side of the gate electrode 18 ( Figure 1 The third position between E1 and oxide semiconductor layer 16 (in the middle) Figure 1 The thickness of the gate insulating layer 20 in the second direction of P3 is defined as the third thickness. Figure 1 t3), the second end of the upper electrode 14 side of the gate electrode 18 ( Figure 1 The fourth position between E2 and oxide semiconductor layer 16 (in the middle) Figure 1 The thickness of the gate insulating layer 20 in the second direction of P4 is defined as the fourth thickness. Figure 1 (t4 in the text).

[0053] The second thickness t2 is greater than the first thickness t1, or the fourth thickness t4 is greater than the third thickness t3. Figure 1 The figure shows the case where the second thickness t2 is thicker than the first thickness t1, and the fourth thickness t4 is thicker than the third thickness t3.

[0054] The second thickness t2 is, for example, more than 1.1 times and less than 1.5 times the first thickness t1. Furthermore, the fourth thickness t4 is, for example, more than 1.1 times and less than 1.5 times the third thickness t3.

[0055] The gate insulating layer 20 of transistor 100 is thicker near the upper electrode 14 than near the lower electrode 12. The thickness of the gate insulating layer 20 increases, for example, in the direction from the lower electrode 12 toward the upper electrode 14.

[0056] A first interlayer insulating layer 22 is disposed between the lower electrode 12 and the gate electrode 18. The first interlayer insulating layer 22 includes a third portion 22a and a fourth portion 22b on a first surface. In a second direction, an oxide semiconductor layer 16 is disposed between the third portion 22a and the fourth portion 22b. In the second direction, a gate insulating layer 20 is disposed between the third portion 22a and the fourth portion 22b.

[0057] like Figure 3 As shown, the first interlayer insulating layer 22 surrounds the gate insulating layer 20 and the oxide semiconductor layer 16.

[0058] The first interlayer insulating layer 22 is connected to the gate insulating layer 20. The third part 22a is connected to the gate insulating layer 20. The fourth part 22b is connected to the gate insulating layer 20. The first interlayer insulating layer 22 is connected to the lower electrode 12.

[0059] A second interlayer insulating layer 24 is disposed between the gate electrode 18 and the upper electrode 14. The second interlayer insulating layer 24 includes a fifth portion 24a and a sixth portion 24b on a first surface. In a second direction, an oxide semiconductor layer 16 is disposed between the fifth portion 24a and the sixth portion 24b. In the second direction, a gate insulating layer 20 is disposed between the fifth portion 24a and the sixth portion 24b.

[0060] like Figure 4 As shown, the second interlayer insulating layer 24 surrounds the gate insulating layer 20 and the oxide semiconductor layer 16.

[0061] The second interlayer insulating layer 24 is connected to the gate insulating layer 20. The fifth part 24a is connected to the gate insulating layer 20. The sixth part 24b is connected to the gate insulating layer 20. The second interlayer insulating layer 24 is connected to the upper electrode 14.

[0062] The first interlayer insulating layer 22 and the second interlayer insulating layer 24 are insulators. The first interlayer insulating layer 22 and the second interlayer insulating layer 24 are, for example, oxides, nitrides, or oxynitrides. The first interlayer insulating layer 22 and the second interlayer insulating layer 24 may contain, for example, silicon (Si) and oxygen (O). The first interlayer insulating layer 22 and the second interlayer insulating layer 24 may contain, for example, silicon oxide. The first interlayer insulating layer 22 and the second interlayer insulating layer 24 may contain, for example, silicon oxide. The first interlayer insulating layer 22 and the second interlayer insulating layer 24 may contain, for example, silicon nitride. The first interlayer insulating layer 22 and the second interlayer insulating layer 24 may be, for example, silicon nitride.

[0063] The first interlayer insulation layer 22 and the second interlayer insulation layer 24 can also be formed of different materials.

[0064] The first distance in the second direction between the portion of the third part 22a that is in contact with the lower electrode 12 and the portion of the fourth part 22b that is in contact with the lower electrode 12. Figure 1 d1) is less than the second distance in the second direction between the portion of the fifth part 24a that is in contact with the upper electrode 14 and the portion of the sixth part 24b that is in contact with the upper electrode 14. Figure 1 (d2 in the text). On the first surface, the outer boundary of the gate insulating layer 20 extends from the lower electrode 12 toward the upper electrode 14. The outer boundary of the gate insulating layer 20 has a so-called positive cone shape.

[0065] Next, an example of the manufacturing method of the semiconductor device according to the first embodiment will be described.

[0066] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 and Figure 18 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first embodiment. Figures 5 to 18 Show respectively with Figure 1 The corresponding cross section. Figures 5 to 18 This is a diagram illustrating an example of a method for manufacturing transistor 100.

[0067] The following explanation will be based on the case where the lower electrode 12 of the transistor 100 is an indium tin oxide layer, the upper electrode 14 is an indium tin oxide layer, the oxide semiconductor layer 16 is an indium gallium zinc oxide layer, the gate electrode 18 is a tungsten layer, the gate insulating layer 20 is a silicon oxide layer, and the first interlayer insulating layer 22 and the second interlayer insulating layer 24 are silicon oxide layers.

[0068] First, a first silicon oxide film 31, a tungsten film 32, and a second silicon oxide film 33 are formed on the first indium tin oxide film 30. Figure 5 The first silicon oxide film 31, the tungsten film 32, and the second silicon oxide film 33 are formed, for example, by chemical vapor deposition (CVD).

[0069] The first indium tin oxide film 30 ultimately becomes the lower electrode 12. A portion of the first silicon oxide film 31 ultimately becomes the first interlayer insulating layer 22. A portion of the tungsten film 32 ultimately becomes the gate electrode 18. A portion of the second silicon oxide film 33 ultimately becomes the second interlayer insulating layer 24.

[0070] Next, an opening 34 is formed that extends from the surface of the second silicon oxide film 33 through the tungsten film 32, the first silicon oxide film 31, and reaches the first indium tin oxide film 30. Figure 6 The opening 34, for example, has a conical shape in which the opening diameter decreases toward the first indium tin oxide film 30. The opening 34 is formed, for example, using photolithography and Reactive Ion Etching (RIE).

[0071] Next, a first silicon nitride film 35 is formed inside the opening 34. Figure 7 The first silicon nitride film 35 is formed, for example, by the Atomic Layer Deposition (ALD) method.

[0072] Next, a second silicon nitride film 36 is formed inside the opening 34. Figure 8 The second silicon nitride film 36 is formed, for example, by a CVD method with a lower step coverage than the ALD method. The second silicon nitride film 36 is formed such that the film thickness at the upper part of the opening 34 is greater than the film thickness at the lower part of the opening 34.

[0073] Next, the first silicon nitride film 35 at the bottom of the opening 34 is etched to expose the first indium tin oxide film 30. Figure 9 The first silicon nitride film 35 was etched using the RIE method.

[0074] During the etching of the first silicon nitride film 35, processing damage is applied because the surfaces of the second silicon nitride film 36 and the first silicon nitride film 35 are exposed to the RIE.

[0075] Next, the opening 34 is filled with a titanium nitride film 37. Figure 10 Titanium nitride film 37 is formed, for example, by the ALD method. Alternatively, if the selectivity ratio with silicon nitride can be ensured when the first silicon nitride film 35 and the second silicon nitride film 36 are removed by etching in subsequent process steps, an aluminum oxide film may be used instead of titanium nitride film 37.

[0076] Next, the upper part of the titanium nitride film 37 is removed, leaving only the titanium nitride film 37 in the opening 34. Figure 11 The removal of the upper part of the titanium nitride film 37 is carried out, for example, by chemical mechanical polishing (CMP).

[0077] Next, the first silicon nitride film 35 and the second silicon nitride film 36 are removed by etching. Figure 12 The titanium nitride film 37 remains in the opening 34 in a columnar shape. The first silicon nitride film 35 and the second silicon nitride film 36 are removed, for example, by wet etching.

[0078] Next, the opening 34 is filled with a third silicon oxide film 38. Figure 13 A third silicon oxide film 38 is formed in the region where the second silicon nitride film 36 and the first silicon nitride film 35 have been removed. The third silicon oxide film 38 is formed, for example, by the ALD method. Because the opening 34 is wider at the top than at the bottom, the filling capacity of the third silicon oxide film 38 is improved. A portion of the third silicon oxide film 38 eventually becomes the gate insulating layer 20.

[0079] Next, the upper part of the third silicon oxide film 38 is removed, leaving only the third silicon oxide film 38 in the opening 34. Figure 14 The removal of the upper part of the third silica film 38 is carried out, for example, using the CMP method.

[0080] Next, the columnar titanium nitride film 37 in the opening 34 is removed. Figure 15 The titanium nitride film 37 can be removed, for example, using a wet etching method.

[0081] Next, the opening 34 is filled with an indium gallium zinc oxide film 39. Figure 16 The indium gallium zinc oxide film 39 is formed, for example, by the ALD method. A portion of the indium gallium zinc oxide film 39 eventually becomes the oxide semiconductor layer 16.

[0082] Next, the upper part of the indium gallium zinc oxide film 39 is removed, leaving only the indium gallium zinc oxide film 39 in the opening 34. Figure 17 The removal of the upper part of the indium gallium zinc oxide film 39 is performed, for example, using the CMP method.

[0083] Next, a second indium tin oxide film 40 is formed on the indium gallium zinc oxide film 39. Figure 18 The second indium tin oxide film 40 is formed, for example, by sputtering. The second indium tin oxide film 40 ultimately becomes the upper electrode 14.

[0084] Using the manufacturing methods described above, the following products were manufactured: Figures 1 to 4 The transistor 100 shown.

[0085] The function and effects of the semiconductor device according to the first embodiment will be explained below.

[0086] Oxide-semiconductor (OSB) transistors, which form channels within an oxide semiconductor layer, possess excellent characteristics such as extremely low channel leakage current during turn-off. Therefore, OSB transistors are being studied, for example, as switching transistors for DRAM memory cells. Because of the extremely low channel leakage current during turn-off, the charge retention characteristics of DRAM are improved by incorporating OSB transistors into switching transistors.

[0087] Figure 19 This is a schematic cross-sectional view of a comparative example semiconductor device. Figure 19 It is the semiconductor device of the first embodiment. Figure 1 The corresponding diagram.

[0088] The comparative example semiconductor device is transistor 900. Transistor 900 is an oxide semiconductor transistor. Transistor 900 differs from transistor 100 of the first embodiment in that the first thickness t1, second thickness t2, third thickness t3, and fourth thickness t4 of the gate insulating layer 20 are equal. Transistor 900 also differs from transistor 100 in that the thickness of the gate insulating layer 20 in the second direction in the first cross-section is constant between the lower electrode 12 and the upper electrode 14.

[0089] Figure 20 , Figure 21 as well as Figure 22 This is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device, as shown in the comparative example. Figure 20 , Figure 21 as well as Figure 22 Show respectively with Figure 19 The corresponding cross section. Figure 20 , Figure 21 as well as Figure 22 This is a diagram illustrating an example of a manufacturing method for transistor 900.

[0090] The manufacturing method of the transistor 900 in the comparative example is the same as the manufacturing method of the semiconductor device in the first embodiment before forming the opening 34 that extends from the surface of the second silicon oxide film 33 through the tungsten film 32, the first silicon oxide film 31 and to the first indium tin oxide film 30.

[0091] Next, a silicon oxide film 42 is formed inside the opening 34. Figure 20 The silicon oxide film 42 is formed, for example, by the ALD process. A portion of the silicon oxide film 42 eventually becomes the gate insulating layer 20.

[0092] Next, the silicon oxide film 42 at the bottom of the opening 34 is etched to expose the first indium tin oxide film 30. Figure 21 The silicon oxide film 42 was etched using the RIE method.

[0093] When etching the silicon oxide film 42, processing damage is applied because the surface of the silicon oxide film 42 is exposed to the RIE.

[0094] Then, similar to the manufacturing method of the first embodiment, the opening 34 is filled with an indium gallium zinc oxide film 39, and a second indium tin oxide film 40 is formed on the indium gallium zinc oxide film 39. Figure 22 ).

[0095] Using the manufacturing methods described above, the following products were manufactured: Figure 19 The transistor 900 is shown.

[0096] In the manufacturing method of the comparative example transistor 900, when etching the silicon oxide film 42 at the bottom of the opening 34, the surface of the silicon oxide film 42, which forms the gate insulating layer 20, is exposed to the etching, resulting in processing damage. Therefore, the reliability of the gate insulating layer 20 of the transistor 900, for example, is reduced.

[0097] In the transistor 100 of the first embodiment, the thickness of the gate insulating layer 20 is thicker near the upper electrode 14 than near the lower electrode 12. By making the thickness of the gate insulating layer 20 thicker near the upper electrode 14 than near the lower electrode 12, a method for manufacturing a transistor with improved reliability of the gate insulating layer 20 can be achieved.

[0098] In the manufacturing method of the transistor 100 of the first embodiment, a first silicon nitride film 35 and a second silicon nitride film 36 are formed inside the opening 34. Figure 8 Then, the first silicon nitride film 35 at the bottom of the opening 34 is etched to expose the first indium tin oxide film 30. Figure 9 At this time, since the surfaces of the second silicon nitride film 36 and the first silicon nitride film 35 are exposed to the RIE, processing damage will be applied. However, since the second silicon nitride film 36 and the first silicon nitride film 35 will... Figure 12 It is removed as shown and therefore will not be used for the gate insulating layer 20.

[0099] In the transistor 100 of the first embodiment, a third silicon oxide film 38 is formed in the region where the second silicon nitride film 36 and the first silicon nitride film 35 have been removed. Figure 13The third silicon oxide film 38 is used as the gate insulating layer 20. The portion of the gate insulating layer 20 used as the third silicon oxide film 38 is not exposed to the RIE and is not subject to processing damage. Therefore, the reliability of the gate insulating layer 20 of the transistor 100 is improved compared to the transistor 900 of the comparative example.

[0100] In the transistor 100 of the first embodiment, the gate insulating layer 20 near the upper electrode 14 is thicker than the gate insulating layer 20 near the lower electrode 12. Therefore, in the manufacturing method of the transistor 100, the opening 34 when the third silicon oxide film 38 is buried is wider at the top than at the bottom. Figure 12 Therefore, the filling properties of the third silicon oxide film 38 are improved. Thus, for example, it is possible to avoid situations where the third silicon oxide film 38 cannot be filled between the gate electrode 18 and the oxide semiconductor layer 16, resulting in the failure to form the gate insulating layer 20.

[0101] Furthermore, in the transistor 100 of the first embodiment, the gate insulating layer 20 near the upper electrode 14 is thicker than the gate insulating layer 20 near the lower electrode 12. Therefore, for example, for the conduction current flowing between the lower electrode 12 and the upper electrode 14, the asymmetry caused by the direction of the current can be adjusted.

[0102] In transistor 100, the fourth thickness t4 of the gate insulating layer 20 between the second end E2 of the gate electrode 18 and the oxide semiconductor layer 16 is thicker than the third thickness t3 of the gate insulating layer 20 between the first end E1 of the gate electrode 18 and the oxide semiconductor layer 16. Therefore, for example, the channel resistance directly below the second end E2 of the gate electrode 18 is higher than the channel resistance directly below the first end E1 of the gate electrode 18.

[0103] Furthermore, the second thickness t2 of the gate insulating layer 20 between the second interlayer insulating layer 24 and the oxide semiconductor layer 16 is thicker than the first thickness t1 of the gate insulating layer 20 between the first interlayer insulating layer 22 and the oxide semiconductor layer 16. Therefore, the intensity of the edge electric field applied from the gate electrode 18 is weaker in the oxide semiconductor layer 16 between the gate electrode 18 and the upper electrode 14 than in the oxide semiconductor layer 16 between the gate electrode 18 and the lower electrode 12. Therefore, for example, the parasitic resistance of the oxide semiconductor layer 16 between the gate electrode 18 and the upper electrode 14 is greater than the parasitic resistance of the oxide semiconductor layer 16 between the gate electrode 18 and the lower electrode 12.

[0104] Based on the above viewpoint, when transistor 100 is in the ON state, for example, electrons have difficulty flowing from the upper electrode 14 to the lower electrode 12. In other words, in transistor 100, when in the ON state, for example, an asymmetry in the conduction current occurs, such as current having difficulty flowing from the lower electrode 12 to the upper electrode 14.

[0105] For example, if there is a difference between the contact resistance between the lower electrode 12 and the oxide semiconductor layer 16 and the contact resistance between the upper electrode 14 and the oxide semiconductor layer 16, electrons may easily flow from the lower electrode 12 to the upper electrode 14 when the transistor is in the on state. In this case, an asymmetry in the conduction current will occur, making it difficult for current to flow from the upper electrode 14 to the lower electrode 12.

[0106] In the transistor 100 of the first embodiment, for example, by utilizing the asymmetry of the conduction current that can be achieved through the difference in film thickness of the gate insulating layer 20, the asymmetry of the conduction current generated by the contact resistance between the lower electrode 12 and the upper electrode 14 and the oxide semiconductor layer 16 can be offset. Therefore, according to the transistor 100 of the first embodiment, the asymmetry of the conduction current can be suppressed. In addition, when the magnitude of the conduction current of the transistor 100 requires asymmetry, the asymmetry of the conduction current can be achieved. Thus, according to the transistor 100, the asymmetry of the conduction current can be adjusted.

[0107] According to the first embodiment, the reliability of the gate insulating layer 20 is improved, and a semiconductor device with excellent transistor characteristics is realized.

[0108] (First variation) The semiconductor device of the first variation of the first embodiment differs from the semiconductor device of the first embodiment in that the first width in the second direction of the portion of the oxide semiconductor layer in the first cross section that is in contact with the first electrode is smaller than the second width in the second direction of the portion of the oxide semiconductor layer in the first cross section that is in contact with the second electrode.

[0109] Figure 23 This is a schematic cross-sectional view of a semiconductor device of a first variation of the first embodiment. Figure 23 It is the same as the first embodiment. Figure 1 The corresponding diagram.

[0110] The semiconductor device in the first variation of the first embodiment is a transistor 101. The first width in the second direction of the portion of the oxide semiconductor layer 16 that is in contact with the lower electrode 12 ( Figure 23 The width (w1) in the second direction of the portion of the oxide semiconductor layer 16 that is in contact with the upper electrode 14 is smaller than the width (w1) in the second direction. Figure 23 (w2 in the text). The width of the oxide semiconductor layer 16 increases, for example, from the lower electrode 12 toward the upper electrode 14. The oxide semiconductor layer 16 has a so-called positive cone shape.

[0111] According to the transistor 101 of the first variant of the first embodiment, the reliability of the gate insulating layer 20 is improved, similar to that of the transistor 100 of the first embodiment. Furthermore, the contact area between the upper electrode 14 and the oxide semiconductor layer 16 can be made larger than the contact area between the lower electrode 12 and the oxide semiconductor layer 16. Therefore, for example, the contact resistance between the upper electrode 14 and the oxide semiconductor layer 16 can be reduced.

[0112] The fourth thickness t4 of the gate insulating layer 20 between the second end E2 of the gate electrode 18 and the oxide semiconductor layer 16 is thicker than the third thickness t3 of the gate insulating layer 20 between the first end E1 of the gate electrode 18 and the oxide semiconductor layer 16. Therefore, for example, if the oxide semiconductor layer 16 does not have a tapered shape, the channel resistance directly below the second end E2 of the gate electrode 18 is higher than the channel resistance directly below the first end E1 of the gate electrode 18. In other words, an asymmetry in the channel resistance occurs. Therefore, for example, an asymmetry in the conduction current may sometimes occur.

[0113] According to transistor 101, since the oxide semiconductor layer 16 has a positive conical shape, the area of ​​the oxide semiconductor layer 16 opposite to the second end E2 of the gate electrode 18 can be made larger than the area of ​​the oxide semiconductor layer 16 opposite to the first end E1 of the gate electrode 18 on the plane perpendicular to the first direction. Therefore, the asymmetry of the channel resistance is mitigated, and the asymmetry of the conduction current is suppressed.

[0114] According to the first variation of the first embodiment, similarly to the first embodiment, the reliability of the gate insulating layer 20 is improved, and a semiconductor device with excellent transistor characteristics is realized.

[0115] (Second variation) The semiconductor device of the second variation of the first embodiment differs from the semiconductor device of the first embodiment in that the first width in the second direction of the portion of the oxide semiconductor layer in the first cross section that is in contact with the first electrode is greater than the second width in the second direction of the portion of the oxide semiconductor layer in the first cross section that is in contact with the second electrode.

[0116] Figure 24 This is a schematic cross-sectional view of a semiconductor device in a second variation of the first embodiment. Figure 24 It is the same as the first embodiment. Figure 1 The corresponding diagram.

[0117] The semiconductor device in the second variation of the first embodiment is a transistor 102. The first width in the second direction of the portion of the oxide semiconductor layer 16 that is in contact with the lower electrode 12 ( Figure 24 The width of w1 in the second direction of the portion of the oxide semiconductor layer 16 that is in contact with the upper electrode 14 is greater than the width of w1 in the second direction. Figure 24 (w2 in the text). The width of the oxide semiconductor layer 16 decreases, for example, from the lower electrode 12 toward the upper electrode 14. The oxide semiconductor layer 16 has a so-called inverted conical shape.

[0118] According to the transistor 102 of the second variation of the first embodiment, the reliability of the gate insulating layer 20 is improved, similar to that of the transistor 100 of the first embodiment. Furthermore, the contact area between the lower electrode 12 and the oxide semiconductor layer 16 can be made larger than the contact area between the upper electrode 14 and the oxide semiconductor layer 16. Therefore, for example, the contact resistance between the lower electrode 12 and the oxide semiconductor layer 16 can be reduced.

[0119] According to the second variation of the first embodiment, similarly to the first embodiment, the reliability of the gate insulating layer 20 is improved, and a semiconductor device with excellent transistor characteristics is realized.

[0120] (Third variation) The semiconductor device of the third variation of the first embodiment differs from the semiconductor device of the first embodiment in that the gate insulating layer disposed between the first insulating layer and the oxide semiconductor layer has a void.

[0121] Figure 25 This is a schematic cross-sectional view of a semiconductor device in a third variation of the first embodiment. Figure 25 It is the same as the first embodiment. Figure 1 The corresponding diagram.

[0122] The semiconductor device in the third variation of the first embodiment is a transistor 103. In the transistor 103, the gate insulating layer 20 between the first interlayer insulating layer 22 and the oxide semiconductor layer 16 has a void 44. The gate insulating layer 20 between the gate electrode 18 and the lower electrode 12 also has a void 44. For example, in the manufacturing method of the semiconductor device of the first embodiment, a void can be formed in the gate insulating layer 20 by adjusting the film formation conditions of the third silicon oxide film 38 that ultimately becomes the gate insulating layer 20.

[0123] There are no voids 44 in the gate insulating layer 20 between the second interlayer insulating layer 24 and the oxide semiconductor layer 16, and in the gate insulating layer 20 between the gate electrode 18 and the oxide semiconductor layer 16.

[0124] The second thickness t2 of the gate insulating layer 20 between the second interlayer insulating layer 24 and the oxide semiconductor layer 16 is thicker than the first thickness t1 of the gate insulating layer 20 between the first interlayer insulating layer 22 and the oxide semiconductor layer 16. Therefore, for example, if there are no gaps in the gate insulating layer 20 between the first interlayer insulating layer 22 and the oxide semiconductor layer 16, the intensity of the edge electric field applied from the gate electrode 18 is weaker in the oxide semiconductor layer 16 between the gate electrode 18 and the upper electrode 14 than in the oxide semiconductor layer 16 between the gate electrode 18 and the lower electrode 12.

[0125] Therefore, for example, the parasitic resistance of the oxide semiconductor layer 16 between the gate electrode 18 and the upper electrode 14 is greater than the parasitic resistance of the oxide semiconductor layer 16 between the gate electrode 18 and the lower electrode 12. Thus, the parasitic resistance of the transistor results in top-to-bottom asymmetry.

[0126] In the transistor 103 of the third variation of the first embodiment, a gap 44 is provided in the gate insulating layer 20 between the first interlayer insulating layer 22 and the oxide semiconductor layer 16. The dielectric constant of the gap is, for example, lower than that of the oxide or nitride. Therefore, compared with the case where there is no gap 44 in the gate insulating layer 20, the intensity of the edge electric field applied to the oxide semiconductor layer 16 between the gate electrode 18 and the lower electrode 12 is weakened. Therefore, for example, the difference between the parasitic resistance of the oxide semiconductor layer 16 between the gate electrode 18 and the upper electrode 14 and the parasitic resistance of the oxide semiconductor layer 16 between the gate electrode 18 and the lower electrode 12 is reduced. Therefore, the vertical asymmetry of the parasitic resistance of the transistor is suppressed.

[0127] According to the transistor 103 of the third variation of the first embodiment, the reliability of the gate insulating layer 20 is improved, similar to that of the transistor 100 of the first embodiment. In addition, by making the gate insulating layer 20 between the gate electrode 18 and the lower electrode 12 have a gap 44, the vertical asymmetry of the parasitic resistance of the transistor 103 is suppressed.

[0128] According to the third variation of the first embodiment, similarly to the first embodiment, the reliability of the gate insulating layer 20 is improved, and a semiconductor device with excellent transistor characteristics is realized.

[0129] Based on the first embodiment and its variations, the reliability of the gate insulating layer 20 is improved, and a semiconductor device with excellent transistor characteristics is realized.

[0130] (Second Implementation) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the gate insulating layer disposed between the second insulating layer and the oxide semiconductor layer, and the gate insulating layer disposed between the gate electrode and the oxide semiconductor layer, contain materials different from those of the gate insulating layer disposed between the first insulating layer and the oxide semiconductor layer. Hereinafter, descriptions that are repeated in the first embodiment will sometimes be omitted.

[0131] Figure 26 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment. Figure 26 It is the same as the first embodiment. Figure 1 The corresponding diagram.

[0132] The semiconductor device in the second embodiment is a transistor 200. In the transistor 200, the gate insulating layer 20 disposed between the second interlayer insulating layer 24 and the oxide semiconductor layer 16, and the gate insulating layer 20 disposed between the gate electrode 18 and the oxide semiconductor layer 16, contain materials different from those of the gate insulating layer 20 disposed between the first interlayer insulating layer 22 and the oxide semiconductor layer 16.

[0133] Figure 26 The first region 20a shown is a portion of the gate insulating layer 20 disposed between the first interlayer insulating layer 22 and the oxide semiconductor layer 16. The second region 20b is a portion of the gate insulating layer 20 disposed between the second interlayer insulating layer 24 and the oxide semiconductor layer 16. The third region 20c is a portion of the gate insulating layer 20 disposed between the gate electrode 18 and the oxide semiconductor layer 16. The second region 20b and the third region 20c contain materials different from those of the first region 20a.

[0134] The first region 20a, for example, contains silicon nitride. The first region 20a is formed of silicon nitride, for example. Additionally, the second region 20b, for example, contains silicon oxide. The second region 20b is formed of silicon oxide, for example. The third region 20c, for example, contains silicon oxide. The third region 20c is formed of silicon oxide, for example.

[0135] The transistor 200 of the second embodiment can be formed, for example, by etching away the first silicon nitride film 35 and the second silicon nitride film 36 in the manufacturing method of the semiconductor device of the first embodiment. Figure 12 When the first silicon nitride film 35 is left in the opening 34, a portion of it remains.

[0136] For example, by making the second region 20b contain a material with a different dielectric constant than the first region 20a, the strength of the edge electric field between the gate electrode 18 and the oxide semiconductor layer 16 can be adjusted. Therefore, by adjusting, for example, the difference between the parasitic resistance of the oxide semiconductor layer 16 between the gate electrode 18 and the upper electrode 14, and the difference between the parasitic resistance of the oxide semiconductor layer 16 between the gate electrode 18 and the lower electrode 12, optimal transistor characteristics can be achieved.

[0137] According to the second embodiment, the reliability of the gate insulating layer 20 is improved, and a semiconductor device with excellent transistor characteristics is realized.

[0138] (Third Implementation) The semiconductor device of the third embodiment differs from the semiconductor device of the first embodiment in the following aspects: the gate insulating layer includes a first film and a second film, the first film being disposed between the gate electrode and the oxide semiconductor layer and containing a first material; the second film being disposed between the first film and the oxide semiconductor layer and containing a second material different from the first material; the gate insulating layer further includes a third film, the third film being disposed between the second film and the oxide semiconductor layer and containing the first material. Hereinafter, descriptions that are repeated in the first embodiment will sometimes be omitted.

[0139] Figure 27 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment. Figure 27 It is the same as the first embodiment. Figure 1 The corresponding diagram.

[0140] The semiconductor device in the third embodiment is a transistor 300. The gate insulating layer 20 of the transistor 300 includes a first film 20x, a second film 20y, and a third film 20z. The gate insulating layer 20 of the transistor 300 includes a stacked film of the first film 20x, the second film 20y, and the third film 20z.

[0141] The first film 20x and the second film 20y, and the second film 20y and the third film 20z are, for example, connected to each other. The first film 20x and the third film 20z are, for example, physically continuous on the lower electrode 12 side of the gate insulating layer 20.

[0142] The first membrane 20x contains a first material. The second membrane 20y contains a second material. The third membrane 20z contains a first material. The first membrane 20x and the third membrane 20z contain the same material.

[0143] The first membrane 20x is formed, for example, from a first material. The second membrane 20y is formed, for example, from a second material. The third membrane 20z is formed, for example, from a first material. The first membrane 20x and the third membrane 20z are formed, for example, from the same material.

[0144] The first material is, for example, an oxide, a nitride, or a nitrogen oxide. Examples of the first material include silicon oxide, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, silicon nitride, aluminum nitride, or silicon oxynitride.

[0145] The second material is a material different from the first material. The third material is, for example, an oxide, a nitride, or a nitrogen oxide. The first material is, for example, silicon oxide, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, silicon nitride, aluminum nitride, or silicon oxynitride.

[0146] For example, the first material is a nitride, and the second material is an oxide. For example, the first material is silicon nitride, and the second material is silicon oxide.

[0147] The second material is, for example, a material having a higher dielectric constant than the first material. The second material is, for example, a material having a higher dielectric constant than silicon oxide. For example, the first material is silicon oxide, and the second material is titanium oxide. For example, the first material is silicon nitride, and the second material is titanium oxide.

[0148] In the case where the second material is a material with a higher dielectric constant than the first material, for example, in the first cross-section, the fifth thickness of the second film 20y between the first end E1 of the gate electrode 18 and the oxide semiconductor layer 16 ( Figure 27 The sixth thickness of the second film 20y between the second end E2 of the gate electrode 18 and the oxide semiconductor layer 16 is (t5) Figure 27 t6) thin.

[0149] In transistor 300, the fourth thickness t4 of the gate insulating layer 20 between the second end E2 of the gate electrode 18 and the oxide semiconductor layer 16 is thicker than the third thickness t3 of the gate insulating layer 20 between the first end E1 of the gate electrode 18 and the oxide semiconductor layer 16. Therefore, for example, the channel resistance directly below the second end E2 of the gate electrode 18 is higher than the channel resistance directly below the first end E1 of the gate electrode 18.

[0150] However, in transistor 300, by using a material with a higher dielectric constant than the first material to form the second material, and making the fifth thickness t5 of the second film 20y thinner than the sixth thickness t6 of the second film 20y, the difference between the equivalent oxide thickness (EOT) of the gate insulating layer 20 at the fourth position P4 and the equivalent oxide thickness of the gate insulating layer 20 at the third position P3 can be reduced. Therefore, the difference between the channel resistance directly below the second end E2 of the gate electrode 18 and the channel resistance directly below the first end E1 of the gate electrode 18 can be reduced.

[0151] The transistor 300 of the third embodiment can be manufactured, for example, by using a laminated film instead of the third silicon oxide film 38 when the opening 34 is filled with the third silicon oxide film 38 that eventually becomes the gate insulating layer 20 in the semiconductor device manufacturing method of the first embodiment.

[0152] The transistor 300 in the third embodiment, like that in the first embodiment, improves the reliability of the gate insulating layer 20. Furthermore, by using a multilayer film in the gate insulating layer 20, the transistor characteristics of 300 are further improved.

[0153] (First variation) The semiconductor device of the first variant of the third embodiment differs from the semiconductor device of the third embodiment in that the first film is separated from the first electrode.

[0154] Figure 28 This is a schematic cross-sectional view of a semiconductor device in the first variation of the third embodiment. Figure 28 It is the same as the third embodiment. Figure 27 The corresponding diagram.

[0155] The semiconductor device in the first variation of the third embodiment is a transistor 301. In addition to the first film 20x, the second film 20y, and the third film 20z, the gate insulating layer 20 of the transistor 301 also includes a fourth film 20w.

[0156] The first membrane 20x is separated from the lower electrode 12 in a first direction. The second membrane 20y is separated from the lower electrode 12 in a first direction. The third membrane 20z is separated from the lower electrode 12 in a first direction.

[0157] A fourth membrane 20w is disposed between the first membrane 20x and the lower electrode 12. A fourth membrane 20w is disposed between the second membrane 20y and the lower electrode 12. A fourth membrane 20w is disposed between the third membrane 20z and the lower electrode 12.

[0158] The fourth film 20w includes a third material. The third material is, for example, a material different from the second material. The third material is, for example, an oxide, a nitride, or a nitrogen oxide. The third material is, for example, silicon oxide, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, silicon nitride, aluminum nitride, or silicon oxynitride.

[0159] The transistor 301 in the first variation of the third embodiment, like that in the first embodiment, improves the reliability of the gate insulating layer 20. Furthermore, by using a multilayer film in the gate insulating layer 20, the transistor characteristics of 301 are further improved.

[0160] (Second variation) The semiconductor device of the second variation of the third embodiment differs from the semiconductor device of the third embodiment in that the gate insulating layer does not contain a third film.

[0161] Figure 29 This is a schematic cross-sectional view of a semiconductor device in a second variation of the third embodiment. Figure 29 It is the same as the third embodiment. Figure 27 The corresponding diagram.

[0162] The semiconductor device in the second variation of the third embodiment is a transistor 302. The gate insulating layer 20 of the transistor 302 includes a first film 20x and a second film 20y. The gate insulating layer 20 of the transistor 302 differs from the gate insulating layer 20 of the third embodiment in that it does not include a third film 20z.

[0163] In the second variation of the third embodiment, the transistor 302, like in the first embodiment, improves the reliability of the gate insulating layer 20. Furthermore, by using a multilayer film in the gate insulating layer 20, the transistor characteristics of 302 are further improved.

[0164] According to the third embodiment and its variations, the reliability of the gate insulating layer 20 is improved, and a semiconductor device with excellent transistor characteristics is realized.

[0165] (Fourth Implementation) The semiconductor memory device of the fourth embodiment includes the semiconductor device of the first embodiment and a capacitor electrically connected to one of the first electrode or the second electrode.

[0166] The semiconductor memory device of the fourth embodiment is a semiconductor memory 400. The semiconductor memory device of the fourth embodiment is a DRAM. The semiconductor memory 400 uses the transistor 100 of the first embodiment as a switching transistor for the memory cell of the DRAM.

[0167] Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0168] Figure 30 This is an equivalent circuit diagram of the semiconductor memory device according to the fourth embodiment. Figure 30 The example illustrates a single storage unit MC, but multiple storage units MC can also be arranged in an array.

[0169] The semiconductor memory 400 includes memory cells MC, word lines WL, bit lines BL, and board lines PL. The memory cell MC includes a switching transistor TR and a capacitor CA. Figure 30 In the diagram, the area enclosed by the dashed line is the memory cell MC.

[0170] Word line WL is electrically connected to the gate electrode of switching transistor TR. Bit line BL is electrically connected to one of the source or drain electrodes of switching transistor TR. One electrode of capacitor CA is electrically connected to the other of the source or drain electrodes of switching transistor TR. The other electrode of capacitor CA is connected to board line PL.

[0171] The storage cell MC stores data by accumulating charge in the capacitor CA. Data writing and reading are performed by turning on the switching transistor TR.

[0172] For example, when the desired voltage is applied to the bit line BL, the switching transistor TR is turned on to write data to the memory cell MC.

[0173] Alternatively, for example, the switching transistor TR is turned on to detect the voltage change of the bit line BL corresponding to the amount of charge stored in the capacitor, and the data of the memory cell MC is read.

[0174] Figure 31 This is a schematic cross-sectional view of the semiconductor memory device according to the fourth embodiment. Figure 31 A cross-section of the memory cell MC of the semiconductor memory 400 is shown.

[0175] The semiconductor memory 400 includes a silicon substrate 10, a switching transistor TR, a capacitor CA, a lower insulating layer 50, and an upper insulating layer 52.

[0176] The switching transistor TR includes a lower electrode 12, an upper electrode 14, an oxide semiconductor layer 16, a gate electrode 18, a gate insulating layer 20, a first interlayer insulating layer 22, and a second interlayer insulating layer 24.

[0177] The switching transistor TR has the same construction as the transistor 100 in the first embodiment.

[0178] A capacitor CA is disposed between the silicon substrate 10 and the switching transistor TR. The capacitor CA is also disposed between the silicon substrate 10 and the lower electrode 12. The capacitor CA is electrically connected to the lower electrode 12. Alternatively, the capacitor CA can be electrically connected to the upper electrode 14.

[0179] The capacitor CA includes a unit electrode 71, a plate electrode 72, and a capacitor insulating film 73. The unit electrode 71 is electrically connected to the lower electrode 12. For example, the unit electrode 71 is connected to the lower electrode 12.

[0180] Unit electrode 71 and plate electrode 72 are, for example, titanium nitride. The capacitor insulating film 73 has, for example, a stacked structure of zirconium oxide, aluminum oxide, and zirconium oxide.

[0181] Gate electrode 18 is electrically connected, for example, to word line WL (not shown). Top electrode 14 is electrically connected, for example, to bit line BL (not shown). Plate electrode 72 is electrically connected, for example, to plate line PL (not shown).

[0182] The semiconductor memory 400 utilizes an oxide semiconductor transistor with extremely low channel leakage current during shutdown operation in the switching transistor TR. Therefore, it achieves DRAM with excellent charge retention characteristics.

[0183] Furthermore, the gate insulating layer 20 of the switching transistor TR in the semiconductor memory 400 has high reliability. Therefore, the reliability of the semiconductor memory 400 is improved.

[0184] In the fourth embodiment, a semiconductor memory using the transistor of the first embodiment was described as an example, but the semiconductor memory of the embodiments of the present invention may also be a semiconductor memory using the transistor of the second or third embodiment.

[0185] The semiconductor memory device according to the fourth embodiment can realize a semiconductor memory device with excellent transistor characteristics.

[0186] In the first to third embodiments, a GAA transistor with a gate electrode disposed in the oxide semiconductor layer surrounding the channel was described as an example. However, the transistor in the embodiments of the present invention may be, for example, a dual-gate transistor in which the gate electrodes are disposed opposite each other in two directions of the oxide semiconductor layer forming the channel, or a tri-gate transistor in which the gate electrodes are disposed opposite each other in three directions of the oxide semiconductor layer forming the channel.

[0187] While several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, an element of one embodiment can be substituted or modified with an element of another embodiment. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents. [Explanation of reference numerals in the attached figures]

[0188] 12 Lower electrode (first electrode) 14. Upper electrode (second electrode) 16 Oxide semiconductor layer 18 gate electrodes 18a Part 1 18b Part Two 20 Gate insulating layer 20x First Membrane 20y Second membrane 20z Third Membrane 22 First interlayer insulation layer (first insulation layer) 22a Part Three 22b Part Four 24. Second interlayer insulation layer (second insulation layer) 24a Part 5 24b Part Six 44 gaps 100 transistors (semiconductor devices) 110 transistors (semiconductor devices) 120 transistors (semiconductor devices) 130 transistors (semiconductor devices) 200 transistors (semiconductor devices) 300 transistors (semiconductor devices) 310 transistors (semiconductor devices) 320 transistors (semiconductor devices) 400 Semiconductor Memory (Semiconductor Storage Device) d1 First distance d2 Second distance t1 First Thickness t2 Second thickness t3 Third Thickness t4 Fourth thickness t5 Fifth Thickness t6 Sixth Thickness w1 First width w2 Second Width CA capacitors E1 First end E2 Second end P1 First Position P2 Second Position P3 Third Position P4 Fourth Position

Claims

1. A semiconductor device comprising: First electrode; Second electrode; An oxide semiconductor layer is disposed between the first electrode and the second electrode; The gate electrode is opposite to the oxide semiconductor layer; A first insulating layer is disposed between the first electrode and the gate electrode; A second insulating layer is disposed between the gate electrode and the second electrode; as well as A gate insulating layer is disposed between the gate electrode and the oxide semiconductor layer, between the first insulating layer and the oxide semiconductor layer, and between the second insulating layer and the oxide semiconductor layer. In a first cross section parallel to the first direction connecting the first electrode and the second electrode The thickness of the gate insulating layer at a first location between the first insulating layer and the oxide semiconductor layer, in a second direction perpendicular to the first direction, is defined as the first thickness. The thickness of the gate insulating layer in the second direction at the second location between the second insulating layer and the oxide semiconductor layer is defined as the second thickness. The thickness of the gate insulating layer in the second direction at the third position between the first end of the first electrode side of the gate electrode and the oxide semiconductor layer is defined as the third thickness. When the thickness of the gate insulating layer in the second direction at the fourth position between the second end of the second electrode side of the gate electrode and the oxide semiconductor layer is set to a fourth thickness, The second thickness is thicker than the first thickness, or the fourth thickness is thicker than the third thickness.

2. The semiconductor device according to claim 1, wherein, The second thickness is thicker than the first thickness, and the fourth thickness is thicker than the third thickness.

3. The semiconductor device according to claim 1, wherein, The second thickness is more than 1.1 times and less than 1.5 times the first thickness, or the fourth thickness is more than 1.1 times and less than 1.5 times the third thickness.

4. The semiconductor device according to claim 1, wherein, In the first cross-section, the gate electrode comprises a first portion and a second portion. In the second direction, the oxide semiconductor layer is disposed between the first portion and the second portion.

5. The semiconductor device according to claim 1, wherein, The gate electrode surrounds the oxide semiconductor layer.

6. The semiconductor device according to claim 1, wherein, In the first cross-section, the first insulating layer comprises a third portion and a fourth portion, and in the second direction, the oxide semiconductor layer is disposed between the third portion and the fourth portion. In the first cross-section, the second insulating layer comprises a fifth portion and a sixth portion, and in the second direction, the oxide semiconductor layer is disposed between the fifth portion and the sixth portion.

7. The semiconductor device according to claim 6, wherein, The first distance in the second direction between the portion of the third part that is in contact with the first electrode and the portion of the fourth part that is in contact with the first electrode is less than the second distance in the second direction between the portion of the fifth part that is in contact with the second electrode and the portion of the sixth part that is in contact with the second electrode.

8. The semiconductor device according to claim 1, wherein, The first width in the second direction of the portion of the oxide semiconductor layer in the first cross section that is in contact with the first electrode is smaller than the second width in the second direction of the portion of the oxide semiconductor layer in the first cross section that is in contact with the second electrode.

9. The semiconductor device according to claim 7, wherein, The first width in the second direction of the portion of the oxide semiconductor layer in the first cross section that is in contact with the first electrode is smaller than the second width in the second direction of the portion of the oxide semiconductor layer in the first cross section that is in contact with the second electrode.

10. The semiconductor device according to claim 1, wherein, The first width in the second direction of the portion of the oxide semiconductor layer in the first cross section that is in contact with the first electrode is greater than the second width in the second direction of the portion of the oxide semiconductor layer in the first cross section that is in contact with the second electrode.

11. The semiconductor device according to claim 7, wherein, The first width in the second direction of the portion of the oxide semiconductor layer in the first cross section that is in contact with the first electrode is greater than the second width in the second direction of the portion of the oxide semiconductor layer in the first cross section that is in contact with the second electrode.

12. The semiconductor device according to claim 1, wherein, The gate insulating layer disposed between the first insulating layer and the oxide semiconductor layer has a void.

13. The semiconductor device according to claim 1, wherein, The gate insulating layer disposed between the second insulating layer and the oxide semiconductor layer, and the gate insulating layer disposed between the gate electrode and the oxide semiconductor layer, contain materials different from those of the gate insulating layer disposed between the first insulating layer and the oxide semiconductor layer.

14. The semiconductor device according to claim 1, wherein, The gate insulating layer includes a first film and a second film. The first film is disposed between the gate electrode and the oxide semiconductor layer and contains a first material. The second film is disposed between the first film and the oxide semiconductor layer and contains a second material different from the first material.

15. The semiconductor device according to claim 14, wherein, The gate insulating layer further includes a third film disposed between the second film and the oxide semiconductor layer, and the third film contains the first material.

16. The semiconductor device according to claim 14, wherein, The dielectric constant of the second material is higher than that of the first material.

17. The semiconductor device according to claim 15, wherein, The dielectric constant of the second material is higher than that of the first material.

18. The semiconductor device according to claim 17, wherein, In the first cross-section, the fifth thickness of the second film in the second direction between the first end and the oxide semiconductor layer is thinner than the sixth thickness of the second film in the second direction between the second end and the oxide semiconductor layer.

19. The semiconductor device according to claim 14, wherein, The first membrane is separated from the first electrode.

20. A semiconductor memory device comprising: The semiconductor device of claim 1; and A capacitor that is electrically connected to either the first electrode or the second electrode.

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