Epitaxial structure integrated with a heit device epitaxy and method of fabrication thereof

Abstract

The application provides an epitaxial structure integrated with an HEMT device epitaxial layer and a preparation method thereof. A preset region of a semiconductor substrate is etched to a preset depth, so that the preset region is formed as a groove, a surface of the semiconductor substrate outside the groove is formed as a mesa, and the mesa is used to form a semiconductor structure other than the HEMT device, and an HEMT device epitaxial layer structure is sequentially formed on a bottom wall and a side wall of the groove. By forming a groove on the semiconductor substrate and arranging the HEMT device epitaxial layer in the groove, other semiconductor devices can be manufactured on the surface of the semiconductor substrate outside the groove, so that the HEMT device and the other semiconductor devices are integrated, the system loss is reduced, the efficiency and reliability are improved, the system size is reduced, and the cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an epitaxial structure integrating HEMT device epitaxy and its fabrication method. Background Technology

[0002] High electron mobility transistors (HEMTs) are characterized by high electron mobility, low noise, high power density, and fast switching speed. They are widely used in 5G communication, satellite communication, radar systems, RF front-ends, power conversion, electric vehicle charging, data center power supplies, and other fields, especially in scenarios that require high frequency, high power, and low loss.

[0003] However, as the demands for performance and power density in device applications increase, the physical bottlenecks of discrete devices (especially parasitic parameters) have become obstacles to performance improvement. To meet the extreme demands of applications requiring efficiency, size, and ease of use, integration is an inevitable choice. However, the conventional approach for HEMT devices is to perform epitaxial growth on a full-surface substrate, and then use front-end and back-end processes to cut and package each HEMT device into an independent discrete device. Following this conventional approach, it is impossible to fabricate other devices on the same substrate as the HEMT device, and therefore, it is impossible to integrate other devices with the HEMT device. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an epitaxial structure integrating HEMT device epitaxy and its fabrication method, so as to solve the problem that conventional HEMT device fabrication methods in the prior art cannot integrate other devices.

[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating an epitaxial structure integrating a HEMT device epitaxial layer, the method comprising:

[0006] Provide semiconductor substrates;

[0007] A predetermined area of ​​the semiconductor substrate is etched to a predetermined depth to form a groove, and the surface of the semiconductor substrate outside the groove is formed as a mesa, which is used to form a semiconductor structure other than the HEMT device.

[0008] HEMT device epitaxial stack structure is sequentially formed on the bottom wall and side wall of the groove; wherein, the HEMT device epitaxial stack structure includes, from bottom to top, a nucleation layer, a buffer layer, a channel layer and a barrier layer.

[0009] Optionally, the epitaxial stack structure of the HEMT device is a III-V compound HEMT device epitaxial stack structure.

[0010] Furthermore, the epitaxial stacked structure of the HEMT device is a GaN-based HEMT device epitaxial stacked structure; wherein, the HEMT device epitaxial stacked structure, from bottom to top, includes an AlN nucleation layer, an Al... x Ga 1-x The structure consists of an N-buffer layer, a GaN channel layer, and an AlGaN barrier layer, where 0 <x<1。

[0011] Optionally, the method for forming the HEMT device epitaxial stack structure on the bottom wall and side wall of the groove includes: sequentially epitaxially growing a material layer of the HEMT device epitaxial stack structure in the mesa and the groove of the semiconductor substrate; and using a CMP process to grind the material layer of the HEMT device epitaxial stack structure to remove the material layer of the HEMT device epitaxial stack structure on the mesa, thereby obtaining the HEMT device epitaxial stack structure retained in the groove.

[0012] Furthermore, the method for etching to form the groove is either dry etching or wet etching.

[0013] The present invention also provides an epitaxial structure integrating an HEMT device epitaxial layer, the epitaxial structure comprising:

[0014] A semiconductor substrate, wherein a groove extending inward from the surface of the semiconductor substrate to a predetermined depth is formed in a predetermined region of the semiconductor substrate, and the surface of the semiconductor substrate outside the groove is formed as a mesa, and the mesa is used to form a semiconductor structure other than a HEMT device;

[0015] The HEMT device epitaxial stack structure is disposed on the bottom wall and side wall of the groove, wherein the HEMT device epitaxial stack structure includes, from bottom to top, a nucleation layer, a buffer layer, a channel layer and a barrier layer.

[0016] Optionally, the HEMT device epitaxial stack structure fills the groove.

[0017] Optionally, the epitaxial stack structure of the HEMT device is a III-V compound HEMT device epitaxial stack structure.

[0018] Furthermore, the epitaxial stacked structure of the HEMT device is a GaN-based HEMT device epitaxial stacked structure; wherein, the HEMT device epitaxial stacked structure, from bottom to top, includes an AlN nucleation layer, an Al... x Ga 1-x The structure consists of an N-buffer layer, a GaN channel layer, and an AlGaN barrier layer, where 0 <x<1。

[0019] Optionally, the semiconductor substrate is made of silicon or silicon carbide.

[0020] As described above, the epitaxial structure integrating HEMT device epitaxy and its fabrication method of the present invention have the following beneficial effects:

[0021] By forming a groove on a semiconductor substrate and epitaxially placing a HEMT device within the groove, other semiconductor devices can be fabricated on the surface of the semiconductor substrate outside the groove. This enables the integration of the HEMT device with other semiconductor devices, thereby reducing system losses, improving efficiency and reliability, reducing system size, and lowering costs. Attached Figure Description

[0022] Figures 1 to 7 The diagram shows cross-sectional structural schematics of each step in the fabrication method of the epitaxial structure integrating HEMT device epitaxy according to Embodiment 1 of the present invention.

[0023] Component marking instructions

[0024] 10 semiconductor substrate 100 groove 101 mesa 11 HEMT device epitaxial stack structure 110 nucleation layer 111 Buffer layer 112 Channel layer 113 Barrier layer Detailed Implementation

[0025] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0026] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0027] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0028] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0029] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0030] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0031] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex. Example 1

[0032] This embodiment provides a method for fabricating an epitaxial structure integrating a HEMT device epitaxial layer, the method comprising:

[0033] S1 provides a semiconductor substrate;

[0034] S2, etching a predetermined area of ​​the semiconductor substrate to a predetermined depth to form a groove, and forming a mesa on the surface of the semiconductor substrate outside the groove, and the mesa is used to form a semiconductor structure other than the HEMT device;

[0035] S3, an epitaxial stacked structure of a HEMT device is sequentially formed on the bottom wall and side wall of the groove; wherein, the epitaxial stacked structure of the HEMT device includes, from bottom to top, a nucleation layer, a buffer layer, a channel layer and a barrier layer.

[0036] The method for fabricating an epitaxial structure integrating HEMT device epitaxy in this embodiment involves forming a groove on a semiconductor substrate and placing the HEMT device epitaxy within the groove. This allows other semiconductor devices to be fabricated on the surface of the semiconductor substrate outside the groove, thereby achieving the integration of HEMT device and other semiconductor devices. This reduces system losses, improves efficiency and reliability, reduces system size, and lowers costs.

[0037] The fabrication method of the epitaxial structure integrating HEMT device epitaxy in this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0038] like Figure 1 As shown, step S1 is performed first, providing a semiconductor substrate 10.

[0039] The material of the semiconductor substrate 10 can be selected according to actual needs, without excessive restrictions. As an example, the material of the semiconductor substrate 10 can be silicon or silicon carbide. Silicon substrates have advantages such as lower cost, larger size, and good compatibility with existing silicon-based CMOS processes, making them suitable for cost-sensitive applications that require integration with silicon-based circuits. Silicon carbide substrates, on the other hand, have high thermal conductivity, high breakdown field strength, and smaller lattice mismatch with GaN materials, making them more suitable for high-frequency, high-power devices, effectively improving the heat dissipation performance and operational reliability of the devices. In practical applications, appropriate substrate materials can be flexibly selected according to specific device performance requirements and application scenarios.

[0040] like Figure 2 As shown, step S2 is then performed, in which a preset area of ​​the semiconductor substrate 10 is etched to a preset depth so that the preset area is formed into a groove 100, and the surface of the semiconductor substrate 10 outside the groove 100 is formed into a mesa 101, and the mesa 101 is used to form a semiconductor structure other than the HEMT device.

[0041] As a specific example, the process of forming the groove 100 is as follows: photoresist is coated onto the entire surface of the semiconductor substrate 10, and then the photoresist is patterned to form patterned photoresist, the patterned photoresist exposing the area where the groove 100 is to be formed; then, the semiconductor substrate 10 is etched based on the patterned photoresist to form the groove 100; finally, the patterned photoresist is removed. The etching method for forming the groove 100 can be dry etching or wet etching. Dry etching, such as reactive ion etching (RIE) or inductively coupled plasma etching (ICP), offers advantages such as high etching rate, good anisotropy, high pattern resolution, and controllable substrate damage. It allows for precise control of the groove depth and sidewall perpendicularity, making it suitable for fabricating high aspect ratio grooves. Wet etching, on the other hand, typically uses a chemical solution to react with the semiconductor material to remove it. It is relatively simple to operate, lower in cost, and causes less damage to the substrate, but exhibits poor anisotropy and struggles to achieve steep sidewalls. It is generally suitable for etching shallow grooves or those with less stringent requirements for groove morphology. In this embodiment, a suitable etching method can be selected based on factors such as the design dimensions, morphology requirements, and process conditions of the groove 100. Through etching, a groove 100 extending from the surface inward to a predetermined depth is formed in a predetermined area of ​​the semiconductor substrate 10, while the surface of the semiconductor substrate 10 outside the groove 100 is formed as a mesa 101. The mesa 101 will be used to form semiconductor structures other than HEMT devices in the future. Taking silicon substrate as an example, it can be CMOS devices, resistors, capacitors, etc., or shielded gate trench MOSFETs (SGT), super junction MOSFETs (SJ), IGBTs, etc. It can also be compatible with silicon-based IC integration solutions, so it has high compatibility, thus laying the foundation for the integration of multiple devices.

[0042] The shape and size of the groove 100 are set according to the design purpose of the pre-formed HEMT device, and no excessive restrictions are imposed here; the depth of the groove 100 is designed according to the thickness of the epitaxial stack structure of the pre-formed HEMT device, preferably, the depth of the groove 100 is not less than the thickness of the epitaxial stack structure of the pre-formed HEMT device.

[0043] like Figures 3 to 4 As shown, in step S3, an epitaxial stacked structure 11 for HEMT devices is sequentially formed on the bottom wall and side wall of the groove 100. The epitaxial stacked structure 11 for HEMT devices includes, from bottom to top, a nucleation layer 110, a buffer layer 111, a channel layer 112, and a barrier layer 113. A two-dimensional electron gas (2DEG) is formed between the channel layer 112 and the barrier layer 113, which is the key to achieving high electron mobility in HEMT devices.

[0044] As an example, such as Figure 3 As shown, the HEMT device epitaxial stack structure 11 can fill the entire groove 100, or it can be as follows: Figure 4 As shown, the entire groove 100 is not filled. In a preferred example, the HEMT device epitaxial stack 11 fills the entire groove 100, such that the upper surface of the HEMT device epitaxial stack within the groove 100 is substantially flush with the surface of the mesa 101 of the semiconductor substrate 10. This facilitates subsequent fabrication processes of other semiconductor structures on the mesa 101, improving integration and process compatibility.

[0045] As an example, the HEMT device epitaxial stack structure 11 is a III-V compound HEMT device epitaxial stack structure, such as a GaAs-based HEMT device epitaxial stack structure, a GaN-based HEMT device epitaxial stack structure, or an InP-based HEMT device epitaxial stack structure. As a specific example, the HEMT device epitaxial stack structure is a GaN-based HEMT device epitaxial stack structure, which, from bottom to top, includes an AlN nucleation layer, an AlxGa1-xN buffer layer, a GaN channel layer, and an AlGaN barrier layer, wherein 0 <x<1。

[0046] As a specific example, the method for forming the HEMT device epitaxial stack structure 11 on the bottom wall and side wall of the groove 100 includes steps S30 and S31:

[0047] S30, such as Figures 5 to 7As shown, the material layers of the HEMT device epitaxial stack structure 11 are sequentially epitaxially grown on the mesa 101 and the groove 100 of the semiconductor substrate 10. The epitaxial growth method can adopt technologies such as metalorganic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). Taking the growth of the GaN-based HEMT device epitaxial stack structure by MOCVD as an example, during the growth process, the semiconductor substrate 10 is placed in the reaction chamber, and the corresponding metalorganic sources and gas sources are introduced. Under certain conditions such as temperature, pressure, and gas flow rate, each material layer is grown layer by layer on the substrate surface, including the bottom wall, side wall of the groove 100, and the mesa 101 region. When growing the AlN nucleation layer, by controlling parameters such as the growth temperature and the ratio of group III-V elements, high-quality nucleation centers can be formed on the substrate surface, providing a good foundation for the growth of subsequent epitaxial layers; the composition x of the AlxGa1-xN buffer layer can be adjusted as needed, 0 < x < 1, and its main function is to relieve the lattice mismatch and thermal mismatch between the substrate and the upper GaN channel layer, reducing the defect density in the epitaxial layer; the GaN channel layer is the main region for electron transport, and its crystal quality directly affects the mobility and concentration of the two-dimensional electron gas; the AlGaN barrier layer forms a heterojunction with the GaN channel layer, and a high-density and high-mobility two-dimensional electron gas is induced at the heterojunction interface through spontaneous polarization and piezoelectric polarization effects.

[0048] S31, such as Figure 3As shown, after the growth of the material layer of the HEMT device epitaxial stack 11 is completed, the HEMT device epitaxial stack 11 on the mesa 101 can be removed in any suitable manner to expose the upper surface of the substrate, so as to facilitate the subsequent fabrication of semiconductor structures other than the HEMT device epitaxial stack 11 on the mesa 101. As an example, chemical mechanical polishing (CMP) can be used to grind the surface of the obtained structure to remove the material layer of the HEMT device epitaxial stack 11 on the mesa 101, thereby obtaining the HEMT device epitaxial stack 11 retained in the groove 100. The CMP process can achieve global planarization of the material surface through the synergistic effect of mechanical polishing and chemical etching, and can accurately remove the epitaxial material in the mesa 101 region, while ensuring the surface flatness of the epitaxial stack structure inside and outside the groove 100. Initially, experimental design and cross-sectional observation are needed to determine the time required to remove the material layer of the HEMT device epitaxial stack 11 on the mesa 101. Subsequently, CMP time recording can be used to determine whether the material layer of the HEMT device epitaxial stack 11 on the mesa 101 has been removed, exposing the surface of the mesa 101. This ensures that the surface of the mesa 101 is exposed while avoiding over-polishing and damage to the HEMT device epitaxial stack 11 within the groove 100. During polishing, appropriate polishing fluid, polishing pads, and process parameters must be selected to ensure uniform polishing rate and protection of the epitaxial layers inside and outside the groove 100, avoiding adverse effects on device performance from over-polishing or under-polishing.

[0049] Example 2

[0050] This embodiment provides an epitaxial structure integrating a HEMT device epitaxial layer. This epitaxial structure can be fabricated using the method described in Embodiment 1. Therefore, information regarding the material and fabrication process of the epitaxial structure can be found in Embodiment 1. Of course, other fabrication processes can also be used to fabricate the epitaxial structure as needed, as long as the epitaxial structure can be formed. The beneficial effects achievable by this epitaxial structure can be found in Embodiment 1, and will not be repeated below.

[0051] like Figure 3 and Figure 4 As shown, the epitaxial structure includes:

[0052] A semiconductor substrate 10, wherein a groove 100 extending inward from the surface of the semiconductor substrate 10 to a predetermined depth is formed in a predetermined region of the semiconductor substrate 10, and the surface of the semiconductor substrate 10 outside the groove 100 is formed as a mesa 101, and the mesa 101 is used to form a semiconductor structure other than a HEMT device.

[0053] HEMT device epitaxial stack structure 11 is disposed on the bottom wall and side wall of the groove 100. The HEMT device epitaxial stack structure 11 includes, from bottom to top, a nucleation layer 110, a buffer layer 111, a channel layer 112 and a barrier layer 113. A two-dimensional electron gas is formed between the channel layer 112 and the barrier layer 113.

[0054] As an example, the HEMT device epitaxial stack structure 11 fills the groove 100.

[0055] As an example, the HEMT device epitaxial stack structure 11 is a III-V compound HEMT device epitaxial stack structure.

[0056] As a specific example, the HEMT device epitaxial stack structure 11 is a GaN-based HEMT device epitaxial stack structure; wherein, the HEMT device epitaxial stack structure 11 includes, from bottom to top, an AlN nucleation layer 110, an Al... x Ga 1-x The structure consists of an N-buffer layer 111, a GaN channel layer 112, and an AlGaN barrier layer 113, wherein 0 <x<1。

[0057] As an example, the semiconductor substrate 10 is made of silicon or silicon carbide.

[0058] In summary, this invention provides an epitaxial structure integrating a HEMT device epitaxial layer and its fabrication method. By forming a groove on a semiconductor substrate and placing the HEMT device epitaxial layer within the groove, other semiconductor devices can be fabricated on the surface of the semiconductor substrate outside the groove, thereby achieving the integration of the HEMT device with other semiconductor devices. This reduces system losses, improves efficiency and reliability, reduces system size, and lowers costs. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0059] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating an epitaxial structure integrating a HEMT device epitaxial layer, characterized in that, The preparation method includes: Provide semiconductor substrates; A predetermined area of ​​the semiconductor substrate is etched to a predetermined depth to form a groove, and the surface of the semiconductor substrate outside the groove is formed as a mesa, which is used to form a semiconductor structure other than the HEMT device. HEMT device epitaxial stack structure is sequentially formed on the bottom wall and side wall of the groove; wherein, the HEMT device epitaxial stack structure includes, from bottom to top, a nucleation layer, a buffer layer, a channel layer and a barrier layer.

2. The method for fabricating an epitaxial structure integrating a HEMT device epitaxial layer according to claim 1, characterized in that: The HEMT device epitaxial stack structure is a III-V group compound HEMT device epitaxial stack structure.

3. The method for fabricating an epitaxial structure integrating a HEMT device epitaxial layer according to claim 2, characterized in that: The HEMT device epitaxial stack structure is a GaN-based HEMT device epitaxial stack structure; wherein, the HEMT device epitaxial stack structure, from bottom to top, includes an AlN nucleation layer, an Al... x Ga 1-x The structure consists of an N-buffer layer, a GaN channel layer, and an AlGaN barrier layer, where 0 <x<1。 4. The method for fabricating an epitaxial structure integrating a HEMT device epitaxial layer according to claim 1, characterized in that, The method for forming the HEMT device epitaxial stack structure on the bottom wall and side wall of the groove includes: epitaxially growing material layers of the HEMT device epitaxial stack structure sequentially in the mesa and the groove of the semiconductor substrate; and grinding the material layers of the HEMT device epitaxial stack structure using a CMP process to remove the material layers of the HEMT device epitaxial stack structure on the mesa, thereby obtaining the HEMT device epitaxial stack structure retained in the groove.

5. The method for fabricating an epitaxial structure integrating a HEMT device epitaxial layer according to claim 4, characterized in that: The method for etching to form the groove is either dry etching or wet etching.

6. An epitaxial structure integrating an HEMT device epitaxial layer, characterized in that, The epitaxial structure includes: A semiconductor substrate, wherein a groove extending inward from the surface of the semiconductor substrate to a predetermined depth is formed in a predetermined region of the semiconductor substrate, and the surface of the semiconductor substrate outside the groove is formed as a mesa, and the mesa is used to form a semiconductor structure other than a HEMT device; The HEMT device epitaxial stack structure is disposed on the bottom wall and side wall of the groove, wherein the HEMT device epitaxial stack structure includes, from bottom to top, a nucleation layer, a buffer layer, a channel layer and a barrier layer.

7. The epitaxial structure integrating HEMT device epitaxy according to claim 6, characterized in that: The HEMT device epitaxial stack structure fills the groove.

8. The epitaxial structure integrating HEMT device epitaxy according to claim 6, characterized in that: The HEMT device epitaxial stack structure is a III-V group compound HEMT device epitaxial stack structure.

9. The epitaxial structure integrating HEMT device epitaxy according to claim 8, characterized in that: The HEMT device epitaxial stack structure is a GaN-based HEMT device epitaxial stack structure; wherein, the HEMT device epitaxial stack structure, from bottom to top, includes an AlN nucleation layer, an Al... x Ga 1-x The structure consists of an N-buffer layer, a GaN channel layer, and an AlGaN barrier layer, where 0 <x<1。 10. The epitaxial structure integrating HEMT device epitaxy according to claim 6, characterized in that: The semiconductor substrate is made of silicon or silicon carbide.

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