Semiconductor device

Abstract

A semiconductor device includes a gate electrode extending in a first direction on a substrate, a semiconductor pattern extending in a second direction intersecting the first direction and penetrating the gate electrode, and a gate insulating layer between the gate electrode and the semiconductor pattern. The semiconductor pattern has side surfaces facing away from each other in the first direction, and upper and lower surfaces facing away from each other in a third direction. The gate electrode includes conductive sub-patterns respectively provided on the side surfaces of the semiconductor pattern and spaced apart from each other in the first direction, and a conductive pattern extending in the first direction to cover the upper and lower surfaces of the semiconductor pattern and cover the conductive sub-patterns. A work function of the conductive sub-patterns is different from a work function of the conductive pattern.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0192284, filed on December 20, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor devices and methods of manufacturing semiconductor devices, and more specifically, to semiconductor devices comprising vertically stacked field-effect transistors and methods of manufacturing semiconductor devices. Background Technology

[0003] Semiconductor devices include integrated circuits composed of metal-oxide-semiconductor field-effect transistors (MOSFETs). As the size and design rules of semiconductor devices continue to shrink, the size of MOSFETs is also shrinking at an increasingly rapid pace. However, as the size of MOSFETs decreases, the operating characteristics of semiconductor devices may degrade. Therefore, to achieve high integration of semiconductor devices, research is being conducted on various structures for stacking MOSFETs on a substrate in the vertical direction. Furthermore, various methods are being investigated to overcome the limitations caused by the high integration of semiconductor devices and to form semiconductor devices with superior performance. Summary of the Invention

[0004] This disclosure provides a semiconductor device with improved electrical properties and a method for manufacturing the semiconductor device.

[0005] This disclosure also provides a semiconductor device that is easy to highly integrate and a method for manufacturing the semiconductor device.

[0006] An embodiment of the present invention provides a semiconductor device comprising: a gate electrode extending on a substrate in a first direction; and a semiconductor pattern extending in a second direction intersecting the first direction and penetrating the gate electrode. The first and second directions are parallel to the upper surface of the substrate and intersect each other. The semiconductor device further comprises a gate insulating layer located between the gate electrode and the semiconductor pattern. The semiconductor pattern has side surfaces opposite to each other in the first direction, and upper and lower surfaces opposite to each other in a third direction perpendicular to the upper surface of the substrate. The gate electrode comprises: conductive electron patterns, each disposed on a side surface of the semiconductor pattern and spaced apart from each other in the first direction; and a conductive pattern extending in the first direction to cover the upper and lower surfaces of the semiconductor pattern and to cover the conductive electron patterns; wherein the work function of the conductive electron pattern is different from the work function of the conductive pattern.

[0007] In an embodiment of the present invention, a semiconductor device includes: a gate electrode extending on a substrate in a first direction; and a semiconductor pattern extending in a second direction intersecting the first direction and penetrating the gate electrode, wherein the first and second directions are parallel to the upper surface of the substrate and intersect each other; the semiconductor pattern includes: a first contact region and a second contact region disposed on opposite sides of the gate electrode in the second direction; and an active region overlapping the gate electrode when viewed from the first and third directions and located between the first and second contact regions; the active region includes: a first boundary region adjacent to the first contact region; a second boundary region adjacent to the second contact region; and a channel region located between the first and second boundary regions; the gate electrode includes: first conductive electronic patterns spaced apart from each other in the first direction; a first boundary region of the semiconductor pattern located between the first conductive electronic patterns; and a conductive pattern extending in the first direction to surround the active region of the semiconductor pattern and cover the first conductive electronic patterns; and the first conductive electronic pattern is located between the conductive pattern and the first boundary region of the semiconductor pattern, and the work function of the first conductive electronic pattern is different from the work function of the conductive pattern. Attached Figure Description

[0008] The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0009] Figure 1 This is a block diagram illustrating some embodiments of a semiconductor device according to the present invention;

[0010] Figure 2 This is a perspective view schematically illustrating some embodiments of a semiconductor device according to the present invention.

[0011] Figure 3 This is a plan view of a semiconductor device according to some embodiments of the present invention;

[0012] Figure 4 It is along Figure 3 A cross-sectional view taken from A-A';

[0013] Figure 5 It is along Figure 3 Cross-sectional views taken from B-B', C-C', and D-D';

[0014] Figure 6 yes Figure 4 An enlarged view of part P1;

[0015] Figure 7 yes Figure 5 Enlarged views of parts P2 and P3;

[0016] Figure 8 , Figure 11 , Figure 14 , Figure 17 , Figure 20 , Figure 23 , Figure 27 , Figure 30 , Figure 33 , Figure 35 and Figure 37 This is a plan view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention;

[0017] Figure 9 , Figure 12 , Figure 15 , Figure 18 , Figure 21 , Figure 24 , Figure 28 , Figure 31 , Figure 34 , Figure 36 and Figure 38 They are along Figure 8 , Figure 11 , Figure 14 , Figure 17 , Figure 20 , Figure 23 , Figure 27 , Figure 30 , Figure 33 , Figure 35 and Figure 37 A cross-sectional view taken from A-A';

[0018] Figure 10 , Figure 13 , Figure 16 , Figure 19 , Figure 22 , Figure 25 , Figure 29 and Figure 32 They are along Figure 8 , Figure 11 , Figure 14 , Figure 17 , Figure 20 , Figure 23 , Figure 27 and Figure 30 Cross-sectional views taken at B-B', C-C', and D-D'; and

[0019] Figure 26 yes Figure 25 Part P4 and Figure 29 An enlarged view of section P5. Detailed Implementation

[0020] In the following, the inventive concept will be described in detail by referring to the accompanying drawings and describing embodiments thereof.

[0021] Figure 1 This is a block diagram illustrating some embodiments of a semiconductor device according to the present invention.

[0022] Reference Figure 1 The semiconductor device may include a memory cell array 1, a row decoder 2, a sense amplifier 3, a column decoder 4, and control logic 5.

[0023] Items described in the singular in this document may be provided in plural form, as shown in the figure. Therefore, unless the context otherwise indicates, a description of a single item provided in plural form should be understood to apply to the remaining multiple terms.

[0024] Throughout this specification, when a component is described as “comprising” a particular element or group of elements, it should be understood that the component consists solely of that element or group of elements, or that the element or group of elements may be combined with other elements to form the component, unless the context otherwise requires. On the other hand, the term “consisting of” indicates that the component consists solely of the listed elements.

[0025] It will be understood that when a component is referred to as being “connected” or “coupled” to another component or “on” another component, the component may be directly connected or coupled to that other component or directly on that other component, or there may be an intermediate component. Conversely, when a component is referred to as being “directly connected” or “directly coupled” to another component, or “in contact” with another component or “in contact” with another component (or using the term “in contact” in any form), there is no intermediate component at the point of contact.

[0026] Ordinal numbers, such as "first," "second," "third," etc., can be simply used as labels to distinguish certain elements, steps, etc., from one another. Terms not described using "first," "second," etc., in the specification may still be referred to as "first" or "second" in the claims. Furthermore, a term referenced with a specific ordinal number (e.g., "first" in a particular claim) may be described elsewhere with a different ordinal number (e.g., "second" in the specification or another claim).

[0027] The terms “intrinsic,” “undoped,” “identical,” “equal,” “constant,” “flat,” etc., used herein are intended to cover the meaning of typical variations resulting from conventional manufacturing processes and / or to accommodate acceptable tolerances in semiconductor device manufacturing processes, unless the context or other statements otherwise indicate. For example, “identical” and “equal” can cover identical or nearly identical. The term “substantially” may be used herein to emphasize this meaning.

[0028] The memory cell array 1 may include multiple memory cells MC arranged in two or three dimensions. Each memory cell MC may be connected between intersecting word lines WL and bit lines BL. Each memory cell MC may include a select element TR and a data storage element DS. The select element TR and the data storage element DS may be electrically connected to each other. The select element TR may be connected to the word line WL and the bit line BL, and may be located at the point where the word line WL and the bit line BL intersect.

[0029] The selector element TR may include a field-effect transistor. The data storage element DS may include a capacitor, a magnetic tunnel junction pattern, or a variable resistor. When the selector element TR includes a field-effect transistor, the gate terminal of the transistor may be connected to the word line WL, and each source / drain terminal of the transistor may be connected to the bit line BL and a corresponding data storage element DS.

[0030] The row decoder 2 can select any word line WL of the memory cell array 1 by decoding the address input from the external circuit. The address decoded by the row decoder 2 can be provided to the row driver (not shown in the figure), and the row driver, in response to the control of the control circuit, provides a predetermined voltage to the selected word line WL and the unselected word line WL.

[0031] The readout amplifier 3 can sense, amplify, and output the voltage difference between the selected bit line BL and the reference bit line based on the address decoded by the column decoder 4.

[0032] The column decoder 4 provides a data transfer path between the sense amplifier 3 and external components (e.g., a memory controller). The column decoder 4 can select any one of the bit lines BL of the memory cell array 1 by decoding the address input from the external circuitry. The control logic 5 generates control signals to control the writing or reading of data from the memory cell array 1.

[0033] Figure 2 This is a perspective view schematically illustrating some embodiments of a semiconductor device according to the present invention.

[0034] Reference Figure 2 The semiconductor device may include adjacent stacked structures SS and plate electrodes PE located between the stacked structures SS. The plate electrodes PE may extend in a first direction D1, and the stacked structures SS may be spaced apart in a second direction D2, with the plate electrodes PE located between the stacked structures SS. The plate electrodes PE may extend along a third direction D3 perpendicular to the first direction D1 and the second direction D2.

[0035] Each stacked structure SS may include multiple word lines WL extending in a first direction D1 and spaced apart from each other in a third direction D3. Each stacked structure SS may also include multiple semiconductor patterns SP extending in a second direction D2 and spaced apart from each other in the first direction D1 and the third direction D3. Each stacked structure SS may also include multiple bit lines BL extending in the third direction D3 and spaced apart from each other in the first direction D1. Each stacked structure SS may also include multiple memory electrodes SE respectively connected to the multiple semiconductor patterns SP.

[0036] Among multiple semiconductor patterns SP, a group of semiconductor patterns SP spaced apart in a first direction D1 can extend in a second direction D2 to penetrate corresponding word lines WL among multiple word lines WL. A group of semiconductor patterns SP spaced apart in a third direction D3 can extend in the second direction D2 to penetrate multiple word lines WL respectively. Each bit line BL can extend in the third direction D3 to connect with the semiconductor patterns SP spaced apart in the third direction D3. Multiple memory electrodes SE can be connected to a plate electrode PE. The stacked structure SS can be configured to be mirror-symmetrical about the plate electrodes PE between the stacked structures SS. The multiple memory electrodes SE and the plate electrodes PE can constitute a data storage pattern DSP.

[0037] Stacked structure SS and plate electrode PE can constitute Figure 1 The memory cell array 1. Each semiconductor pattern SP and its corresponding word line WL can correspond to Figure 1 The selection element TR and word line WL. The corresponding bit line BL connected to each semiconductor pattern SP can correspond to Figure 1 The bit line BL, the plate electrode PE, and the memory electrode SE corresponding to and connected to each semiconductor pattern SP can constitute... Figure 1 Data storage pattern DS.

[0038] Figure 3 This is a plan view of a semiconductor device according to some embodiments of the present invention. Figure 4 It is along Figure 3 The cross-sectional view taken from A-A', and Figure 5 It is along Figure 3 The cross-sectional views taken from B-B', C-C' and D-D'. Figure 6 yes Figure 4 An enlarged view of part P1, and Figure 7 yes Figure 5 Enlarged views of parts P2 and P3.

[0039] Reference Figure 3 , Figure 4 and Figure 6The stacked structures SS and plate electrodes PE can be disposed on the substrate 100. The substrate 100 can be a semiconductor substrate, an insulating substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. For example, the semiconductor substrate can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The plate electrodes PE can extend in a first direction D1, and the stacked structures SS can be spaced apart from each other in a second direction D2, with the plate electrodes PE located between the stacked structures SS. The first direction D1 and the second direction D2 can be parallel to the upper surface 100U of the substrate 100 and can intersect each other. The plate electrodes PE can extend between the stacked structures SS in a third direction D3 perpendicular to the upper surface 100U of the substrate 100.

[0040] Each stacked structure SS may include a plurality of semiconductor patterns SP extending in a second direction D2. The plurality of semiconductor patterns SP may be spaced apart from the upper surface 100U of the substrate 100 in a third direction D3, and may be spaced apart from each other in the first direction D1 and the third direction D3. The plurality of semiconductor patterns SP may include at least one of a semiconductor material, an oxide semiconductor, or a two-dimensional semiconductor material. For example, the plurality of semiconductor patterns SP may include at least one of silicon (e.g., single-crystal silicon), germanium, or silicon-germanium. For example, the plurality of semiconductor patterns SP may include In... x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O、Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O, Al x Zn y Sn z O、Yb x Ga y Zn z O、In x Ga yO or combinations thereof. For example, multiple semiconductor patterns SP may include indium gallium zinc oxide (IGZO). For example, multiple semiconductor patterns SP may include graphene, carbon nanotubes, or combinations thereof.

[0041] Each stacked structure SS may include multiple gate electrodes GE extending in a first direction D1 and spaced apart from each other in a third direction D3. The multiple gate electrodes GE can be used as... Figure 1 and Figure 2 The word line WL. Multiple gate electrodes GE may be spaced apart from the upper surface 100U of the substrate 100 on a third-direction D3. According to some embodiments, the lowermost gate electrode GE and the uppermost gate electrode GE among the multiple gate electrodes GE may be dummy gate electrodes. The term "dummy" as used herein refers to an element having the same or similar structure and shape as other similarly named elements but without the substantial function of those elements. A dummy gate electrode may, for example, be a conductor having a shape and size similar to a normal gate electrode but not used to access the memory cell MC. In some examples, the dummy gate electrode may be electrically floating.

[0042] Among a plurality of semiconductor patterns SP, a group of semiconductor patterns SP that are spaced apart from each other in a first direction D1 can extend in a second direction D2 to penetrate the corresponding gate electrode GE among a plurality of gate electrodes GE. Among a plurality of semiconductor patterns SP, a group of semiconductor patterns SP that are spaced apart from each other in a third direction D3 can extend in the second direction D2 to penetrate the plurality of gate electrodes GE respectively.

[0043] Each stacked structure SS may further include a plurality of molded patterns 150, spaced apart from a plurality of gate electrodes GE and in a third direction D3. The plurality of molded patterns 150 may extend in a first direction D1 between the plurality of gate electrodes GE. The plurality of gate electrodes GE and the plurality of molded patterns 150 may be alternately arranged in the third direction D3. The plurality of molded patterns 150 may extend in a second direction D2 between a plurality of semiconductor patterns SP. The plurality of molded patterns 150 may include an insulating material and may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0044] Each stacked structure SS may further include a first capping pattern CP1 and a second capping pattern CP2 disposed on both sides (e.g., opposite sides) of each of the plurality of gate electrodes GE. The first capping pattern CP1 and the second capping pattern CP2 may extend in a first direction D1. Each of the plurality of semiconductor patterns SP may extend in a second direction D2 to penetrate the first capping pattern CP1 and the second capping pattern CP2. Each of the plurality of gate electrodes GE, the first capping pattern CP1 and the second capping pattern CP2 may be located between a pair of molded patterns 150 that are adjacent to each other in a third direction D3. The first capping pattern CP1 and the second capping pattern CP2 may include an insulating material and may include, for example, silicon oxide, silicon nitride and / or silicon oxynitride.

[0045] Each stacked structure SS may further include a gate insulating layer GI between each of a plurality of semiconductor patterns SP and each of a plurality of gate electrodes GE. Each of the plurality of semiconductor patterns SP may be spaced apart from each of the plurality of gate electrodes GE, with the gate insulating layer GI located between the semiconductor pattern SP and the gate electrode GE. The gate insulating layer GI may extend in a second direction D2 to be between a first capping pattern CP1 and each of the plurality of semiconductor patterns SP, and between a second capping pattern CP2 and the plurality of semiconductor patterns SP. Each of the plurality of semiconductor patterns SP may be spaced apart from the first capping pattern CP1 and the second capping pattern CP2, with the gate insulating layer GI located between the semiconductor pattern SP and the first capping pattern CP1 and the second capping pattern CP2. The gate insulating layer GI may be located between the substrate 100 and the lowest gate electrode GE. The lowermost first capping pattern CP1 and the lowermost second capping pattern CP2 can be disposed on both sides (e.g., opposite sides) of the lowermost gate electrode GE, and the gate insulating layer GI can extend between the substrate 100 and the lowermost first capping pattern CP1 and between the substrate 100 and the lowermost second capping pattern CP2. For example, the gate insulating layer GI can include at least one of silicon oxide or a high-dielectric material. The high-dielectric material can be a material with a dielectric constant higher than that of silicon oxide, and can include, for example, a metal oxide or a metal nitride. For example, the high-dielectric material can include at least one of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, or Al2O3.

[0046] Each stacked structure SS may further include multiple bit lines BL, which are spaced apart from each other in a first direction D1 and extend in a third direction D3. Each bit line BL may extend in the third direction D3 to be electrically connected to semiconductor patterns SP that are spaced apart from each other in the third direction D3. The multiple bit lines BL may include at least one of the following materials: doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), metals (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), metal silicides (e.g., silicides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), or conductive metal nitrides (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). According to some embodiments, the multiple bit lines BL may include carbon-based two-dimensional materials (e.g., graphene), carbon-based three-dimensional materials (e.g., carbon nanotubes), or combinations thereof.

[0047] Each stacked structure SS may also include a buried insulating layer 190 extending between multiple bit lines BL on a third-direction D3. Each bit line BL may penetrate the buried insulating layer 190 on the third-direction D3. The buried insulating layer 190 may include an insulating material and may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0048] Each stacked structure SS may further include multiple memory electrodes SE, each connected to multiple semiconductor patterns SP. The multiple memory electrodes SE may be spaced apart from each other in a first direction D1 and a third direction D3. The multiple memory electrodes SE may be spaced apart from multiple bit lines BL in a second direction D2, and the multiple semiconductor patterns SP, multiple gate electrodes GE, a first capping pattern CP1 and a second capping pattern CP2, multiple molded patterns 150, and a gate insulating layer GI may be disposed between the multiple memory electrodes SE and the multiple bit lines BL. The multiple memory electrodes SE may be electrically connected to a plate electrode PE.

[0049] Multiple storage electrodes SE and plate electrodes PE may include at least one of the following: doped silicon (Si), doped silicon germanium (SiGe), metals (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, Ag, etc.), metal nitrides (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, Ag, etc., titanium silicon nitrides (e.g., TiSiN), titanium aluminum nitrides (e.g., TiAlN), tantalum aluminum nitrides (e.g., TaAlN), etc.), conductive oxides (e.g., PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3) or LSCo), or metal silicides.

[0050] Each stacked structure SS may further include a dielectric layer 200 between a plurality of memory electrodes SE and a plate electrode PE. The dielectric layer 200 may conformally cover each of the plurality of memory electrodes SE and may extend between the plurality of memory electrodes SE in a first direction D1 and a third direction D3. Each stacked structure SS may further include an insulating layer IL between a first capping pattern CP1 and the dielectric layer 200 located between the plurality of memory electrodes SE. The dielectric layer 200 may extend between the substrate 100 and the plate electrode PE in a second direction D2. The plate electrode PE may be spaced apart from the substrate 100, and the dielectric layer 200 is located between the plate electrode PE and the substrate 100.

[0051] Each of the plurality of storage electrodes SE may be spaced apart from the plate electrode PE, and a dielectric layer 200 is located between the storage electrode SE and the plate electrode PE. The plurality of storage electrodes SE, the plate electrode PE, and the dielectric layer 200 may constitute a data storage pattern DSP, and the data storage pattern DSP may be, for example, a capacitor. The dielectric layer 200 may include at least one of a metal oxide (e.g., HfO2, ZrO2, Al2O3, La2O3, Ta2O3, or TiO2) or a dielectric material having a perovskite structure (e.g., SrTiO3(STO), (Ba,Sr)TiO3(BST), BaTiO3, PZT, or PLZT). The insulating layer IL may include an insulating material and may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. The stacked structure SS may be configured to be mirror symmetric, with the plate electrode PE located between the stacked structures SS.

[0052] Each semiconductor pattern SP may extend in the second direction D2 to penetrate its corresponding gate electrode GE, first capping pattern CP1, and second capping pattern CP2. The semiconductor pattern SP may include a first contact region CT1 and a second contact region CT2 disposed on both sides (e.g., opposite sides) of the gate electrode GE, and an active region AR located between the first contact region CT1 and the second contact region CT2. When viewed from the first direction and / or a third direction, the active region AR may overlap with the gate electrode GE. When viewed from the first direction and / or a third direction, the first contact region CT1 may overlap with the first capping pattern CP1, and the second contact region CT2 may overlap with the second capping pattern CP2. The active region AR may include a first boundary region BR1 adjacent to the first contact region CT1, a second boundary region BR2 adjacent to the second contact region CT2, and a channel region CH located between the first boundary region BR1 and the second boundary region BR2.

[0053] The first contact region CT1 and the second contact region CT2 can have N-type or P-type conductivity and can be regions implanted with N-type or P-type dopants (or impurities or charge carrier impurities). The first contact region CT1 and the second contact region CT2 can have the same conductivity type. The first contact region CT1 and the second contact region CT2 can be referred to as the first source / drain region and the second source / drain region, respectively. The channel region CH can be an intrinsic semiconductor region. At least a portion of the first boundary region BR1 can have the same conductivity type as the first contact region CT1 and can include the same dopants as the first contact region CT1. At least a portion of the second boundary region BR2 can have the same conductivity type as the second contact region CT2 and can include the same dopants as the second contact region CT2.

[0054] In some embodiments, the first boundary region BR1 may have the same conductivity type as the first contact region CT1, and the doping concentration of CT1 may be greater than that of the first boundary region BR1. The second boundary region BR2 may have the same conductivity type as the second contact region CT2, and the doping concentration of the second contact region CT2 may be greater than that of the second boundary region BR2. The doping concentrations of the first contact region CT1 and the second contact region CT2 may be greater than the doping concentration of the channel region CH, and the doping concentrations of the first boundary region BR1 and the second boundary region BR2 may be greater than the doping concentration of the channel region CH.

[0055] In semiconductor technology, if a semiconductor contains both p-type and n-type impurities (charge carrier impurities), its conductivity type is determined by the concentration of the dominant impurity. Therefore, if a semiconductor has both p-type and n-type impurities, the net conductivity type is determined by the concentration of the dominant impurity. As used herein, a semiconductor region of "first conductivity type" indicates that the dominant impurity in the semiconductor region is a first conductivity type impurity, and the "first conductivity type concentration" (or "doping concentration") in the semiconductor region refers to the net concentration of the impurity in the semiconductor region (i.e., (amount of first conductivity type impurity minus amount of second conductivity type impurity) / volume of the semiconductor region).

[0056] According to some embodiments, the first contact area CT1 of the semiconductor pattern SP can be connected to the corresponding memory electrode SE, and the second contact area CT2 of the semiconductor pattern SP can be connected to the corresponding bit line BL. According to other embodiments, unlike those shown, the first contact area CT1 of the semiconductor pattern SP can be connected to the corresponding bit line BL, and the second contact area CT2 of the semiconductor pattern SP can be connected to the corresponding memory electrode SE.

[0057] Reference Figure 3 , Figure 5 , Figure 6 and Figure 7 Each gate electrode GE may extend in a first direction D1 and may surround the active region AR of the corresponding semiconductor pattern SP. The semiconductor pattern SP may have side surfaces SP_S opposite to each other in the first direction D1, and upper surfaces SP_U and lower surfaces SP_L opposite to each other in a third direction D3. For example, each semiconductor pattern SP may have two opposite side surfaces SP_S facing away from each other in the first direction D1, and each semiconductor pattern SP may have upper surfaces SP_U and lower surfaces SP_L facing away from each other in the third direction D3. The gate electrode GE may cover the upper surface SP_U and lower surface SP_L of the active region AR of the semiconductor pattern SP and may extend onto the side surface SP_S of the active region AR of the semiconductor pattern SP. The gate electrode GE may have a fully surrounding gate structure, wherein the gate electrode GE surrounds the active region AR of the semiconductor pattern SP. A first capping pattern CP1 may extend in the first direction D1 and may surround the first contact region CT1 of the semiconductor pattern SP. A second capping pattern CP2 may extend in the first direction D1 and may surround the second contact region CT2 of the semiconductor pattern SP.

[0058] The gate electrode GE may include first conductive sub-patterns 162 respectively disposed on the side surfaces SP_S of the active regions AR of the semiconductor pattern SP. The first conductive sub-patterns 162 may be disposed on the side surfaces SP_S of the first boundary regions BR1 of the semiconductor pattern SP, and may be spaced apart from each other in the first direction D1. The gate electrode GE may also include second conductive sub-patterns 164 respectively disposed on the side surfaces SP_S of the active regions AR of the semiconductor pattern SP. The second conductive sub-patterns 164 may be disposed on the side surfaces SP_S of the second boundary regions BR2 of the semiconductor pattern SP, and may be spaced apart from each other in the first direction D1. The gate electrode GE may also include a conductive pattern 160 extending in the first direction D1 to cover the upper surface SP_U and lower surface SP_L of the active regions AR of the semiconductor pattern SP, and extending to the side surfaces SP_S of the active regions AR of the semiconductor pattern SP to cover the first conductive sub-patterns 162 and the second conductive sub-patterns 164.

[0059] According to some embodiments, the first conductive sub-pattern 162 may be omitted, and in this case, the gate electrode GE may include a conductive pattern 160 and a second conductive sub-pattern 164. According to other embodiments, the second conductive sub-pattern 164 may be omitted, and in this case, the gate electrode GE may include a conductive pattern 160 and a first conductive sub-pattern 162.

[0060] The work function of the first conductive electronic pattern 162 may differ from that of the conductive pattern 160, and may also differ from that of the first contact region CT1 of the semiconductor pattern SP. The work function of the first conductive electronic pattern 162 may be lower than that of the conductive pattern 160, and may be higher than that of the first contact region CT1 of the semiconductor pattern SP. The first conductive electronic pattern 162 may have an N-type or P-type conductivity, and may have the same conductivity type as the first contact region CT1 of the semiconductor pattern SP. The work function of the second conductive electronic pattern 164 may differ from that of the conductive pattern 160, and may also differ from that of the second contact region CT2 of the semiconductor pattern SP. The work function of the second conductive electronic pattern 164 may be lower than that of the conductive pattern 160, and may be higher than that of the second contact region CT2 of the semiconductor pattern SP. The second conductive electronic pattern 164 may have an N-type or P-type conductivity, and may also have the same conductivity type as the second contact region CT2 of the semiconductor pattern SP.

[0061] For example, the first conductive electronic pattern 162 and the second conductive electronic pattern 164 may comprise polycrystalline silicon. For example, the first conductive electronic pattern 162 and the second conductive electronic pattern 164 may comprise polycrystalline silicon doped with N-type or P-type dopants. The conductive pattern 160 may comprise a metal. For example, the conductive pattern 160 may comprise at least one of a metal (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), a metal silicide (e.g., silicides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), or a conductive metal nitride (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0062] The gate insulating layer GI may be located between the first conductive electronic pattern 162 and the side surface SP_S of the first boundary region BR1 of the semiconductor pattern SP, and may extend between the conductive pattern 160 and the upper surface SP_U of the first boundary region BR1 of the semiconductor pattern SP, and between the conductive pattern 160 and the lower surface SP_L of the first boundary region BR1 of the semiconductor pattern SP. The conductive pattern 160 may extend between the first conductive electronic patterns 162 to contact the gate insulating layer GI on the upper surface SP_U and the lower surface SP_L of the semiconductor pattern SP. The first conductive electronic pattern 162 may be disposed between the first conductive pattern 160 and the side surface SP_S of the first boundary region BR1 of the semiconductor pattern SP, and may contact the gate insulating layer GI on the side surface SP_S of the first boundary region BR1 of the semiconductor pattern SP. The first boundary region BR1 of the semiconductor pattern SP may overlap with the first conductive electronic pattern 162 in the first direction D1.

[0063] Each first conductive electronic pattern 162 may extend to partially cover the upper surface SP_U and the lower surface SP_L of the first boundary region BR1 of the semiconductor pattern SP. Therefore, each first conductive electronic pattern 162 may cover the upper edge EG_U between the upper surface SP_U and each side surface SP_S of the first boundary region BR1 of the semiconductor pattern SP, and the lower edge EG_L between the lower surface SP_L and each side surface SP_S of the first boundary region BR1 of the semiconductor pattern SP. Each first conductive electronic pattern 162 may cover the gate insulating layer GI on the lower edge EG_L and the upper edge EG_U of the first boundary region BR1 of the semiconductor pattern SP, and may extend to partially cover the gate insulating layer GI on the upper surface SP_U and the lower surface SP_L of the first boundary region BR1 of the semiconductor pattern SP. Each first conductive electronic pattern 162 may have [missing information] in a cross-sectional view. shape.

[0064] The gate insulating layer GI may be located between the second conductive electronic pattern 164 and the side surface SP_S of the second boundary region BR2 of the semiconductor pattern SP, and may extend between the conductive pattern 160 and the upper surface SP_U of the second boundary region BR2 of the semiconductor pattern SP, and between the conductive pattern 160 and the lower surface SP_L of the second boundary region BR2 of the semiconductor pattern SP. The conductive pattern 160 may extend between the second conductive electronic patterns 164 to contact the gate insulating layer GI on the lower surface SP_L and the upper surface SP_U of the semiconductor pattern SP. The second conductive electronic pattern 164 may be located between the conductive pattern 160 and the side surface SP_S of the second boundary region BR2 of the semiconductor pattern SP, and may contact the gate insulating layer GI on the side surface SP_S of the second boundary region BR2 of the semiconductor pattern SP. The second boundary region BR2 of the semiconductor pattern SP may overlap with the second conductive electronic pattern 164 in the first direction D1.

[0065] Each second conductive electronic pattern 164 can extend to partially cover the upper surface SP_U and the lower surface SP_L of the second boundary region BR2 of the semiconductor pattern SP. Therefore, each second conductive electronic pattern 164 can cover the upper edge EG_U between the upper surface SP_U and each side surface SP_S of the second boundary region BR2 of the semiconductor pattern SP, and the lower edge EG_L between the lower surface SP_L and each side surface SP_S of the second boundary region BR2. Each second conductive electronic pattern 164 can cover the gate insulating layer GI on the lower edge EG_L and the upper edge EG_U of the second boundary region BR2 of the semiconductor pattern SP, and can extend to partially cover the gate insulating layer GI on the lower surface SP_L and the upper surface SP_U of the second boundary region BR2 of the semiconductor pattern SP. Each second conductive electronic pattern 164 can have in a cross-sectional view... shape.

[0066] The gate insulating layer GI can extend between each side surface SP_S of the channel region CH of the conductive pattern 160 and the semiconductor pattern SP, between the upper surface SP_U of the channel region CH of the conductive pattern 160 and the semiconductor pattern SP, and between the lower surface SP_L of the channel region CH of the conductive pattern 160 and the semiconductor pattern SP. The conductive pattern 160 can contact the gate insulating layer GI on the side surface SP_S, upper surface SP_U, and lower surface SP_L of the channel region CH of the semiconductor pattern SP. In the first direction D1, the channel region CH of the semiconductor pattern SP may not overlap with the first conductive pattern 162 and the second conductive pattern 164. In the second direction D2, the first conductive pattern 162 may be spaced apart from the second conductive pattern 164.

[0067] Because there is a difference between the work function of the first contact region CT1 of the semiconductor pattern SP and the work function of the conductive pattern 160 of the gate electrode GE, an electric field may be formed between the first contact region CT1 of the semiconductor pattern SP and the conductive pattern 160 of the gate electrode GE, which may lead to gate-induced drain leakage (GIDL) between the first contact region CT1 of the semiconductor pattern SP and the conductive pattern 160 of the gate electrode GE. Similarly, because there is a difference between the work function of the second contact region CT2 of the semiconductor pattern SP and the work function of the conductive pattern 160 of the gate electrode GE, an electric field may be formed between the second contact region CT2 of the semiconductor pattern SP and the conductive pattern 160 of the gate electrode GE, which may lead to gate-induced drain leakage (GIDL) between the second contact region CT2 of the semiconductor pattern SP and the conductive pattern 160 of the gate electrode GE.

[0068] According to the present invention, the gate electrode GE may include a first conductive electron pattern 162 and a second conductive electron pattern 164 having a work function different from that of the conductive pattern 160. The first conductive electron pattern 162 may be disposed on the side surface SP_S of the first boundary region BR1 of the semiconductor pattern SP. The work function of the first conductive electron pattern 162 may differ from the work function of the conductive pattern 160 and the work function of the first contact region CT1 of the semiconductor pattern SP. For example, the work function of the first conductive electron pattern 162 may be lower than that of the conductive pattern 160, and may be higher than that of the first contact region CT1 of the semiconductor pattern SP. Therefore, the electric field generated between the first contact region CT1 of the semiconductor pattern SP and the conductive pattern 160 of the gate electrode GE can be minimized, thereby preventing or suppressing gate-induced drain leakage (GIDL) between the first contact region CT1 of the semiconductor pattern SP and the conductive pattern 160 of the gate electrode GE. The second conductive electron pattern 164 may be disposed on the side surface SP_S of the second boundary region BR2 of the semiconductor pattern SP. The work function of the second conductive electronic pattern 164 can differ from the work function of the conductive pattern 160 and the work function of the second contact region CT2 of the semiconductor pattern SP. For example, the work function of the second conductive electronic pattern 164 can be lower than that of the conductive pattern 160, but higher than that of the second contact region CT2 of the semiconductor pattern SP. Therefore, the electric field generated between the second contact region CT2 of the semiconductor pattern SP and the conductive pattern 160 of the gate electrode GE can be minimized, thereby preventing or suppressing gate-induced drain leakage (GIDL) between the second contact region CT2 of the semiconductor pattern SP and the conductive pattern 160 of the gate electrode GE.

[0069] Furthermore, the semiconductor device conceived according to the present invention may include a plurality of transistors stacked in a direction perpendicular to the upper surface 100U of the substrate 100 (e.g., third direction D3), and each of the plurality of transistors may include a gate electrode GE and a semiconductor pattern SP. Therefore, a semiconductor device with improved electrical characteristics and easy high integration can be provided.

[0070] Figure 8 , Figure 11 , Figure 14 , Figure 17 , Figure 20 , Figure 23 , Figure 27 , Figure 30 , Figure 33 , Figure 35 and Figure 37 This is a plan view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. Figure 9 , Figure 12 , Figure 15 , Figure 18 , Figure 21 , Figure 24 , Figure 28 , Figure 31 , Figure 34 , Figure 36 and Figure 38 They are along Figure 8 , Figure 11 , Figure 14 , Figure 17 , Figure 20 , Figure 23 , Figure 27 , Figure 30 , Figure 33 , Figure 35 and Figure 37 The cross-sectional view taken from A-A', and Figure 10 , Figure 13 , Figure 16 , Figure 19 , Figure 22 , Figure 25 , Figure 29 and Figure 32 They are along 8, Figure 11 , Figure 14 , Figure 17 , Figure 20 , Figure 23 , Figure 27 and Figure 30 Cross-sectional views taken along B-B', C-C', and D-D'. Figure 33 , Figure 35 and Figure 37 The cross-sectional views taken at B-B', C-C', and D-D' and along Figure 30 The cross-sectional views taken from B-B', C-C', and D-D' are basically the same. Figure 26 yes Figure 25 Part P4 and Figure 29 A magnified view of section P5. For simplicity, references will be omitted. Figures 1 to 7 The repeated description of the semiconductor device.

[0071] Reference Figures 8 to 10A sacrificial layer 105 and a semiconductor layer SL can be alternately stacked on a substrate 100. The sacrificial layer 105 and the semiconductor layer SL can comprise semiconductor materials, and the sacrificial layer 105 can comprise a material that is etch-selective for the semiconductor layer SL. The semiconductor layer SL can comprise one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe). The sacrificial layer 105 can comprise one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), but can comprise a material different from the material of the semiconductor layer SL. For example, the semiconductor layer SL can comprise silicon (Si), and the sacrificial layer 105 can comprise silicon-germanium (SiGe). Each of the sacrificial layer 105 and the semiconductor layer SL can have a thickness in a third direction D3, and the thickness of each sacrificial layer 105 can be greater than the thickness of each semiconductor layer SL. The lowest sacrificial layer 105 can be located between the substrate 100 and the lowest semiconductor layer SL. The highest semiconductor layer SL can be disposed on the highest sacrificial layer 105.

[0072] Vias LH can be formed to penetrate the sacrificial layer 105 and the semiconductor layer SL. Vias LH can be spaced apart from each other in a first direction D1 and a second direction D2. Each via LH can extend in a third direction D3 to penetrate the sacrificial layer 105 and the semiconductor layer SL, and can expose the upper surface 100U of the substrate 100. Vias LH can include a first column and a second column, the first column including vias LH spaced apart from each other in the first direction D1, the second column including vias LH spaced apart from each other in the first direction D1, and the vias LH in the second column spaced apart from the vias LH in the first column in the second direction D2. The vias LH in the first column can be aligned with the vias LH in the second column in the second direction D2. The sacrificial layer 105 and the semiconductor layer SL can extend longer in the first direction D1 between the vias LH in the first column and between the vias LH in the second column, and can extend longer in the second direction D2 between the vias LH in the first column and between the vias LH in the second column.

[0073] A first fill pattern 110 can be formed to fill the vias LH respectively. The first fill pattern 110 may include an insulating material and may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. The first fill pattern 110 may include a first column and a second column, the first column including first fill patterns 110 spaced apart from each other in a first direction D1, and the second column including first fill patterns 110 spaced apart from each other in the first direction D1. The first fill patterns 110 in the second column may be spaced apart from the first fill patterns 110 in the first column in a second direction D2. The first fill patterns 110 in the first column may be aligned with the first fill patterns 110 in the second column in the second direction D2 respectively. The semiconductor layer SL and the sacrificial layer 105 may extend longer in the first direction D1 between the first fill patterns 110 in the first column and the first fill patterns 110 in the second column, and may extend longer in the second direction D2 between the first fill patterns 110 in the first column and between the first fill patterns 110 in the second column.

[0074] A first trench T1 can be formed to penetrate the sacrificial layer 105, the semiconductor layer SL, and the first fill pattern 110. The first trenches T1 can extend in a first direction D1 and can be spaced apart from each other in a second direction D2. Each first trench T1 can extend in a third direction D3 to penetrate the sacrificial layer 105, the semiconductor layer SL, and the first fill pattern 110. Each first trench T1 can expose the upper surface 100U of the substrate 100. The remaining portions of the sacrificial layer 105, the semiconductor layer SL, and the first fill pattern 110 can be disposed between the first trenches T1. Each first trench T1 can expose the side surfaces of the sacrificial layer 105, the semiconductor layer SL, and the first fill pattern 110.

[0075] Reference Figures 11 to 13 The side surfaces of the sacrificial layer 105 and the first fill pattern 110 exposed by the first trench T1 can be laterally recessed. Therefore, a first recessed region INR1 can be formed. The first recessed region INR1 can be located between semiconductor layers SL spaced apart from each other in the third direction D3, and can extend between semiconductor layers SL spaced apart from each other along the first direction D1. The lowest first recessed region INR1 can be located between the substrate 100 and the lowest semiconductor layer SL, and can expose the upper surface 100U of the substrate 100.

[0076] Reference Figures 14 to 16 A second filling pattern 120 can be formed to fill the first recessed region INR1 and the first trench T1. The second filling pattern 120 may include an insulating material and may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0077] A second trench T2 can be formed to penetrate the sacrificial layer 105 and the semiconductor layer SL. The second trench T2 can extend in the first direction D1 and the third direction D3, and can expose the upper surface 100U of the substrate 100. The semiconductor layer SL can be separated by the second trench T2 into a plurality of semiconductor patterns SP spaced apart from each other in the first direction D1, the second direction D2, and the third direction D3. Each semiconductor pattern SP can have a stripe extending in the second direction D2. The second trench T2 can expose the side surfaces of the sacrificial layer 105 and the first filler pattern 110.

[0078] The remaining portion of the sacrificial layer 105 and the first fill pattern 110 can be removed by laterally recessing the side surfaces of the sacrificial layer 105 and the first fill pattern 110 exposed by the second trench T2. Thus, a second recessed region INR2 can be formed. The second recessed region INR2 can be located between semiconductor patterns SP spaced apart from each other in the third direction D3, and can extend between semiconductor patterns SP spaced apart from each other along the first direction D1. The lowermost second recessed region INR2 can be located between the substrate 100 and the lowermost semiconductor pattern SP, and can expose the upper surface 100U of the substrate 100. The second recessed region INR2 can expose the side surfaces of the second fill pattern 120.

[0079] Reference Figures 17 to 19 A third fill pattern 130 can be formed to fill the second trench T2 and the second recessed region INR2. The third fill pattern 130 may include an insulating material and may include, for example, silicon oxide, silicon nitride, and / or silicon oxynitride. The second fill pattern 120 can then be removed, and each semiconductor pattern SP can be partially exposed.

[0080] An initial gate insulating layer (GIL) can be formed to conformally cover the exposed portion of the semiconductor pattern SP. The initial gate insulating layer (GIL) can extend to conformally cover the side surface of the third fill pattern 130 between the semiconductor patterns SP, the side surface of the third fill pattern 130 between the substrate 100 and the lowermost semiconductor pattern SP, and the upper surface 100U of the substrate 100.

[0081] A capping insulating layer 140 may be formed on the initial gate insulating layer GIL and may be formed to conformally cover the exposed portions of the semiconductor pattern SP. The capping insulating layer 140 may extend to conformally cover the side surface of the third fill pattern 130 between the semiconductor patterns SP, the side surface of the third fill pattern 130 between the substrate 100 and the lowermost semiconductor pattern SP, and the upper surface 100U of the substrate 100. The initial gate insulating layer GIL may be located between the capping insulating layer 140 and the exposed portions of the semiconductor pattern SP, between the capping insulating layer 140 and the side surface of the third fill pattern 130, and between the capping insulating layer 140 and the upper surface 100U of the substrate 100.

[0082] A molded insulating layer 150 can be formed to cover the exposed portions of the semiconductor pattern SP. The molded insulating layer 150 can extend in a second direction D2 between the exposed portions of the semiconductor pattern SP, and can also extend in the second direction D2 between the substrate 100 and the lowermost semiconductor pattern SP. The initial gate insulating layer GIL and the capping insulating layer 140 can be located between the molded insulating layer 150 and the exposed portions of the semiconductor pattern SP, between the molded insulating layer 150 and the side surface of the third fill pattern 130, and between the molded insulating layer 150 and the upper surface 100U of the substrate 100.

[0083] Reference Figures 20 to 22 A third trench T3 can be formed to penetrate the molding insulating layer 150. The third trenches T3 can extend in a first direction D1 and can be spaced apart from each other in a second direction D2. Each third trench T3 can extend in a third direction D3 to expose the initial gate insulating layer GIL on the upper surface 100U of the substrate 100. Each third trench T3 can expose the side surfaces of the semiconductor pattern SP, the initial gate insulating layer GIL, the capping insulating layer 140, and the molding insulating layer 150. The remaining portions of the semiconductor pattern SP, the initial gate insulating layer GIL, the capping insulating layer 140, the molding insulating layer 150, and the third fill pattern 130 can be disposed between the third trenches T3. The remaining portion of the molding insulating layer 150 can be referred to as the molding pattern 150. The molding pattern 150 can extend between the semiconductor patterns SP in the first direction D1 and the second direction D2.

[0084] The side surfaces of the capping insulating layer 140 can be exposed through each third trench T3. The side surfaces of the capping insulating layer 140 can be laterally recessed. Therefore, a first capping pattern CP1 can be formed. The first capping pattern CP1 can extend in the first direction D1 and can partially surround each semiconductor pattern SP. The first capping pattern CP1 can extend between the side surfaces of the molded pattern 150 and the third fill pattern 130.

[0085] The side surface of the capping insulating layer 140 can be laterally recessed to form an empty region, and a first initial conductive layer 160-1 can be formed to fill the empty region. Forming the first initial conductive layer 160-1 may include: forming a first initial conductive layer 160-1 that fills the empty region and partially fills each third trench T3, and removing a first portion of the first initial conductive layer 160-1 in each third trench T3. Each third trench T3 may expose the semiconductor pattern SP, the molded pattern 150, the initial gate insulating layer GIL, and the side surface of the conductive layer 160.

[0086] Reference Figures 23 to 25 The side surface of the first initial conductive layer 160-1 can be exposed through each third trench T3. The side surface of the first initial conductive layer 160-1 can be laterally recessed. Therefore, a third recessed region INR3 can be formed, and the remaining portion of the first initial conductive layer 160-1 can remain adjacent to the first capping pattern CP1.

[0087] Each third recessed region INR3 may surround each semiconductor pattern SP located between a pair of molded patterns 150 adjacent to each other on a third-direction D3 within the molded pattern 150. Each third recessed region INR3 may expose the initial gate insulating layer GIL on each semiconductor pattern SP.

[0088] Reference Figure 23 , Figure 25 and Figure 26 Each semiconductor pattern SP may have side surfaces SP_S that are opposite to each other in a first direction D1, and upper surfaces SP_U and lower surfaces SP_L that are opposite to each other in a third direction D3. An initial gate insulating layer GIL may cover the side surfaces SP_S, upper surfaces SP_U, and lower surfaces SP_L of each semiconductor pattern SP. Each third recessed region INR3 may expose the initial gate insulating layer GIL on the side surfaces SP_S, upper surfaces SP_U, and lower surfaces SP_L of each semiconductor pattern SP. The remaining portion of the first initial conductive layer 160-1 may be configured to be adjacent to the first capping pattern CP1 and may be locally disposed on the upper surfaces SP_U and lower surfaces SP_L of each semiconductor pattern SP. Therefore, in the region adjacent to the first capping pattern CP1, the initial gate insulating layer GIL on the side surfaces SP_S, upper edges EG_U, and lower edges EG_L of each semiconductor pattern SP may be exposed through each third recessed region INR3.

[0089] A first conductive electronic pattern 162 can be formed on the side surface SP_S of each semiconductor pattern SP, and the first conductive electronic patterns 162 can be spaced apart from each other in the first direction D1. Forming the first conductive electronic pattern 162 may include: forming a first conductive electronic layer that fills the third recessed region INR3, and laterally recessing the first conductive electronic layer through a third trench T3. The first conductive electronic pattern 162 can be configured to be adjacent to the first capping pattern CP1. In the region adjacent to the first capping pattern CP1, the first conductive electronic pattern 162 can cover the initial gate insulating layer GIL on the side surface SP_S, the upper edge EG_U, and the lower edge EG_L of each semiconductor pattern SP, and can at least partially cover the remaining portion of the first initial conductive layer 160-1.

[0090] Reference Figures 27 to 29 A first additional conductive layer can be formed to fill the third recessed region INR3, thereby forming a second initial conductive layer 160-2. Forming the second initial conductive layer 160-2 may include: forming a first additional conductive layer that fills the third recessed region INR3 and partially fills each third trench T3; removing the first additional conductive layer in each third trench T3; and laterally recessing the first additional conductive layer in each third recessed region INR3. Thus, the combination of the remaining portions of the first initial conductive layer 160-1 and the first additional conductive layer can form the second initial conductive layer 160-2. For example, the first initial conductive layer 160-1 and the first additional conductive layer can be formed of the same material, and the second initial conductive layer 160-2 can be a single homogeneous body. The second initial conductive layer 160-2 can cover the first conductive subpattern 162 and can surround each semiconductor pattern SP located between a pair of molded patterns 150.

[0091] Reference Figure 26 , Figure 27 and Figure 29 The second initial conductive layer 160-2 can be locally (or partially) disposed on the upper surface SP_U and lower surface SP_L of each semiconductor pattern SP. Therefore, the initial gate insulating layer GIL on the side surface SP_S, upper edge EG_U, and lower edge EG_L of each semiconductor pattern SP can be exposed through each third recessed region INR3.

[0092] The second conductive electronic pattern 164 can be formed on the side surface SP_S of each semiconductor pattern SP, and can be spaced apart from each other in the first direction D1. Forming the second conductive electronic pattern 164 may include: forming a second conductive electronic layer that fills the third recessed region INR3, and laterally recessing the second conductive electronic layer through the third trench T3. The first conductive electronic pattern 162 can be spaced apart from the second conductive electronic pattern 164 in the second direction D2. The second conductive electronic pattern 164 can cover the initial gate insulating layer GIL on the side surface SP_S, the upper edge EG_U, and the lower edge EG_L of each semiconductor pattern SP, and can partially cover the second initial conductive layer 160-2.

[0093] Reference Figures 30 to 32 A second additional conductive layer can be formed to fill the third recessed region INR3, thereby forming a conductive pattern 160. Forming the conductive pattern 160 may include: forming a second additional conductive layer that fills the third recessed region INR3 and partially fills each third trench T3, removing a portion of the second additional conductive layer in each third trench T3, and laterally recessing the second additional conductive layer in each third recessed region INR3. Therefore, the combination of the second initial conductive layer 160-2 and the remaining portion of the second additional conductive layer can form the conductive pattern 160. For example, the second initial conductive layer 160-2 and the second additional conductive layer can be formed of the same material, and the conductive pattern 160 can be a single homogeneous body. The conductive pattern 160 can cover the second conductive sub-pattern 164 and can surround each semiconductor pattern SP located between a pair of molded patterns 150.

[0094] For example, the first initial conductive layer 160-1 and the remaining portions of the first and second additional conductive layers can be collectively referred to as conductive pattern 160. Conductive pattern 160, first conductive sub-pattern 162, and second conductive sub-pattern 164 can constitute a gate electrode GE. The gate electrode GE can extend in the first direction D1 and can surround the corresponding semiconductor pattern SP.

[0095] Reference Figure 33 and Figure 34 The second capping pattern CP2 can be formed to fill the third recessed region INR3. The second capping pattern CP2 can extend in the first direction D1 and can partially surround each semiconductor pattern SP. The initial gate insulating layer GIL can be located between the gate electrode GE and each semiconductor pattern SP, and can extend between the first capping pattern CP1 and each semiconductor pattern SP and between the second capping pattern CP2 and each semiconductor pattern SP. The initial gate insulating layer GIL can also extend between the first capping pattern CP1 and the side surface of the third fill pattern 130.

[0096] The buried insulating layer 190 may be formed to fill each third trench T3. For example, forming the buried insulating layer 190 may include partially removing the initial gate insulating layer GIL exposed by each third trench T3 from the upper surface 100U of the substrate 100, and forming the buried insulating layer 190 to fill each third trench T3.

[0097] Multiple bit lines BL can be formed to penetrate the buried insulating layer 190. The bit lines BL can be spaced apart from each other in a first direction D1. Each bit line BL can penetrate the buried insulating layer 190 in a third direction D3. Each bit line BL can extend in the third direction D3 to be electrically connected to semiconductor patterns SP that are spaced apart from each other in the third direction D3.

[0098] Reference Figure 35 and Figure 36 A fourth trench T4 can be formed to penetrate the third fill pattern 130. The fourth trench T4 can extend in the first direction D1 and in the third direction D3 to expose the upper surface 100U of the substrate 100. The fourth trench T4 can expose the side surfaces of the remaining portion of the third fill pattern 130 between the semiconductor patterns SP. The remaining portion of the third fill pattern 130 can be exposed through the fourth trench T4. The remaining portion of the third fill pattern 130 can be removed, and thus a fourth recessed region INR4 can be formed between the semiconductor patterns SP. During the formation of the fourth recessed region INR4, the initial gate insulating layer GIL can be partially removed together. Therefore, each fourth recessed region INR4 can expose the side surface of the first capping pattern CP1. The remaining portion of the initial gate insulating layer GIL can be referred to as the gate insulating layer GI.

[0099] An insulating layer IL can be formed to fill each fourth recessed region INR4. For example, forming the insulating layer IL may include: forming an insulating layer IL that fills each fourth recessed region INR4 and at least partially fills the fourth trench T4, and removing the insulating layer IL from the fourth trench T4. The insulating layer IL may surround the end of each semiconductor pattern SP. The fourth trench T4 may expose the side surfaces of the end of the semiconductor pattern SP.

[0100] Reference Figure 37 and Figure 38 The exposed side surfaces of the semiconductor pattern SP can be laterally recessed, thus forming empty regions in the insulating layer IL that expose the semiconductor pattern SP respectively. Multiple storage electrodes SE can be formed to fill the empty regions respectively. The multiple storage electrodes SE can be electrically connected to the multiple semiconductor patterns SP respectively. The fourth trench T4 can expose the side surfaces of the multiple storage electrodes SE and the side surfaces of the insulating layer IL.

[0101] Return to reference Figures 3 to 5The insulating layer IL can be laterally recessed on the side surface exposed by the fourth trench T4, thus exposing the upper and lower surfaces of the plurality of storage electrodes SE. The dielectric layer 200 can be formed to conformally cover the side, upper, and lower surfaces of the plurality of storage electrodes SE. The remainder of the insulating layer IL can remain between the first capping pattern CP1 and the dielectric layer 200. The plate electrode PE can be formed to fill the fourth trench T4. The plate electrode PE can extend into the space between the plurality of storage electrodes SE, and the dielectric layer 200 can be interposed between the plate electrode PE and each of the plurality of storage electrodes SE. The plurality of storage electrodes SE, the dielectric layer 200, and the plate electrode PE can constitute a data storage pattern DSP. For example, the data storage pattern DSP can be a capacitor.

[0102] According to the present invention, a gate electrode may extend in a first direction, and a semiconductor pattern may extend in a second direction to penetrate the gate electrode. The semiconductor pattern may include contact regions disposed on both sides (e.g., opposite sides) of the gate electrode, and active regions located between the contact regions and overlapping the gate electrode. The gate electrode may include a conductive pattern and conductive sub-patterns with work functions different from the work functions of the conductive patterns. The conductive sub-patterns may be spaced apart from each other in the first direction, with the active regions of the semiconductor pattern located between the conductive sub-patterns, and the conductive sub-patterns may be configured to be adjacent to corresponding contact regions within the contact regions. The work function of the conductive sub-patterns may be between the work function of the conductive pattern and the work function of the corresponding contact region. Therefore, the electric field generated between the conductive pattern of the gate electrode and the corresponding contact region of the semiconductor pattern can be minimized, thereby preventing or suppressing gate-induced drain leakage (GIDL) between the conductive pattern of the gate electrode and the corresponding contact region of the semiconductor pattern.

[0103] Furthermore, semiconductor patterns and gate electrodes can form transistors, and multiple transistors can be stacked vertically on a substrate.

[0104] Therefore, it is possible to provide semiconductor devices with improved electrical properties and high integration density (as well as methods for manufacturing such semiconductor devices).

[0105] The foregoing description of embodiments of the inventive concept provides examples for illustrating the inventive concept. Therefore, the inventive concept is not limited to the above embodiments, and those skilled in the art can make various modifications and changes within the technical spirit of the inventive concept, such as combining the above embodiments.

Claims

1. A semiconductor device, comprising: The gate electrode extends on the substrate in a first direction; A semiconductor pattern extends in a second direction and penetrates the gate electrode, wherein the first direction and the second direction are parallel to the upper surface of the substrate and intersect each other; and A gate insulating layer is located between the gate electrode and the semiconductor pattern. The semiconductor pattern has a side surface, a top surface, and a bottom surface. Wherein, the side surfaces of the semiconductor pattern are opposite to each other in the first direction. Wherein, the upper surface and the lower surface of the semiconductor pattern are separated from each other in a third direction perpendicular to the upper surface of the substrate. The gate electrode includes: Conductive electronic patterns are each disposed on the side surface of the semiconductor pattern, and the conductive electronic patterns are spaced apart from each other in the first direction. A conductive pattern extends in the first direction, the conductive pattern covering the upper and lower surfaces of the semiconductor pattern, and the conductive pattern covering the conductive sub-pattern. The work function of the conductive sub-pattern is different from the work function of the conductive pattern.

2. The semiconductor device according to claim 1, wherein, The work function of the conductive sub-pattern is lower than that of the conductive pattern.

3. The semiconductor device according to claim 1, wherein: Each of the conductive patterns extends along and covers the upper edge, the upper edge being between the upper surface of the semiconductor pattern and the corresponding side surface of the semiconductor pattern, and Each of the conductive semiconductor patterns extends along and covers the lower edge, which is between the lower surface of the semiconductor pattern and the corresponding side surface of the semiconductor pattern.

4. The semiconductor device according to claim 1, wherein: The gate insulating layer is located between the side surface of the semiconductor pattern and the conductive subpattern. The gate insulating layer is disposed between the upper surface of the semiconductor pattern and the conductive pattern, and The gate insulating layer is disposed between the lower surface of the semiconductor pattern and the conductive pattern.

5. The semiconductor device according to claim 4, wherein: The conductive pattern is disposed between the conductive sub-patterns, and The conductive pattern is in contact with the gate insulating layer.

6. The semiconductor device according to claim 1, wherein, The semiconductor pattern includes: The first contact region and the second contact region are disposed on opposite sides of the gate electrode in the second direction; and The active region overlaps with the gate electrode when viewed from the first direction and the third direction, and the active region is located between the first contact region and the second contact region. The active region includes a first boundary region adjacent to the first contact region, a second boundary region adjacent to the second contact region, and a channel region located between the first boundary region and the second boundary region. Wherein, in the second direction, the conductive sub-pattern is configured to be adjacent to one of the first boundary region and the second boundary region, and The first boundary region and the second boundary region have the same conductivity type as the first contact region and the second contact region, and the doping concentration of the first contact region and the second contact region is greater than the doping concentration of the first boundary region and the second boundary region.

7. The semiconductor device according to claim 6, further comprising: A data storage pattern is electrically connected to the first contact area of ​​the semiconductor pattern; as well as Bit lines are electrically connected to the second contact area of ​​the semiconductor pattern.

8. The semiconductor device according to claim 6, wherein, When viewed from the first direction, the conductive electron pattern overlaps with one of the first boundary region and the second boundary region.

9. The semiconductor device according to claim 8, in, The gate insulating layer is located between the side surfaces of one of the first boundary region and the second boundary region of the conductive subpattern and the semiconductor pattern. Wherein, the gate insulating layer extends to the side surface of the channel region of the semiconductor pattern, and The gate insulating layer is in contact with the side surface of the channel region of the semiconductor pattern.

10. The semiconductor device according to claim 6, in, The work function of the conductive electronic pattern is greater than the work functions of the first contact region and the second contact region of the semiconductor pattern, and Wherein, the work function of the conductive sub-pattern is lower than the work function of the conductive pattern.

11. The semiconductor device according to claim 6, wherein, The conductivity type of the conductive sub-pattern is the same as that of the first contact area and the second contact area.

12. A semiconductor device, comprising: The gate electrode extends on the substrate in a first direction; as well as A semiconductor pattern extends in a second direction and penetrates the gate electrode. Wherein, the first direction and the second direction are parallel to the upper surface of the substrate, and the first direction and the second direction intersect each other. The semiconductor pattern includes: The first contact region and the second contact region are disposed on opposite sides of the gate electrode in the second direction, and The active region, when viewed from the first direction and a third direction perpendicular to the upper surface of the substrate, overlaps with the gate electrode, and the active region is located between the first contact region and the second contact region. The active region includes: The first boundary region is adjacent to the first contact region. The second boundary region is adjacent to the second contact region, and The channel region is located between the first boundary region and the second boundary region. The gate electrode includes: The first conductive electronic patterns are spaced apart from each other in the first direction, and the first boundary region of the semiconductor pattern is located between the first conductive electronic patterns. A conductive pattern extends in the first direction, the conductive pattern surrounds the active region of the semiconductor pattern, and the conductive pattern covers the first conductive sub-pattern. Wherein, the first conductive sub-pattern is located between the first boundary region of the conductive pattern and the semiconductor pattern; Wherein, the work function of the first conductive electronic pattern is different from the work function of the conductive pattern, and The first boundary region and the second boundary region have the same conductivity type as the first contact region and the second contact region, and the doping concentration of the first contact region and the second contact region is greater than the doping concentration of the first boundary region and the second boundary region.

13. The semiconductor device according to claim 12, wherein, The work function of the first conductive electronic pattern is different from the work function of the first contact region of the semiconductor pattern.

14. The semiconductor device according to claim 13, wherein, The conductivity type of the first conductive subpattern is the same as the conductivity type of the first contact region of the semiconductor pattern.

15. The semiconductor device according to claim 12, wherein, The work function of the first conductive electronic pattern is lower than the work function of the conductive pattern.

16. The semiconductor device according to claim 15, wherein, The work function of the first conductive electronic pattern is greater than the work function of the first contact region of the semiconductor pattern.

17. The semiconductor device according to claim 12, wherein, The first conductive electron pattern has an N-type conductivity.

18. The semiconductor device according to claim 12, in, The first boundary region of the semiconductor pattern overlaps with the first conductive semiconductor pattern in the first direction, and Wherein, the channel region of the semiconductor pattern does not overlap with the first conductive semiconductor pattern in the first direction.

19. The semiconductor device of claim 12, further comprising: A gate insulating layer is located between the semiconductor pattern and the gate electrode. The semiconductor pattern has side surfaces that are opposite to each other in the first direction, and upper and lower surfaces that are opposite to each other in the third direction. The gate insulating layer extends along the upper surface, lower surface, and side surface of the semiconductor pattern. Wherein, a first portion of the gate insulating layer is disposed on the side surface of the first boundary region of the semiconductor pattern, and the first portion is in contact with the first conductive semiconductor pattern, and The second portion of the gate insulating layer is disposed on the side surface of the channel region of the semiconductor pattern, and the second portion is in contact with the conductive pattern.

20. The semiconductor device according to claim 12, in, The gate electrode further includes second conductive sub-patterns, which are spaced apart from each other in the first direction, and the second boundary region of the semiconductor pattern is located between the second conductive sub-patterns. Wherein, the second conductive electron pattern is spaced apart from the first conductive electron pattern in the second direction, and The work function of the second conductive electronic pattern is different from the work function of the conductive pattern.

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