Semiconductor structure and method of forming the same

Abstract

The application provides a semiconductor structure and a forming method thereof, and the semiconductor structure comprises an SOI substrate, a dielectric layer is formed on the surface of the SOI substrate, an epitaxial layer is formed in the dielectric layer and penetrates the dielectric layer, the epitaxial layer comprises a core region located in the middle and a peripheral region surrounding the core region, a groove is formed in the epitaxial layer of the peripheral region and exposes the SOI substrate, the groove also exposes first, second, third and fourth side walls of the epitaxial layer of the core region in sequence, a first doped layer is formed on the first and second side walls of the epitaxial layer of the core region and the surface of the SOI substrate adjacent to the first and second side walls, and a second doped layer is formed on the third and fourth side walls of the epitaxial layer of the core region and the surface of the SOI substrate adjacent to the third and fourth side walls. The application provides a semiconductor structure and a forming method thereof, and can solve or alleviate the problem of bandwidth degradation of a germanium detector under high input power.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] The era of "big data" has posed enormous challenges to traditional communication systems. Optical communication systems based on silicon-based optoelectronic technology offer advantages such as low cost, low power consumption, and high speed, making them an effective solution for addressing data transmission capacity and rate limitations. Silicon-based germanium detectors (PDs), as one of the core components in optical communication systems, have key parameters such as bandwidth and responsivity that directly impact system performance. The main optimization direction for high-performance silicon-based germanium detectors is to resolve or improve the trade-offs between bandwidth, input power, responsivity, and saturation power.

[0003] When the input optical power is weak, the detector is considered a linear device and can directly achieve photoelectric conversion. As the optical power gradually increases, the nonlinearity of the detector increases due to the nonlinearity of light absorption, the nonlinearity of carrier movement within the PIN junction, and the nonlinearity of the radio frequency signal in the circuit. This manifests as the detector failing to function properly and its performance deteriorating. Since the nonlinear processes are mutually coupled and closely related to carrier movement, the most critical factor is the nonlinearity of carrier movement within the PIN junction. The main mechanism is the space charge effect: the built-in electric field of the PIN junction separates photogenerated electron-hole pairs, but the Coulomb force formed by these pairs hinders this separation mechanism. When the number of photogenerated carriers is large, the number of space charges increases, and the Coulomb force can affect the distribution of the built-in electric field, preventing the photogenerated carriers from being separated and transported to the outside. This is reflected in a decrease in detector bandwidth and output power saturation.

[0004] Therefore, it is necessary to develop a solution suitable for silicon-based optoelectronic platforms to solve or mitigate the problem of bandwidth degradation of germanium detectors under high input power. Summary of the Invention

[0005] This application provides a semiconductor structure and a method for forming the same, which can solve or alleviate the problem of bandwidth degradation of germanium detectors under high input power.

[0006] One aspect of this application provides a method for forming a semiconductor structure, comprising: providing an SOI substrate, wherein a dielectric layer is formed on the surface of the SOI substrate, and an epitaxial layer penetrating the dielectric layer is formed therein, the epitaxial layer including a core region located in the middle and a peripheral region surrounding the core region; etching the epitaxial layer of the peripheral region to form a trench exposing the SOI substrate, the trench further exposing a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall of the epitaxial layer of the core region that are sequentially connected; forming a first doped layer on a portion of the first and second sidewalls of the epitaxial layer of the core region and on the adjacent surface of the SOI substrate; and forming a second doped layer on a portion of the third and fourth sidewalls of the epitaxial layer of the core region and on the adjacent surface of the SOI substrate.

[0007] In some embodiments of this application, the doping types of the first doped layer and the second doped layer are opposite.

[0008] In some embodiments of this application, the SOI substrate includes mutually perpendicular x and y directions, the cross-sectional pattern of the epitaxial layer is rectangular, the cross-sectional pattern of the core region is rectangular, the ratio of the size of the core region in the x direction to the sum of the sizes of the core region and the peripheral region in the x direction is 1:(1.5-8), and the ratio of the size of the core region in the y direction to the size of the epitaxial layer in the y direction is 1:(1.1-2).

[0009] In some embodiments of this application, the ratio of the dimension of the first doped layer located on the first sidewall in the y direction to the dimension of the first sidewall in the y direction is (0.5-0.9):1, and the ratio of the dimension of the first doped layer located on the second sidewall in the x direction to the dimension of the second sidewall in the x direction is (0.1-0.9):1.

[0010] In some embodiments of this application, the ratio of the size of the second doped layer located on the third sidewall in the y-direction to the size of the third sidewall in the y-direction is (0.5-0.9):1, and the ratio of the size of the second doped layer located on the fourth sidewall in the x-direction to the size of the fourth sidewall in the x-direction is (0.1-0.9):1.

[0011] In some embodiments of this application, the thickness of the first doped layer is 40-60 nanometers, and the thickness of the second doped layer is 40-60 nanometers.

[0012] Another aspect of this application provides a semiconductor structure comprising: an SOI substrate, a dielectric layer formed on the surface of the SOI substrate, an epitaxial layer formed in the dielectric layer penetrating the dielectric layer, the epitaxial layer including a core region located in the middle and a peripheral region surrounding the core region; a trench in the epitaxial layer located in the peripheral region exposing the SOI substrate, the trench also exposing a first sidewall, a second sidewall, a third sidewall and a fourth sidewall of the epitaxial layer in the core region connected sequentially; a portion of the first sidewall and the second sidewall of the epitaxial layer located in the core region and a first doped layer on the surface of the SOI substrate adjacent thereto; and a portion of the third sidewall and the fourth sidewall of the epitaxial layer located in the core region and a second doped layer on the surface of the SOI substrate adjacent thereto.

[0013] In some embodiments of this application, the doping types of the first doped layer and the second doped layer are opposite.

[0014] In some embodiments of this application, the SOI substrate includes mutually perpendicular x and y directions, the cross-sectional pattern of the epitaxial layer is rectangular, the cross-sectional pattern of the core region is rectangular, the ratio of the size of the core region in the x direction to the sum of the sizes of the core region and the peripheral region in the x direction is 1:(1.5-8), and the ratio of the size of the core region in the y direction to the size of the epitaxial layer in the y direction is 1:(1.1-2).

[0015] In some embodiments of this application, the ratio of the dimension of the first doped layer located on the first sidewall in the y direction to the dimension of the first sidewall in the y direction is (0.5-0.9):1, and the ratio of the dimension of the first doped layer located on the second sidewall in the x direction to the dimension of the second sidewall in the x direction is (0.1-0.9):1.

[0016] In some embodiments of this application, the ratio of the size of the second doped layer located on the third sidewall in the y-direction to the size of the third sidewall in the y-direction is (0.5-0.9):1, and the ratio of the size of the second doped layer located on the fourth sidewall in the x-direction to the size of the fourth sidewall in the x-direction is (0.1-0.9):1.

[0017] In some embodiments of this application, the thickness of the first doped layer is 40-60 nanometers, and the thickness of the second doped layer is 40-60 nanometers.

[0018] This application provides a semiconductor structure and a method for forming the same, which can solve or alleviate the problem of bandwidth degradation of germanium detectors under high input power. Attached Figure Description

[0019] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0020] in:

[0021] Figures 1 to 16 This is a schematic diagram of each step in the method for forming a semiconductor structure according to the embodiments of this application. Detailed Implementation

[0022] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0023] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0024] Figures 1 to 16 This is a schematic diagram of each step in the method for forming a semiconductor structure according to an embodiment of this application. The method for forming a semiconductor structure according to an embodiment of this application will be described in detail below with reference to the accompanying drawings.

[0025] refer to Figure 1 and Figure 2 As shown, where, Figure 1 This is a top view. Figure 2 For along Figure 1 A longitudinal cross-sectional view at the dashed line AA. An SOI substrate 100 is provided, the SOI substrate 100 including a bottom silicon layer 101, an insulating layer 102 and a top silicon layer 103, a dielectric layer 110 formed on the surface of the SOI substrate 100, an epitaxial layer 120 formed in the dielectric layer 110, the epitaxial layer 120 including a core region 121 located in the middle and a peripheral region 122 surrounding the core region 121.

[0026] In some embodiments of this application, the semiconductor structure is, for example, a silicon-based germanium photodetector based on an SOI substrate.

[0027] In some embodiments of this application, the bottom silicon layer 101 is made of silicon, the insulating layer 102 is made of silicon dioxide, and the top silicon layer 103 is made of silicon. Silicon-on-insulator (SOI) substrates are common substrate structures in semiconductor structures; therefore, the formation process and detailed structure of the SOI substrate 100 will not be described here.

[0028] In some embodiments of this application, the material of the dielectric layer 110 includes silicon oxide.

[0029] In some embodiments of this application, the epitaxial layer 120 is made of germanium. The epitaxial layer 120 is epitaxially grown using the top silicon layer 103 as a substrate. The epitaxial layer 120 is used to fabricate the silicon-based germanium photodetector, and the position and size of the epitaxial layer 120 are set according to the semiconductor layout design.

[0030] In some embodiments of this application, reference is made to Figure 1 As shown, the SOI substrate 100 includes mutually perpendicular x and y directions. The cross-sectional pattern of the epitaxial layer 120 is rectangular, and the cross-sectional pattern of the core region 121 is rectangular. The ratio of the size of the core region 121 in the x direction to the sum of the sizes of the core region 121 and the peripheral region 122 in the x direction is 1:(1.5-8). The ratio of the size of the core region 121 in the y direction to the size of the epitaxial layer 120 in the y direction is 1:(1.1-2).

[0031] Specifically, for example, the epitaxial layer 120 has a dimension of 0.5 micrometers in the x-direction and a dimension of 12 micrometers in the y-direction. The core region 121 has a dimension of 0.15 micrometers in the x-direction and a dimension of 10 micrometers in the y-direction. The height of the epitaxial layer 120 is 0.15-0.5 micrometers.

[0032] refer to Figure 3 and Figure 4 As shown, where, Figure 3 This is a top view. Figure 4 For along Figure 3 Longitudinal cross-section at the dashed line AA. The epitaxial layer 120 of the peripheral region 122 is etched to form a trench 130 that exposes the SOI substrate 100. The trench 130 also exposes the first sidewall 131, the second sidewall 132, the third sidewall 133 and the fourth sidewall 134 of the epitaxial layer 120 of the core region 121, which are connected in sequence.

[0033] In some embodiments of this application, the method of etching the epitaxial layer 120 of the peripheral region 122 to form a trench 130 exposing the SOI substrate 100 includes: forming a patterned mask layer on the surfaces of the dielectric layer 110 and the epitaxial layer 120, the patterned mask layer defining the location of the trench 130; and etching the epitaxial layer 120 using the patterned mask layer as a mask to form the trench 130. The patterned mask layer may be removed after the trench 130 is formed or retained first to protect the dielectric layer 110 and the remaining epitaxial layer 120, and then removed after the formation of the first doped layer and the second doped layer.

[0034] refer to Figures 5 to 8 As shown, a first doped layer 150 is formed on a portion of the first sidewall 131 and the second sidewall 132 of the epitaxial layer 120 in the core region 121 and on the surface of the SOI substrate 100 adjacent thereto.

[0035] Specifically, refer to Figure 5 and Figure 6 As shown, where, Figure 5 This is a top view. Figure 6 For along Figure 5 A longitudinal cross-sectional view at the dashed line AA. A patterned hard mask layer 140 is formed on the sidewalls and bottom of the trench 130 and on the surfaces of the dielectric layer 110 and the epitaxial layer 120. The patterned hard mask layer 140 defines the location of the first doped layer 150. That is, the patterned hard mask layer 140 exposes a portion of the first sidewall 131 and the second sidewall 132 of the epitaxial layer 120 in the core region 121, as well as the surface of the adjacent SOI substrate 100.

[0036] In some embodiments of this application, the patterned hard mask layer 140 is made of silicon nitride.

[0037] refer to Figure 7 and Figure 8 As shown, where, Figure 7 This is a top view. Figure 8 For along Figure 7 Longitudinal cross-section at the dashed line AA. A first doped layer 150 is formed on a portion of the first sidewall 131 and the second sidewall 132 of the epitaxial layer 120 in the core region 121 and on the surface of the adjacent SOI substrate 100.

[0038] In some embodiments of this application, the method for forming the first doped layer 150 is as follows: the first doped layer 150 is formed by in-situ doping epitaxial growth process using a portion of the first sidewall 131 and the second sidewall 132 of the epitaxial layer 120 of the core region 121 and the surface of the adjacent SOI substrate 100 as the matrix.

[0039] In some embodiments of this application, the material of the first doped layer 150 is doped silicon. The doping type of the first doped layer 150 is P-type or N-type.

[0040] In some embodiments of this application, the thickness of the first doped layer 150 is 40-60 nanometers.

[0041] In some embodiments of this application, the ratio of the dimension of the first doped layer 150 located on the first sidewall 131 in the y direction to the dimension of the first sidewall 131 in the y direction is (0.5-0.9):1, and the ratio of the dimension of the first doped layer 150 located on the second sidewall 132 in the x direction to the dimension of the second sidewall 132 in the x direction is (0.1-0.9):1.

[0042] refer to Figure 9 and Figure 10 As shown, where, Figure 9 This is a top view. Figure 10 For along Figure 9 Longitudinal cross-section at the dashed line AA. A cover layer 160 is formed in the trench 130 and on the surface of the patterned hard mask layer 140, filling the trench 130 and covering the hard mask layer 140.

[0043] In some embodiments of this application, the material of the cover layer 160 includes silicon oxide.

[0044] refer to Figures 11 to 14 As shown, a second doped layer 170 is formed on a portion of the third sidewall 133 and the fourth sidewall 134 of the epitaxial layer 120 in the core region 121 and on the surface of the SOI substrate 100 adjacent thereto.

[0045] Specifically, refer to Figure 11 and Figure 12 As shown, where, Figure 11 This is a top view. Figure 12 For along Figure 11 Longitudinal cross-section at the dashed line AA. The capping layer 160 and the patterned hard mask layer 140 are etched to expose portions of the third sidewall 133 and the fourth sidewall 134 of the epitaxial layer 120 of the core region 121 and the surface of the adjacent SOI substrate 100 to define the location of the second doped layer 170.

[0046] refer to Figure 13 and Figure 14 As shown, where, Figure 13 This is a top view. Figure 14 For along Figure 13 Longitudinal cross-section at the dashed line AA. A second doped layer 170 is formed on a portion of the third sidewall 133 and the fourth sidewall 134 of the epitaxial layer 120 in the core region 121 and on the surface of the adjacent SOI substrate 100.

[0047] In some embodiments of this application, the method for forming the second doped layer 170 is as follows: the second doped layer 170 is formed by in-situ doping epitaxial growth process using a portion of the third sidewall 133 and the fourth sidewall 134 of the epitaxial layer 120 of the core region 121 and the surface of the adjacent SOI substrate 100 as the matrix.

[0048] In some embodiments of this application, the material of the second doped layer 170 is doped silicon. The doping type of the second doped layer 170 is P-type or N-type.

[0049] In some embodiments of this application, the first doped layer 150 and the second doped layer 170 have opposite doping types.

[0050] In some embodiments of this application, the ratio of the dimension of the second doped layer 170 located on the third sidewall 133 in the y direction to the dimension of the third sidewall 133 in the y direction is (0.5-0.9):1, and the ratio of the dimension of the second doped layer 170 located on the fourth sidewall 134 in the x direction to the dimension of the fourth sidewall 134 in the x direction is (0.1-0.9):1.

[0051] In some embodiments of this application, the thickness of the second doped layer 170 is 40-60 nanometers.

[0052] refer to Figure 15 and Figure 16 As shown, where, Figure 15 This is a top view. Figure 16 For along Figure 15 A longitudinal cross-sectional view at the dashed line AA. The cover layer 160 and the patterned hard mask layer 140 above the top surface of the dielectric layer 110 are removed, leaving the remaining patterned hard mask layer 140 as an isolation layer 180. The isolation layer 180 isolates the first doped layer 150 and the second doped layer 170, preventing short circuits between them.

[0053] refer to Figure 15 As shown, in the technical solution of this application, by introducing a PIN junction in the y direction, an accelerating electric field is formed in the y direction within the germanium absorption region, making the carrier distribution in the y direction more uniform, reducing the accumulation of photogenerated carriers, alleviating the space charge effect, and significantly improving the device bandwidth while being compatible with existing processes.

[0054] In some embodiments of this application, the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer on the SOI substrate 100 covering the SOI substrate 100, the dielectric layer 110, and the first doped layer 150 and the second doped layer 170; and forming a contact structure in the interlayer dielectric layer that penetrates the interlayer dielectric layer and electrically connects the first doped layer 150 and the second doped layer 170 respectively.

[0055] This application provides a method for forming a semiconductor structure, which can solve or alleviate the problem of bandwidth degradation of germanium detectors under high input power.

[0056] Embodiments of this application also provide a semiconductor structure, referencing Figure 15 and Figure 16 As shown, the system includes: an SOI substrate 100, a dielectric layer 110 formed on the surface of the SOI substrate 100, an epitaxial layer 120 formed in the dielectric layer 110 penetrating the dielectric layer 110, the epitaxial layer 120 including a core region 121 located in the center and a peripheral region 122 surrounding the core region 121; a trench 130 exposed in the epitaxial layer 120 located in the peripheral region 122 exposing the SOI substrate 100, the trench 130 also exposing the outer surface of the core region 121. The epitaxial layer 120 consists of a first sidewall 131, a second sidewall 132, a third sidewall 133, and a fourth sidewall 134 connected in sequence; a portion of the first sidewall 131 and the second sidewall 132 of the epitaxial layer 120 located in the core region 121, and a first doped layer 150 located on the surface of the SOI substrate 100 adjacent to them; and a portion of the third sidewall 133 and the fourth sidewall 134 of the epitaxial layer 120 located in the core region 121, and a second doped layer 170 located on the surface of the SOI substrate 100 adjacent to them.

[0057] In some embodiments of this application, the semiconductor structure is, for example, a silicon-based germanium photodetector based on an SOI substrate.

[0058] In some embodiments of this application, the SOI substrate 100 includes a bottom silicon layer 101, an insulating layer 102, and a top silicon layer 103. The bottom silicon layer 101 is made of silicon, the insulating layer 102 is made of silicon dioxide, and the top silicon layer 103 is made of silicon. Silicon-on-insulator (SOI) substrates are common substrate structures in semiconductor structures; therefore, the formation process and detailed structure of the SOI substrate 100 will not be described here.

[0059] In some embodiments of this application, the material of the dielectric layer 110 includes silicon oxide.

[0060] In some embodiments of this application, the epitaxial layer 120 is made of germanium. The epitaxial layer 120 is epitaxially grown using the top silicon layer 103 as a substrate. The epitaxial layer 120 is used to fabricate the silicon-based germanium photodetector, and the position and size of the epitaxial layer 120 are set according to the semiconductor layout design.

[0061] In some embodiments of this application, reference is made to Figure 1 As shown, the SOI substrate 100 includes mutually perpendicular x and y directions. The cross-sectional pattern of the epitaxial layer 120 is rectangular, and the cross-sectional pattern of the core region 121 is rectangular. The ratio of the size of the core region 121 in the x direction to the sum of the sizes of the core region 121 and the peripheral region 122 in the x direction is 1:(1.5-8). The ratio of the size of the core region 121 in the y direction to the size of the epitaxial layer 120 in the y direction is 1:(1.1-2).

[0062] Specifically, for example, the epitaxial layer 120 has a dimension of 0.5 micrometers in the x-direction and a dimension of 12 micrometers in the y-direction. The core region 121 has a dimension of 0.15 micrometers in the x-direction and a dimension of 10 micrometers in the y-direction. The height of the epitaxial layer 120 is 0.5 micrometers.

[0063] In some embodiments of this application, the material of the first doped layer 150 is doped silicon. The doping type of the first doped layer 150 is P-type or N-type.

[0064] In some embodiments of this application, the thickness of the first doped layer 150 is 40-60 nanometers.

[0065] In some embodiments of this application, the ratio of the dimension of the first doped layer 150 located on the first sidewall 131 in the y direction to the dimension of the first sidewall 131 in the y direction is 0.9:1, and the ratio of the dimension of the first doped layer 150 located on the second sidewall 132 in the x direction to the dimension of the second sidewall 132 in the x direction is 0.5:1.

[0066] In some embodiments of this application, the material of the second doped layer 170 is doped silicon. The doping type of the second doped layer 170 is P-type or N-type.

[0067] In some embodiments of this application, the first doped layer 150 and the second doped layer 170 have opposite doping types.

[0068] In some embodiments of this application, the ratio of the dimension of the second doped layer 170 located on the third sidewall 133 in the y direction to the dimension of the third sidewall 133 in the y direction is (0.5-0.9):1, and the ratio of the dimension of the second doped layer 170 located on the fourth sidewall 134 in the x direction to the dimension of the fourth sidewall 134 in the x direction is (0.1-0.9):1.

[0069] In some embodiments of this application, the thickness of the second doped layer 170 is 40-60 nanometers.

[0070] Continue to refer to Figure 15 and Figure 16 As shown, an isolation layer 180 is also formed on the surface of the SOI substrate 100 where the first doped layer 150 and the second doped layer 170 are not formed in the peripheral region 122, and on the sidewalls of the epitaxial layer 120 where the first doped layer 150 and the second doped layer 170 are not formed. The isolation layer 180 is used to isolate the first doped layer 150 and the second doped layer 170, preventing the first doped layer 150 and the second doped layer 170 from short-circuiting.

[0071] In some embodiments of this application, the material of the isolation layer 180 includes silicon nitride.

[0072] refer to Figure 15 As shown, in the technical solution of this application, by introducing a PIN junction in the y direction, an accelerating electric field is formed in the y direction within the germanium absorption region, making the carrier distribution in the y direction more uniform, reducing the accumulation of photogenerated carriers, alleviating the space charge effect, and significantly improving the device bandwidth while being compatible with existing processes.

[0073] In some embodiments of this application, the semiconductor structure further includes: an interlayer dielectric layer covering the SOI substrate 100, the dielectric layer 110, and the first doped layer 150 and the second doped layer 170; and a contact structure located in the interlayer dielectric layer and passing through the interlayer dielectric layer to electrically connect the first doped layer 150 and the second doped layer 170 respectively.

[0074] This application provides a semiconductor structure and a method for forming the same, which can solve or alleviate the problem of bandwidth degradation of germanium detectors under high input power.

[0075] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0076] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0077] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0078] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0079] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: An SOI substrate is provided, wherein a dielectric layer is formed on the surface of the SOI substrate, and an epitaxial layer is formed in the dielectric layer, the epitaxial layer including a core region located in the middle and a peripheral region surrounding the core region; The epitaxial layer of the peripheral region is etched to form a trench that exposes the SOI substrate. The trench also exposes a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall that are sequentially connected to the epitaxial layer of the core region. A first doped layer is formed on a portion of the first and second sidewalls of the epitaxial layer in the core region and on the surface of the adjacent SOI substrate. A second doped layer is formed on a portion of the third and fourth sidewalls of the epitaxial layer in the core region and on the surface of the adjacent SOI substrate.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first doped layer and the second doped layer have opposite doping types.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The SOI substrate includes mutually perpendicular x and y directions. The cross-sectional pattern of the epitaxial layer is rectangular, and the cross-sectional pattern of the core region is rectangular. The ratio of the size of the core region in the x direction to the sum of the sizes of the core region and the peripheral region in the x direction is 1:(1.5-8). The ratio of the size of the core region in the y direction to the size of the epitaxial layer in the y direction is 1:(1.1-2).

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The ratio of the dimension of the first doped layer in the y-direction to the dimension of the first sidewall in the y-direction is (0.5-0.9):1, and the ratio of the dimension of the first doped layer in the x-direction to the dimension of the second sidewall in the x-direction is (0.1-0.9):

1.

5. The method for forming a semiconductor structure as described in claim 3, characterized in that, The ratio of the dimension of the second doped layer located on the third sidewall in the y-direction to the dimension of the third sidewall in the y-direction is (0.5-0.9):1, and the ratio of the dimension of the second doped layer located on the fourth sidewall in the x-direction to the dimension of the fourth sidewall in the x-direction is (0.1-0.9):

1.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the first doped layer is 40-60 nanometers, and the thickness of the second doped layer is 40-60 nanometers.

7. A semiconductor structure, characterized in that, include: An SOI substrate, wherein a dielectric layer is formed on the surface of the SOI substrate, and an epitaxial layer is formed in the dielectric layer, the epitaxial layer including a core region located in the middle and a peripheral region surrounding the core region; The trench in the epitaxial layer of the peripheral region exposes the SOI substrate, and the trench also exposes the first sidewall, second sidewall, third sidewall and fourth sidewall of the epitaxial layer of the core region connected in sequence; The first and second sidewalls of the epitaxial layer located in the core region and the first doped layer on the surface of the adjacent SOI substrate; The third and fourth sidewalls of the epitaxial layer located in the core region and the second doped layer on the surface of the SOI substrate adjacent to them.

8. The semiconductor structure as described in claim 7, characterized in that, The first doped layer and the second doped layer have opposite doping types.

9. The semiconductor structure as described in claim 7, characterized in that, The SOI substrate includes mutually perpendicular x and y directions. The cross-sectional pattern of the epitaxial layer is rectangular, and the cross-sectional pattern of the core region is rectangular. The ratio of the size of the core region in the x direction to the sum of the sizes of the core region and the peripheral region in the x direction is 1:(1.5-8). The ratio of the size of the core region in the y direction to the size of the epitaxial layer in the y direction is 1:(1.1-2).

10. The semiconductor structure as described in claim 9, characterized in that, The ratio of the dimension of the first doped layer in the y-direction to the dimension of the first sidewall in the y-direction is (0.5-0.9):1, and the ratio of the dimension of the first doped layer in the x-direction to the dimension of the second sidewall in the x-direction is (0.1-0.9):

1.

11. The semiconductor structure as described in claim 9, characterized in that, The ratio of the dimension of the second doped layer located on the third sidewall in the y-direction to the dimension of the third sidewall in the y-direction is (0.5-0.9):1, and the ratio of the dimension of the second doped layer located on the fourth sidewall in the x-direction to the dimension of the fourth sidewall in the x-direction is (0.1-0.9):

1.

12. The semiconductor structure as claimed in claim 7, characterized in that, The thickness of the first doped layer is 40-60 nanometers, and the thickness of the second doped layer is 40-60 nanometers.

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