Image sensor comprising a grid

Abstract

An image sensor includes: a substrate including a first surface, a second surface opposite to the first surface, a first region located at a central region of the substrate, an optical black region, and a second region located between the first region and the optical black region in a planar view; a plurality of color filters located on the second surface of the substrate; a first grid located on the first region between the plurality of color filters; and a second grid located on the second region between the plurality of color filters. The first grid may include N layers stacked in a first direction perpendicular to the second surface of the substrate, and the second grid may include M layers stacked in the first direction. The height of the first grid in the first direction may be different from the height of the second grid in the first direction. N and M may be integers equal to or greater than 1, and N may be different from M. The image sensor may be configured to receive light from the second surface of the substrate.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0194687, filed on December 23, 2024, and Korean Patent Application No. 10-2025-0010617, filed on January 23, 2025, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] Embodiments of this disclosure relate to image sensors. Background Technology

[0003] An image sensor is a device that converts optical image signals into electrical signals. Image sensors include charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors. An image sensor comprises multiple pixels. Each of these pixels may include a photoelectric conversion region that receives incident light and converts the received light into an electrical signal, and pixel circuitry that outputs the pixel signal using the charge generated in the photoelectric conversion region. Image sensors are used in a variety of fields, such as digital cameras, camcorders, smartphones, gaming devices, surveillance cameras, medical miniature cameras, robots, and vehicles. Summary of the Invention

[0004] The embodiments disclosed herein provide an image sensor with improved optical properties. However, the embodiments are not limited thereto.

[0005] According to one or more embodiments, an image sensor includes: a substrate including a first surface, a second surface opposite to the first surface, a first region located at a central region of the substrate, an optical black region, and a second region located between the first region and the optical black region in a planar view; a plurality of color filters located on the second surface of the substrate; a first grid located on the first region between the plurality of color filters; and a second grid located on the second region between the plurality of color filters. The first grid may include N layers stacked in a first direction perpendicular to the second surface of the substrate, and the second grid may include M layers stacked in the first direction. The height of the first grid in the first direction may be different from the height of the second grid in the first direction. N and M may be integers equal to or greater than 1, N may be different from M, and the image sensor may be configured to receive light from the second surface of the substrate.

[0006] According to one or more embodiments, an image sensor includes: a substrate including a first surface, a second surface opposite to the first surface, a first region located at a central region of the substrate, an optical black region, and a second region located between the first region and the optical black region in a plan view; a plurality of color filters located on the second surface of the substrate; a first grid located between the plurality of color filters on the first region; a second grid located between the plurality of color filters on the second region; and a third grid located on the second surface of the substrate on the optical black region. The first grid may include N layers stacked in a first direction perpendicular to the second surface of the substrate, the second grid may include M layers stacked in the first direction, and the third grid may include L layers stacked in the first direction. The height of the first grid in the first direction may be less than the height of the second grid in the first direction, and the height of the first grid in the first direction may be less than the height of the third grid in the first direction. N, M, and L may be integers equal to or greater than 1, M may be greater than N, and L may be greater than N. The image sensor may be configured to receive light from the second surface of the substrate.

[0007] According to one or more embodiments, an image sensor includes: a substrate including a first surface, a second surface opposite to the first surface, a first region located at a central region of the substrate, an optical black region, and a second region located between the first region and the optical black region in a plan view; a plurality of color filters located on the second surface of the substrate; a first grid located on the first region between the plurality of color filters; a second grid located on the second region between the plurality of color filters; a first microlens located on the first region on a first photodiode and a second photodiode; and a second microlens located on the second region on a third photodiode and a fourth photodiode. The first grid may include N layers stacked in a first direction perpendicular to the second surface of the substrate, and the second grid may include M layers stacked in the first direction. The height of the first grid in the first direction may be less than the height of the second grid in the first direction. N and M may be integers equal to or greater than 1, and N may be different from M. The first grid may not be located at the center of the first microlens in a vertical view, and the second grid may not be located at the center of the second microlens in a vertical view. The image sensor may be configured to receive light from the second surface of the substrate. Attached Figure Description

[0008] Figure 1 This is a plan view illustrating the pixel region of an image sensor according to one or more embodiments.

[0009] Figure 2 This illustrates one or more embodiments. Figure 1 A planar graph of pixels in the image.

[0010] Figure 3A It is shown Figure 1 Pixels in the first region along Figure 2 The cross-sectional view taken from line B1-B1'.

[0011] Figure 3B It is shown Figure 1 Pixels in the first region along Figure 2 The cross-sectional view taken from line B2-B2'.

[0012] Figure 4A This is an enlarged cross-sectional view of the transmission gate structure.

[0013] Figure 4B This is an enlarged cross-sectional view of the pixel gate structure.

[0014] Figure 4C This is an enlarged cross-sectional view of the second insulating layer.

[0015] Figure 5A It is shown Figure 1 Pixels in the middle region along Figure 2 The cross-sectional view taken from line B1-B1'.

[0016] Figure 5B It is shown Figure 1 Pixels in the middle region along Figure 2 The cross-sectional view taken from line B2-B2'.

[0017] Figure 6A It is shown Figure 1 Pixels in the second region along Figure 2 The cross-sectional view taken from line B1-B1'.

[0018] Figure 6B It is shown Figure 1 Pixels in the second region along Figure 2 The cross-sectional view taken from line B2-B2'.

[0019] Figure 7A It is shown Figure 1 The pseudo-pixels on the third region along Figure 2 The cross-sectional view taken from line B1-B1'.

[0020] Figure 7B It is shown Figure 1 The pseudo-pixels on the third region along Figure 2 The cross-sectional view taken from line B2-B2'. Detailed Implementation

[0021] In the following description, exemplary embodiments are described in detail with reference to the accompanying drawings. The same components are indicated by the same reference numerals throughout the specification, and repeated descriptions thereof are omitted. It will be understood that when an element or layer is referred to as being "on" another element or layer, "connected to," or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly on" another element or layer, "directly connected to," or "directly coupled to" another element or layer, or is referred to as "in contact" with another element (or in any form using the word "in contact"), there are no intermediate elements or layers.

[0022] The embodiments described herein are exemplary embodiments, and therefore, this disclosure is not limited thereto, and may be implemented in various other forms. Each exemplary embodiment provided in the following description does not exclude association with one or more features of another example or another example embodiment also provided herein or not provided herein but consistent with this disclosure. It will also be understood that if a step or operation of a manufacturing apparatus or structure is described after another step or operation, then unless the other step or operation is described as being performed after the other step or operation, the step or operation may be performed after the other step or operation.

[0023] As used herein, when referring to orientation, layout, location, shape, size, quantity, or other measure, terms such as “identical,” “equal,” “planar,” or “coplanar” do not necessarily mean exactly the same orientation, layout, location, shape, size, quantity, or other measure, but are intended to cover substantially identical orientations, layouts, locations, shapes, sizes, quantities, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. Unless the context or other statement otherwise indicates otherwise, the term “substantially” may be used herein to emphasize this meaning. For example, items described as “substantially identical,” “substantially equal,” or “substantially flat” may be exactly the same, equal, or flat, or may be the same, equal, or flat within acceptable variations that may occur, for example, due to manufacturing processes.

[0024] Figure 1 This is a plan view illustrating the pixel region of an image sensor according to one or more embodiments.

[0025] The pixel region PA may include a pixel array region PAR and an optical black region OBR. The optical black region OBR may be disposed at the edge of the pixel region PA to surround the pixel array region PAR. In one or more embodiments, the pixel array region PAR may be an active pixel sensor region, and the optical black region OBR may be an optical black pixel region.

[0026] The pixel array region PAR may include a first region R1, an intermediate region IR, and a second region R2. The optical black region OBR may include a third region R3. The first region R1 may be located at the center of the pixel array region PAR. The intermediate region IR may surround the first region R1 in a planar view. The second region R2 may surround the intermediate region IR in a planar view. The optical black region OBR may surround the second region R2 in a planar view. For example, the second region R2 may be positioned between the first region R1 and the optical black region OBR in a planar view. The second region R2 may be positioned adjacent to the optical black region OBR in a planar view. In some embodiments, the intermediate region IR may be multiple. For example, the intermediate region IR may include two or more intermediate regions. Alternatively, in some embodiments, the intermediate regions may be omitted.

[0027] The pixel array region PAR may include a plurality of pixels PX arranged in a two-dimensional manner. The plurality of pixels PX can convert optical signals into electrical signals. The plurality of pixels PX can be arranged in a specific pattern to generate a high-quality image. In one or more embodiments, the plurality of pixels PX can be arranged in a Bayer pattern or a checkerboard mosaic pattern. For example, each of the plurality of pixels PX can be configured to receive red light, green light, or blue light.

[0028] In one or more embodiments, a plurality of pixels PX can be grouped into a plurality of pixel groups arranged in a two-dimensional manner. For example, a single pixel group within a plurality of pixel groups may include four pixel PX arranged in a 2×2 configuration. Alternatively, a single pixel group may include four pixel PX arranged in a 1×4 configuration. Alternatively, a single pixel group may include eight pixel PX arranged in a 2×4 configuration. However, embodiments are not limited thereto. The arrangement of the corresponding pixel PX of a pixel group according to one or more embodiments may be designed differently based on desired optical characteristics.

[0029] For example, pixels PX within the same pixel group of a plurality of pixels PX can be configured to receive light of the same color and can be positioned below the same color filter. The plurality of pixel groups can be arranged in a specific pattern to generate a high-quality image. In one or more embodiments, the plurality of pixel groups can be arranged in a Bayer pattern or a checkerboard mosaic pattern. For example, each of the plurality of pixel groups may include a plurality of pixels PX configured to receive red, green, or blue light.

[0030] The optical black region (OBR) may include a plurality of pseudo-pixel DPXs arranged in a two-dimensional manner. The plurality of pseudo-pixel DPXs may be configured not to receive incident light. For example, an image sensor may include light-blocking elements, such as light-blocking layers, configured to prevent incident light from reaching the plurality of pseudo-pixel DPXs. In one or more embodiments, the plurality of pseudo-pixel DPXs may be formed in the same process steps as the plurality of pixel PXs.

[0031] Each of the multiple pixels PX may include a photodiode (e.g., a photoelectric conversion element). A photodiode can absorb light and generate charge carriers (e.g., electrons or holes). As described above, a photodiode may include one or more photodiodes, phototransistors, photogates, or pinned photodiodes. The output voltage of the multiple pixels PX can be determined based on the generated charge carriers.

[0032] In one or more embodiments, although not shown, adjacent pixels PX among a plurality of pixels PX may be configured to share a reset transistor, a select transistor, and a source follower transistor.

[0033] Each of the plurality of pixels may include a photodiode and at least one gate terminal of a transmission transistor. The photodiode can generate and accumulate photocharge proportional to the amount of light incident from the outside. The photodiode may include a phototransistor, a photogate, a pinned photodiode, or a combination thereof.

[0034] The transmission transistor may include a gate terminal. The gate terminal may be located between the photodiode and the floating diffusion region FD (see [reference]). Figure 2 Between ), the gate terminal can be configured to transfer the generated photocharge within the photodiode to the floating diffusion region FD based on a transfer control voltage applied to the gate terminal.

[0035] The floating diffusion region (FD) receives, accumulates, and stores the photocharge generated in the photodiode. The source follower transistor can be controlled based on the amount of charge accumulated in the floating diffusion region (FD). The gate terminal of the source follower transistor can be electrically connected to the floating diffusion region (FD). The source terminal of the source follower transistor can be electrically connected to the drain terminal of the select transistor. The source follower transistor can be a source follower buffer amplifier that outputs a current proportional to the amount of charge accumulated in the floating diffusion region (FD). A reset transistor can periodically reset the charge accumulated in the floating diffusion region (FD).

[0036] The select transistor allows you to select a portion of multiple pixels PX on a row-by-row basis. The select transistor can deliver the current generated in the source follower transistor of each of the pixels PX in that portion to the output line.

[0037] Figure 2 This illustrates one or more embodiments. Figure 1 A planar graph of pixels in the image. Figure 3A It is shown Figure 1 The pixel edge in the first region Figure 2 A cross-sectional view taken from line B1-B1'. Figure 3B It is shown Figure 1 Pixels in the first region along Figure 2 The cross-sectional view taken from line B2-B2'. Figure 4A Yes, it is an enlarged cross-sectional view of the transmission gate structure. Figure 4B It is an enlarged cross-sectional view of the pixel gate structure, and Figure 4C This is an enlarged cross-sectional view of the second insulating layer. Figure 5A It is shown Figure 1 Pixels in the middle region along Figure 2 The cross-sectional view taken by line B1-B1', and Figure 5B It is shown Figure 1 Pixels in the middle region along Figure 2 The cross-sectional view taken from line B2-B2'. Figure 6A It is shown Figure 1 Pixels in the second region along Figure 2 The cross-sectional view taken by line B1-B1', and Figure 6B It is shown Figure 1 Pixels in the second region along Figure 2 The cross-sectional view taken from line B2-B2'. Figure 7A It is shown Figure 1 The pseudo-pixels on the third region along Figure 2 The cross-sectional view taken by line B1-B1', and Figure 7B It is shown Figure 1 The pseudo-pixels on the third region along Figure 2 The cross-sectional view taken from line B2-B2'.

[0038] Reference Figure 2 , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 4C and Figures 5A to 7BA substrate 100 may be provided. The substrate 100 may have a first surface 100a and a second surface 100b opposite to the first surface 100a. A first direction DR1 may be perpendicular to the first surface 100a and the second surface 100b of the substrate 100. The first surface 100a and the second surface 100b may extend along a second direction DR2 and a third direction DR3. The first surface 100a and the second surface 100b may be spaced apart from each other along the first direction DR1. The second direction DR2 may be parallel to the first surface 100a. The third direction DR3 may be parallel to the first surface 100a, and the third direction DR3 may intersect with the second direction DR2. The first direction DR1 may be perpendicular to the second direction DR2 and the third direction DR3.

[0039] Substrate 100 may be a semiconductor substrate. For example, substrate 100 may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). Substrate 100 may have a first conductivity type. For example, the first conductivity type may be P-type or N-type. For example, when the conductivity type of substrate 100 is P-type, substrate 100 may include group 3 elements (e.g., boron (B), aluminum (Al), gallium (Ga), indium (In), etc.) or group 2 elements as impurities. In the following, regions having a P-type conductivity type may include group 3 elements or group 2 elements as impurities. For example, when the conductivity type of substrate 100 is N-type, substrate 100 may include group 5 elements (e.g., phosphorus (P), arsenic (As), antimony (Sb), etc.), group 6 elements, or group 7 elements as impurities. In the following, regions having an N-type conductivity type may include group 5 elements, group 6 elements, or group 7 elements as impurities. A second conductivity type may be the opposite of the first conductivity type. For example, when the first conductivity type is P-type, the second conductivity type may be N-type. Alternatively, when the first conductivity type is N-type, the second conductivity type can be P-type.

[0040] The substrate 100 can be an epitaxial layer formed by an epitaxial growth process.

[0041] Substrate 100 may include a first region R1, an intermediate region IR, a second region R2, and a third region R3. The third region R3 may be as described above. Figure 1 The optically black region OBR is described.

[0042] In one or more embodiments, each of the first region R1, the intermediate region IR, the second region R2, and the third region R3 may include a first pixel group PXG1, a second pixel group PXG2, a third pixel group PXG3, and a fourth pixel group PXG4. Each of the first to fourth pixel groups PXG1, PXG2, PXG3, and PXG4 may be defined by a photodiode isolation pattern 102.

[0043] The first pixel group PXG1 and the second pixel group PXG2 can be arranged on the third-direction DR3. (Refer to...) Figure 2 The second pixel group PXG2 can be symmetrical with respect to the first pixel group PXG1, which is positioned between the first pixel group PXG1 and the second pixel group PXG2 along an axis extending in the second direction DR2. The first pixel group PXG1 and the third pixel group PXG3 can be arranged in the second direction DR2. (Refer to...) Figure 2 The third pixel group, PXG3, can have substantially the same shape as the first pixel group, PXG1. The third pixel group, PXG3, and the fourth pixel group, PXG4, can be arranged on the third-direction DR3. (See reference...) Figure 2 The fourth pixel group, PXG4, can have essentially the same shape as the second pixel group, PXG2.

[0044] Each of the first to fourth pixel groups PXG1, PXG2, PXG3, and PXG4 may include a first pixel PX1, a second pixel PX2, a third pixel PX3, and a fourth pixel PX4. Each of the first to fourth pixels PX1, PX2, PX3, and PX4 may be defined by a photodiode isolation pattern 102.

[0045] The first pixel PX1 and the second pixel PX2 can be arranged on the third-direction DR3. (Refer to...) Figure 2 The second pixel PX2 can be symmetrical with respect to the first pixel PX1, with respect to an axis extending in the second direction DR2 between the first pixel PX1 and the second pixel PX2. The first pixel PX1 and the third pixel PX3 can be arranged in the second direction DR2. (See reference...) Figure 2 The third pixel PX3 can have essentially the same shape as the first pixel PX1 rotated 90 degrees counterclockwise. The third pixel PX3 and the fourth pixel PX4 can be arranged on the third-direction DR3. (See reference...) Figure 2 The fourth pixel PX4 can have essentially the same shape as the second pixel PX2 rotated 90 degrees clockwise.

[0046] Each of the first to fourth pixels PX1, PX2, PX3, and PX4 in the third region R3 may include a photodiode region AR. The photodiode region AR of each of the first to fourth pixels PX1, PX2, PX3, and PX4 in the third region R3 may be a pseudo-photodiode region. Photoelectric conversion regions CR may be respectively disposed within the photodiode regions AR. In some embodiments, such as... Figure 2As shown, each of the photodiode regions AR may include a ground region GND. In this case, the substrate 100 may be electrically connected to the ground region GND. However, embodiments of this disclosure are not limited thereto. In some embodiments, the ground region may be disposed among multiple photodiode regions, and the multiple photodiode regions may share this region.

[0047] In one or more embodiments, each of the photoelectric conversion regions CR may include at least one photodiode. For example, the first region R1 may include a first photodiode (which may be referred to as a first first region photodiode in this specification) and a second photodiode (which may be referred to as a second first region photodiode in this specification), and the second region R2 may include a third photodiode (which may be referred to as a first second region photodiode in this specification) and a fourth photodiode (which may be referred to as a second second region photodiode in this specification).

[0048] In one or more embodiments, each of the first to fourth pixel groups PXG1, PXG2, PXG3, and PXG4 may include four photodiodes arranged in a 2×2 matrix in a planar view. In this specification, the four photodiodes of the first pixel group PXG1 in the first region R1 may be referred to as the first to fourth photodiodes, the four photodiodes of the second pixel group PXG2 in the first region R1 may be referred to as the second to fourth photodiodes, the four photodiodes of the third pixel group PXG3 in the first region R1 may be referred to as the third to fourth photodiodes, and the four photodiodes of the fourth pixel group PXG4 in the first region R1 may be referred to as the fourth to fourth photodiodes.

[0049] For example, each of the photoelectric conversion regions CR may include a PN photodiode. The PN photodiode may include a PN junction. Each of the photoelectric conversion regions CR may include a P-type region and an N-type region. The substrate 100 may have a first conductivity type. For example, the first conductivity type may be P-type. When the substrate 100 has a P-type conductivity type, the P-type region of the photoelectric conversion region CR may be the substrate 100, and the N-type region of the photoelectric conversion region CR may be a region on the substrate 100 implanted with impurities to give the substrate 100 an N-type conductivity type. For example, the N-type region of the photoelectric conversion region CR may be a region on the substrate 100 implanted with impurities including group 5, group 6, or group 7 elements. In one or more embodiments, each of the photoelectric conversion regions CR may include a plurality of PN diodes located at different depths. For example, each of the photoelectric conversion regions CR may include a plurality of PN junctions located at different depths.

[0050] When light is incident on the photoelectric conversion region CR, electron-hole pairs (EHP) can be generated within the photoelectric conversion region CR.

[0051] Floating diffusion regions FD can be disposed in the photodiode region AR. Each floating diffusion region FD can be disposed in a region adjacent to the first surface 100a of the substrate 100. Each floating diffusion region FD can have a second conductivity type opposite to the first conductivity type. Each floating diffusion region FD can include an impurity that causes the floating diffusion region FD to have the second conductivity type. For example, an impurity that causes the floating diffusion region FD to have the second conductivity type can be implanted into the floating diffusion region FD. The floating diffusion region FD can be spaced apart from the photoelectric conversion region CR.

[0052] The transfer gate structure TG can be disposed in a region adjacent to the first surface 100a. Each of the transfer gate structures TG can be adjacent to the corresponding floating diffusion region FD and the corresponding photoelectric conversion region CR. The transfer gate structure TG can be related to the above-mentioned reference... Figure 1 The described transmission transistor corresponds to the gate terminal.

[0053] A portion of each of the transfer gate structures TG can be disposed on the first surface 100a of the substrate 100, and another portion of each of the transfer gate structures TG can be inserted into the substrate 100. Each of the transfer gate structures TG, including the portion on the first surface 100a of the substrate 100 and the portion inside the substrate 100, can be a vertical transfer gate (VTG). (See reference...) Figure 4A Each of the transfer gate structures TG may include a transfer gate electrode TGE, a transfer gate insulating layer TGI, and a transfer gate spacer TGP.

[0054] Each of the transport gate electrodes TGEs may be adjacent to a corresponding floating diffusion region FD and a corresponding photoelectric conversion region CR. A portion of each of the transport gate electrodes TGEs may be disposed on the first surface 100a. Another portion of each of the transport gate electrodes TGEs may be inserted into (or extended into) the substrate 100.

[0055] Each of the transfer gate insulating layers (TGIs) can be disposed between the corresponding transfer gate electrode (TGE) and the corresponding photodiode region (AR). Each of the transfer gate insulating layers (TGIs) can be configured to electrically isolate the corresponding transfer gate electrode (TGE) and the corresponding photodiode region (AR). Each of the transfer gate insulating layers (TGIs) can extend along the surface of the corresponding photodiode region (AR).

[0056] The transfer gate spacer (TGP) can be disposed on the opposite side surface of the corresponding transfer gate electrode (TGE). Each of the transfer gate spacers (TGP) may include an insulating material.

[0057] Each of the first to fourth pixels PX1, PX2, PX3, and PX4 may include a pixel gate structure PG, a first source / drain region SD1, a second source / drain region SD2, and a shallow trench isolation pattern STI. The pixel gate structure PG, the first source / drain region SD1, and the second source / drain region SD2 can form a transistor for driving an image sensor. For example, the pixel gate structure PG, the first source / drain region SD1, and the second source / drain region SD2 can constitute one of a reset transistor, a source follower transistor, and a select transistor. (See reference...) Figure 4B Each of the pixel gate structures PG may include a pixel gate electrode PGE, a pixel gate insulating layer PGI, and a pixel gate spacer PGP.

[0058] Photodiode isolation trenches can be provided. These trenches can extend from a first surface 100a of the substrate 100 through at least a portion of the substrate 100. In one or more embodiments, a first region R1 may include a photodiode isolation trench extending through the substrate 100.

[0059] The photodiode isolation pattern 102 can fill the photodiode isolation trench. In a plan view, the photodiode isolation pattern 102 can surround each of the photoelectric conversion regions CR. The photodiode isolation pattern 102 can surround the first to fourth pixels PX1, PX2, PX3, and PX4. The photodiode isolation pattern 102 can extend in the first direction DR1.

[0060] In one or more embodiments, the photodiode isolation pattern 102 may penetrate the substrate 100. In one or more embodiments, the photodiode isolation pattern 102 may penetrate at least a portion of the substrate 100. As shown, a photodiode isolation trench may penetrate the substrate 100, and therefore, the photodiode isolation pattern 102 filling the photodiode isolation trench may penetrate the substrate 100. Alternatively, the photodiode isolation trench may penetrate only a portion of the substrate 100, and therefore, the photodiode isolation pattern 102 filling the photodiode isolation trench may penetrate only this portion of the substrate 100. The image sensor may also include a doped isolation region formed in another portion of the substrate 100 and vertically overlapping the photodiode isolation pattern 102.

[0061] The photodiode isolation pattern 102 can significantly reduce crosstalk caused by charge carrier exchange between adjacent pixels from the first pixel to the fourth pixel PX1, PX2, PX3 and PX4, which degrades the signal-to-noise ratio (SNR).

[0062] The photodiode isolation pattern 102 may include at least one of a conductive material and an insulating material. For example, the conductive material may include at least one of doped polysilicon, a metal, a metal silicide, a metal nitride, and a metal-containing material. For example, the insulating material may include at least one of a silicon-based insulating material and a high-k dielectric. For example, the silicon-based insulating material may include at least one of silicon nitride, silicon oxide, and silicon oxynitride. For example, the high-k dielectric material may include a metal oxide comprising at least one metal selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y), or lanthanum (La).

[0063] In one or more embodiments, a photodiode isolation pattern 102 may be disposed in a photodiode isolation trench passing through a substrate 100, and a plurality of insulating layers including at least one anti-reflective layer may be disposed between the sidewall of the photodiode isolation trench and the photodiode isolation pattern 102 in a vertical view.

[0064] In one or more embodiments, the photodiode isolation trench may further include a shallow isolation pattern located between the photodiode isolation pattern 102 and the first surface 100a. The shallow isolation pattern can provide electrical isolation between adjacent elements. In one or more embodiments, the shallow isolation pattern may include an insulating material. For example, the shallow isolation pattern may include at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0065] Vertical conductive line VCL and horizontal conductive line HCL can be disposed on the first surface 100a. The vertical conductive line VCL can extend in a first direction DR1. The horizontal conductive line HCL can extend, for example, in a second direction DR2 or a sixth direction DR6. The vertical conductive line VCL and the horizontal conductive line HCL can comprise at least one of doped polycrystalline silicon and a metal (e.g., at least one of copper (Cu), aluminum (Al), molybdenum (Mo), platinum (Pt), titanium (Ti), tantalum (Ta), and tungsten (W).

[0066] A first insulating layer 110 may be disposed on a first surface 100a of the substrate 100. The first insulating layer 110 may protect the vertical conductive line VCL, the horizontal conductive line HCL, and the components disposed on the first surface 100a. The first insulating layer 110 may include an insulating material. For example, the first insulating layer 110 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0067] The second insulating layer 120 can be disposed on the second surface 100b of the substrate 100. For example... Figure 4C As shown, the second insulating layer 120 may include a first sub-insulating layer 121, a second sub-insulating layer 122, a third sub-insulating layer 123, and a fourth sub-insulating layer 124 sequentially stacked on the second surface 100b. For example, the first sub-insulating layer 121 may include aluminum oxide. For example, the second sub-insulating layer 122 may include hafnium oxide or titanium oxide. For example, the third sub-insulating layer 123 may include silicon oxide. For example, the fourth sub-insulating layer 124 may include hafnium oxide. In one or more embodiments, the second insulating layer 120 may be configured to suppress the reflection of incident light and increase the amount of light incident on the photoelectric conversion region CR based on the thickness and refractive index of the first to fourth sub-insulating layers 121, 122, 123, and 124.

[0068] A barrier metal layer BM may be disposed on the second insulating layer 120. The barrier metal layer BM can improve the adhesion between the fourth sub-insulating layer 124 and the grid 130. For example, the barrier metal layer BM may include a composite layer of titanium and titanium nitride layers, and at least one of titanium nitride layers.

[0069] Grid 130 can be disposed on the pixel array region PAR. For example, grid 130 can be disposed on the barrier metal layer BM of the pixel array region PAR.

[0070] In one or more embodiments, grid 130 may be disposed on the pixel array region PAR and may not be disposed on the optical black region OBR. Alternatively, grid 130 may be disposed on both the pixel array region PAR and the optical black region OBR.

[0071] In this specification, the grid 130 on the first region R1 of the pixel array region PAR can be referred to as the first grid, the grid 130 on the middle region IR of the pixel array region PAR can be referred to as the middle region grid, and the grid 130 on the second region R2 of the pixel array region PAR can be referred to as the second grid. When the grid 130 is set on the optical black region OBR, the grid 130 on the optical black region OBR can be referred to as the third grid.

[0072] like Figure 3A , Figure 3B and Figures 5A to 7B As shown, grid 130 may have a layered structure on each of the first region R1, the intermediate region IR, and the second region R2. For example, grid 130 may have a single-layer structure or a multi-layer structure on each of the first region R1, the intermediate region IR, and the second region R2. The third region R3 may include a layer containing the same material as the material forming the first grid, the intermediate region grid, and the second grid.

[0073] Alternatively, grid 130 may have a layered structure on each of the first region R1, the intermediate region IR, the second region R2, and the third region R3. Even on the third region R3, grid 130 may have a single-layer structure or a multi-layer structure.

[0074] The first grid may comprise N layers stacked in the first direction DR1. The intermediate region grid may comprise K layers stacked in the first direction DR1. The second grid may comprise M layers stacked in the first direction DR1. The third region R3 may comprise a layer composed of the same material as the first grid, the intermediate region grid, and the second grid. Each of N, K, and M may be an integer equal to or greater than 1. N, K, and M may be different integers. For example, M may be greater than N. For example, M may be greater than K. For example, K may be greater than N.

[0075] Alternatively, when grid 130 is disposed on the optical black region OBR, the third grid may include L layers stacked on the first direction DR1. Each of N, K, M, and L may be an integer greater than or equal to 1. M may be an integer greater than N, and L may be an integer greater than N. In one or more embodiments, M and L may be integers greater than or equal to 2. In one or more embodiments, M may be an integer equal to L.

[0076] In one or more embodiments, the grid 130 may have a single-layer structure in the first region R1, may include two layers in the intermediate region IR, and may include three layers in the second region R2. Furthermore, the grid 130 may not have a layer structure in the third region R3.

[0077] Alternatively, when the grid 130 is disposed on the optical black region OBR, the grid 130 may also have a layered structure in the third region R3. The grid 130 may have three layers in the third region R3, but the embodiments are not limited thereto.

[0078] Alternatively, grid 130 may have four or more layers in the first region R1, the intermediate region IR, the second region R2, and the third region R3.

[0079] However, the embodiments are not limited thereto. The pixel array region PAR may include multiple regions, and the grid 130 may have a single-layer structure or a multi-layer structure in each of the multiple regions. In one or more embodiments, the number of layers of the grid 130 may increase in a direction from the central region among the multiple regions to the outermost region. Alternatively, the grid 130 may have an irregular number of layers in the multiple regions.

[0080] In the following text, for ease of description, a grid 130 may be described as having a single-layer structure in the first region R1, two layers in the intermediate region IR, and three layers in the second region R2.

[0081] In this specification, the grid 130 on the first region R1 of the pixel array region PAR can be referred to as the first grid, the grid 130 on the middle region IR of the pixel array region PAR can be referred to as the middle region grid, and the grid 130 on the second region R2 of the pixel array region PAR can be referred to as the second grid. When the grid 130 is set on the optical black region OBR, the grid 130 on the optical black region OBR can be referred to as the third grid.

[0082] The height of the first grid in the first direction DR1 may be different from the height of the second grid in the first direction DR1. In one or more embodiments, the heights of the first grid, the intermediate region grid, and the second grid in the first direction DR1 may differ from each other. For example, the height of the first grid in the first direction DR1 may be less than the height of the second grid in the first direction DR1. In one or more embodiments, when the grid 130 is disposed on the optical black region OBR, the heights of the first grid, the intermediate region grid, the second grid, and the third grid in the first direction DR1 may differ from each other. For example, the height of the first grid in the first direction DR1 may be less than the height of the second grid in the first direction DR1, and the height of the first grid in the first direction DR1 may be less than the height of the third grid in the first direction DR1.

[0083] like Figure 3A and Figure 3B As shown, the N layers of the first grid may include a first sub-grid pattern 132. In one or more embodiments, N may be an integer equal to 1. The height of the first grid may be the height of the first sub-grid pattern 132 in the first direction DR1. The first sub-grid pattern 132 may include a material with a low refractive index. For example, the refractive index of the first sub-grid pattern 132 may be about 1.5 or less. For example, the first sub-grid pattern 132 may include at least one of tetraethoxysilane (TEOS), phenyltriethoxysilane (PTEOS), and porous low-k dielectric.

[0084] like Figure 5A and Figure 5BAs shown, the K layers of the intermediate region grid may include a first sub-grid pattern 132 and a second sub-grid pattern 134. The second sub-grid pattern 134 may be disposed between the first sub-grid pattern 132 and the second surface 100b of the substrate 100. For example, the second sub-grid pattern 134 may be disposed between the first sub-grid pattern 132 and the photodiode of the intermediate region IR. The height of the first sub-grid pattern 132 in the first direction DR1 may be greater than the height of the second sub-grid pattern 134 in the first direction DR1. In one or more embodiments, the height of the first sub-grid pattern 132 in the first direction DR1 may be approximately three times or more the height of the second sub-grid pattern 134 in the first direction DR1. Alternatively, the height of the first sub-grid pattern 132 in the first direction DR1 may be approximately twice or more the height of the second sub-grid pattern 134 in the first direction DR1. In one or more embodiments, K may be an integer equal to 2. The height of the intermediate region grid can be the sum of the height of the first sub-grid pattern 132 in the first direction DR1 and the height of the second sub-grid pattern 134 in the first direction DR1. Therefore, the height of the intermediate region grid can be greater than the height of the first grid. The second sub-grid pattern 134 can include a material with a low refractive index. For example, the refractive index of the second sub-grid pattern 134 can be about 1.5 or less. In one or more embodiments, the second sub-grid pattern 134 can include a material different from the material of the first sub-grid pattern 132. For example, the second sub-grid pattern 134 can include a metal (e.g., at least one of tungsten (W) and titanium nitride (TiN)).

[0085] like Figure 6A and Figure 6BAs shown, the M layers of the second grid may include a first sub-grid pattern 132, a second sub-grid pattern 134, and a third sub-grid pattern 136. The second sub-grid pattern 134 may be disposed between the first sub-grid pattern 132 and the second surface 100b of the substrate 100. For example, the second sub-grid pattern 134 may be disposed between the first sub-grid pattern 132 and the photodiode of the second region R2. The third sub-grid pattern 136 may be disposed between the first sub-grid pattern 132 and the second sub-grid pattern 134. The height of the first sub-grid pattern 132 in the first direction DR1 may be greater than the height of the second sub-grid pattern 134 in the first direction DR1. The height of the first sub-grid pattern 132 in the first direction DR1 may be greater than the height of the third sub-grid pattern 136. In one or more embodiments, the height of the first sub-grid pattern 132 in the first direction DR1 may be approximately three times or more the height of the second sub-grid pattern 134 in the first direction DR1. Alternatively, the height of the first sub-grid pattern 132 in the first direction DR1 can be approximately twice or more than the height of the second sub-grid pattern 134 in the first direction DR1. In one or more embodiments, M can be an integer 3. The height of the second grid can be the sum of the heights of the first sub-grid pattern 132, the second sub-grid pattern 134, and the third sub-grid pattern 136 in the first direction DR1. Therefore, the height of the second grid can be greater than the height of the first grid and the height of the intermediate region grid. The third sub-grid pattern 136 can include a material with a low refractive index. For example, the refractive index of the third sub-grid pattern 136 can be approximately 1.5 or less. In one or more embodiments, the third sub-grid pattern 136 can include a material different from the material of the first sub-grid pattern 132. The third sub-grid pattern 136 can include a material substantially the same as the second sub-grid pattern 134. For example, the third sub-grid pattern 136 can include a metal (e.g., at least one of tungsten (W) and titanium nitride (TiN)).

[0086] However, the embodiments are not limited thereto. The first to third subgrid patterns 132, 134 and 136 may comprise substantially the same material. For example, the first to third subgrid patterns 132, 134 and 136 may comprise at least one of tetraethoxysilane (TEOS), phenyltriethoxysilane (PTEOS) and porous low-k dielectric.

[0087] like Figure 7A and Figure 7BAs shown, a first peripheral layer ML1 and a second peripheral layer ML2 may be disposed in a third region R3. The first peripheral layer ML1 and the second peripheral layer ML2 may be stacked along a first direction DR1. The first peripheral layer ML1 may comprise the same material as the second sub-grid pattern 134, and the height of the first peripheral layer ML1 in the first direction DR1 may be substantially the same as the height of the second sub-grid pattern 134 in the first direction DR1. The second peripheral layer ML2 may comprise the same material as the third sub-grid pattern 136, and the height of the second peripheral layer ML2 in the first direction DR1 may be substantially the same as the height of the third sub-grid pattern 136 in the first direction DR1. For example, the refractive index of the first peripheral layer ML1 and the second peripheral layer ML2 may be about 1.5 or less. In one or more embodiments, each of the first peripheral layer ML1 and the second peripheral layer ML2 may comprise a metal (e.g., at least one of tungsten (W) and titanium nitride (TiN). Alternatively, each of the first peripheral layer ML1 and the second peripheral layer ML2 may comprise at least one of tetraethoxysilane (TEOS), phenyltriethoxysilane (PTEOS), and a porous low-k dielectric.

[0088] The upper UL layer can be disposed on the second outer layer ML2 of the third region R3. In one or more embodiments, the upper UL layer can have a multi-layer structure. For example, the upper UL layer may include a light-blocking layer and a resin layer.

[0089] Contrary to the illustrated embodiment, in one or more embodiments, when the grid 130 is disposed on the optical black region OBR, the L layers of the third grid may include a first sub-grid pattern 132, a second sub-grid pattern 134, and a third sub-grid pattern 136. The first to third sub-grid patterns 132, 134, and 136 may be consistent with those referenced above. Figure 6A and Figure 6B The first to third sub-grid patterns 132, 134, and 136 described are identical. In one or more embodiments, L can be an integer equal to 3. The height of the third grid can be the sum of the heights of the first sub-grid pattern 132 in the first direction DR1, the second sub-grid pattern 134 in the first direction DR1, and the third sub-grid pattern 136 in the first direction DR1.

[0090] Grid 130 may have a grid shape that defines the color filter region CFR. For example, grid 130 may extend along the edges of each of the first to fourth pixel groups PX1, PX2, PX3, and PX4. Therefore, grid 130 may be positioned along the edges of the first to fourth pixel groups PXG1, PXG2, PXG3, and PXG4. In a planar view, grid 130 may be positioned in a central region surrounded by the first to fourth pixel groups PXG1, PXG2, PXG3, and PXG4.

[0091] In one or more embodiments, each of the first to fourth pixel groups PXG1, PXG2, PXG3, and PXG4 may include four photodiodes arranged in a 2×2 matrix in a planar view. In this specification, the four photodiodes of the first pixel group PXG1 in the first region R1 may be referred to as the first-fourth photodiodes, the four photodiodes of the second pixel group PXG2 in the first region R1 may be referred to as the second-fourth photodiodes, the four photodiodes of the third pixel group PXG3 in the first region R1 may be referred to as the third-fourth photodiodes, and the four photodiodes of the fourth pixel group PXG4 in the first region R1 may be referred to as the fourth-fourth photodiodes. In a planar view, the first grid may not be located in the central portion surrounded by the first-fourth photodiodes. In one or more embodiments, in a planar view, the first grid may not be located in the central portion surrounded by the first-fourth photodiodes, may not be located in the central portion surrounded by the second-fourth photodiodes, may not be located in the central portion surrounded by the third-fourth photodiodes, and may not be located in the central portion surrounded by the fourth-fourth photodiodes.

[0092] Multiple color filters CF can be disposed on the second surface 100b of the substrate 100. For example, multiple color filters CF can be disposed on a color filter region CFR. Therefore, a first grid can be disposed on a first region R1 and can be disposed between the color filters CF located in the first region R1 among the multiple color filters CF. An intermediate region grid can be disposed on an intermediate region IR and can be disposed between the color filters CF located in the intermediate region IR among the multiple color filters CF. A second grid can be disposed on a second region R2 and can be disposed between the color filters CF located in the second region R2 among the multiple color filters CF.

[0093] In one or more embodiments, when each of the first to fourth pixel groups PXG1, PXG2, PXG3, and PXG4 includes four photodiodes arranged in a 2×2 matrix in a planar view, the first pixel group PXG1 of the first region R1 may include the first to fourth photodiodes arranged in a 2×2 matrix in the planar view and a first first region color filter on the first to fourth photodiodes. The second pixel group PXG2 of the first region R1 may include the second to fourth photodiodes arranged in a 2×2 matrix in the planar view and a second first region color filter on the second to fourth photodiodes. The third pixel group PXG3 of the first region R1 may include the third to fourth photodiodes arranged in a 2×2 matrix in the planar view and a third first region color filter on the third to fourth photodiodes. The fourth pixel group PXG4 of the first region R1 may include the fourth to fourth photodiodes arranged in a 2×2 matrix in the planar view and a fourth first region color filter on the fourth to fourth photodiodes.

[0094] Incident light passing through the color filter CF can be incident on the photodiode region AR. The photodiode region AR corresponds to the color filter region CFR, and the color filter region CFR corresponds to the color filter CF.

[0095] The central axis of each of the photodiode regions AR in the first region R1 can be substantially aligned with the central axis of the corresponding color filter region CFR. The central axis of each of the photodiode regions AR can pass through the center of the photodiode region AR and can extend in the first direction DR1. The central axis of each of the color filter regions CFR can pass through the center of the color filter region CFR and can extend in the first direction DR1.

[0096] The central axis of each photodiode region AR in the intermediate region IR may not be aligned with the central axis of the corresponding color filter region CFR. For example, the central axis of each photodiode region AR in the intermediate region IR may be offset from the central axis of the corresponding color filter region CFR. The distance between the central axis of each photodiode region AR in the intermediate region IR and the central axis of the corresponding color filter region CFR may be a first separation distance.

[0097] In one or more embodiments, reference is made to Figure 1Each of the photodiode regions AR on the intermediate region IR arranged relative to the first region R1 on the third direction DR3 can be spaced apart from the central axis of the corresponding color filter region CFR on the third direction DR3. Each of the photodiode regions AR on the intermediate region IR arranged relative to the first region R1 on the second direction DR2 can be spaced apart from the central axis of the corresponding color filter region CFR on the second direction DR2. Each of the photodiode regions AR on the intermediate region IR arranged relative to the first region R1 on the fourth direction DR4 can be spaced apart from the central axis of the corresponding color filter region CFR on the fourth direction DR4. Each of the photodiode regions AR on the intermediate region IR arranged relative to the first region R1 on the fifth direction DR5 can be spaced apart from the central axis of the corresponding color filter region CFR on the fifth direction DR5.

[0098] The central axis of each photodiode region AR in the second region R2 may not be aligned with the central axis of the corresponding color filter region CFR. For example, the central axis of each photodiode region AR in the second region R2 may be offset from the central axis of the corresponding color filter region CFR. The distance between the central axis of each photodiode region AR in the second region R2 and the central axis of the corresponding color filter region CFR may be a second separation distance. The second separation distance may be greater than the first separation distance.

[0099] In one or more embodiments, reference is made to Figure 1 Each of the photodiode regions AR on the second region R2 arranged relative to the intermediate region IR on the third direction DR3 can be spaced apart from the central axis of the corresponding color filter region CFR on the third direction DR3. Each of the photodiode regions AR on the second region R2 arranged relative to the intermediate region IR on the second direction DR2 can be spaced apart from the central axis of the corresponding color filter region CFR on the second direction DR2. Each of the photodiode regions AR on the second region R2 arranged relative to the intermediate region IR on the fourth direction DR4 can be spaced apart from the central axis of the corresponding color filter region CFR on the fourth direction DR4. Each of the photodiode regions AR on the second region R2 arranged relative to the intermediate region IR on the fifth direction DR5 can be spaced apart from the central axis of the corresponding color filter region CFR on the fifth direction DR5.

[0100] Color filters CF can be disposed on the barrier metal layer BM and can be disposed on each of the color filter regions CFR. Each of the color filters CF can be surrounded by a grid 130.

[0101] In one or more embodiments, the height of the color filter CF in the first region R1 along the first direction DR1 may be greater than the height of the first grid along the first direction DR1. Therefore, the color filter CF in the first region R1 can cover the upper surface of the first grid. The height of the color filter CF in the intermediate region IR along the first direction DR1 may be less than the height of the intermediate region grid along the first direction DR1. Therefore, the intermediate region grid in the intermediate region IR can protrude upward from the upper surface of the color filter CF. The height of the color filter CF in the second region R2 along the first direction DR1 may be less than the height of the second grid along the first direction DR1. Therefore, the second grid in the second region R2 can protrude upward from the upper surface of the color filter CF.

[0102] In one or more embodiments, the color filter CF can be respectively disposed in the first to fourth pixels PX1, PX2, PX3, and PX4. For example, the color filter CF on the first pixel PX1 can be a red color filter, the color filter CF on the second pixel PX2 can be a green color filter, the color filter CF on the third pixel PX3 can be a green color filter, and the color filter CF on the fourth pixel PX4 can be a blue color filter. Alternatively, the color filter CF on the first pixel PX1 can be a cyan color filter, the color filter CF on the second pixel PX2 can be a yellow color filter, the color filter CF on the third pixel PX3 can be a green color filter, and the color filter CF on the fourth pixel PX4 can be a magenta color filter.

[0103] The lens layer LL can be disposed on the second surface 100b of the substrate 100. Therefore, the second surface 100b of the substrate 100 can be configured to receive light. The lens layer LL may include a lens LS.

[0104] In one or more embodiments, each of the lenses LS may be a microlens. The first region R1, the intermediate region IR, and the second region R2 may include microlenses. The microlens on the first region R1 may be referred to as a first microlens, the microlens on the intermediate region IR may be referred to as an intermediate region microlens, and the microlens on the second region R2 may be referred to as a second microlens.

[0105] In a vertical view, the first grid may not be located at the center of each of the first microlenses. Similarly, in a vertical view, the second grid may not be located at the center of the second microlens. For example, when one of the first microlenses covers the first to fourth pixels PX1, PX2, PX3, and PX4 of the first pixel group PXG1, the center of this first microlens may vertically overlap with the centers of the first to fourth pixels PX1, PX2, PX3, and PX4. The first grid may not be located at the center of this single first microlens.

[0106] In this specification, the second microlens in the second region R2 can be referred to as the first and second region microlens. Furthermore, the color filter disposed between the first and second region photodiode and the first and second region microlens can be referred to as the first and second region color filter. The distance from the second surface 100b of the substrate 100 to the upper surface of the second grid in the first direction DR1 can be greater than the distance from the second surface 100b of the substrate 100 to the upper surface of the first and second region color filter.

[0107] The second region R2 may further include a second photodiode. Microlenses in the first and second regions may be disposed on the first and second region photodiodes. However, the embodiments are not limited thereto. Each of the microlenses may be disposed on a single photodiode or multiple photodiodes based on the efficiency and purpose of the image sensor.

[0108] Each of the lenses LS can be configured to focus incident light onto the corresponding photoelectric conversion region CR. The lenses LS can comprise resin-based materials. For example, the lenses LS can comprise at least one of styrene-based resins, acrylic resins, styrene-acrylic acid copolymer resins, and siloxane resins.

[0109] The central axis of each of the color filter regions CFR in the first region R1 can be substantially aligned with the central axis of the corresponding lens LS. The central axis of each of the lenses LS can pass through the center of the lens LS and can extend in the first direction DR1.

[0110] The central axis of each color filter region (CFR) in the intermediate region IR may not be aligned with the central axis of the corresponding lens LS. That is, the central axis of each color filter region (CFR) in the intermediate region IR may be offset from the central axis of the corresponding lens LS. The central axis of each color filter region (CFR) in the intermediate region IR and the central axis of the corresponding lens LS may have a third separation distance.

[0111] In one or more embodiments, reference is made to Figure 1Each of the color filter regions CFRs on the intermediate region IR arranged relative to the first region R1 on the third direction DR3 can be spaced apart from the central axis of the corresponding lens LS along the third direction DR3. Each of the color filter regions CFRs on the intermediate region IR arranged relative to the first region R1 on the second direction DR2 can be spaced apart from the central axis of the corresponding lens LS on the second direction DR2. Each of the color filter regions CFRs on the intermediate region IR arranged relative to the first region R1 on the fourth direction DR4 can be spaced apart from the central axis of the corresponding lens LS on the fourth direction DR4. Each of the color filter regions CFRs on the intermediate region IR arranged relative to the first region R1 on the fifth direction DR5 can be spaced apart from the central axis of the corresponding lens LS on the fifth direction DR5.

[0112] The central axis of each color filter region CFR in the second region R2 may not be aligned with the central axis of the corresponding lens LS. For example, the central axis of each color filter region CFR in the second region R2 may be offset from the central axis of the corresponding lens LS. The distance between the central axis of each color filter region CFR in the second region R2 and the central axis of the corresponding lens LS can be a fourth separation distance. The fourth separation distance can be greater than the third separation distance.

[0113] In one or more embodiments, reference is made to Figure 1 Each of the color filter regions CFRs on the second region R2, arranged relative to the intermediate region IR on the third direction DR3, can be spaced apart from the central axis of the corresponding lens LS on the third direction DR3. Each of the color filter regions CFRs on the second region R2, arranged relative to the intermediate region IR on the second direction DR2, can be spaced apart from the central axis of the corresponding lens LS on the second direction DR2. Each of the color filter regions CFRs on the second region R2, arranged relative to the intermediate region IR on the fourth direction DR4, can be spaced apart from the central axis of the corresponding lens LS on the fourth direction DR4. Each of the color filter regions CFRs on the second region R2, arranged relative to the intermediate region IR on the fifth direction DR5, can be spaced apart from the central axis of the corresponding lens LS on the fifth direction DR5.

[0114] Incident light can be incident on the pixel array region PAR with a larger principal ray angle (CRA) in the direction toward the edge of the pixel array region PAR, and incident light can be incident on the pixel array region PAR with a relatively smaller principal ray angle in the direction toward the center of the pixel array region PAR. The incident light can be incident on the lens LS, and can subsequently reach the photoelectric conversion region CR of the photodiode region AR corresponding to each of the photodiode regions in the lens LS.

[0115] Incident light at the edge of the pixel array region PAR can enter at an angle due to the relatively large principal ray angle, and therefore can be incident toward the grid 130. For example, optical crosstalk may occur due to the large principal ray angle of the incident light.

[0116] The image sensor according to the above embodiments may include grids 130 with different heights based on the probability of optical crosstalk occurring. For example, a first region R1 may have the lowest probability of optical crosstalk occurring, and the first grid of the first region R1 may have the lowest height. A second region R2 (e.g., the region closest to the optical black region OBR) may have the highest probability of optical crosstalk occurring, and the second grid of the second region R2 may have the highest height. As a result, the optical characteristics of the image sensor can be improved.

[0117] In a method of manufacturing an image sensor including a grid 130, a first initial grid layer may be formed on a barrier metal layer BM. The first initial grid layer may be formed on the pixel array region PAR and the optical black region OBR. In one or more embodiments, the first initial grid layer may be formed by a deposition process.

[0118] The first initial grid layer can be patterned to form a second sub-grid pattern 134. The second sub-grid pattern 134 can be formed on the intermediate region IR and the second region R2. The first initial grid layer on the first region R1 can be removed. For example, the first initial grid layer on the first region R1 can be completely removed. The first initial grid layer on the third region R3 can be retained without being patterned. The remaining first initial grid layer in the third region R3 can be a first peripheral layer ML1. In one or more embodiments, when the grid 130 is disposed on the optical black region OBR, the first initial grid layer of the third region R3 can be patterned to form the second sub-grid pattern 134.

[0119] Then, a second initial grid layer can be formed to cover the second sub-grid pattern 134. The second initial grid layer can be formed on the pixel array region PAR and the optical black region OBR. The second initial grid layer can be patterned to form a third sub-grid pattern 136 on the second sub-grid pattern 134 on the second region R2. The initial second grid layer on the first region R1 and the intermediate region IR can be removed. For example, the initial second grid layer on the first region R1 and the intermediate region IR can be completely removed. The initial second grid layer of the third region R3 can be retained without patterning. The remaining initial second grid layer of the third region R3 can be a second peripheral layer ML2. In one or more embodiments, when the grid 130 is disposed on the optical black region OBR, the second initial grid layer of the third region R3 can be patterned to form a third sub-grid pattern 136 on the third region R3. The third sub-grid pattern 136 of the third region R3 can be formed on the second sub-grid pattern 134.

[0120] Then, a substrate grid layer can be formed on the pixel array region PAR and the optical black region OBR. The substrate grid layer can be patterned to form a first sub-grid pattern 132. The first sub-grid pattern 132 can be formed on the barrier metal layer BM on the first region R1. For example, a first grid of the first region R1 can be formed on the barrier metal layer BM. The first sub-grid pattern 132 can be formed on the second sub-grid pattern 134 on the intermediate region IR. The first sub-grid pattern 132 can be formed on the third sub-grid pattern 136 on the second region R2.

[0121] As described above, according to the embodiments, an image sensor with improved optical properties can be provided. However, the embodiments are not limited thereto.

[0122] Although various embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and changes can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. An image sensor, comprising: The substrate includes a first surface, a second surface opposite to the first surface, a first region located at the center region of the substrate, an optical black region, and a second region located between the first region and the optical black region in a plan view; Multiple color filters are located on the second surface of the substrate; A first grid is located in the first region between the plurality of color filters; as well as The second grid is located in the second region between the plurality of color filters. The first grid comprises N layers stacked in a first direction perpendicular to the second surface of the substrate. The second grid comprises M layers stacked in the first direction. Wherein, the height of the first grid in the first direction is different from the height of the second grid in the first direction. Where N and M are integers equal to or greater than 1. Where N and M are different, and The image sensor is configured to receive light from the second surface of the substrate.

2. The image sensor of claim 1, wherein, M is greater than N.

3. The image sensor of claim 2, wherein, The second region includes: First and second region photodiodes; First and second region microlenses; and The first and second region color filters are located between the first and second region photodiodes and the first and second region microlenses. Wherein, the distance from the second surface of the substrate to the top surface of the second grid in the first direction is greater than the distance from the second surface of the substrate to the top surface of the first second region color filter in the first direction.

4. The image sensor of claim 3, wherein, The second region also includes: Second region photodiode, The first and second region microlenses are disposed on the first and second region photodiodes and the second and second region photodiodes.

5. The image sensor of claim 4, wherein, The M layers include: The first subgrid pattern; and The second sub-grid pattern is located between the first sub-grid pattern and the first and second region photodiodes. Wherein, the height of the first sub-grid pattern in the first direction is greater than the height of the second sub-grid pattern in the first direction.

6. The image sensor according to claim 4, wherein, The first region includes: The first pixel group includes first to four photodiodes arranged in a 2×2 matrix in a planar view, and a first first region color filter located on the first to four photodiodes; The second pixel group includes a second to fourth photodiodes arranged in the 2×2 matrix in the plan view, and a second first region color filter located on the second to fourth photodiodes; The third pixel group includes a third and fourth photodiode arranged in a 2×2 matrix in the planar view, and a third region color filter located on the third and fourth photodiodes; and The fourth pixel group includes a fourth to fourth photodiodes arranged in a 2×2 matrix in the plan view, and a fourth first region color filter located on the fourth to fourth photodiodes.

7. The image sensor according to claim 6, wherein, The first grid is located in the central region of the plan view, which is surrounded by the first pixel group to the fourth pixel group.

8. The image sensor according to claim 7, wherein, The first grid is not located in the central region surrounded by the first four photodiodes in the plan view.

9. The image sensor according to claim 5, wherein, The height of the first sub-grid pattern in the first direction is equal to or greater than three times the height of the second sub-grid pattern in the first direction.

10. The image sensor according to claim 9, wherein, The optical black area includes: The third grid is located on the second surface of the substrate. Wherein, the height of the first grid in the first direction is less than the height of the third grid in the first direction.

11. The image sensor according to claim 10, wherein, The third grid includes: L layers, Where L is an integer equal to or greater than 2.

12. The image sensor according to claim 6, wherein, The first region also includes: Photodiode isolation trench that penetrates the substrate.

13. An image sensor comprising: The substrate includes a first surface, a second surface opposite to the first surface, a first region located at the center region of the substrate, an optical black region, and a second region located between the first region and the optical black region in a plan view; Multiple color filters are located on the second surface of the substrate; A first grid is located in the first region between the plurality of color filters; A second grid is located in the second region between the plurality of color filters; as well as The third grid is located on the second surface of the substrate within the optically black area. The first grid comprises N layers stacked in a first direction perpendicular to the second surface of the substrate. The second grid comprises M layers stacked in the first direction. The third grid comprises L layers stacked in the first direction. Wherein, the height of the first grid in the first direction is less than the height of the second grid in the first direction. Wherein, the height of the first grid in the first direction is less than the height of the third grid in the first direction. Where N, M, and L are integers equal to or greater than 1. Where M is greater than N, Where L is greater than N, and The image sensor is configured to receive light from the second surface of the substrate.

14. The image sensor according to claim 13, wherein, Each of M and L is equal to or greater than 2.

15. The image sensor according to claim 13, wherein, The M layers comprise metallic materials.

16. The image sensor according to claim 15, wherein, The M layers include: The first subgrid pattern; and The second sub-grid pattern is located between the first sub-grid pattern and the photodiode. Wherein, the height of the first sub-grid pattern in the first direction is greater than the height of the second sub-grid pattern in the first direction.

17. The image sensor according to claim 16, wherein, The height of the first sub-grid pattern in the first direction is equal to or greater than twice the height of the second sub-grid pattern in the first direction.

18. The image sensor according to claim 17, wherein, The first region also includes: Photodiode isolation trench that penetrates the substrate.

19. The image sensor according to claim 14, wherein, M equals L.

20. An image sensor, comprising: The substrate includes a first surface, a second surface opposite to the first surface, a first region located at the center region of the substrate, an optical black region, and a second region located between the first region and the optical black region in a plan view; Multiple color filters are located on the second surface of the substrate; A first grid is located in the first region between the plurality of color filters; The second grid is located in the second region between the plurality of color filters. A first microlens is located on the first photodiode and the second photodiode in the first region; as well as The second microlens is located on top of the third and fourth photodiodes in the second region. The first grid comprises N layers stacked in a first direction perpendicular to the second surface of the substrate. The second grid comprises M layers stacked in the first direction. Wherein, the height of the first grid in the first direction is less than the height of the second grid in the first direction. Where N and M are integers equal to or greater than 1. Among them, N and M are different. In the vertical view, the first grid is not located at the center of the first microlens. In the vertical view, the second grid is not positioned at the center of the second microlens, and The image sensor is configured to receive light from the second surface of the substrate.

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