A preparation method of a wafer-level InGaAs single-photon detector and a structure thereof

Abstract

The application discloses a preparation method and structure of a wafer-level InGaAs single-photon detector. The method comprises the following steps: sequentially epitaxially growing an InP buffer layer, an InGaAs / InAlAs sacrificial layer and an SAGCM epitaxial functional layer (containing an n-type InP contact layer, an intrinsic InGaAs absorption layer and the like) on an InP substrate; forming a Zn diffusion zone and a carrier avalanche zone through MOCVD-Zn secondary diffusion; forming an electrically isolated dead zone through Fe ion implantation limited by a photolithography mask and repairing lattice damage through RTP high-temperature annealing. Subsequently, a passivation layer and a metal electrode with a thick gold bonding layer are prepared, the detector wafer and the readout circuit wafer are Au-Au wafer-level bonded, the InP substrate is stripped by using a 1064nm pulsed laser and is reused, the residual sacrificial layer is cleaned by using a solution, near-infrared adaptive antireflection film is evaporated, and finally, the finished product is obtained through cutting along a cutting path, processing of a light window and single-chip cutting. Thus, the traditional dry etching defects are avoided, the dark count is significantly reduced, the manufacturing cost is greatly reduced, the product yield is improved, batch production is realized, and the application is suitable for high-end fields such as quantum communication and laser radar.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and specifically to a method for fabricating a wafer-level InGaAs single-photon detector and its structure. Background Technology

[0002] A single-photon detector (SPD) is an ultra-low noise device whose enhanced sensitivity enables it to detect the smallest energy quantum of light—the photon. SPDs have irreplaceable application value in many fields such as quantum communication, single-photon radar, bio-fluorescence imaging, deep-space laser ranging, and fiber optic sensing, and are key components driving technological upgrades and industrial development in these fields. Although InGaAs-based single-photon detectors possess advantages such as eye safety, strong penetration, and long monitoring distance, traditional single-photon detector technologies still have many shortcomings due to cost factors and limitations imposed by low-temperature operation, severely restricting their mass production and widespread adoption. These shortcomings are mainly reflected in the following aspects: 1. Limited array size and low processing yield: Most mainstream single-photon detectors are currently 64×64 arrays, with only a few products reaching 128×128 arrays. The pixel pitch is fixed at 50μm or 100μm, which is insufficient in array integration and specification flexibility, making it difficult to meet the high-resolution detection requirements of high-end application scenarios. At the same time, due to the small product size, damage and deviation are prone to occur during subsequent processing, resulting in low product yield and indirectly increasing the manufacturing cost per qualified product.

[0003] 2. Complex and costly interconnection process: In existing technologies, the interconnection between the single-photon detector chip and the readout circuit adopts the die-to-die bonding mode (interconnection between a single chip and the readout circuit). After bonding, back-side thinning and polishing are required. The entire interconnection and subsequent processing steps are cumbersome and lengthy, which not only increases equipment investment and labor costs, but also easily introduces additional defects in multiple processes, further affecting product yield. In addition, the cumbersome process also leads to a longer production cycle, further increasing the equipment cost and manufacturing cost of the chip.

[0004] 3. A contradiction exists between device performance and process cost: On the one hand, traditional processes often use dry etching to form isolation trenches between pixels to achieve electrical isolation. However, dry etching easily introduces sidewall leakage and recombination centers, leading to an increase in the detector's dark count, which seriously affects detection accuracy and device stability. As the core noise indicator of the detector, an increase in dark count will reduce the system's signal-to-noise ratio, limiting the detector's application performance in low-light detection scenarios. On the other hand, the current substrate usage method is disposable, and the substrate cost accounts for a significant portion of the overall detector cost. The inability to reuse substrates further exacerbates cost pressures, contradicting the market demand for low cost.

[0005] Therefore, how to solve the technical bottlenecks of existing single-photon detectors, such as limited array specifications, complicated interconnection processes, low yield, high cost, high dark count, and non-reusable substrates, and how to overcome the dual limitations of low-temperature operation and cost, improve device performance and cost-effectiveness, and promote their mass market application, has become an important issue that needs to be addressed by those skilled in the art. Summary of the Invention

[0006] This invention addresses the technical problems of existing InGaAs single-photon detectors, such as cumbersome fabrication processes, low yields, high costs, and the tendency of traditional pixel isolation processes to introduce defects leading to increased dark counts and insufficient array size adaptability. It provides a wafer-level InGaAs single-photon detector fabrication method and its structure. This invention achieves non-destructive stripping and reuse of the InP substrate by introducing a sacrificial layer of specific composition, uses Fe ion implantation to replace dry etching to form pixel electrical isolation, and combines wafer-level Au-Au bonding to simplify the interconnect process. It precisely controls the process parameters at each step and is compatible with various mainstream pixel array sizes, fundamentally solving the core bottlenecks of traditional processes. This achieves low-cost, high-yield, and high-performance detector fabrication, and the fabrication process is compatible with existing semiconductor equipment, facilitating industrial-scale mass production. To achieve the above objectives, this invention adopts the following technical solutions: The first aspect of this invention provides a method for fabricating a wafer-level InGaAs single-photon detector, which includes the following steps: S1. Prepare an InP substrate (1), and sequentially grow an InP buffer layer (2), an InGaAs / InAlAs sacrificial layer (3), an n-type InP contact layer (4), an intrinsic InGaAs absorption layer (5), an InGaAsP transition layer (6), an InP charge layer (7), and an intrinsic InP multiplication layer (8) on the InP substrate (1) to obtain a detector epitaxial substrate. S2. Using MOCVD-Zn diffusion process, Zn is doped in the intrinsic InP multiplication layer (8) through secondary diffusion to form a uniform Zn diffusion region (9). The intrinsic InP multiplication layer region below the Zn diffusion region (9) is the carrier avalanche region. S3. An implantation mask is prepared by photolithography to define the gap region between adjacent pixels on the detector epitaxial substrate, and ion implantation is performed on the gap region to form an electrically isolated dead region (10). After implantation, the implantation mask is removed, and lattice damage introduced by ion implantation is repaired by annealing. S4. A passivation dielectric film is grown on the surface of the intrinsic InP multiplication layer (8), and a passivation layer (14) is formed by annealing. S5. A metal electrode (11) is prepared on the surface of the detector epitaxial substrate by photolithography, etching and evaporation processes, and a bonding metal layer is provided on the surface of the metal electrode (11) to form a detector wafer; S6. Using Au-Au bonding, the detector wafer with metal electrodes (11) and the readout circuit wafer (12) are bonded at the wafer level under alignment conditions to achieve electrical interconnection and mechanical fixation. S7. The back side of the InP substrate (1) is irradiated with a laser, so that the laser penetrates the InP substrate (1) and the InP buffer layer (2). The energy is confined to the InGaAs / InAlAs sacrificial layer (3) and absorbed, thus achieving the stripping of the InP substrate (1). S8. Clean the back side of the detector after peeling off the InP substrate (1) to remove the residual sacrificial layer and expose the n-type InP contact layer (4). Then, after evaporating the antireflection film (13), it is processed and cut to obtain the finished single-photon detector.

[0007] Preferably, in step S1, the epitaxial growth is performed using MOCVD or MBE technology; the InGaAs / InAlAs sacrificial layer (3) is a 3-5 pair of alternating layer structures, with each layer having a thickness of 100-200 nm.

[0008] Preferably, in step S1, the InGaAs / InAlAs sacrificial layer (3) is In 0.53 Ga 0.47 As / In 0.52 Al 0.48 As sacrificial layer; the intrinsic InGaAs absorber layer (5) is intrinsic In 0.53 Ga 0.47 As absorption layer Preferably, in step S2, the parameters of the MOCVD-Zn diffusion process are: diffusion temperature 520~560℃, diffusion pressure 80~110 Torr, primary diffusion time 1000~1500s, secondary diffusion time 700~1000s, and Zn source diffusion flow rate 80~120cc.

[0009] Preferably, in step S3, the ion implantation is performed using Fe ion implantation, and the Fe ion implantation process parameters are: implantation energy 320 keV, implantation dose 4.5 × 10⁻⁶. 13 cm -2 The injection depth stops above the InGaAs / InAlAs sacrificial layer (3); the annealing adopts RTP high-temperature annealing, and the process parameters of RTP high-temperature annealing are: annealing temperature is 450℃, annealing time is 50s; the width of the electrical isolation dead zone (10) is 1~3μm.

[0010] Preferably, in step S3, the preparation of the injection mask includes the following steps: uniformly coating a positive photoresist on the surface of the epitaxial wafer, and removing the photoresist in the gap area between adjacent pixels after exposure and development to expose the area to be injected. The surface of the epitaxial wafer in the non-gap area is covered and protected by the photoresist mask.

[0011] Preferably, in step S5, the thickness of the bonding metal layer of the metal electrode (11) is not less than 1 μm; in step S6, the process parameters of the Au-Au bonding method are: bonding pressure of 5 MPa and bonding temperature of 180 °C.

[0012] Preferably, in step S7, the laser used is a 1064nm laser pulse; In step S8, the residual sacrificial layer is removed using a sulfuric acid solution; the cutting includes: cutting the cutting channel and processing the optical window before single-piece cutting.

[0013] The second aspect of this invention provides a wafer-level InGaAs single-photon detector structure, which is a single-photon detector fabricated by the fabrication method described in the first aspect.

[0014] Preferably, the pixel array of the single-photon detector is 64×64 or 128×128, the pixel pitch is 50μm or 100μm, and the anti-reflection film (13) is a single-layer or double-layer film structure adapted to the near-infrared detection band, covering the light window area on the back of the single-photon detector.

[0015] Compared with the prior art, the beneficial effects of the present invention are: 1. By introducing an InGaAs / InAlAs sacrificial layer (3) and combining it with laser pulse stripping technology, this invention enables the non-destructive stripping of the InP substrate (1). After being cleaned, the stripped substrate can be reused for epitaxial growth, which completely changes the traditional one-time consumption mode of the substrate and enables the substrate to be reused, thus significantly reducing the cost of substrate consumables. At the same time, wafer-level bonding, wafer-level dicing and other processes replace the traditional wafer-by-wafer processing, reducing equipment investment and labor costs, and further reducing the overall manufacturing cost of the detector.

[0016] 2. In this case, Fe ion implantation is used to form an electrically isolated dead zone (10), which replaces the traditional dry etching isolation trench process. This avoids sidewall leakage and carrier recombination centers introduced during the etching process, thereby reducing the dark count of the detector from the source and improving the detection accuracy and signal-to-noise ratio. At the same time, the implanted lattice damage is repaired by RTP high-temperature annealing, which ensures the crystal quality and performance stability of the detector.

[0017] 3. This project uses wafer-level Au-Au bonding to achieve the overall interconnection of the detector and readout circuit, replacing the cumbersome process of traditional Die-to-Die bonding + back-side thinning and polishing. This reduces the probability of chip damage during processing and significantly improves product yield. Moreover, each process step is based on mature semiconductor processes such as MOCVD / MBE epitaxy, ion implantation, and wafer-level bonding, which are highly controllable, have precise process parameters, and are suitable for mass production.

[0018] 4. This case uses an independent passivation layer preparation process to complete the growth and annealing of the passivation dielectric film before the preparation of the metal electrode, which can form a complete passivation protection on the device surface, isolate air, water vapor and external impurities, avoid oxidation or contamination of the multiplication layer surface, reduce surface leakage channels and carrier recombination centers, and further reduce the dark count of the detector; the surface of the metal electrode (11) is provided with a bonding alloy layer with a thickness of not less than 1μm, and the Au-Au bonding interface formed with the readout circuit has low contact resistance and high connection stability, ensuring efficient and stable transmission of electrical signals; the back of the detector is deposited with an anti-reflection film (13) adapted to the near-infrared band, which reduces light reflection loss, improves photon absorption efficiency, and further optimizes the detection performance of the detector.

[0019] 5. The detector in this invention supports two mainstream pixel array specifications: 64×64 and 128×128. The pixel pitch can be selected as 50μm or 100μm, which can meet the needs of different high-end application scenarios such as quantum communication and lidar, thus expanding the application range of the detector. Moreover, the fabrication method of this invention is based on existing mature semiconductor processes, is fully compatible with existing semiconductor production equipment, requires no additional special equipment, and has a reasonable structural design and simple fabrication process, making it easy to achieve industrial-scale mass production and promoting the marketization and popularization of InGaAs single-photon detectors. Attached Figure Description

[0020] Figure 1 This is a schematic flowchart of the fabrication method of a wafer-level InGaAs single-photon detector according to the present invention.

[0021] Figure 2 This is a schematic diagram of the structure of the detector epitaxial substrate formed by step S1 of the present invention; Figure 3 This is a schematic diagram of the structure of the present invention after the Zn diffusion region is formed in step S2; Figure 4 This is a schematic diagram of the structure after the formation of the electrically isolated dead zone by ion implantation in step S3 of the present invention; Figure 5 This is a schematic diagram of the interconnect structure of the present invention after sequentially forming a passivation layer in step S4, preparing a metal electrode in step S5 to obtain a detector wafer, and completing Au-Au bonding with the readout circuit wafer in step S6. Figure 6This is a schematic diagram of the laser irradiation process in step S7 of the present invention; Figure 7 This is a schematic diagram of the process after the InP substrate is peeled off by laser irradiation in step S7 of the present invention. Figure 8 This is a schematic diagram of the structure of the finished photon detector obtained after step S8 of the present invention is completed. Detailed Implementation

[0022] The following examples further illustrate the features and other related characteristics of the present invention to facilitate understanding by those skilled in the art: Example

[0023] like Figures 1-8 As shown, this embodiment is a method for fabricating a wafer-level InGaAs single-photon detector, including the following steps: S1. Fabrication of the detector epitaxial substrate

[0024] First, prepare an InP substrate (1) as the growth carrier for the entire epitaxial structure, ensuring that the substrate surface is flat and free of impurities and defects, providing a good foundation for subsequent epitaxial layer growth. Then, using MOCVD or MBE technology, grow each functional layer sequentially on the InP substrate (1), in the following order: InP buffer layer (2), InGaAs / InAlAs sacrificial layer (3), n-type InP contact layer (4), intrinsic InGaAs absorption layer (5), InGaAsP transition layer (6), InP charge layer (7), and intrinsic InP multiplication layer (8). Specifically, MOCVD (metal-organic chemical vapor deposition) and MBE (molecular beam epitaxy) are two core atomic-level thin film epitaxial growth technologies in the semiconductor field, both used to prepare high-quality single-crystal thin films, and are key processes for the manufacture of optoelectronic, radio frequency, and power devices. The main function of the InP buffer layer (2) is to alleviate lattice mismatch stress, reduce defect propagation, and provide better growth conditions for the epitaxial layer. For example, in InP-based devices, if there is a difference in lattice constant between the epitaxial layer and the InP substrate, the buffer layer can reduce the dislocation density by gradually changing the lattice constant, thereby improving the quality of the epitaxial layer and the reliability of the device. The InP charge layer (7) is used to precisely distribute the electric field between the absorption layer and the multiplication layer, so that the absorption layer is in a low electric field (to avoid premature avalanche and reduce dark count) and the multiplication layer is in a high electric field (to ensure avalanche multiplication efficiency). It is the core control layer of the SAGCM structure avalanche photodiode.

[0025] Furthermore, in specific implementation, this application utilizes MOCVD or MBE technology to grow a 500nm InP buffer layer (2) on an InP substrate (1), and alternately grow 3-5 pairs of InP layers. 0.53 Ga 0.47 As / In0.52 Al 0.48 The structure consists of an As sacrificial layer, a 500 nm thick n-type InP contact layer (4), a 2 μm thick intrinsic InGaAs absorption layer (5), a 300 nm thick InGaAsP transition layer (6), and a 3.5 μm thick intrinsic InP multiplication layer (8).

[0026] S2 and Zn diffuse to form the core functional area.

[0027] Using MOCVD-Zn diffusion technology, Zn doping is performed in the intrinsic InP multiplication layer (8) through secondary diffusion to form a uniformly doped P-type Zn diffusion region (9) with controllable junction depth. The intrinsic InP multiplication layer region below the Zn diffusion region (9) is the avalanche region where carriers undergo avalanche multiplication. Together, they form an electric field region, providing an electric field environment for the transport and avalanche multiplication of photogenerated carriers. Specifically, MOCVD-Zn diffusion refers to a Zn diffusion doping process performed on an InP-based epitaxial wafer using a metal-organic chemical vapor deposition (MOCVD) device as a carrier and employing Zn source gas phase transport, to prepare the P-type doped region required for the device. Among them, the electric field region: the P+ region formed by Zn diffusion and the N-region of the charge layer constitute a PN junction. Under the action of an applied reverse bias voltage, the space charge region of the PN junction forms a stable electric field. The core function of this electric field region is to regulate carrier transport, efficiently and directionally drawing electron-hole pairs (photogenerated carriers) generated after the absorption layer captures a single photon to the avalanche region, while avoiding carrier accumulation at the interface and ensuring signal transmission efficiency. Avalanche region: is the core region in the electric field region where the electric field intensity is precisely enhanced to the critical value. When carriers (electrons / holes) enter this high field region, they are accelerated by the electric field to gain sufficient energy, collide with lattice atoms and ionize, generating new electron-hole pairs; the newly generated carriers are accelerated and collide again, forming an "avalanche" carrier multiplication effect. n-type InP contact layer (4) is n + The n-type InP contact layer, also known as the heavily doped n-type InP contact layer, is used to reduce contact resistance and form an ohmic contact.

[0028] S3. Ion implantation forms an electrically isolated dead zone, which is then repaired by annealing.

[0029] An implantation mask is prepared on the surface of the detector epitaxial substrate using photolithography: First, positive photoresist is uniformly coated on the surface of the epitaxial wafer. After exposure and development, the photoresist in the gap area between adjacent pixels is removed to expose the implantation area. The epitaxial wafer surface in the non-gap area is covered and protected by the photoresist mask. Ion implantation is performed on the exposed gap area at the pixel gap of the detector epitaxial substrate to form an electrically isolated dead zone (10), which is used to achieve electrical isolation between adjacent detector pixels and avoid crosstalk and leakage between pixels. After implantation, all implantation masks are stripped off, and then annealing is used to repair the lattice damage introduced by ion implantation and restore the crystal quality of the epitaxial layer.

[0030] The gap region between adjacent pixels refers to the blank area between two adjacent detection pixels on the outer epitaxial substrate of the detector; a pixel is the smallest unit of the detector to realize single photon detection (array distribution, such as 64×64 and 128×128 arrays in the patent), while the pixel gap region is the interval between two adjacent independent detection pixels, which does not undertake the photon detection function, but is only used to realize electrical isolation between pixels.

[0031] S4, Passivation layer preparation

[0032] A passivation dielectric film is grown on the surface of the intrinsic InP multiplication layer (8) using PECVD (plasma-enhanced chemical vapor deposition) technology. In specific implementation, the passivation dielectric film is preferably a SiNx or SiO2 dielectric film with a thickness controlled at 200~350nm. After the passivation dielectric film is grown, annealing is performed to reduce the semiconductor surface state density and form a passivation layer (14).

[0033] S5. Metal Electrode Preparation

[0034] Electrode contact windows are opened on the passivation layer (14) by photolithography and etching processes to expose the Zn diffusion region (9), and then metal electrodes (11) are prepared by electron beam evaporation. The metal electrode (11) is a conventional TiPtAu electrode (3 layers) with a bonding metal layer on its surface. The thickness of the bonding metal layer is not less than 1 μm. This thickness can ensure the reliability of subsequent Au-Au bonding, reduce contact resistance, and provide a guarantee for the efficient transmission of electrical signals. After the electrode is prepared, a detector wafer is formed.

[0035] S6, wafer-level Au-Au bonding

[0036] Using Au-Au bonding, the detector wafer with metal electrodes (11) and the readout circuit wafer are bonded at the wafer level under high-precision alignment conditions to achieve electrical interconnection and mechanical fixation between the detector and the readout circuit.

[0037] S7, Laser lift-off of InP substrate

[0038] The back side of the InP substrate (1) is irradiated with laser pulses. Utilizing the penetrating characteristics of the laser, the laser can penetrate the InP substrate (1) and the InP buffer layer (2) without damage. The laser energy is confined and absorbed within the InGaAs / InAlAs sacrificial layer (3), generating localized high temperatures that cause thermal decomposition of the sacrificial layer, thereby achieving the non-destructive removal of the InP substrate (1). After cleaning, the InP substrate (1) can be reused for epitaxial growth, realizing substrate reuse and significantly reducing manufacturing costs.

[0039] S8, Post-processing and Single-piece Cutting

[0040] The back side of the detector after stripping the InP substrate (1) was cleaned with a sulfuric acid solution to completely remove the residual InGaAs / InAlAs sacrificial layer (3), exposing the complete n-type InP contact layer (4), providing good conditions for subsequent photon absorption and signal transmission. Subsequently, an antireflection film (13) was deposited on the back side of the detector to reduce the reflection loss of near-infrared photons and improve the photon absorption efficiency of the detector. After the deposition was completed, the dicing and optical window processing were performed first, followed by wafer-level monolithic dicing, finally obtaining a single wafer-level InGaAs single-photon detector product.

[0041] As described above, step S1 of the wafer-level InGaAs single-photon detector fabrication method of this application involves sequentially epitaxially growing seven functional layers, including an InP buffer layer (2) and an InGaAs / InAlAs sacrificial layer (3), on an InP substrate (1). This ensures lattice matching and good interface quality between layers, effectively reducing interlayer defects and stress accumulation, and avoiding problems such as epitaxial layer detachment and cracking in subsequent processes. Among them, InP… The buffer layer (2) can effectively buffer the lattice mismatch between the substrate and the subsequent epitaxial layer, reducing crystal defects; the InGaAs / InAlAs sacrificial layer (3) provides core support for the non-destructive removal of the substrate in the subsequent S7 step, breaking the limitation of the traditional substrate being consumed at once; the orderly growth of the n-type InP contact layer (4), the intrinsic InGaAs absorption layer (5), the InGaAsP transition layer (6), the InP charge layer (7), and the intrinsic InP multiplication layer (8) provides dedicated functional foundations for the detector's electrical signal transmission, photon absorption, carrier transition, electric field modulation, and avalanche multiplication, ensuring that the detector has efficient optical response and signal amplification capabilities. At the same time, this step adopts a mature epitaxial growth process, which is highly controllable and suitable for wafer-level mass production, laying the foundation for the efficient development of subsequent processes.

[0042] In step S2, the Zn diffusion region (9) and avalanche region are formed in the intrinsic InP multiplication layer (8) by MOCVD-Zn diffusion process, without the need for additional functional layers, which simplifies the preparation process. The Zn diffusion process parameters are controllable, which can accurately control the diffusion depth and concentration distribution of Zn atoms, forming a doped region with a reasonable gradient. This ensures that the electric field region can achieve efficient separation and directional transport of photogenerated carriers, and the avalanche region can achieve stable avalanche multiplication of carriers, thereby amplifying the small number of carriers generated by a single photon into a recognizable electrical signal and improving the single-photon detection sensitivity of the detector. At the same time, the InP charge layer (7) can effectively suppress the reverse diffusion of carriers, reduce carrier recombination, further reduce the dark count of the detector, optimize the detection performance, and this process is compatible with existing semiconductor epitaxial equipment, without the need for additional dedicated equipment, thus reducing process costs.

[0043] In step S3, the injection area is precisely defined by photolithography to prepare an injection mask. Ion implantation is performed only at the pixel gap to form an electrically isolated dead zone (10), which replaces the traditional dry etching process for preparing isolation trenches. This completely avoids the sidewall leakage channels and carrier recombination centers introduced during the etching process, reduces the dark count of the detector from the source, improves the signal-to-noise ratio of the system, and eliminates the need for additional isolation trench passivation treatment, simplifying the process steps and reducing the processing cost. Subsequently, the annealing repair process can effectively repair the lattice damage caused during ion implantation, restore the crystal quality of the epitaxial substrate, reduce the impact of lattice defects on carrier transport, and ensure the stability of the detector's electrical performance. In addition, the electrically isolated dead zone (10) is formed only at the pixel gap and does not occupy the effective detection area, which can ensure the high integration of the detector and meet the needs of wafer-level batch preparation.

[0044] The setting of step S4, which completes the passivation layer growth and annealing before the metal electrode preparation, can form a complete passivation protection on the device surface, isolate external impurities and moisture, reduce surface states and surface leakage current, and further reduce dark count; at the same time, the process sequence of passivation first and then electrode preparation avoids damage to the passivation layer during electrode preparation, ensures the integrity of the passivation layer, and improves the stability of the device during long-term operation.

[0045] The metal electrode (11) prepared in step S5 by photolithography, etching and vapor deposition processes has a precise pattern and controllable size, which can realize the precise electrical connection between the detector and the readout circuit and reduce contact resistance. The thick gold bonding layer on the surface of the metal electrode (11) can greatly improve the conductivity and oxidation resistance of the electrode, and at the same time provide a good bonding interface for Au-Au bonding in step S6, ensuring the reliability and stability of the bonding and avoiding problems such as poor contact and debonding during the bonding process. After the electrode is prepared, a complete detector wafer is formed, which provides a unified processing carrier for subsequent wafer-level bonding, cutting and other processes, improving production efficiency. Moreover, the vapor deposition and photolithography processes are mature and suitable for mass production, which can reduce the cost and difficulty of electrode preparation.

[0046] Step S6 adopts Au-Au bonding to achieve wafer-level bonding between the detector wafer and the readout circuit wafer (12) under alignment conditions, replacing the traditional die-to-die bonding mode. This significantly reduces the amount of bonding operations, improves production efficiency, and avoids chip damage and bonding deviations that occur during die-to-die bonding, thus significantly improving product yield. The bonding interface formed by Au-Au bonding has low contact resistance and high connection stability, enabling efficient electrical interconnection between the detector and the readout circuit, ensuring stable transmission of electrical signals, and avoiding signal loss and interference. No additional adhesive is required during the bonding process, reducing the introduction of impurities. At the same time, the process parameters are mild, avoiding damage to the detector's epitaxial structure and core functional area caused by high temperature and high pressure, ensuring the detector's detection performance. Furthermore, wafer-level bonding is suitable for mass production requirements, further reducing the manufacturing cost per unit product.

[0047] The settings in step S7 enable the non-destructive peeling and reuse of the InP substrate (1), significantly reducing manufacturing costs while avoiding damage to the detector structure during the peeling process. In addition, the laser peeling process is simple to operate and highly efficient, adapting to the wafer-level batch peeling requirements, further improving production efficiency. Moreover, the laser parameters are controllable, enabling precise and non-destructive peeling of the substrate and reducing process difficulty.

[0048] Step S8 thoroughly removes the residual sacrificial layer by cleaning the back of the detector after the substrate is stripped, exposing the complete n-type InP contact layer (4), ensuring that photons can be efficiently absorbed by the intrinsic InGaAs absorption layer (5), while avoiding interference from the residual sacrificial layer to the transmission of electrical signals; the vapor-deposited antireflection film (13) can effectively reduce the reflection loss of near-infrared photons, improve the photon absorption efficiency of the detector, further optimize the detection performance, and adapt to the needs of near-infrared detection scenarios; through processing and cutting processes, the detector wafer is cut into individual finished products, and the cutting channels and optical windows can be processed according to requirements, ensuring that the finished detector has accurate dimensions and complete structure, and adapts to the installation requirements of different application scenarios; the entire post-processing and cutting process is adapted to wafer-level batch processing, and the operation is controllable, which can ensure the consistency and pass rate of the finished detector, and provide a guarantee for subsequent market applications.

[0049] As a specific implementation method, the InGaAs / InAlAs sacrificial layer (3) adopts a 3-5 pair of alternating layer structures, specifically 3-5 groups of "InGaAs layer + InAlAs layer" are alternately stacked, for example: InGaAs layer → InAlAs layer → InGaAs layer → InAlAs layer → InGaAs layer → InAlAs layer (6 layers in total, 3 alternating groups); the thickness of each layer is 100-200nm. This structure can accurately absorb subsequent laser energy and help the substrate to be peeled off without damage; preferably In 0.53 Ga 0.47 As / In 0.52 Al 0.48 As a sacrificial layer, this composition of the sacrificial layer can be precisely matched with the laser energy, providing a guarantee for subsequent non-destructive removal of the substrate; the intrinsic InGaAs absorber layer (5) is preferably intrinsic In. 0.53 Ga 0.47 As the absorption layer, this component can efficiently absorb photons in the near-infrared band, improving the photoresponse performance of the detector.

[0050] As mentioned above, by limiting the sacrifice layer to In 0.53 Ga 0.47 As / In 0.52 Al 0.48 As a sacrificial layer, it can utilize In 0.53 Ga 0.47 As / In 0.52 Al 0.48As the band gap widths of the two materials (InGaAs approximately 0.75 eV, InAlAs approximately 1.4 eV) are precisely matched with the photon energy of a 1064 nm laser (approximately 1.17 eV), the laser energy can be rapidly absorbed by the sacrificial layer and is almost not absorbed by the upper n-type InP contact layer (4), the InGaAs absorption layer (5), the lower InP buffer layer (2), and the InP substrate (1) (InP has extremely low absorption rate for 1064 nm lasers and can be considered "transparent"). In this way, the laser energy is concentrated and released only within the sacrificial layer, without damaging other functional layers and the substrate. In addition, by using a "3-5 pairs of alternating InGaAs / InAlAs stacked layers" design (100-200 nm per layer) instead of a single material layer, the interface of such a stacked structure further enhances the absorption efficiency of laser energy (interface reflection and scattering superposition), making the heat more concentrated inside the sacrificial layer and preventing heat diffusion to the substrate or functional layers.

[0051] As a specific implementation method, the parameters of the Zn diffusion process in step S2 are strictly controlled as follows: diffusion temperature 520~560℃, diffusion pressure 80~110 Torr, primary diffusion time 1000~1500s, secondary diffusion time 700~1000s, and Zn source diffusion flow rate 80~120cc.

[0052] The Zn diffusion process parameters defined in this invention were compared using a single-variable control method, focusing on four core performance indicators: Zn diffusion uniformity, carrier mobility, detector dark count, and quantum efficiency. The experimental data are shown in the table below: The experimental data above show that when the Zn diffusion process parameters are within the range of 520~560℃, 80~110 Torr, primary diffusion time 1000~1500s, secondary diffusion time 700~1000s, and Zn source diffusion flux 80~120cc as defined in this invention, the Zn diffusion uniformity reaches over 92%, and the carrier mobility is ≥3500cm³. 2Under testing conditions of / V·s and -40℃, the dark count is ≤18.5 kHz, and the detectivity is ≥26%, with all performance indicators reaching and exceeding the mainstream levels in the industry. The optimal overall performance is achieved when the parameters are at the median value, with a detectivity reaching 30% and a dark count as low as 12.8 kHz (-40℃). However, when the parameters exceed the specified range, problems such as insufficient diffusion, uneven diffusion, and epitaxial layer lattice damage occur, leading to increased dark count, decreased quantum efficiency, and reduced carrier mobility, thus compromising the core detection performance of the detector. This demonstrates that the Zn diffusion process parameter range defined in this invention can effectively ensure uniform and sufficient diffusion of Zn atoms, constructing a stable electric field region and avalanche region, thereby optimizing the detector's detection performance and adapting to the process requirements of wafer-level mass production. Thus, by precisely controlling the diffusion parameters, ensuring uniform diffusion of Zn atoms and forming a reasonably gradient doped region provides core support for the avalanche multiplication effect in single-photon detection.

[0053] In one specific implementation method, step S3 employs Fe ion implantation, with the process parameters strictly limited to: implantation energy of 320 keV and implantation dose of 4.5 × 10⁻⁶. 13 cm -2 The implantation depth stops above the InGaAs / InAlAs sacrificial layer (3) to avoid damaging the sacrificial layer and affecting subsequent substrate stripping. After ion implantation, the lattice damage caused during ion implantation is repaired by RTP high-temperature annealing process. The annealing parameters are: annealing temperature of 450℃ and annealing time of 50s to ensure the crystal quality of the detector epitaxial substrate and reduce the impact of lattice defects on detector performance. The width of the electrical isolation dead zone (10) is controlled to be 1~3μm, which can achieve effective electrical isolation and avoid occupying too much pixel space, thus ensuring the integration of the detector.

[0054] To determine the optimal parameter range for the Zn diffusion process and ensure the core performance of the detector, this invention selected different diffusion temperatures, pressures, times, and Zn source fluxes for testing. The focus was on four core performance indicators: Zn diffusion uniformity, carrier mobility, detector dark count, and quantum efficiency. Based on the experimental results, the optimal parameter range was selected. Specific experimental data are shown in the table below: The experimental data above show that the implantation energy determines the ion penetration depth; the higher the energy, the deeper the penetration. The implantation dose affects the ion distribution concentration but does not significantly change the penetration depth. This invention studies the effects of implantation energy and dose on implantation depth and substrate stability through multiple sets of comparative experiments: when the implantation parameters are 320 keV and 4.5 × 10⁻⁶ ppm... 12 cm -2At the measured injection depth range of 5.5~6µm, the injection is positioned between the upper and lower surfaces of the sacrificial layer, precisely stopping within the sacrificial layer region. This effectively creates an electrical isolation dead zone without penetrating the InP buffer layer beneath the sacrificial layer. When the injection energy is below 320keV, the injection is too shallow to reach the sacrificial layer region, failing to achieve effective isolation. When the injection energy is above 320keV, the injection is too deep, penetrating the sacrificial layer and damaging the buffer layer. The injection dose deviates from 4.5×10⁻⁶. 12 cm -2 At this time, either effective isolation cannot be formed, or severe lattice damage occurs. Therefore, based on the above experimental results, this invention determines the optimal injection energy of 320 keV and the optimal lattice strength of 4.5 × 10⁻⁶ kJ / m³. 12 cm -2 The injection dose, a parameter that allows for precise control of the injection depth to stop above the sacrificial layer, balances electrical isolation with substrate structural stability, thus meeting the fabrication requirements of the detector of this invention.

[0055] As a specific implementation method, step S3 is divided into three core stages: implantation mask preparation, selective ion implantation, and mask removal and lattice damage repair, as detailed below: 1. Implantation mask preparation: Positive photoresist is uniformly coated on the surface of the epitaxial wafer. After pre-baking, alignment exposure, development, and post-baking, the photoresist in the gap area between adjacent pixels is removed, and the gap area to be implanted is precisely exposed. The epitaxial wafer surface (including the active area of ​​the pixel core) in the non-gap area is completely covered and protected by the photoresist mask, so as to achieve precise definition of the ion implantation area. 2. Selective ion implantation: Fe ions are implanted into the gap region exposed by the mask to form a high-resistivity electrical isolation dead zone (10) that penetrates the core functional layer in the gap region. This is used to achieve electrical isolation between adjacent detection pixels and avoid crosstalk and leakage of electrical signals between pixels. 3. Mask Removal and Damage Repair: After ion implantation, a semiconductor-specific stripping solution is used to thoroughly remove all implantation masks from the wafer surface. Subsequently, an RTP high-temperature annealing process is used to repair the lattice damage introduced during ion implantation and restore the crystal quality of the epitaxial layer.

[0056] As a specific implementation method, in step S6, the process parameters of Au-Au bonding are strictly controlled as follows: bonding pressure is 5MPa and bonding temperature is 180℃. Under these parameters, a stable bonding interface with low contact resistance can be formed, while avoiding damage to the detector epitaxial structure caused by high temperature and high pressure. Wafer-level bonding replaces the traditional die-to-die bonding mode, which greatly improves production efficiency, reduces the probability of chip damage, and improves product yield.

[0057] In one specific implementation, step S7 uses a 1064nm laser pulse; thus, the photon energy of the 1064nm pulsed laser is similar to the preferred In energy level of this invention. 0.53 Ga 0.47 As / In 0.47 Al 0.48 As the bandgap width of the sacrificial layer is highly compatible (the photon energy is slightly higher than the bandgap width of the sacrificial layer), it can be precisely absorbed by the sacrificial layer without penetrating to the InP buffer layer below or the core functional layer of the detector above, thus achieving energy localization. This precise energy matching ensures that the sacrificial layer can fully absorb laser energy and convert it into heat energy, quickly reaching the thermal decomposition temperature (450~550℃) to achieve interlayer bond breakage, while avoiding lattice damage to adjacent epitaxial layers caused by laser energy penetrating the sacrificial layer, laying the foundation for non-destructive substrate peeling. At the same time, unlike other wavelength lasers (such as 808nm, 1550nm), it can effectively avoid the problems of insufficient energy absorption or excessive penetration. In addition, the 1064nm pulsed laser has good penetrability and can easily penetrate the InP substrate (1) and the InP buffer layer (2). Compared with short-wavelength lasers (such as ultraviolet lasers) which have insufficient penetrability and cannot penetrate the InP substrate, and long-wavelength lasers (such as 1550nm) whose energy easily penetrates the sacrificial layer and causes damage to the underlying structure, the penetration depth of the 1064nm pulsed laser is more suitable for the epitaxial layer structure of this invention.

[0058] In one specific implementation, step S8 involves using a sulfuric acid-based solution to remove the residual sacrificial layer; the cutting includes single-piece cutting after kerfing and optical window processing. Thus, the sulfuric acid-based solution exhibits extremely strong selective dissolution capability for the InGaAs / InAlAs sacrificial layer, rapidly and thoroughly dissolving the residual sacrificial layer. Simultaneously, it has almost no corrosive effect on the detector core epitaxial layers (n-type InP contact layer, intrinsic InGaAs absorption layer, etc.), preventing the residual sacrificial layer from obscuring the n-type InP contact layer and ensuring that subsequent photons can be efficiently captured by the intrinsic InGaAs absorption layer. Furthermore, it prevents the residual sacrificial layer from introducing impurities and creating leakage channels, further reducing the detector's dark count and improving detection sensitivity and performance stability. The cutting method, which involves first cutting the wafer path, then processing the optical window, and finally cutting the individual wafers, allows for precise division of the cutting area, avoids damage to the core functional areas of the detector, and ensures the integrity and yield of the finished product structure. Simultaneously, it enables precise optical window processing within the entire wafer, improving processing accuracy and efficiency, adapting to mass production, ensuring accurate finished product dimensions, and guaranteeing the correspondence between the optical window and the pixel array, thus improving light response performance. It flexibly adapts to two array specifications: 64×64 and 128×128. Combined with precise impurity removal using a sulfuric acid-based solution, the overall quality and core performance of the detector are guaranteed, improving production efficiency and reducing process costs.

[0059] In one specific implementation, the passivation layer (14) only covers the area outside the metal electrode (11), without obscuring the bonding surface of the metal electrode (11), and does not affect the electrical interconnection effect of subsequent Au-Au bonding. Thus, on the one hand, the passivation layer (14) protects the surface of the intrinsic InP multiplication layer (8), isolating it from air, moisture and external impurities, preventing oxidation or contamination of the multiplication layer surface, reducing surface leakage channels and carrier recombination centers, further reducing the dark count of the detector, and improving the stability of the detection performance; on the other hand, the insulating properties of the passivation layer (14) can further enhance the electrical isolation effect between pixels, avoid electrical signal crosstalk between adjacent pixels, and work synergistically with the electrical isolation dead zone (10) formed in step S3 to improve the integration and performance reliability of the detector. Example

[0060] This invention also provides a wafer-level InGaAs single-photon detector structure, which is fabricated by the method described in Example 1 above. It possesses structural features corresponding to the fabrication method and can achieve efficient and stable single-photon detection. The pixel array of this detector is 64×64 or 128×128, with a pixel pitch of 50μm or 100μm, which can be flexibly selected according to the needs of different application scenarios. The anti-reflection film (13) is a single-layer or double-layer film structure adapted to the near-infrared detection band, covering the optical window area on the back of the single-photon detector to further improve photon absorption efficiency and ensure the detector's detection performance. Specifically, the anti-reflection film can be a Si3N4 anti-reflection film.

[0061] In summary, this invention discloses a method for fabricating a wafer-level InGaAs single-photon detector and its structure, which involves growing In on top of an InP buffer layer (2). 0.53 Ga 0.47 As / In 0.52 Al 0.48As sacrificial layer (3), then conventional SAGCM epitaxial structure layers (corresponding to the n-type InP contact layer (4), intrinsic InGaAs absorption layer (5), InGaAsP transition layer (6), InP charge layer (7), intrinsic InP multiplication layer (8) of this invention) are grown. Subsequently, a Zn diffusion region (9) (P region) is formed by MOCVD-Zn secondary diffusion process. Then, Fe ions are implanted at the pixel gap of the detector epitaxial substrate to form an electrically isolated dead region (10). After the implantation is completed, RTP high-temperature annealing is performed to repair the implantation defects. A passivation layer (14) is then grown and a metal electrode (11) is prepared. The metal electrode (11) is conventional TiPtAu, and the surface layer is a thick Au bonding layer with a thickness of not less than 1 μm. Subsequently, the detector wafer and the readout circuit wafer (12) are directly interconnected and mechanically fixed by Au-Au bonding, replacing the conventional In interconnect and subsequent filler curing method. After bonding, a 1064nm pulsed laser (pulse width 10~20ns, energy density 1.5~4.0J / cm²) is used. 2 The laser beam (50-100 μm) is used to irradiate the back side of the InP substrate (1). Since the laser can penetrate the InP substrate (1) and the InP buffer layer (2) without damage, the energy is confined within the InGaAs / InAlAs sacrificial layer (3) and rapidly absorbed, generating local high temperature to achieve the stripping of the InP substrate (1). After the stripping is completed, the residual InGaAs / InAlAs sacrificial layer (3) on the back side of the detector is treated with a sulfuric acid solution to remove the sacrificial layer residue and expose the n-type InP contact layer (4). Then, the antireflection film (13) on the back side is deposited. Finally, the dicing, window processing and single-piece cutting are performed in sequence to obtain a single complete detector device. Among them, the P contact region corresponds to the Zn diffusion region (9) formed by MOCVD-Zn secondary diffusion in step S2. It is located on the surface of the intrinsic InP multiplication layer (8) and is a P-type doped region. The metal electrode (11) contacts this region and draws out the P electrode electrical signal. The N-contact region corresponds to the n-type InP contact layer (4) grown in step S1. It is an N-type doped region located above the InGaAs / InAlAs sacrificial layer (3). After the substrate is peeled off, it serves as the back light incident window to realize the N-pole electrical connection.

[0062] Thus, this invention significantly reduces the adverse effects of high cost and low yield caused by the complex process of InGaAs single-photon detectors. Not only can the substrate be reused, but the electrical isolation dead zone is formed by the mature, controllable, and low-cost ion implantation method, replacing the isolation trench formed by the dry etching process. This method avoids sidewall leakage and recombination centers introduced by dry etching, reduces dark count, and improves device performance. It also provides feasibility for subsequent wafer-level Au-Au bonding. Based on the above technical solution, the equipment cost and manufacturing cost are greatly reduced, increasing the possibility of commercial application of InGaAs single-photon detectors.

[0063] As stated above, this case protects a method for fabricating a wafer-level InGaAs single-photon detector and its structure. All technical solutions that are the same as or similar to this case should be considered to fall within the scope of protection of this case.

Claims

1. A method for fabricating a wafer-level InGaAs single-photon detector, characterized in that, Includes the following steps: S1. Prepare an InP substrate (1), and sequentially grow an InP buffer layer (2), an InGaAs / InAlAs sacrificial layer (3), an n-type InP contact layer (4), an intrinsic InGaAs absorption layer (5), an InGaAsP transition layer (6), an InP charge layer (7), and an intrinsic InP multiplication layer (8) on the InP substrate (1) to obtain a detector epitaxial substrate. S2. Using MOCVD-Zn diffusion process, Zn is doped in the intrinsic InP multiplication layer (8) through secondary diffusion to form a uniform Zn diffusion region (9). The intrinsic InP multiplication layer region below the Zn diffusion region (9) is the carrier avalanche region. S3. An implantation mask is prepared by photolithography to define the gap region between adjacent pixels on the detector epitaxial substrate, and ion implantation is performed on the gap region to form an electrically isolated dead zone (10). After implantation, the implantation mask is removed, and the lattice damage introduced by ion implantation is repaired by annealing. S4. A passivation dielectric film is grown on the surface of the intrinsic InP multiplication layer (8), and a passivation layer (14) is formed by annealing. S5. A metal electrode (11) is prepared on the surface of the detector epitaxial substrate by photolithography, etching and evaporation processes, and a bonding metal layer is provided on the surface of the metal electrode (11) to form a detector wafer; S6. Using Au-Au bonding, the detector wafer with metal electrodes (11) and the readout circuit wafer (12) are bonded at the wafer level under alignment conditions to achieve electrical interconnection and mechanical fixation. S7. The back side of the InP substrate (1) is irradiated with a laser, so that the laser penetrates the InP substrate (1) and the InP buffer layer (2). The energy is confined to the InGaAs / InAlAs sacrificial layer (3) and absorbed, thus achieving the stripping of the InP substrate (1). S8. Clean the back side of the detector after peeling off the InP substrate (1) to remove the residual sacrificial layer and expose the n-type InP contact layer (4). Then, after evaporating the antireflection film (13), it is processed and cut to obtain the finished single-photon detector.

2. The method for fabricating a wafer-level InGaAs single-photon detector according to claim 1, characterized in that, In step S1, the epitaxial growth is performed using MOCVD or MBE technology; the InGaAs / InAlAs sacrificial layer (3) is a 3-5 pair of alternating layer structures, with each layer having a thickness of 100-200 nm.

3. The method for fabricating a wafer-level InGaAs single-photon detector according to claim 1 or 2, characterized in that, In step S1, the InGaAs / InAlAs sacrificial layer (3) is In 0.53 Ga 0.47 As / In 0.52 Al 0.48 As sacrificial layer; the intrinsic InGaAs absorber layer (5) is intrinsic In 0.53 Ga 0.47 As absorption layer.

4. The method for fabricating a wafer-level InGaAs single-photon detector according to claim 1, characterized in that, In step S2, the parameters of the MOCVD-Zn diffusion process are: diffusion temperature 520~560℃, diffusion pressure 80~110 Torr, primary diffusion time 1000~1500s, secondary diffusion time 700~1000s, and Zn source diffusion flow rate 80~120cc.

5. The method for fabricating a wafer-level InGaAs single-photon detector according to claim 1, characterized in that, In step S3, the ion implantation adopts Fe ion implantation. The Fe ion implantation process parameters are: implantation energy 320 KeV, implantation dose 4.5 × 10¹³ cm⁻², and implantation depth stops above the InGaAs / InAlAs sacrificial layer (3); the annealing adopts RTP high-temperature annealing. The RTP high-temperature annealing process parameters are: annealing temperature 450℃, annealing time 50s; the width of the electrical isolation dead zone (10) is 1~3 μm.

6. The method for fabricating a wafer-level InGaAs single-photon detector according to claim 1 or 5, characterized in that, In step S3, the preparation of the injection mask by photolithography includes the following steps: uniformly coating a positive photoresist on the surface of the epitaxial wafer, and removing the photoresist in the gap area between adjacent pixels after exposure and development to expose the injection area. The surface of the epitaxial wafer in the non-gap area is covered and protected by the photoresist mask.

7. The method for fabricating a wafer-level InGaAs single-photon detector according to claim 1, characterized in that, In step S5, the thickness of the bonding metal layer of the metal electrode (11) is not less than 1 μm; in step S6, the process parameters of the Au-Au bonding method are: bonding pressure of 5 MPa and bonding temperature of 180 °C.

8. The method for fabricating a wafer-level InGaAs single-photon detector according to claim 1, characterized in that, In step S7, a 1064nm laser pulse is used; In step S8, a sulfuric acid solution is used to remove the residual sacrificial layer; the cutting includes: cutting the cutting channel and processing the optical window before single-piece cutting.

9. A wafer-level InGaAs single-photon detector structure, characterized in that, This includes single-photon detectors prepared by the preparation method described in any one of claims 1-8.

10. The wafer-level InGaAs single-photon detector structure according to claim 9, characterized in that, The pixel array of the single-photon detector is 64×64 or 128×128, and the pixel pitch is 50μm or 100μm. The anti-reflection film (13) is a single-layer or double-layer film structure adapted to the near-infrared detection band, covering the light window area on the back of the single-photon detector.

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