Bonding apparatus, bonding method, and method for manufacturing semiconductor device

Abstract

Improving yield of semiconductor devices. A bonding apparatus of an embodiment includes a first and a second stage and a processor. The first stage has a main body portion, a heater that heats the main body portion, and a plurality of stage pins on the main body portion configured to be capable of holding a first substrate. The second stage is configured to be capable of holding a second substrate. The processor performs a bonding process that bonds the first substrate and the second substrate. At least one of an area and a length of a plurality of first pins that are arranged in a first direction among the plurality of stage pins is different between a first pin located at a central portion of the first stage and a first pin located at an outer peripheral portion. At least one of an area and a length of a plurality of second pins that are arranged in a second direction different from the first direction among the plurality of stage pins is substantially the same between a second pin located at the central portion of the first stage and the second pin located at the outer peripheral portion.

Description

Technical Field

[0001] The embodiments relate to bonding apparatus, bonding method, and method of manufacturing semiconductor device. Background Technology

[0002] Three-dimensional stacking technology is known to be used to stack semiconductor circuit substrates in three dimensions. Summary of the Invention

[0003] Improving the yield of semiconductor devices. The bonding apparatus of this embodiment includes a first worktable, a second worktable, and a processor. The first worktable has a main body, a plurality of worktable pins disposed on the upper part of the main body, and a heater for heating the main body, configured to hold a first substrate using each of the plurality of worktable pins. The second worktable is configured to hold a second substrate. The processor is configured to control the first and second worktables to perform a bonding process for bonding the first and second substrates. The first worktable, when viewed from above, has a central portion including the center of the first worktable and an outer peripheral portion located on the outer periphery of the central portion. At least one of the area and length of the plurality of first pins arranged in a first direction differs between the first pins located in the central portion of the first worktable and the first pins located in the outer peripheral portion. At least one of the area and length of the plurality of second pins arranged in a second direction different from the first direction is substantially the same between the second pins located in the central portion of the first worktable and the second pins located in the outer peripheral portion. Attached Figure Description

[0004] Figure 1 It is a schematic diagram showing an outline of the manufacturing process of a semiconductor device.

[0005] Figure 2 This is a schematic diagram illustrating an example of the configuration of alignment marks used in the manufacturing process of a semiconductor device.

[0006] Figure 3 This is a table illustrating an example of the correction performance of the exposure and bonding apparatus for overlapping components within the wafer surface that may remain due to bonding alignment control.

[0007] Figure 4 This is a block diagram illustrating an example of the configuration of a semiconductor manufacturing system according to the first embodiment.

[0008] Figure 5 This is a block diagram illustrating an example of the configuration of the exposure apparatus included in the semiconductor manufacturing system of the first embodiment.

[0009] Figure 6 This is a block diagram illustrating an example of the configuration of the bonding apparatus included in the semiconductor manufacturing system of the first embodiment.

[0010] Figure 7 This is a schematic diagram illustrating an example of the configuration of the lower worktable included in the coupling device of the first embodiment.

[0011] Figure 8 This is a top view showing an example of the planar layout of the lower worktable in a first configuration example of the coupling device of the first embodiment.

[0012] Figure 9 This is an example of the cross-sectional structure along the X direction of the lower worktable in the first configuration example of the coupling device of the first embodiment. Figure 8 A cross-sectional view of the IX-IX line.

[0013] Figure 10 This is an example of the cross-sectional structure along the Y direction of the lower worktable in the first configuration example of the coupling device of the first embodiment. Figure 8 A cross-sectional view along the XX line.

[0014] Figure 11 This is a top view showing an example of the planar layout of the lower worktable in a second configuration example of the coupling device of the first embodiment.

[0015] Figure 12 This is an example of the cross-sectional structure along the X direction of the lower worktable in a second configuration example of the joining device of the first embodiment. Figure 11 A sectional view of line XII-XII.

[0016] Figure 13 This is an example of the cross-sectional structure along the Y direction of the lower worktable in a second configuration example of the joining device of the first embodiment. Figure 11 A cross-sectional view of line XIII-XIII.

[0017] Figure 14 This is a top view showing an example of the planar layout of the lower worktable in a third configuration example of the coupling device of the first embodiment.

[0018] Figure 15 This is an example of the cross-sectional structure along the X direction of the lower worktable in the third configuration example of the joining device of the first embodiment. Figure 14 A cross-sectional view of the XV-XV line.

[0019] Figure 16 This is an example of the cross-sectional structure along the Y direction of the lower worktable in the third configuration example of the joining device of the first embodiment. Figure 14 A cross-sectional view along the XVI-XVI line.

[0020] Figure 17This is a block diagram illustrating an example of the configuration of a server included in the semiconductor manufacturing system of the first embodiment.

[0021] Figure 18 This is a schematic diagram showing an outline of the joining process in the joining device of the first embodiment.

[0022] Figure 19 This is a schematic diagram illustrating the heat transfer method to the lower wafer held on the lower stage of the bonding apparatus in the first embodiment.

[0023] Figure 20 This is a graph showing the temperature change of the lower wafer on the lower stage of the bonding apparatus in the first embodiment.

[0024] Figure 21 This is a graph showing a second example of temperature change of the lower wafer on the lower stage of the bonding apparatus in the first embodiment.

[0025] Figure 22 This is a diagram illustrating the effect of thermal expansion of the lower worktable in the joining device of the first embodiment.

[0026] Figure 23 This is a flowchart illustrating an example of a method for learning wafer ratio correction values ​​in a semiconductor manufacturing system according to the first embodiment.

[0027] Figure 24 This is a graph illustrating an example of the learning result of the wafer ratio correction value in the semiconductor manufacturing system of the first embodiment.

[0028] Figure 25 This is a flowchart illustrating a first example of the joining method of the joining device according to the first embodiment.

[0029] Figure 26 This is a flowchart illustrating a second example of the joining method of the joining device according to the first embodiment.

[0030] Figure 27 This is a flowchart illustrating an example of a method for learning wafer ratio correction values ​​in a semiconductor manufacturing system according to the second embodiment.

[0031] Figure 28 This is a graph illustrating an example of the learning result of the wafer ratio correction value in the semiconductor manufacturing system of the second embodiment.

[0032] Figure 29 This is a block diagram illustrating an example of the overall configuration of the memory device according to the third embodiment.

[0033] Figure 30This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array provided in the memory device of the third embodiment.

[0034] Figure 31 This is a perspective view showing an example of the structure of the memory device according to the third embodiment.

[0035] Figure 32 This is a top view showing an example of the planar layout of the memory cell array provided by the memory device of the third embodiment.

[0036] Figure 33 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array provided by the memory device of the third embodiment.

[0037] Figure 34 This is an example of the cross-sectional structure of the memory pillars of the memory device according to the third embodiment. Figure 33 A sectional view of the XXXIV-XXXIV line.

[0038] Figure 35 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device according to the third embodiment. Detailed Implementation

[0039] Hereinafter, various embodiments will be described with reference to the accompanying drawings. Each embodiment illustrates an apparatus and method for embodying the technical concept of this application. The drawings are schematic diagrams or conceptual diagrams. The dimensions, scales, etc., of each drawing are not necessarily the same as reality. Depicted structures are appropriately omitted. Components having substantially the same function and structure are given the same reference numerals. Numbers and other reference numerals attached to the reference numerals in the accompanying drawings are referred to by the same reference numerals and are used to distinguish similar elements from each other.

[0040] Hereinafter, the two intersecting directions will be referred to as the "X direction" and the "Y direction," and the plane parallel to the X and Y directions will be referred to as the "XY plane." In the following description, the direction perpendicular to the XY plane will be referred to as the "Z direction." In this specification, "above" means vertically above the component serving as a reference. In this specification, "below" means vertically below the component serving as a reference. In this specification, "view from above" means, for example, visually recognizing a horizontally placed component such as a layer from above. "Visual recognition" includes observing an object using a microscope, camera, or similar means.

[0041] The semiconductor device described in this specification is formed by bonding two semiconductor circuit substrates on which semiconductor circuits are formed respectively, and then separating the bonded semiconductor circuit substrates into individual chips. Hereinafter, the semiconductor circuit substrate is referred to as a "wafer". The process of bonding two wafers is called a "bonding process". The apparatus for performing the bonding process is called a "bonding apparatus". During the bonding process, the wafers positioned on the upper and lower sides are referred to as the "upper wafer UW" and the "lower wafer LW", respectively. The group of the bonded upper wafer UW and lower wafer LW is called the "bonded wafer BW". "Front side of the wafer" corresponds to the side on which the semiconductor circuits are formed in the previous process. "Back side of the wafer" corresponds to the side of the wafer opposite to the front side.

[0042] <0> Overview of semiconductor device manufacturing methods

[0043] Figure 1 This is a schematic diagram illustrating an outline of a semiconductor device manufacturing process. See below for reference. Figure 1 This section describes the general process flow in the manufacturing method of semiconductor devices.

[0044] First, wafers are allocated into lots (“lot allocations”). A lot can contain multiple wafers. Lots are, for example, classified into lots containing upper wafers (UWs) and lots containing lower wafers (LWs). Each upper wafer (UW) is associated with a lower wafer (LW).

[0045] Then, the front-end processes are performed on the batches containing the upper UW wafer and the batches containing the lower LW wafer. The front-end processes include a combination of "exposure processing", "overlay (alignment control) measurement", and "etching processing". In addition, although omitted in this specification, the front-end processes may also include heating processes, cleaning processes, film deposition processes, etc.

[0046] Exposure processing is the process of transferring the pattern of a mask (intermediate mask) onto the resist material on a wafer in shooting units. "Shot" corresponds to the division of the exposure area in the exposure processing. The shooting configuration for the upper wafer (UW) is set to be the same as that for the lower wafer (LW). In exposure processing, single shots are repeatedly performed at staggered positions. That is, the exposure apparatus exposes the wafer in a step-and-repeat manner. Then, a portion of the resist material is removed by development processing, and the desired pattern is transferred onto the resist material. In exposure processing, the configuration and shape of each shot are corrected based on the measurement results of alignment marks, various correction values, etc. This adjusts the alignment of the pattern on the substrate with the pattern formed by the exposure processing.

[0047] Exposure OL measurement is the process of measuring the offset between the pattern on the substrate and the pattern of the resist material formed through exposure processing. The measurement results obtained by exposure OL measurement are used for, for example, to determine rework in exposure processing and to calculate alignment correction values ​​for subsequent batches.

[0048] Etching is a process that uses a resist material formed through exposure as a mask to process components on a wafer. Through etching, the components on the wafer are shaped based on patterns formed by the resist material. The circuit pattern of each layer can be formed through a combination of such exposure and etching processes.

[0049] By performing the front-end process of the upper wafer UW, the desired semiconductor circuit is formed on the front side of the upper wafer UW. By performing the front-end process of the lower wafer LW, the desired semiconductor circuit is formed on the front side of the lower wafer LW (“front-end process complete”). Then, a bonding process is performed using the associated upper wafer UW and lower wafer LW.

[0050] In the bonding process, the bonding apparatus holds the front sides of the upper wafer UW and the lower wafer LW facing each other. Then, based on the measurement results of alignment marks, the bonding apparatus adjusts the alignment of the patterns formed on the front sides of the upper wafer UW and the lower wafer LW. Next, the bonding apparatus brings the front sides of the upper wafer UW into contact with the front sides of the lower wafer LW. Thus, the front sides of the upper wafer UW and the lower wafer LW are bonded together to form a bonded wafer BW. Afterwards, bonding OL (overlay) measurements are performed on the bonded wafer BW.

[0051] Bonding OL measurement is a process that measures the offset of the overlap between the pattern formed on the bonding surface of the upper wafer (UW) and the pattern formed on the bonding surface of the lower wafer (LW). The "bonding layer" corresponds to the layer that contacts the boundary portion of the upper wafer (UW) and the lower wafer (LW). Both the upper wafer (UW) and the lower wafer (LW) have bonding layers. The measurement results obtained through bonding OL measurement can be used for calculations of alignment correction values ​​applied in subsequent batch exposure processes.

[0052] Next, a wiring process is performed on the bonding wafer BW to form wiring and pads for external connections to the circuitry disposed on the bonding wafer BW. Then, the bonding wafer BW is separated into individual chips by a dicing process, thereby forming multiple semiconductor devices from a single bonding wafer BW.

[0053] Furthermore, in this specification, alignment corresponds to the shape of the wafer under the reference of the exposure apparatus or bonding apparatus. The offset of coincidence corresponds to the positional offset between the pattern of the coincident source and the pattern of the coincident target. That is, the component that cannot be corrected by exposure processing or bonding processing based on the measurement results of alignment is called the coincidence offset. Hereinafter, the correction value used in the alignment at the coincident position will be called the "alignment correction value". The coefficients of the terms in the case where a polynomial is used in the alignment correction will be called the "alignment correction coefficients". The alignment correction value can be calculated based on the alignment correction coefficients of the terms and the exposure position.

[0054] The overlap offsets that can occur during exposure and joining processes can be represented by a combination of various components. For example, the alignment measurement results are decomposed into K values ​​using polynomial regression. The alignment components represented by K values ​​include offset (shift) components, magnification components, and orthogonality components. The mathematical expressions corresponding to each component are listed below. Furthermore, in the following mathematical expressions, "x" and "y" correspond to the coordinates in the X and Y directions, respectively. "dx" and "dy" correspond to the overlap offsets in the X and Y directions, respectively. "K1" to "K6" correspond to the alignment correction coefficients (polynomial regression coefficients).

[0055] Offset (displacement) component in the X direction: dx = K1

[0056] Offset (displacement) component in the Y direction: dy = K2

[0057] The magnification component in the X direction: dx = K3*x

[0058] The magnification component in the Y direction: dy = K4*y

[0059] Orthogonality component in the X direction: dx = K5*y

[0060] Orthogonality component in the Y direction: dy = K6*x.

[0061] In this example, the overlap offset Ex in the X direction is calculated using "Ex = K1 + K3*x + K5*y". The overlap offset Ey in the Y direction is calculated using "Ey = K2 + K4*y + K6*x". Furthermore, when representing the overlap components using polynomial regression, not only K1 to K6 can be used as polynomial regression coefficients, but also coefficients assigned to higher-order overlap components. Additionally, the aforementioned overlap offsets can be calculated separately for the imaging unit and the wafer plane. Hereinafter, the overlap component generated within the wafer plane will also be referred to as the "wafer magnification component". The wafer magnification component corresponds to the size of the wafer. The overlap component randomly generated within the wafer plane will be called the "random component".

[0062] Figure 2 This is a schematic diagram illustrating an example of the configuration of alignment marks AM used in the manufacturing process of a semiconductor device. Figure 2 (A) illustrates the configuration of multiple alignment marks AM on a wafer WF measured during exposure processing. Figure 2 (B) illustrates the configuration of multiple alignment marks AM on a wafer WF measured during the bonding process.

[0063] like Figure 2 As shown in (A), during the exposure process, the exposure apparatus measures alignment marks AM at multiple points disposed on the wafer WF (i.e., upper wafer UW or lower wafer LW). Preferably, the number of alignment marks AM measurements is three or more. By approximating the measurement results of the multiple alignment marks AM in an orthogonal coordinate system, the exposure apparatus can calculate alignment correction values ​​such as displacement components, magnification components, and orthogonality components in the X and Y directions. Furthermore, the exposure apparatus can correct the overlap of the imaging unit and the in-plane overlap of the wafer based on the measurement results of the multiple alignment marks AM.

[0064] like Figure 2 As shown in (B), during the bonding process, the bonding apparatus, for example, measures three alignment marks AM_C, AM_L, and AM_R respectively disposed on the upper wafer UW and the lower wafer LW. Alignment mark AM_C is located at the center of the wafer. Alignment marks AM_L and AM_R are located on one side and the other side of the outer periphery of the wafer WF, respectively. The bonding apparatus can calculate alignment correction values ​​for the shift and rotation components based on the measurement results of the alignment marks AM_C, AM_L, and AM_R on the upper wafer UW and the lower wafer LW, respectively. Furthermore, the bonding apparatus can also be configured to measure multiple alignment marks AM and calculate the wafer magnification components, similar to an exposure apparatus.

[0065] Figure 3 This table illustrates an example of the correction performance of exposure and bonding apparatuses for overlapping components within the wafer surface that may remain due to bonding alignment control. For example... Figure 3 As shown, the XY difference of the wafer magnification component can be corrected in the exposure apparatus, but it is difficult to correct in the bonding apparatus.

[0066] <1> First Implementation Method

[0067] The first embodiment relates to a bonding apparatus, a bonding method, and a method for manufacturing a semiconductor device that can improve the XY difference of the wafer ratio component between the upper wafer UW and the lower wafer LW during the bonding process.

[0068] <1-1> Composition

[0069] The configuration of the semiconductor manufacturing system PS according to the first embodiment will be described below.

[0070] <1-1-1> Composition of a Semiconductor Manufacturing System (PS)

[0071] Figure 4 This is a block diagram illustrating an example of the configuration of the semiconductor manufacturing system PS according to the first embodiment. For example... Figure 4 As shown, a semiconductor manufacturing system PS includes, for example, an exposure apparatus 1, a bonding apparatus 2, and a server 3. The exposure apparatus 1, bonding apparatus 2, and server 3 are configured to communicate via a network NW. The network NW can utilize wired or wireless communication. The bonding apparatus 2 uses the upper wafer UW and lower wafer LW, which were used in the previous process of the exposure apparatus 1, to perform bonding processing, creating a bonded wafer BW. The server 3 is, for example, a computer that controls the entire manufacturing process of the semiconductor device. The server 3 manages batch processing steps, correction values ​​used in each manufacturing step, etc. Furthermore, the semiconductor manufacturing system PS may also include a coincidence measurement device, etc.

[0072] <1-1-2> Composition of Exposure Device 1

[0073] Figure 5 This is a block diagram illustrating an example of the configuration of the exposure apparatus 1 included in the semiconductor manufacturing system PS according to the first embodiment. For example... Figure 5 As shown, the exposure apparatus 1 includes, for example, a control device 10, a storage device 11, a transport device 12, an exposure unit 13, and a communication device 14.

[0074] The control device 10 is a computer or similar device that controls the overall operation of the exposure apparatus 1. The control device 10 controls the storage device 11, the transport device 12, the exposure unit 13, and the communication device 14. Although not shown in the figures, the control device 10 includes a CPU (Central Processing Unit), ROM (Read Only Memory), and RAM (Random Access Memory). The CPU is a processor that executes various programs related to the control of the apparatus. ROM is a non-volatile storage medium that stores the control programs for the apparatus. RAM is a volatile storage medium that serves as the operating area for the CPU.

[0075] Storage device 11 is a storage medium used to store data, programs, etc. Storage device 11 stores, for example, exposure process 110 and correction value information 111. Exposure process 110 is a table recording the settings for exposure processing. Exposure process 110 includes information such as the shape and layout of the image, exposure amount, focus setting, and alignment setting. Exposure process 110 can be prepared for each processing step and batch. Correction value information 111 is a log recording the alignment correction values ​​(i.e., alignment results) used during exposure processing.

[0076] The transport device 12 is an apparatus equipped with a transport arm capable of transporting wafers, a transport device for temporarily holding multiple wafers, and the like. For example, the transport device 12 transports wafers (WF) received from an external coating and developing apparatus to the exposure unit 13. Additionally, after exposure processing, the transport device 12 transports wafers (WF) received from the exposure unit 13 to the outside of the exposure apparatus 1. Furthermore, the "coating and developing apparatus" is an apparatus that performs pre-processing and post-processing of the exposure process. Pre-processing of the exposure process includes coating the wafer with a resist material (photosensitive material). Post-processing of the exposure process includes developing the pattern exposed on the wafer. Multiple semiconductor manufacturing apparatuses can be used as the apparatuses used in the pre-processing and post-processing of the exposure process.

[0077] Exposure unit 13 is a collection of components used in the exposure process. Exposure unit 13 includes, for example, a wafer stage 130, an intermediate mask stage 131, a light source 132, a projection optics system 133, and a camera 134. Wafer stage 130 functions to hold the wafer facet (WF). Intermediate mask stage 131 functions to hold the intermediate mask 135 (mask). The respective stage positions of wafer stage 130 and intermediate mask stage 131 can be controlled based on the control of control device 10. Light source 132 illuminates the intermediate mask 135 with generated light. Projection optics system 133 focuses the light transmitted through intermediate mask 135 onto the surface of the wafer facet (WF). Camera 134 is an imaging mechanism for measuring alignment marks (AM).

[0078] The communication device 14 is a communication interface that can connect to a network. The exposure device 1 can operate based on the operation of a terminal on the network, or it can have a server on the network store the exposure process 110 and correction value information 111.

[0079] <1-1-3> Composition of the coupling device 2

[0080] Figure 6 This is a block diagram illustrating an example of the configuration of the bonding device 2 included in the semiconductor manufacturing system PS according to the first embodiment. For example... Figure 6 As shown, the joining device 2 includes, for example, a control device 20, a storage device 21, a conveying device 22, a joining unit 23, and a communication device 24.

[0081] The control device 20 is a computer or similar device that controls the overall operation of the coupling unit 2. The control device 20 controls the storage device 21, the transport device 22, the coupling unit 23, and the communication device 24. Although not shown in the figure, the control device 20 includes a CPU, ROM, RAM, etc. The control device 20 may also be referred to as a processor.

[0082] Storage device 21 is a storage medium used to store data, programs, etc. Storage device 21 stores, for example, relation 211. Relation 211 is a mathematical expression used to correct the XY difference of the wafer scaling component between the lower wafer LW and the upper wafer UW during the bonding process of the lower wafer LW and the upper wafer UW. Details of relation 211 will be described later.

[0083] The transport device 22 is a device equipped with a transport arm capable of transporting wafers, a transfer device for temporarily holding multiple wafers, and the like. For example, the transport device 22 transports the upper wafer UW and the lower wafer LW received from the pre-processing unit of the bonding process to the bonding unit 23. Furthermore, after the bonding process, the transport device 22 transports the bonding wafer BW received from the bonding unit 23 to the outside of the bonding device 2. The transport device 22 may also have a mechanism for reversing the wafer's orientation.

[0084] The bonding unit 23 is a collection of components used in the bonding process. The bonding unit 23 includes, for example, a lower stage 230, a stress device 231, a camera 232, an upper stage 233, a pressing pin 234, and a camera 235. The lower stage 230 is, for example, a wafer stage that functions as a wafer chuck to hold the lower wafer (LW) by vacuum suction. The stress device 231 applies stress to the lower stage 230, deforming the lower wafer (LW) via the lower stage 230. The scaling of the lower wafer (LW) held on the lower stage 230 changes depending on the amount of deformation of the lower stage 230 caused by the stress device 231. The camera 232 is disposed on the lower stage 230 side and is an imaging mechanism for measuring the alignment mark AM of the upper wafer (UW). The upper stage 233 is, for example, a wafer stage that functions as a wafer chuck to hold the upper wafer (UW) by vacuum suction. The pressing pin 234 is driven vertically under the control of the control device 20 and is capable of pressing the pin held at the center of the upper wafer UW on the upper stage 233. The camera 235, located on the upper stage 233 side, is a photographing mechanism for measuring the alignment mark AM of the lower wafer LW. The bonding device 2 may also include a vacuum pump used in the vacuum adsorption of the lower stage 230 and the upper stage 233.

[0085] The lower stage 230 and upper stage 233 are configured to allow the lower wafer LW held on the lower stage 230 and the upper wafer UW held on the upper stage 233 to be positioned opposite each other. During the bonding process, the upper surface of the upper wafer UW is its back surface and is held on the upper stage 233 of the bonding apparatus 2. During the bonding process, the lower surface of the upper wafer UW is its surface surface and corresponds to the bonding surface. The upper surface of the lower wafer LW is its surface surface and corresponds to the bonding surface. The lower surface of the lower wafer LW is its back surface and is held on the lower stage 230 of the bonding apparatus 2. By adjusting the relative positions of the lower stage 230 and the upper stage 233, the bonding apparatus 2 can adjust the displacement and rotation components of the overlap offset. Furthermore, by using the stress device 231 to deform the lower stage 230, the bonding device 2 can adjust the shared XY wafer scaling component of the lower wafer LW held by the deformed lower stage 230. Moreover, by adjusting the temperature of the lower stage 230, the bonding device 2 can adjust the XY difference of the wafer scaling component of the lower wafer LW.

[0086] The communication device 24 is a communication interface that can connect to the network NW. The coupling device 2 can operate based on the control of the terminal on the network NW, or the operation log can be stored on the server 3 on the network NW, and the alignment correction value can be calculated based on the information stored on the server 3.

[0087] Furthermore, the aforementioned "pre-treatment apparatus for bonding" is an apparatus that modifies and hydrophilizes the bonding surfaces of the upper wafer UW and the lower wafer LW in a manner suitable for bonding before the bonding process of the bonding apparatus 2. In short, the pre-treatment apparatus first performs plasma treatment on the surfaces of the upper wafer UW and the lower wafer LW to modify their surfaces. During plasma treatment, oxygen ions or nitrogen ions are generated based on oxygen or nitrogen as the treatment gas under a specified reduced pressure atmosphere, and the generated oxygen ions or nitrogen ions are irradiated onto the bonding surfaces of each wafer. Afterward, the pre-treatment apparatus supplies pure water to the surfaces of the upper wafer UW and the lower wafer LW. Then, hydroxyl groups are attached to the surfaces of the upper wafer UW and the lower wafer LW to hydrophilize them. In the bonding process, the upper wafer UW and the lower wafer LW, having undergone this surface modification and hydrophilization, are used. The bonding apparatus 2 can also be combined with the pre-treatment apparatus to form a bonding system.

[0088] (Outline of the construction of the lower worktable 230)

[0089] Figure 7 This is a schematic diagram illustrating an example of the configuration of the lower worktable 230 included in the coupling device 2 of the first embodiment. Figure 7 (A) indicates the planar layout of the lower worktable 230 in the first embodiment. Figure 7 (B) indicates the cross-sectional structure of the lower worktable 230 in the first embodiment. For example... Figure 7 As shown, the lower worktable 230 has a main body 40, ribs 41, multiple worktable pins 42, multiple suction ports 43, and a heater 44.

[0090] The diameter of the main body 40 is at least larger than the lower wafer LW when viewed from above. Ribs 41 and a plurality of stage pins 42 are provided on the upper surface of the main body 40. The upper surface of the main body 40 corresponds to the adsorption surface of the wafer chuck. The heights of the ribs 41 and the plurality of stage pins 42 are approximately equal. In other words, the positions (heights) of the upper surfaces of the ribs 41 and the plurality of stage pins 42 are consistent. The ribs 41 are arranged in a ring shape and are disposed on the outer periphery of the wafer chuck portion of the lower stage 230. The plurality of stage pins 42 are disposed separately from each other on the inner side of the ribs 41 when viewed from above.

[0091] Multiple suction ports 43 are arranged separately on the inner side of ribs 41 when viewed from above. Each suction port 43 is connected to a vacuum pump (not shown). When a wafer WF is placed on the lower worktable 230, the vacuum pump can depressurize the space surrounded by the upper surface of the main body 40, ribs 41, and wafer WF via the multiple suction ports 43. When the space surrounded by the upper surface of the main body 40, ribs 41, and wafer WF is depressurized, the lower wafer LW is attracted and held on the lower worktable 230 side in accordance with the external atmosphere, such as atmospheric pressure. When the lower wafer LW is attracted, ribs 41 support the outer periphery of the lower surface of the lower wafer LW, and multiple worktable pins 42 support a portion of the lower surface of the lower wafer LW respectively. By using multiple worktable pins 42 to support the lower surface of the lower wafer LW, the lower wafer LW can be kept in a flat shape, and deformation (warping) in the Z direction of the lower wafer LW can be suppressed.

[0092] The heater 44 has the function of heating the main body 40 under the control of the control device 20. The heater 44 is preferably configured to heat each stage pin 42 disposed on the upper surface of the main body 40 substantially evenly within the main body 40. The heater 44 may also be arranged in a segmented configuration within the main body 40. When the main body 40 is heated by the heater 44, the heat from the main body 40 moves via the multiple stage pins 42 towards the lower wafer LW to which it is attached.

[0093] Furthermore, the shape of the lower worktable 230 can deform according to the temperature of the lower worktable 230 and the stress applied by the stress device 231. In this case, the lower wafer LW adsorbed by the lower worktable 230 deforms accordingly with the deformation of the lower worktable 230. In addition, the lower worktable 230 supports the lower wafer LW using worktable pins 42, thereby suppressing the influence of particles remaining on the lower surface of the lower wafer LW on the flatness of the adsorbed lower wafer LW. Moreover, by using worktable pins 42, the contact area between the lower worktable 230 and the lower wafer LW is reduced, so when the lower worktable 230 releases the adsorption of the lower wafer LW, the lower wafer LW is easily peeled off from the lower worktable 230.

[0094] In the bonding apparatus 2 of the first embodiment, the lower worktable 230 is further configured such that, by utilizing the arrangement and shape of the plurality of worktable pins 42 and the shape of the main body 40, the heat transfer mode to the adsorbed lower wafer LW is uneven within the wafer surface. Hereinafter, first to third configuration examples of the lower worktable 230 in the bonding apparatus 2 of the first embodiment will be described. Furthermore, in the accompanying drawings of the lower worktable 230 used in the description of the first to third configuration examples, illustrations of the suction port 43 and the heater 44 are omitted, and the characteristic parts are emphasized.

[0095] (First example of composition)

[0096] Figure 8 This is a top view showing an example of the planar layout of the lower worktable 230 in a first configuration example of the joining device 2 of the first embodiment. (See attached image.) Figure 8 As shown, in the lower worktable 230 of the first configuration example, the density of the number of worktable pins 42 is set to vary in one direction. For example, the density of the multiple worktable pins 42 decreases in the X direction as they move from the center of the lower worktable 230 (main body 40) towards the outer periphery. On the other hand, the multiple worktable pins 42 are arranged, for example, at equal intervals in the Y direction. Furthermore, in Figure 8 The example shown illustrates a grid-like arrangement of multiple worktable pins 42, but the multiple worktable pins 42 may not be arranged in a grid-like manner. In the first configuration example, the width and size of each of the multiple worktable pins 42 are approximately equal.

[0097] Figure 9 This is an example of the cross-sectional structure along the X direction of the lower worktable 230 in the first configuration example of the joining device 2 of the first embodiment. Figure 8 A cross-sectional view along line IX-IX. In the first configuration example, the spacing between the plurality of table pins 42 arranged in the X direction is, for example, in the range of 2000 to 20000 μm. Specifically, as... Figure 9As shown, at the center of the lower worktable 230, the distance D1 between two adjacent worktable pins 42 in the X direction is, for example, 2000 μm. At the outer periphery of the lower worktable 230, the distance D2 between two adjacent worktable pins 42 in the X direction is, for example, 20000 μm.

[0098] Figure 10 This is an example of the cross-sectional structure along the Y direction of the lower worktable 230 in the first configuration example of the joining device 2 of the first embodiment. Figure 8 A cross-sectional view along the XX line. In the first configuration example, the spacing between the plurality of worktable pins 42 arranged in the Y direction is, for example, a fixed value. Specifically, as... Figure 10 As shown, the distance D3 between two adjacent worktable pins 42 in the Y direction at the center of the lower worktable 230 is approximately equal to the distance D4 between two adjacent worktable pins 42 in the Y direction at the outer periphery of the lower worktable 230. The distances D3 and D4 are, for example, 10000 μm. Therefore, the distance between the worktable pins 42 is in the relationship D2 > D3 = D4 > D1.

[0099] Furthermore, in the first embodiment, the lower stage 230 can be designed such that the ratio of the area of ​​the portion where the lower wafer LW contacts the stage pin 42 decreases in the X direction from the center of the lower stage 230 towards the outer periphery. More preferably, in the lower stage 230 of the first embodiment, the ratio of the area of ​​the portion where the lower wafer LW contacts the stage pin 42 is in the range of 1% to 25%. For example, the ratio of the area of ​​the upper surface of the stage pin 42 at the center of the lower stage 230 (i.e., the portion where the stage pin 42 contacts the lower wafer LW) is 25%, and the ratio of the area of ​​the upper surface of the stage pin 42 at the outer periphery of the lower stage 230 is 1%. In other words, in the lower stage 230 of the first embodiment, the ratio of the area of ​​the lower wafer LW when it is held in place is 1 cm. 2 The contact area between the lower wafer LW and the stage pin 42 within the region is 0.25 cm² at the center. 2 (That is, the contact ratio = 25%), with a contact rate of 0.01 cm on the outer periphery. 2 (That is, the contact ratio = 1%).

[0100] (Second example of composition)

[0101] Figure 11 This is a top view showing an example of the planar layout of the lower worktable 230a in a second configuration example of the joining device 2 of the first embodiment. (See attached image.) Figure 11As shown, in the lower stage 230a of the second configuration example, the dimensions of the plurality of stage pins 42 are configured to vary in one direction. Here, the "dimensionality of the stage pin 42" corresponds to the area of ​​the upper surface of the stage pin 42, that is, the area of ​​the contact portion between the stage pin 42 and the lower wafer LW when the lower wafer LW is adsorbed onto the lower stage 230a.

[0102] For example, the size of each worktable pin 42 included in the plurality of worktable pins 42 arranged in the X direction decreases from the center of the lower worktable 230a (main body 40) toward the outer periphery. On the other hand, the size of each worktable pin 42 included in the plurality of worktable pins 42 arranged in the Y direction is, for example, approximately the same. Specifically, the diameter R1 of each worktable pin 42 in the X direction decreases from the center of the lower worktable 230a toward the outer periphery, and the diameter R2 of each worktable pin 42 in the Y direction is approximately the same. Here, "approximately the same" includes, for example, an error of a few μm. Furthermore, in Figure 11 The example shown illustrates a grid-like arrangement of multiple worktable pins 42, but the multiple worktable pins 42 may also be arranged in a less strict grid pattern. The diameter of the worktable pins 42 may decrease from the center of the lower worktable 230a towards the outer periphery, or there may be a case where worktable pins 42 of approximately the same diameter are arranged continuously.

[0103] Figure 12 This is an example of the cross-sectional structure along the X direction of the lower worktable 230a in the second configuration example of the joining device 2 of the first embodiment. Figure 11 A cross-sectional view along line XII-XII. (See example...) Figure 12 As shown, in the second configuration example, the diameter R1e of the worktable pin 42 arranged in the X direction on the outer periphery of the lower worktable 230a is smaller than the diameter R1c of the worktable pin 42 arranged in the center of the lower worktable 230a. In the lower worktable 230a, the diameter R1 of the plurality of worktable pins 42 in the X direction is, for example, in the range of 100 to 1000 μm. Specifically, the diameter R1c of the worktable pin 42 in the X direction at the center is, for example, 1000 μm. The diameter R1e of the worktable pin 42 on the outer periphery is, for example, 100 μm.

[0104] Figure 13 This is an example of the cross-sectional structure along the Y direction of the lower worktable 230a in the second configuration example of the joining device 2 of the first embodiment. Figure 11A cross-sectional view along line XIII-XIII. In the second configuration example, the diameter R2e in the X direction of the worktable pin 42 located on the outer periphery of the lower worktable 230a is approximately the same as the diameter R2c in the X direction of the worktable pin 42 located at the center of the lower worktable 230a. In the lower worktable 230a, the diameter R2 in the Y direction of the plurality of worktable pins 42 is, for example, in the range of 100 to 1000 μm. Specifically, the diameter R2c in the Y direction of the worktable pin 42 at the center of the lower worktable 230a and the diameter R2e in the Y direction of the worktable pin 42 on the outer periphery are, for example, 500 μm. Therefore, the diameters of the worktable pins 42 are in the relationship R1c > R2c = R2e > R1e.

[0105] Furthermore, the size of the worktable pin 42 in the second configuration example can also be adjusted by changing the diameter R2 in the Y direction. The lower worktable 230a in the second configuration example is designed such that the ratio of the area of ​​the lower wafer LW in contact with the worktable pin 42 decreases in the X direction from the center to the outer periphery of the lower worktable 230a. In the lower worktable 230a of the second configuration example, the ratio of the diameter R1 in the X direction to the diameter R2 in the Y direction is more preferably in the range of 0.3 to 3.0. Furthermore, in the lower worktable 230a of the second configuration example, it is more preferable that the ratio of the area of ​​the lower wafer LW in contact with the worktable pin 42 is in the range of 1% to 25%. In this case, the ratio of the area of ​​the upper surface of the worktable pin 42 at the center of the lower worktable 230a (i.e., the area where the worktable pin 42 contacts the lower wafer LW) is 25%, and the ratio of the area of ​​the upper surface of the worktable pin 42 at the outer periphery of the lower worktable 230a is 1%. In other words, in the lower stage 230a of the second configuration example, the 1cm section when the lower wafer LW is adsorbed... 2 The contact area between the lower wafer LW and the stage pin 42 within the region is 0.25 cm² at the center. 2 (That is, the contact ratio = 25%), with a contact rate of 0.01 cm on the outer periphery. 2 (That is, the contact ratio = 1%).

[0106] (Third example)

[0107] Figure 14 This is a top view showing an example of the planar layout of the lower worktable 230b in a third configuration example of the joining device 2 of the first embodiment. (See attached image.) Figure 14 As shown, in the lower worktable 230b of the third configuration example, the worktable pins 42 of the same size are arranged in a grid pattern. Furthermore, in Figure 14 The example shown illustrates a grid-like arrangement of multiple worktable pins 42, but the multiple worktable pins 42 can also be arranged in a less strict grid-like manner.

[0108] Figure 15 This is an example of the cross-sectional structure along the X direction of the lower worktable 230b in the third configuration example of the joining device 2 of the first embodiment. Figure 14 A cross-sectional view of the XV-XV line. (See example...) Figure 15 As shown, in the lower worktable 230b of the third configuration example, the heights of the plurality of worktable pins 42 are arranged in a manner that varies in the X direction. Here, the "height of the worktable pin 42" corresponds to the length along the Z direction between the bottom and the upper surface of the worktable pin 42.

[0109] For example, the height of each of the plurality of worktable pins 42 arranged in the X direction increases from the center of the lower worktable 230b (main body 40) towards the outer periphery. In this example, among the plurality of worktable pins 42 arranged in the X direction, the height HPc of the worktable pin 42 at the center of the lower worktable 230b is lower than the height HPe of the worktable pins 42 at the outer periphery of the lower worktable 230b. In the lower worktable 230b, the height HP of the plurality of worktable pins 42 is, for example, in the range of 100 to 2000 μm. Specifically, the height HPc of the worktable pin 42 at the center is, for example, 100 μm. The height HPe of the worktable pins 42 at the outer periphery is, for example, 2000 μm.

[0110] The lower worktable 230b in the third configuration example can also be represented by the thickness of the main body 40. In this case, the thickness of the main body 40 of the lower worktable 230b decreases from the center to the outer periphery in a cross-section along the X direction. That is, the thickness HBc of the center of the lower worktable 230b is thicker than the thickness HBe of the outer periphery of the lower worktable 230b. In addition, the case where the height of the worktable pins 42 increases from the center to the outer periphery of the lower worktable 230b can also include the case where worktable pins 42 of approximately the same height are continuously arranged.

[0111] Figure 16 This is an example of the cross-sectional structure along the Y direction of the lower worktable 230b in the third configuration example of the joining device 2 of the first embodiment. Figure 14 A cross-sectional view along the XVI-XVI line. (See example...) Figure 16 As shown, in the lower worktable 230b of the third configuration example, a plurality of worktable pins 42 arranged along the Y direction are set at approximately the same height. For example, in a cross-section along the Y direction including the center portion of the lower worktable 230b, the height of the worktable pins 42 is HPc, and the thickness of the main body portion 40 of the lower worktable 230b is HBc.

[0112] Furthermore, the above description illustrates a case where the height of the worktable pins 42 arranged in the X direction is changed, but it is not limited to this. The lower worktable 230b of the third configuration example can also be configured such that the height of each worktable pin 42 included in the plurality of worktable pins 42 arranged in the Y direction increases from the center portion of the lower worktable 230b (main body portion 40) toward the outer periphery.

[0113] <1-1-4> Composition of Server 3

[0114] Figure 17 This is a block diagram illustrating an example of the configuration of the server 3 included in the semiconductor manufacturing system PS according to the first embodiment. For example... Figure 17 As shown, server 3 includes, for example, CPU 30, ROM 31, RAM 32, storage device 33, and communication device 34. CPU 30 is a processor that executes various programs related to the control of server 3. ROM 31 is a non-volatile storage device that stores the control programs of server 3. RAM 32 is a volatile storage device that serves as the operating area of ​​CPU 30. Storage device 33 is a non-volatile storage medium capable of storing information received from exposure device 1, bonding device 2, etc. Communication device 34 is a communication interface capable of connecting to network NW.

[0115] <1-2> Manufacturing Method

[0116] Hereinafter, an example of a specific process using an exposure apparatus 1, a bonding apparatus 2, and a server 3 will be described as a method for manufacturing a semiconductor device according to the first embodiment. That is, a semiconductor device can be manufactured using the bonding method (bonding process) of the first embodiment described below.

[0117] <1-2-1> Overview of the jointing process

[0118] Figure 18 This is a schematic diagram showing an outline of the joining process in the joining device 2 of the first embodiment. Figure 18 (1) to (8) respectively represent the states of the joining unit 23 in the joining process. In the following description, the alignment of the shift component is referred to as "shift alignment" and the alignment of the rotation component is referred to as "rotation alignment".

[0119] Figure 18 (1) indicates the state of the joining unit 23 before the joining process.

[0120] When the control device 20 begins the engagement process, such as Figure 18As shown in (2), the heater 44 is controlled based on the difference in the XY difference of the wafer magnification components of the upper wafer UW and the lower wafer LW, which are the objects of the bonding process, to adjust the temperature of the lower stage 230. The bonding device 2 can obtain information on the XY difference of the wafer magnification components from the server 3, or it can calculate it based on the alignment correction value obtained from the exposure device 1 or the server 3. Figure 18 After the processing of (2), the control device 20 can also control the stress device 231 based on the alignment correction value of the wafer magnification component shared in the X and Y directions, so as to deform the lower worktable 230.

[0121] Next, the control device 20 causes the conveyor 22 to convey the lower wafer LW to the lower worktable 230 and the upper wafer UW to the upper worktable 233. Then, as... Figure 18 As shown in (3), the control device 20 holds the lower wafer LW on the lower stage 230 and holds the upper wafer UW on the upper stage 233. In addition, the surfaces of the upper wafer UW and the lower wafer LW, which are transported to the bonding device 2, are modified and hydrophilized by the pretreatment device for bonding treatment.

[0122] Next, the control device 20 performs rotational alignment. Specifically, firstly, as... Figure 18 As shown in (4), the control device 20 controls the positions of the lower stage 230 and the upper stage 233, aligning the optical axis of the camera 232 on the lower stage 230 with the alignment mark AM_L on the upper wafer UW, and aligning the optical axis of the camera 235 on the upper stage 233 with the alignment mark AM_L on the lower wafer LW. Then, the control device 20 uses the camera 232 to measure the alignment mark AM_L on the upper wafer UW and uses the camera 235 to measure the alignment mark AM_L on the lower wafer LW.

[0123] Next, as Figure 18 As shown in (5), the control device 20 controls the positions of the lower stage 230 and the upper stage 233, aligning the optical axis of the camera 232 on the lower stage 230 with the alignment mark AM_R on the upper wafer UW, and aligning the optical axis of the camera 235 on the upper stage 233 with the alignment mark AM_R on the lower wafer LW. Then, the control device 20 uses the camera 232 to measure the alignment mark AM_R on the upper wafer UW and the camera 235 to measure the alignment mark AM_R on the lower wafer LW. Then, the control device 20, based on the... Figure 18 The processing of (4) and (5) yields the measurement results of the alignment marks AM_L and AM_R of cameras 232 and 235, and the correction amount of the coincidence offset of the rotation component is calculated.

[0124] Next, the control device 20 performs camera origin alignment. Specifically, as... Figure 18As shown in (6), the control device 20 controls the positions of the lower worktable 230 and the upper worktable 233, and inserts a common target TG between the optical axis of the camera 232 on the lower worktable 230 and the optical axis of the camera 235 on the upper worktable 233. Then, the control device 20 adjusts the origin of each of the cameras 232 and 235 based on the measurement results of the common target TG by each of the cameras 232 and 235.

[0125] Next, the control device 20 performs the shift alignment. Specifically, firstly, as... Figure 18 As shown in (7), the control device 20 controls the positions of the lower stage 230 and the upper stage 233, aligning the optical axis of the camera 232 on the lower stage 230 with the alignment mark AM_C on the upper wafer UW, and aligning the optical axis of the camera 235 on the upper stage 233 with the alignment mark AM_C on the lower wafer LW. Then, the control device 20 uses the camera 232 to measure the alignment mark AM_C on the upper wafer UW and the camera 235 to measure the alignment mark AM_C on the lower wafer LW. Finally, the control device 20 calculates the alignment correction value for the shift component based on the measurement results of the alignment marks AM_C on the lower wafer LW and the upper wafer UW respectively.

[0126] Next, as Figure 18 As shown in (8), the control device 20 executes the joining sequence. Specifically, firstly, the control device 20 performs horizontal alignment based on the alignment correction values ​​calculated by rotational alignment and shift alignment, and the correction results of the camera origin, adjusting the relative positions of the lower stage 230 and the upper stage 233. Then, the control device 20 brings the position of the upper stage 233 closer to the lower stage 230 and adjusts the spacing between the upper wafer UW and the lower wafer LW. Then, the control device 20 presses the center of the upper wafer UW by lowering the pressing pin 234, bringing the surface of the upper wafer UW into contact with the surface of the lower wafer LW.

[0127] Subsequently, the control device 20 releases the upper stage 233 from holding the upper wafer UW (vacuum adsorption) from the inside out. The upper wafer UW then falls onto the lower wafer LW, and the surfaces of the upper wafer UW and lower wafer LW are bonded. Specifically, van der Waals forces (intermolecular forces) are generated between the bonding surfaces of the modified upper wafer UW and the modified lower wafer LW, bonding the contact portions of the upper wafer UW and lower wafer LW. Furthermore, since the bonding surfaces of the upper wafer UW and lower wafer LW are hydrophilized, hydrogen bonds (intermolecular forces) are formed between the hydrophilic groups at the contact portions of the upper wafer UW and lower wafer LW, resulting in a more robust bond between the contact portions of the upper wafer UW and lower wafer LW.

[0128] (Temperature variation of the lower wafer LW)

[0129] The following describes the temperature variation of the lower wafer LW held on the lower stage 230.

[0130] Figure 19 This is a schematic diagram illustrating the heat transfer method to the lower wafer LW held on the lower stage 230 of the bonding device 2 in the first embodiment. (See diagram below.) Figure 19 As shown, the air temperature within the bonding unit 23 corresponds to room temperature (RT). The initial temperature of the lower wafer LW is, for example, room temperature. When the lower wafer LW is held on the lower stage 230, the space enclosed by the bottom surface of the lower wafer LW, the plurality of stage pins 42, and the main body 40 becomes a vacuum. When the main body 40 is heated by the heater 44, the heat of the main body 40 is transferred to the bottom of the lower wafer LW via the plurality of stage pins 42. On the other hand, since the parts of the lower wafer LW not held by the stage pins 42 are a vacuum, no heat is transferred to the main body 40.

[0131] The lower stage 230 in the first embodiment and the lower stage 230a in the second embodiment can change the thermal conductivity from the lower stage 230 to the lower wafer LW within the wafer surface based on the ratio of the area of ​​the contact portion between the lower wafer LW and the stage pin 42. The lower stage 230b in the third embodiment can change the thermal conductivity from the lower stage 230b to the lower wafer LW within the wafer surface based on the length of the stage pin 42 it passes through. The effects obtained in the first to third embodiments of the lower stage 230 are all the same. Hereinafter, the use of... Figure 8 The case of the lower worktable 230 in the first configuration example shown will be explained.

[0132] Figure 20 and Figure 21 These are graphs showing the temperature changes of the lower wafer LW on the lower stage 230 of the bonding device 2 in the first embodiment, respectively. Figure 20 and Figure 21 The horizontal axis of the graph represents time, and the vertical axis represents the temperatures of the center CP and the outer periphery EP of the lower wafer LW. The temperature of the lower stage 230 differs between the first and second examples. Specifically, the lower stage 230 in the second example is adjusted to a higher temperature than that in the first example. When the lower wafer LW is held on the lower stage 230, heat is transferred from the main body 40 of the lower stage 230 to the lower wafer LW via multiple stage pins 42, causing the temperature of the lower wafer LW to rise from room temperature RT.

[0133] like Figure 20As shown, in the first example, at time t1, the temperature of the central portion CP of the lower wafer LW rises to TCP1, and the temperature of the outer periphery EP of the lower wafer LW rises to TEP1. Afterward, the temperatures of the central portion CP and the outer periphery EP of the lower wafer LW reach equilibrium based on the heat transferred via the multiple stage pins 42 and the room temperature of the bonding unit 23. At this time, since the thermal conductivity of the central portion CP is higher than that of the outer periphery EP, temperature TCP1 is higher than temperature TEP1.

[0134] On the other hand, such as Figure 21 As shown, in the second example, at time t2, the temperature of the central portion CP of the lower wafer LW rises to TCP2, and the temperature of the outer periphery EP of the lower wafer LW rises to TEP2. Afterward, the temperatures of the central portion CP and the outer periphery EP of the lower wafer LW reach equilibrium based on the heat transferred via the multiple stage pins 42 and the room temperature of the bonding unit 23. At this time, since the thermal conductivity of the central portion CP is higher than that of the outer periphery EP, temperature TCP2 is higher than temperature TEP2.

[0135] Preferably, the bonding of the lower wafer LW and the upper wafer UW is performed after the temperature of the lower wafer LW has reached equilibrium. Because the temperature of the lower stage 230 in the second example is higher than that in the first example, the temperature difference between the center portion CP and the outer periphery EP after reaching equilibrium is greater in the second example than in the first example. Thus, the bonding apparatus 2 of the first embodiment can adjust the temperature difference within the wafer surface in the X direction of the lower wafer LW by adjusting the temperature of the lower stage 230. As a result, the XY difference of the wafer scaling component of the lower wafer LW can be adjusted based on the temperature difference within the wafer surface and the thermal expansion coefficient of the lower wafer LW. On the other hand, by adjusting the temperature of the lower stage 230, the lower wafer LW is heated in the Y direction, and the temperature difference within the wafer surface is suppressed. Therefore, changes in the wafer scaling component in the Y direction can be suppressed. Therefore, the bonding apparatus 2 can adjust the XY difference of the wafer scaling component by adjusting the temperature of the lower stage 230. Furthermore, the timing for achieving a temperature equilibrium for the lower wafer LW through temperature adjustment of the lower stage 230 may differ between the central portion CP and the outer periphery EP. For example, when the lower wafer LW is placed on the lower stage 230 in the first to third embodiments and heat is transferred to the lower wafer LW via multiple stage pins 42, along the Y direction, the temperature of the central portion CP of the lower wafer LW in the X direction becomes higher, while the temperature of the outer periphery EP of the lower wafer LW in the X direction becomes lower. For example, the semiconductor substrate (wafer) expands as the temperature rises, therefore the lower wafer LW placed on the lower stage 230 in the first to third embodiments expands more in the Y direction than in the X direction. Furthermore, if it is desired that the lower wafer LW expands more in the X direction than in the Y direction, for example, the lower wafer LW can be placed on the lower stage 230 with the lower wafer LW rotated 90 degrees.

[0136] (The effect of thermal expansion of the lower worktable 230)

[0137] Figure 22 This is a diagram illustrating the effect of thermal expansion on the lower worktable 230 in the joining device 2 of the first embodiment. Figure 22 (A) and (B) represent the positions of the lower worktable 230 when measuring the alignment mark AM_L located on the outer periphery and the alignment mark AM_C located in the center, respectively, and represent the side and upper surfaces of the lower worktable 230. Additionally, in Figure 22 Part of the configuration for position control of the lower worktable 230 is also shown in (A) and (B).

[0138] The joining unit 23 further includes, for example, movable mirrors 236 and 237 and interferometers 238 and 239. Movable mirrors 236 and 237 are respectively disposed on the lower worktable 230 in a manner capable of reflecting light incident from the X and Y directions. Interferometers 238 and 239 calculate the movement distance of the worktable based on the wave difference between the fixed beam and the movable beam. Specifically, interferometer 238 uses the reflected light from movable mirror 236 to calculate the movement distance of the lower worktable 230 in the X direction. Interferometer 239 uses the reflected light from movable mirror 237 to calculate the movement distance of the lower worktable 230 in the Y direction. Thus, the control device 20 can control the position of the lower worktable 230 based on the measurement results of interferometers 238 and 239.

[0139] When using heater 44 (refer to) Figure 7 When the lower worktable 230 is heated, the lower worktable 230 undergoes thermal expansion. Figure 22 Only the thermal expansion of the lower worktable 230 in the Y direction is shown. Furthermore, the thermal expansion of the lower worktable 230 occurs in both the X and Y directions, but... Figure 22 Only thermal expansion in the Y direction is shown. The heater 44 is configured to provide approximately uniform temperature control over the entire lower stage 230. Therefore, the amount of thermal expansion in the Y direction of the lower stage 230 due to temperature changes is approximately equal at the center and end sides of the lower stage 230 in the X direction. Thus, in the bonding apparatus of the first embodiment, when using the interferometer 239 as a reference during alignment measurement of the lower wafer LW, the difference in wafer position measurement results in the Y direction can be suppressed between measuring the alignment mark AM_C at the center and measuring the alignment mark AM_L at the end side.

[0140] <1-2-2> Learning Methods

[0141] Figure 23This is a flowchart illustrating an example of a method for learning wafer rate correction values ​​in a semiconductor manufacturing system PS according to the first embodiment. The wafer rate correction value refers to the correction value for the wafer rate component, which will be described later. Hereinafter, refer to... Figure 23 As a learning method for wafer ratio correction values, an example of the order of generating relation 211 is explained.

[0142] First, multiple upper wafers (UW) with approximately the same XY difference in the wafer magnification components at the bonding surface are prepared (step S101), and multiple lower wafers (LW) with approximately the same XY difference in the wafer magnification components at the bonding surface are prepared (step S102). In this specification, "wafer magnification components at the bonding surface" are, for example, based on the alignment results measured by the exposure apparatus 1 in the last photolithography process performed in the preceding process. The "wafer magnification components at the bonding surface" can be used for adjusting the overlap of the upper wafers (UW) and lower wafers (LW) during the bonding process, or the values ​​of the wafer magnification components measured in other processes can be used. The prepared multiple upper wafers (UW) and multiple lower wafers (LW) are transported to the bonding apparatus 2 of the first embodiment. The bonding apparatus 2 has a lower stage 230 in any of the first to third configuration examples.

[0143] Next, the bonding process of the prepared lower wafer (LW) and upper wafer (UW) is performed (step S103). In step S103, the temperature of the lower stage 230 is adjusted to a predetermined temperature, which is the temperature of the learning object, and at least one set of lower wafers (LW) and upper wafers (UW) are bonded. The predetermined temperature may be, for example, the temperature of the heater 44. When the bonding process of at least one set of lower wafers (LW) and upper wafers (UW) using the predetermined temperature is completed, the bonding device 2 confirms whether the bonding process at all temperatures of the learning object is completed (step S104).

[0144] If the bonding process is not completed at all temperatures of the learning object (step S104: No), the bonding device 2 changes the temperature (step S105) and proceeds to step S103. That is, the bonding device 2 performs at least one set of bonding processes for the lower wafer (LW) and the upper wafer (UW) using a different temperature than before. If the bonding process is completed at all temperatures of the learning object (step S104: Yes), the semiconductor manufacturing system PS proceeds to step S106.

[0145] In step S106, the overlap of multiple bonding wafers (BWs) produced in step S103 is measured using an overlap inspection device. The overlap measurement results are transmitted to server 3, for example. Then, server 3 calculates the difference in XY difference of the wafer scaling components of the lower wafer (LW) and upper wafer (UW) at the multiple temperatures used (let's call it the XY difference of the wafer scaling components of the bonding wafers BW) based on the overlap measurement results of the multiple bonding wafers BW (step S107). Then, server 3 generates a relationship 211 between the XY difference of the wafer scaling components of the bonding wafers BW and the temperature of the lower stage 230 (step S108). The temperature of the lower stage 230 in step S108 can also be the temperature of heater 44. Afterwards, server 3 transmits the generated relationship 211 to bonding device 2, and bonding device 2 saves the relationship 211 transmitted from server 3 to storage device 21. Furthermore, the processes in steps S107 and S108 can also be performed by bonding device 2.

[0146] Figure 24 This is a graph representing an example of the learning result of the wafer ratio correction value in the semiconductor manufacturing system PS of the first embodiment. Figure 24 The horizontal axis of the graph shows the XY difference of the wafer scaling component of the bonded wafer BW, and the vertical axis shows the temperature of the lower stage 230. For example... Figure 24 As shown, the XY difference of the wafer scaling component of the bonded wafer BW and the temperature of the lower stage 230 can be represented, for example, by a linear function relationship 211. That is, the higher the temperature of the lower stage 230, the greater the XY difference of the wafer scaling component of the bonded wafer BW during the bonding process. By using relationship 211, which is a learning result of such wafer scaling correction value, the bonding apparatus 2 can select the temperature of the lower stage 230, where the XY difference of the wafer scaling component of the bonded wafer BW is close to zero, based on the wafer scaling information of the lower wafer LW and the upper wafer UW of the bonding object, for bonding alignment control measurement.

[0147] <1-2-3> Joining Method

[0148] Hereinafter, as a joining method using the joining device 2 of the first embodiment, an example of the joining process sequence utilizing relation 211 will be described.

[0149] (first example)

[0150] Figure 25 This is a flowchart illustrating a first example of the joining method of the joining device 2 according to the first embodiment. Hereinafter, refer to... Figure 25 An example of the order in which the bonding device 2 performs the bonding process using the calculation results of the XY difference of the wafer ratio component of the bonding wafer BW based on the server 3 is explained.

[0151] First, server 3 obtains the alignment result of the upper wafer UW (step S111). The alignment result of the upper wafer UW corresponds to the alignment measurement result in the exposure process, which serves as the reference for overlap adjustment during the bonding process. Alternatively, the overlap inspection result of the overlap inspection device may be used instead of the alignment result of the upper wafer UW.

[0152] Next, server 3 obtains the alignment result of the lower wafer (LW) (step S112). This alignment result of the lower wafer (LW) corresponds to the alignment measurement result in the exposure process, which serves as the reference for overlap adjustment during the bonding process. Alternatively, the overlap inspection result of the overlap inspection device can be used instead of the alignment result of the lower wafer (LW).

[0153] Next, server 3 calculates the XY difference of the wafer scaling components of the upper wafer UW and the lower wafer LW to be combined (step S113). Then, server 3 transmits the calculated XY difference of the wafer scaling components to bonding device 2 (step S114). Bonding device 2 saves the XY difference of the wafer scaling components transmitted from server 3 in, for example, storage device 21.

[0154] Next, the bonding device 2 calculates (or selects) the optimal temperature of the lower stage 230 based on relation 211 (step S115). The calculation of the optimal temperature of the lower stage 230 is performed, for example, according to each combination of the upper wafer UW and the lower wafer LW. Then, the bonding device 2 uses the calculated optimal temperature to perform the bonding process for the combination of the corresponding lower wafer LW and upper wafer UW (step S116).

[0155] (Second example)

[0156] Figure 26 This is a flowchart illustrating a second example of the joining method of the joining device according to the first embodiment. Hereinafter, refer to... Figure 26 An example of the sequence in which the bonding device 2 calculates the XY difference of the wafer ratio component and performs the bonding process will be described.

[0157] First, the bonding device 2 performs alignment measurements for the upper wafer UW and the lower wafer LW respectively (step S121). That is, in the second example, in Figure 18 Before processing (2), execute with Figure 18 The processing corresponding to (4) to (7) is then performed. Then, based on the alignment measurement results, the bonding device 2 calculates the XY difference of the wafer ratio components of the combined upper wafer UW and lower wafer LW (step S122). Then, similarly to the first example of the bonding method, the bonding device 2 calculates the optimal temperature of the lower stage 230 based on relation 211 (step S115), and uses the calculated optimal temperature to perform the bonding process for the combination of the corresponding lower wafer LW and upper wafer UW (step S116).

[0158] <1-3> Effects of the first implementation method

[0159] The semiconductor manufacturing system PS according to the first embodiment can improve the yield of semiconductor devices. The effects of the first embodiment will be described in detail below.

[0160] In semiconductor devices with a bonding structure, the difference in XY ratio of the wafer scaling components of the upper wafer UW and the lower wafer LW can be a major cause of deterioration in the bonding alignment control of the bonded wafer BW. In bonding apparatus 2, the wafer scaling components shared by the upper wafer UW and the lower wafer LW in the X and Y directions can be corrected, for example, by deforming the lower stage 230 using a stress device 231. On the other hand, the stress device 231 cannot correct the XY ratio difference of the wafer scaling components.

[0161] In contrast, in the lower stage 230 of the bonding device 2 in the first embodiment, the arrangement density, shape, or height of the plurality of stage pins 42 of the lower stage 230 is configured such that the thermal conductivity varies in the X and Y directions within the wafer plane. In other words, the plurality of stage pins 42 arranged along one direction (e.g., the X direction) are configured such that at least one of their area and length differs between the central portion and the outer periphery of the lower stage 230.

[0162] Therefore, the bonding apparatus 2 of the first embodiment can generate a desired temperature difference within the wafer surface of the lower wafer LW. Furthermore, the bonding apparatus 2 of the first embodiment can generate a temperature difference (thermal expansion difference) in the X and Y directions of the lower wafer LW, and can adjust the XY difference of the wafer ratio component between the lower wafer LW and the upper wafer UW. As a result, the bonding apparatus 2 of the first embodiment can make the XY difference of the wafer ratio component between the lower wafer LW and the upper wafer UW consistent, and can suppress overlap misalignment in the bonding alignment control of the bonding wafer BW. Therefore, the semiconductor manufacturing system PS of the first embodiment can improve the accuracy of bonding alignment control and improve the yield of semiconductor devices with bonding structures.

[0163] <2> Second Implementation Method

[0164] In the semiconductor manufacturing system PS of the second embodiment, the bonding device 2 is configured to fabricate relation 211 using a bonding wafer BW. Hereinafter, the differences between the semiconductor manufacturing system PS of the second embodiment and the first embodiment will be mainly explained.

[0165] <2-1> Composition

[0166] The semiconductor manufacturing system PS in the second embodiment has the same configuration as in the first embodiment.

[0167] <2-2> Manufacturing Method

[0168] Figure 27 This is a flowchart illustrating an example of a method for learning wafer ratio correction values ​​in a semiconductor manufacturing system PS according to the second embodiment. Hereinafter, refer to... Figure 27 As a learning method for wafer ratio correction values, an example of the order of generating relation 211 is explained.

[0169] First, the lower wafer (LW) is prepared before bonding (step S201). In this specification, "lower wafer (LW) before bonding" corresponds to the lower wafer (LW) after the previous process has been completed. The prepared lower wafer (LW) is transported to the bonding apparatus 2 and held on the lower worktable 230.

[0170] Next, temperature adjustment of the lower stage 230 is performed (step S202). The temperature of the lower stage 230 is a predetermined temperature used as the learning target. Then, after the temperature of the lower stage 230, after temperature adjustment, reaches equilibrium with the temperature of the lower wafer LW, the bonding device 2 performs alignment measurement using the camera 235 on the upper stage 233 side (step S203). The alignment measurement target in step S203 is the bonding layer formed in the previous process or a layer near the bonding layer. The results of the alignment measurement are stored, for example, in the storage device 21. If the alignment measurement is completed, the bonding device 2 confirms whether the alignment measurement at all temperatures of the learning target is complete (step S204).

[0171] If the alignment measurement is not completed at all temperatures of the target material (step S204: No), the bonding device 2 changes the temperature (step S205) and proceeds to step S202. That is, the bonding device 2 performs temperature adjustment of the lower stage 230 and alignment measurement of the lower wafer LW using a different temperature than before. If the alignment measurement is completed at all temperatures of the target material (step S204: Yes), the bonding device 2 proceeds to step S206.

[0172] In step S206, the bonding device 2 calculates the XY difference of the wafer scaling component of the lower wafer LW at each of the multiple temperatures used, based on the alignment measurement results. Then, the bonding device 2 generates a relationship 211 between the XY difference of the wafer scaling component of the lower wafer LW and the temperature of the lower stage 230 (step S207). The temperature of the lower stage 230 in step S207 can also be the temperature of the heater 44. Afterwards, the bonding device 2 saves the generated relationship 211 to the storage device 21.

[0173] Figure 28 This is a graph representing an example of the learning result of the wafer ratio correction value in the semiconductor manufacturing system PS of the second embodiment. Figure 28The horizontal axis of the graph shown represents the XY difference of the wafer ratio component of the lower wafer LW before bonding, and the vertical axis represents the temperature of the lower stage 230. For example... Figure 28 As shown, the XY difference of the wafer scaling component of the lower wafer LW and the temperature of the lower stage 230 can be represented, for example, by a linear function relationship 211. In this case, the higher the temperature of the lower stage 230, the greater the correction amount of the XY difference of the wafer scaling component in the bonding process. By using the relationship 211, which is a learning result of the wafer scaling correction value, the bonding apparatus 2 can select the temperature of the lower stage 230 of the wafer scaling component XY difference of the lower wafer LW and the upper wafer UW, which is such that the difference between the XY differences of the wafer scaling components of the lower wafer LW and the upper wafer UW in the bonding alignment control measurement is close to zero.

[0174] <2-3> Effects of the Second Implementation Method

[0175] The semiconductor manufacturing system PS of the second embodiment can produce the correction form 211 for correcting the XY difference of the wafer ratio component with fewer resources than that of the first embodiment. Therefore, the semiconductor manufacturing system PS of the second embodiment can achieve the same effect as the first embodiment, and can suppress the cost required to produce the correction form 211 compared with the first embodiment.

[0176] <3> Third Implementation Method

[0177] The third embodiment relates to a specific example of a semiconductor device manufactured using the bonding method described in the above embodiments. Hereinafter, a memory device having a bonding structure will be described as a specific example of a semiconductor device.

[0178] <3-1> Overall Structure of Memory Device 500

[0179] Figure 29 This is a block diagram illustrating an example of the overall configuration of the memory device 500 according to the third embodiment. For example... Figure 29 As shown, the memory device 500 includes a memory interface (memory I / F) 501, a sequencer 502, a memory cell array 503, a driver module 504, a line decoder module 505, and a sense amplifier module 506.

[0180] The memory I / F501 connects to an external memory controller via a channel CH for communication according to an interface standard. The memory I / F501, for example, supports the NAND interface standard.

[0181] The sequencer 502 is a control circuit that controls the overall operation of the memory device 500. Based on the instructions received via the memory I / F 501, the sequencer 502 controls the driver module 504, the line decoder module 505, and the sense amplifier module 506 to perform read operations, write operations, erase operations, etc.

[0182] The memory cell array 503 is a memory circuit containing a collection of multiple memory cells. The memory cell array 503 contains multiple blocks BLK0 to BLKn (n is an integer greater than or equal to 1). Multiple bit lines and multiple word lines are configured in the memory cell array 503. Each memory cell is associated with, for example, one bit line BL and one word line WL.

[0183] Driver module 504 is a driver circuit that generates the voltages used in read, write, and erase operations. Driver module 504 applies the generated voltages to multiple signal lines connected to line decoder module 505.

[0184] The row decoder module 505 decodes the row address received via the memory I / F 501 and selects one block BLK based on the decoding result. Furthermore, the row decoder module 505 transmits voltages applied to multiple signal lines to multiple wirings (word lines WL, etc.) located on the selected block BLK.

[0185] During the read operation, the sense amplifier module 506 determines the data to be read from the selected memory cell based on the voltage of the bit line BL, and sends it to the memory controller via the memory I / F 501. Furthermore, during the write operation, the sense amplifier module 506 applies a voltage corresponding to the data written to the memory cell for each bit line BL.

[0186] <3-2> Circuit configuration of memory cell array 503

[0187] Figure 30 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array 503 included in the memory device 500 of the third embodiment. Figure 30 This shows one of the multiple block BLKs contained in the storage cell array 503. For example... Figure 30 As shown, the data block BLK contains, for example, four string units SU0 to SU3.

[0188] Each string cell (SU) contains multiple NAND strings (NS) associated with bit lines BL0 to BLm (where m is an integer greater than or equal to 1). Each bit line BL is shared among multiple blocks (BLK) by NAND strings (NS) assigned the same column address. Each NAND string (NS) contains, for example, memory cell transistors MT0 to MT7 and selection transistors STD and STS.

[0189] Each memory cell transistor MT includes a control gate and a charge storage layer, storing data non-volatilely. Memory cell transistors MT0 to MT7 of each NAND string NS are connected in series. The control gates of memory cell transistors MT0 to MT7 are respectively connected to word lines WL0 to WL7. Each word line WL0 to WL7 is configured according to each block BLK. A collection of multiple memory cell transistors MT connected to a common word line WL in the same string cell SU is, for example, called a "cell unit CU". A cell unit CU can have a storage capacity of more than two pages of data, corresponding to the number of bits of data stored by the memory cell transistor MT.

[0190] Select transistors STD and STS are used to select the serial cell SU. The drain of select transistor STD is connected to the associated bit line BL. Series-connected memory cell transistors MT0 to MT7 are connected between the source of select transistor STD and the drain of select transistor STS. The gates of the select transistors STD contained in serial cells SU0 to SU3 are connected to select gate lines SGD0 to SGD3, respectively. The source of select transistor STS is connected to the source line SL. The gate of select transistor STS is connected to the select gate line SGS. The source line SL is shared, for example, in multiple blocks BLK.

[0191] Furthermore, in the memory cell array 503, the number of word lines WL, select gate lines SGD, and select gate lines SGS, or the number of memory cell transistors MT, select transistors STD, and STS, can also be other quantities.

[0192] <3-3> Construction of Memory Device 500

[0193] Hereinafter, an example of the construction of the memory device 500 according to the third embodiment will be described. In the third embodiment, the X direction corresponds, for example, to the extension direction of the word line WL. The Y direction corresponds, for example, to the extension direction of the bit line BL. The Z direction corresponds to the vertical direction relative to the front surface of the semiconductor substrate (wafer) used to form the memory device 500.

[0194] Figure 31 This is a perspective view showing an example of the structure of the memory device 500 according to the third embodiment. Figure 31 As shown, the memory device 500 includes a memory chip MC and a CMOS chip CC. The memory chip MC includes a storage region MR, lead-out regions HR1 and HR2, and a pad region PR1. The CMOS chip CC includes a sensing and amplification region SR, a peripheral circuit region PER1, transmission regions XR1 and XR2, and a pad region PR2.

[0195] The memory region MR includes a memory cell array 503. Lead-out regions HR1 and HR2 include wiring for connections between the stacked wiring of the memory chip MC and the row decoder module 505 of the CMOS chip CC. Pad region PR1 includes pads for connections between the memory device 500 and the memory controller. Lead-out regions HR1 and HR2 sandwich the memory region MR in the X direction. Pad region PR1 is adjacent to the memory region MR and lead-out regions HR1 and HR2 in the Y direction, respectively.

[0196] The sensing amplification region SR includes a sensing amplifier module 506. The peripheral circuit region PERI includes a sequencer 502, a driver module 504, etc. The transmission regions XR1 and XR2 include a line decoder module 505. The pad region PR2 includes a memory I / F 501. The sensing amplification region SR and the peripheral circuit region PERI are arranged adjacently in the Y direction and overlap with the memory region MR in the Z direction. The transmission regions XR1 and XR2 sandwich the sensing amplification region SR and the peripheral circuit region PERI in the X direction and overlap with the lead-out regions HR1 and HR2, respectively. The pad region PR2 overlaps with the pad region PR1 of the memory chip MC in the Z direction.

[0197] The memory chip MC has multiple bonding pads BP at the bottom of each of the memory region MR, lead-out regions HR1 and HR2, and pad region PR1. The bonding pads BP of the memory region MR are connected to associated bit lines BL. The bonding pads BP of the lead-out regions HR are connected to associated wirings (e.g., word lines WL) in the stacked wiring provided in the memory region MR. The bonding pads BP of the pad region PR1 are connected to pads (not shown) located on the upper surface of the memory chip MC. The pads on the upper surface of the memory chip MC are used, for example, for connections between the memory device 500 and the memory controller.

[0198] The CMOS chip CC has multiple bonding pads BP on the upper part of the sensing amplification region SR, the peripheral circuit region PERI, the transmission regions XR1 and XR2, and the pad region PR2. The bonding pads BP of the sensing amplification region SR overlap with the bonding pads BP of the memory region MR in the Z direction. The bonding pads BP of the transmission regions XR1 and XR2 overlap with the bonding pads BP of the lead-out regions HR1 and HR2, respectively, in the Z direction. The bonding pads BP of the pad region PR1 overlap with the bonding pads BP of the pad region PR2 in the Z direction.

[0199] The memory device 500 has a structure in which the lower surface of a memory chip MC (the front side of the semiconductor substrate on which the memory chip MC is formed) is bonded to the upper surface of a CMOS chip CC (the front side of the semiconductor substrate on which the CMOS chip CC is formed). Two bonding pads BP, which are disposed between the memory chip MC and the CMOS chip CC, are electrically connected by bonding among a plurality of bonding pads BP disposed in the memory device 500. Thus, the circuitry within the memory chip MC and the circuitry within the CMOS chip CC are electrically connected via the bonding pads BP. The set of two bonding pads BP facing each other between the memory chip MC and the CMOS chip CC can be either boundary-bounded or integrated.

[0200] <3-3-1> Construction of the storage cell array 503

[0201] The structure of the storage cell array 503 will be described below.

[0202] (Planar layout of memory cell array 503)

[0203] Figure 32 This is a top view showing an example of the planar layout of the memory cell array 503 provided in the memory device 500 of the third embodiment. Figure 32 This displays the region containing a block BLK within the storage region MR. For example... Figure 32 As shown, the memory device 500 includes multiple slots (SLT), multiple slots (SHE), multiple memory pillars (MP), multiple bit lines (BL), and multiple contacts (CV). Within the memory region (MR), the planar layout described below is repeatedly configured in the Y direction.

[0204] Each slit SLT has, for example, a structure with embedded insulating components. Each slit SLT insulates the wiring (word lines WL0-WL7, and select gate lines SGD and SGS) adjacent to it. Each slit SLT has a portion extending along the X direction, and the memory region MR and the lead-out regions HR1 and HR2 are traversed along the X direction. Multiple slit SLTs are arranged in the Y direction. The area divided by the slit SLT corresponds to the block BLK.

[0205] Each slit SHE has, for example, a structure with embedded insulating components. Each slit SHE insulates the adjacent select gate line SGD separated by that slit SHE. Each slit SHE has a portion extending along the X direction, traversing the memory region MR. Multiple slit SHEs are arranged in the Y direction. In this example, three slit SHEs are arranged between adjacent slits SLT. The multiple regions divided by the slits SLT and SHEs correspond to the string cells SU0 to SU3, respectively.

[0206] Each memory column (MP) functions as a NAND string (NS). Multiple memory columns (MPs) are arranged in an alternating pattern, for example, in 19 columns, within the region between two adjacent slots (SLTs). Furthermore, counting from the top of the paper, the memory columns (MPs) in the 5th, 10th, and 15th columns each overlap with a slot (SHE).

[0207] Each bit line BL has a portion extending along the Y direction and traversing an area where multiple blocks BLK are arranged along the Y direction. Multiple bit lines BL are arranged in the X direction. Each bit line BL is configured to overlap with at least one memory column MP for each string cell SU. In this example, two bit lines BL overlap with each memory column MP.

[0208] Each contact CV is positioned between one of the multiple bit lines BL overlapping the memory cylinder MP and the memory cylinder MP. The contact CV electrically connects the memory cylinder MP and the bit line BL. Additionally, the contact CV between the memory cylinder MP and the bit line BL overlapping the slit SHE is omitted.

[0209] (Cross-sectional structure of memory cell array 503)

[0210] Figure 33 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array 503 provided in the memory device 500 of the third embodiment. Figure 33 This shows a cross-section along the Y direction within the storage region MR, including the storage column MP and the slot SLT. (Example) Figure 33 As shown, the memory device 500 includes insulating layers 510-518, conductive layers 520-526, and contacts V1 and V2.

[0211] Insulator layer 510 is located, for example, at the bottom layer of memory chip MC. Wiring for connecting conductor layer 520 and pads PD may also be provided on the layer where insulator layer 510 is formed. Conductor layer 520 and insulator layer 511 are sequentially disposed on insulator layer 510. Conductor layer 521 and insulator layer 512 are alternately disposed on insulator layer 511. Insulator layer 513 is disposed on the top conductor layer 521. Conductor layer 522 and insulator layer 514 are alternately disposed on insulator layer 513. Insulator layer 515 is disposed on the top conductor layer 522. Conductor layer 523 and insulator layer 516 are alternately disposed on insulator layer 515. Insulator layer 517, conductor layer 524, and insulator layer 518 are sequentially disposed on the top conductor layer 523. Insulating layer 518 includes contacts V1 and V2, and conductive layers 525 and 526. Contact V1 connects conductive layer 524 and conductive layer 525. Contact V2 connects conductive layer 525 and conductive layer 526.

[0212] Conductor layers 520, 521, 522, and 523 each have, for example, plate-like portions formed extending along the XY plane. Conductor layer 524 has, for example, line-like portions formed extending in the Y direction. Conductor layers 520, 521, and 523 serve as source line SL, select gate line SGS, and select gate line SGD, respectively. Multiple conductor layers 522, from bottom to top, serve as word lines WL0 to WL7. Conductor layer 524 serves as bit line BL. Conductor layer 526 serves as bonding pad BP for the memory chip MC. Conductor layer 526, for example, contains copper.

[0213] The slit SLT has a portion extending along the XZ plane, separating the insulating layers 511-516 and the conductive layers 521-523. Each memory pillar MP extends along the Z direction and penetrates the insulating layers 511-516 and the conductive layers 521-523. Each memory pillar MP includes, for example, a core component 530, a semiconductor layer 531, and a laminated film 532. The core component 530 is an insulator extending along the Z direction. The semiconductor layer 531 covers the core component 530. The lower portion of the semiconductor layer 531 is in contact with the conductive layer 520. The laminated film 532 covers the side surface of the semiconductor layer 531. A contact CV is provided on the semiconductor layer 531. The semiconductor layer 531 is electrically connected to the conductive layer 524 via the contact CV. Furthermore, the portions where the memory pillar MP intersects with the multiple conductive layers 521 function as selection transistors (STS). The portions where the memory pillar MP intersects with the conductive layers 522 function as memory cell transistors (MT). The portion where the storage pillar MP intersects with the multiple conductor layers 523 functions as the select transistor STD.

[0214] (Cross-sectional structure of storage column MP)

[0215] Figure 34 This is an example of the cross-sectional structure of the memory column MP provided in the memory device 500 of the third embodiment, along... Figure 33 A sectional view of the XXXIV-XXXIV line. Figure 34 This represents a cross-section containing the storage pillar MP and the conductive layer 522, parallel to both the X and Y directions. For example... Figure 34As shown, the laminated film 532 includes a tunnel insulating film 533, an insulating film 534, and a barrier insulating film 535. A core component 530 is disposed at the center of the memory pillar MP. A semiconductor layer 531 surrounds the sides of the core component 530. The tunnel insulating film 533 surrounds the sides of the semiconductor layer 531. The insulating film 534 surrounds the sides of the tunnel insulating film 533. The barrier insulating film 535 surrounds the sides of the insulating film 534. A conductive layer 522 surrounds the sides of the barrier insulating film 535. The semiconductor layer 531 serves as the channel (current path) for the memory cell transistors MT0 to MT7 and the selection transistors STD and STS. The tunnel insulating film 533 and the barrier insulating film 535 each contain, for example, silicon dioxide (SiO2). The insulating film 534 serves as the charge storage layer for the memory cell transistor MT and contains, for example, silicon nitride (SiN).

[0216] <3-3-2> Cross-sectional structure of memory device 500

[0217] Figure 35 This is a cross-sectional view showing an example of the cross-sectional structure of the memory device 500 according to the third embodiment. Figure 35 The diagram shows a cross-section including the memory region (MR) and the sensing amplification region (SR), i.e., a cross-section including the memory chip (MC) and the CMOS chip (CC). Figure 35 As shown, the memory device 500 includes, for example, a semiconductor substrate 540, conductive layers GC and 541 to 544, and contacts CS and C0 to C3 in the sensing amplification region SR.

[0218] Semiconductor substrate 540 is a substrate used to form a CMOS chip CC. Semiconductor substrate 540 includes multiple well regions (not shown). Transistors TR are formed, for example, in each of the multiple well regions. A conductive layer GC is provided on semiconductor substrate 540 via a gate insulating film. The conductive layer GC within the sensing amplification region SR serves as the gate electrode of the transistor TR included in the sensing amplifier module 506. Contact C0 is provided on conductive layer GC. Two contacts CS are provided on semiconductor substrate 540 corresponding to the source and drain of transistor TR.

[0219] Each contact CS is connected to a corresponding conductive layer 541. Contact C0 is also connected to a corresponding conductive layer 541. A conductive layer 541 is connected to the bonding pad BP (conductive layer 544) of the CMOS chip CC via contact C1, conductive layer 542, contact C2, conductive layer 543, and contact C3. The conductive layer 544 in the sensing amplification region SR is bonded to the conductive layer 526 (i.e., the bonding pad BP of the memory chip MC) in the oppositely arranged memory region MR. Furthermore, each conductive layer 544 in the sensing amplification region SR is electrically connected to a bit line BL. The conductive layer 544 may contain, for example, copper. Additionally, the number of wiring layers for the memory chip MC and the CMOS chip CC can be appropriately varied depending on the configuration of the memory device 500.

[0220] <3-4> Effects of the Third Implementation Method

[0221] As explained above, in the memory device 500, the memory chip MC includes a memory cell array 503, and the CMOS chip CC includes CMOS circuitry. Furthermore, for example, the memory chip MC is used as the upper wafer (UW) in the bonding process, and the CMOS chip CC is used as the lower wafer (LW) in the bonding process. As described above, the circuit structures formed in the memory chip MC and the CMOS chip are quite different. In particular, the memory chip MC tends to have a larger XY difference in wafer scaling components as the memory cell array 503 is formed. Therefore, the yield may decrease due to the XY difference in wafer scaling components at the bonding surfaces of the memory chip MC and the CMOS chip CC.

[0222] Therefore, it is considered to apply the bonding method and semiconductor device manufacturing method described in the first and second embodiments in the manufacturing of the memory device 500 of the third embodiment. That is, during the bonding process of the memory chip MC and the CMOS chip CC in the memory device 500 of the third embodiment, the alignment accuracy of the memory chip MC and the CMOS chip CC can be improved by applying the correction of the XY difference of the wafer ratio component based on the temperature adjustment of the lower stage 230. As a result, the yield of the memory device 500 of the third embodiment can be improved by applying the semiconductor device manufacturing method of the first or second embodiment.

[0223] Furthermore, the application of the bonding method and semiconductor device manufacturing method described in each of the first and second embodiments is not limited to the memory device 500. The application of the bonding method or semiconductor device manufacturing method described in each of the first and second embodiments is applicable to any semiconductor device having a bonding structure.

[0224] <4> Modified examples, etc.

[0225] In the above embodiment, a heater 44 is provided on the lower stage 230 of the bonding apparatus 2, but the embodiment is not limited to this. The lower stage 230 can be configured to be temperature-adjustable. The lower stage 230 can also be configured to be adjustable to a temperature lower than room temperature RT. In such a case, the bonding apparatus 2 can also correct the XY difference of the wafer scaling components in the lower wafer LW and the upper wafer UW of the bonding object by adjusting the temperature of the lower stage 230 (main body 40). In the second embodiment, the bonding apparatus 2 performs the following... Figure 27 The processing described is as shown, but is not limited to this. Figure 27 The process shown can be performed using any device equipped with a wafer stage capable of temperature adjustment and alignment measurement. In this case, the process is performed... Figure 27 The wafer stage of the processing apparatus shown is more preferably configured to be the same as the lower stage 230 of the bonding apparatus 2 (stage pin 42, heater 44, etc.).

[0226] In the above embodiments, the flowcharts used in the description of the bonding method and the semiconductor device manufacturing method are merely one example. Regarding the actions described using the flowcharts, the order of processing can be interchanged to the extent possible, additional processes can be added, and some processes can be omitted. As control devices 10 and 20, MPU (Micro Processing Unit), ASIC (Application Specific Integrated Circuit), or FPGA (Field-Programmable Gate Array) can be used instead of a CPU. The processes described in the above embodiments can also be implemented using dedicated hardware. The processes described in the above embodiments can be a combination of software-executed processes and hardware-executed processes, or only one of them.

[0227] The circuit configuration, planar layout, and cross-sectional structure of the memory device 500 described in the third embodiment can be appropriately modified according to the design of the memory device 500. For example, in the third embodiment, a case is illustrated where a memory chip MC is provided on a CMOS chip CC, but a CMOS chip CC may also be provided on top of the memory chip MC. That is, a CMOS chip CC may be assigned to the upper wafer UW, and a memory chip MC may be assigned to the lower wafer LW. In this specification, "connection" means electrical connection, and does not exclude the case of connection via other components. "Electrical connection" may also be via an insulator as long as it can operate in the same way as an electrical connection.

[0228] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, with various omissions, substitutions, and modifications possible without departing from the spirit of the claim. These embodiments and their variations are included within the scope and spirit of the claim, and are also included within the scope of the technical solutions described in the claims and their equivalents.

[0229] Explanation of reference numerals in the attached figures

[0230] 1… Exposure apparatus, 10… Control device, 11… Storage device, 12… Transport device, 13… Exposure unit, 14… Communication device, 110… Exposure process, 111… Correction value information, 130… Wafer stage, 131… Intermediate mask stage, 132… Light source, 133… Projection optical system, 134… Camera, 2… Bonding device, 20… Control device, 21… Storage device, 22… Transport device, 23… Bonding unit, 24… Communication device, 211… Relationship, 2 30…lower worktable, 231…stress device, 232…camera, 233…upper worktable, 234…pressing pin, 235…camera, 236, 237…moving mirror, 238, 239…interferometer, 3…server, 40…main body, 41…rib, 42…worktable pin, 43…suction port, 44…heater, 500…memory device, 501…memory interface, 502…sequencer, 503…memory cell array, 504…driver module, 505…line decoder Module, 506…sensor amplifier module, 510-518…insulator layer, 520-526…conductor layer, 530…core component, 531…semiconductor layer, 532…layer film, 533…tunnel insulating film, 534…insulator film, 535…barrier insulating film, 540…semiconductor substrate, GC, 541-544…conductor layer, MP…memory pillar, SLT, SHE…slit, TR…transistor, BLK…block, SU…string cell, NS…NAND string, MT …Memory cell transistor, STD, STS…select transistor, BL…bit line, WL…word line, SGD, SGS…select gate line, SL…source line, MC…memory chip, CC…CMOS chip, C0~C3, V1, V2, CV…contacts, BP…bonding pads, MR…memory area, HR1, HR2…lead-out areas, XR1, XR2…transfer areas, SR…sensor amplification area, PR1, PR2…pad areas, PERI…peripheral circuit area

Claims

1. A joining device characterized by comprising: have: The first worktable has a main body, a plurality of worktable pins disposed on the upper part of the main body, and a heater for heating the main body, and is configured to hold a first substrate using each of the plurality of worktable pins. The second worktable is configured to hold the second substrate; and The processor is configured to control the first worktable and the second worktable to perform a bonding process that joins the first substrate and the second substrate. The first worktable, when viewed from above, has a central portion including the center of the first worktable and an outer peripheral portion located on the outer periphery of the central portion. At least one of the areas and lengths of the plurality of first pins arranged in a first direction among the plurality of worktable pins differs between the first pin located at the center of the first worktable and the first pin located at the outer periphery; at least one of the areas and lengths of the plurality of second pins arranged in a second direction different from the first direction among the plurality of worktable pins is substantially the same between the second pin located at the center of the first worktable and the second pin located at the outer periphery.

2. The joining device according to claim 1, characterized in that, The processor is further configured to adjust the temperature of the heater during the bonding process based on a third difference between a first difference between the magnification components in the first and second directions of the first substrate and a second difference between the magnification components in the first and second directions of the second substrate.

3. The joining device according to claim 1, characterized in that, The first worktable is configured such that the ratio of the area of ​​the first substrate in contact with the plurality of worktable pins decreases in the first direction from the center of the first worktable toward the outer periphery.

4. The joining device according to claim 3, characterized in that, The first worktable is further configured such that the spacing between two adjacent worktable pins among a plurality of worktable pins arranged in the first direction widens as it moves from the center of the first worktable toward the outer periphery.

5. The joining device according to claim 4, characterized in that, The spacing between two adjacent worktable pins in the plurality of worktable pins arranged in the first direction is in the range of 2000μm to 20000μm.

6. The joining device according to claim 3, characterized in that, The first worktable is further configured such that the diameter of the upper surface of each of the plurality of worktable pins arranged in the first direction decreases from the center of the first worktable toward the outer periphery.

7. The joining device according to claim 6, characterized in that, The diameter of each of the plurality of worktable pins arranged in the first direction is in the range of 100μm to 1000μm.

8. The coupling device according to claim 1, characterized in that, The first worktable is further configured such that the height of each of the plurality of worktable pins arranged in the first direction increases from the center of the first worktable toward the outer periphery.

9. The joining device according to claim 8, characterized in that, The height of each of the multiple worktable pins arranged in the first direction is in the range of 100μm to 2000μm.

10. The engagement device of claim 2, wherein, The joining device also includes: A first measuring instrument is capable of measuring a plurality of first alignment marks disposed on the first substrate held on the first worktable; and The second measuring device is capable of measuring a plurality of second alignment marks disposed on the second substrate held on the second worktable. The processor is further configured to calculate the first difference based on the measurement results of the first measuring device on the plurality of first alignment marks, and to calculate the second difference based on the measurement results of the second measuring device on the plurality of second alignment marks.

11. The coupling device according to claim 2, characterized in that, The bonding device further includes a first measuring device capable of measuring a plurality of first alignment marks disposed on the first substrate held on the first worktable. The processor is further configured to, A combination of performing the process of adjusting the temperature of the heater at multiple temperatures and measuring the multiple first alignment marks. The first difference of the magnification components of the first substrate in the first direction and the second direction is calculated based on the measurement results of the plurality of first alignment marks, corresponding to the plurality of temperatures respectively. Based on the calculation results of the first difference of each of the multiple temperatures, a relationship between the first difference and the temperature of the heater is constructed. The optimal temperature of the heater is selected based on the aforementioned relationship.

12. A joining method utilizing a joining device, the joining device comprising: A first worktable includes a main body, a plurality of worktable pins disposed on the upper part of the main body, and a heater for heating the main body, configured to hold a first substrate using each of the plurality of worktable pins; and The second worktable is configured to hold the second substrate. At least one of the areas and lengths of the plurality of worktable pins arranged in the first direction differs between the center and the outer periphery of the first worktable; the areas and lengths of the plurality of worktable pins arranged in the second direction, which is different from the first direction, are substantially the same between the center and the outer periphery of the first worktable. The joining method is characterized by including the following steps: Calculate the first difference between the magnification components of the first substrate in the first direction and the second direction; Calculate the second difference of the magnification components of the second substrate in the first direction and the second direction; The temperature of the main body is adjusted based on the third difference between the first difference and the second difference, so that the first substrate is held on the first worktable; Keep the second substrate on the second worktable; as well as The first worktable and the second worktable are controlled to join the first substrate and the second substrate.

13. The joining method according to claim 12, characterized in that, The joining method further includes the following steps: Multiple bonded substrates are fabricated by bonding multiple first substrates to multiple second substrates by adjusting the heaters at multiple different temperatures. For each of the plurality of bonding substrates, the overlap between the first substrate and the second substrate is measured, and the fourth difference of the magnification components of the bonding substrates in the first direction and the second direction is calculated. Based on the calculation results of the fourth difference of each of the multiple temperatures, a relationship between the fourth difference and the temperature of the heater is constructed; as well as The temperature of the heater is adjusted based on the aforementioned relationship.

14. The joining method according to claim 12, characterized in that, The joining method further includes the following steps: A combination of performing the step of adjusting the temperature of the heater at multiple temperatures and measuring multiple alignment marks disposed on the first substrate held on the first worktable; The first difference of the magnification components of the first substrate in the first direction and the second direction is calculated based on the measurement results of the multiple alignment marks, corresponding to the multiple temperatures respectively. Based on the calculation results of the first difference of each of the plurality of temperatures, a relationship between the first difference and the temperature of the heater is made; as well as The temperature of the heater is adjusted based on the aforementioned relationship.

15. A method for manufacturing a semiconductor device, utilizing a bonding apparatus, the bonding apparatus comprising: The first worktable has a main body, a plurality of worktable pins disposed on the upper part of the main body, and a heater for heating the main body, and is configured to hold a first substrate using each of the plurality of worktable pins. The second worktable is configured to hold the second substrate. The first worktable, when viewed from above, has a central portion including the center of the first worktable and an outer peripheral portion located on the outer periphery of the central portion. At least one of the areas and lengths of the plurality of first pins arranged in a first direction differs between the first pins located at the center of the first worktable and the first pins located at the outer periphery; the areas and lengths of the plurality of second pins arranged in a second direction different from the first direction are substantially the same between the second pins located at the center of the first worktable and the second pins located at the outer periphery. The method for manufacturing the semiconductor device is characterized by comprising the following steps: Calculate the first difference between the magnification components of the first substrate in the first direction and the second direction; Calculate the second difference of the magnification components of the second substrate in the first direction and the second direction; The temperature of the heater is adjusted based on a third difference between the first difference and the second difference, so that the first substrate is held on the first worktable; Keep the second substrate on the second worktable; as well as The first worktable and the second worktable are controlled to join the first substrate and the second substrate.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that, The method for manufacturing the semiconductor device further includes the following steps: Multiple first substrates are bonded to multiple second substrates by adjusting the heaters at multiple different temperatures, thereby creating multiple bonded substrates. For each of the plurality of bonding substrates, the overlap between the first substrate and the second substrate is measured, and the fourth difference of the magnification components of the bonding substrates in the first direction and the second direction is calculated. Based on the calculation results of the fourth difference of each of the multiple temperatures, a relationship between the fourth difference and the temperature of the heater is constructed; as well as The temperature of the heater is adjusted based on the aforementioned relationship.

17. The method for manufacturing a semiconductor device according to claim 15, characterized in that, The method for manufacturing the semiconductor device further includes the following steps: A combination of performing the step of adjusting the temperature of the heater at multiple temperatures and measuring multiple alignment marks disposed on the first substrate held on the first worktable; The first difference of the magnification components of the first substrate in the first direction and the second direction is calculated based on the measurement results of the multiple alignment marks, corresponding to the multiple temperatures respectively. Based on the calculation results of the first difference of each of the plurality of temperatures, a relationship between the first difference and the temperature of the heater is made; as well as The temperature of the heater is adjusted based on the aforementioned relationship.

Images