Screening method, processing method, wafer, screening device, apparatus, and medium

Abstract

The present disclosure provides a screening method, a processing method, a wafer, a screening device, an apparatus and a medium. The screening method comprises: obtaining wafer trace information of a wafer to be screened; determining whether the wafer to be screened has intrinsic gettering capability based on the wafer trace information and a preset gettering capability judgment standard, wherein the intrinsic gettering capability refers to the ability of the wafer to be screened to bind copper impurities by using the intrinsic defect structure naturally formed in the growth process of the wafer; if the determination is yes, the wafer to be screened is marked as a wafer with intrinsic gettering capability; if the determination is no, the wafer to be screened is marked as other wafers. The screening method screens the wafer with intrinsic gettering capability according to the wafer trace information, avoids the complex steps of actively introducing gettering traps in the traditional process, simplifies the screening process, improves the efficiency, and helps to ensure the surface cleanliness of the wafer in the subsequent manufacturing.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and more specifically, to a screening method, processing method, wafer, screening device, equipment, and medium. Background Technology

[0002] In the semiconductor manufacturing field, especially in the fabrication of high-performance wafers, extremely high requirements are placed on controlling the concentration of copper impurities in the wafers. This is because copper is a highly hazardous metallic contaminant; even at extremely low concentrations, it can severely damage the electrical performance and reliability of devices. Therefore, developing efficient copper contamination suppression technologies is one of the core objectives for improving the quality of semiconductor materials and expanding process windows.

[0003] To address copper contamination, gettering techniques are commonly used. The core of this technique is to actively introduce defects as impurity traps to capture and immobilize copper impurities, preventing their migration to the wafer, especially the active regions near the wafer surface. However, this method inevitably increases process complexity and production costs due to the need to introduce additional defect structures, and may introduce secondary defects that damage the wafer's lattice integrity, which contradicts the goal of high-purity, low-defect wafer fabrication.

[0004] Therefore, there is an urgent need to provide a new method to solve the technical problem of how to effectively suppress the diffusion of copper impurities to the near surface of the wafer, especially the active region, during the wafer fabrication process without introducing additional defects. Summary of the Invention

[0005] This disclosure provides a screening method, processing method, wafer, screening device, equipment, and medium. The screening method can identify and distinguish wafers with intrinsic gettering capabilities. These wafers can reduce or eliminate the need for gettering processes that actively introduce additional defects in subsequent manufacturing processes, thereby controlling the risk of copper contamination from the source of materials and avoiding the negative impact of introducing secondary defects.

[0006] The first aspect of this disclosure provides a wafer screening method, which includes: obtaining wafer traceability information of the wafer to be screened; determining whether the wafer to be screened has intrinsic getter capability based on the wafer traceability information and a preset getter capability judgment standard, wherein intrinsic getter capability refers to the ability of the wafer to be screened to use the intrinsic defect structure naturally formed during its growth process to bind copper impurities; if the determination is yes, then the wafer to be screened is marked as a wafer with intrinsic getter capability; if the determination is no, then the wafer to be screened is marked as another wafer.

[0007] Thus, the screening method provided in this disclosure, based on the acquisition of wafer traceability information and according to preset getter capability judgment criteria, directly identifies wafers with intrinsic getter capability. Through this screening mechanism, wafer materials with excellent resistance to copper contamination can be obtained without relying on the complex steps of artificially introducing additional defect layers in traditional processes. Therefore, this method not only simplifies the process flow and reduces manufacturing costs and thermal budgets, but also avoids secondary defect problems that may arise from actively introducing external defects, achieving economical and reliable control of copper contamination from the source of the material.

[0008] In one specific embodiment of the first aspect of this disclosure, the wafer traceability information includes wafer origin information and wafer quality information; wherein, the wafer origin information includes at least the axial position distance of the wafer to be screened on the corresponding ingot and the process growth conditions of the ingot corresponding to the wafer to be screened; the wafer quality information includes at least the interstitial oxygen concentration of the wafer to be screened.

[0009] In one specific embodiment of the first aspect of this disclosure, the gettering capability judgment criteria include a traceability matching criterion and a quality judgment criterion; wherein, the traceability matching criterion is the basis for comparing and matching with wafer traceability information; and the quality judgment criterion is the basis for judging by comparing and judging with wafer quality information.

[0010] In one specific embodiment of the first aspect of this disclosure, the traceability matching criteria include that the axial position distance of the wafer to be screened on the corresponding ingot is less than or equal to a first preset threshold, and the growth process conditions of the ingot corresponding to the wafer to be screened include non-nitrogen-doped process conditions; the quality judgment criteria include that the interstitial oxygen concentration of the wafer to be screened is greater than or equal to a second preset threshold.

[0011] In one specific embodiment of the first aspect of this disclosure, the first preset threshold is less than or equal to 10 cm, and the second preset threshold is greater than or equal to 14 ppm.

[0012] In one specific embodiment of the first aspect of this disclosure, determining whether a wafer to be screened possesses intrinsic getter capability based on wafer traceability information and a preset getter capability judgment standard includes: comparing the wafer traceability information with the traceability matching standard to determine whether the wafer to be screened meets the traceability matching standard; if it does not meet the standard, then determining that the wafer to be screened does not possess intrinsic getter capability; if it does meet the standard, then comparing the wafer traceability information with the quality judgment standard to determine whether the wafer to be screened meets the quality judgment standard; if it does not meet the standard, then determining that the wafer to be screened does not possess intrinsic getter capability; if it does meet the standard, then determining that the wafer to be screened possesses intrinsic getter capability.

[0013] The second aspect of this disclosure provides a wafer processing method, the processing method comprising: obtaining a wafer to be processed, wherein the wafer to be processed is a wafer with intrinsic gettering capability obtained by the screening method in the first aspect described above; and performing heat treatment on the wafer to be processed based on preset conditions, wherein the heat treatment is configured to activate the intrinsic defect structure of the wafer to be processed to bind copper impurities.

[0014] A third aspect of this disclosure provides a wafer obtained by the processing method described in the second aspect above, wherein the surface copper impurity concentration of the wafer is 1.0 × 10⁻⁶. 7 atoms / cm 2 - 1.0×10 8 atoms / cm 2 Within the range.

[0015] This disclosure provides a wafer screening apparatus, comprising an acquisition module, a judgment module, and an execution module. The acquisition module is configured to acquire wafer traceability information of the wafer to be screened; the judgment module is configured to determine whether the wafer to be screened possesses intrinsic getter capability based on the wafer traceability information and a preset getter capability judgment standard, wherein intrinsic getter capability refers to the ability of the wafer to be screened to utilize intrinsic defect structures naturally formed during its growth process to bind copper impurities; the execution module is configured to mark the wafer to be screened as having intrinsic getter capability if the determination is yes, and to mark the wafer to be screened as another wafer if the determination is no.

[0016] The fifth aspect of this disclosure provides a computing device including a processor and a memory, the processor being configured to execute instructions stored in the memory to implement the filtering method of the first aspect described above.

[0017] The sixth aspect of this disclosure provides a computer storage medium storing at least one instruction, which is executed by a processor to implement the filtering method of the first aspect described above. Attached Figure Description

[0018] Figure 1 This is a schematic flowchart illustrating a wafer screening method according to an embodiment of the present disclosure.

[0019] Figure 2 This is a partial flowchart illustrating a wafer screening method provided in one embodiment of the present disclosure.

[0020] Figure 3 This is a schematic flowchart illustrating a wafer screening method according to an embodiment of the present disclosure.

[0021] Figure 4 This is a schematic flowchart of a wafer screening method provided in another embodiment of the present disclosure.

[0022] Figure 5 This is a schematic flowchart of a wafer processing method provided in one embodiment of the present disclosure.

[0023] Figure 6 This is a schematic block diagram of a wafer screening device provided in one embodiment of the present disclosure.

[0024] Figure 7 A schematic block diagram of a computing device provided in an embodiment of this disclosure. Detailed Implementation

[0025] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0026] In semiconductor wafer fabrication and subsequent device manufacturing processes, copper impurities are key contaminants that negatively impact wafer quality and device performance. This is because copper impurities have a high diffusion coefficient and solid solubility in the silicon substrate, even at extremely low concentrations such as 10⁻⁶. 9 atoms / cm 3 In the lower energy level, it can also serve as a deep-level recombination center. This deep-level recombination center provides additional recombination pathways for electrons and holes, significantly accelerating the minority carrier recombination rate and reducing minority carrier lifetime. The decrease in minority carrier lifetime directly leads to increased device leakage current, deterioration of switching characteristics, and reduction of breakdown voltage. It also exacerbates the failure risk of the device under high temperature and reverse bias conditions, ultimately degrading the device's electrical performance and long-term operational reliability.

[0027] As the feature size of semiconductor devices continues to shrink, especially in applications such as high-performance logic devices, power devices, and radio frequency devices where the intrinsic quality requirements of wafers are extremely high, the cleanliness requirements of the active region near the wafer surface have increased significantly. This has led to extremely stringent control standards for the content and diffusion behavior of copper impurities, and it is urgent to strictly suppress the diffusion of copper impurities into the active region near the wafer surface in order to ensure the core performance and long-term stability of the devices.

[0028] To address the aforementioned need for copper impurity diffusion control, gettering technology is currently the mainstream solution. Specifically, gettering technology is mainly divided into two categories: intrinsic gettering and intriguing gettering. Intrinsic gettering involves inducing oxygen precipitation and associated dislocation loop networks within the wafer through high-temperature heat treatment, forming a bulk getter layer. Intrinsic gettering involves creating a defect-rich getter region on the back side of the wafer through methods such as backside mechanical damage, polysilicon deposition, or ion implantation. Additional processes such as sandblasting, laser treatment, or polysilicon deposition can introduce a mechanical damage layer or heavily doped layer on the back side of the wafer, forming a high-defect-density getter region to capture and fix copper impurities. Therefore, regardless of the method used, gettering technology relies on additional, purposeful process steps to artificially construct defect structures for capturing copper impurities.

[0029] However, this technical approach has several inherent drawbacks. First, both the nucleation and growth of oxygen precipitation and the preparation of the back-side damage layer require additional independent process steps, which not only increases process complexity and manufacturing costs but also prolongs the production cycle. Second, the introduced getter layer itself is a defect structure with poor controllability; its formation process may damage lattice integrity or evolve into harmful secondary defects, thus introducing new material quality issues while controlling contamination. Furthermore, to obtain sufficient getter efficiency, high heat treatment temperatures and long processing times are often required, significantly increasing the process's thermal budget and contradicting the trend of reducing thermal history in modern manufacturing. These drawbacks are particularly pronounced against the backdrop of continuously shrinking device feature sizes and increasingly stringent requirements for the quality of wafer starting materials.

[0030] Therefore, there is an urgent need to provide a new technical solution that can effectively suppress the diffusion of copper impurities while avoiding the problems of process complexity and secondary defects caused by actively introducing external defects, thereby achieving simpler, more economical and reliable pollution control.

[0031] In view of this, embodiments of the present disclosure provide a wafer screening method, which includes: obtaining wafer traceability information of the wafer to be screened; determining whether the wafer to be screened has intrinsic getter capability based on the wafer traceability information and a preset getter capability judgment standard, wherein intrinsic getter capability refers to the ability of the wafer to be screened to use the intrinsic defect structure naturally formed during its growth process to bind copper impurities; if the determination is yes, then the wafer to be screened is marked as a wafer with intrinsic getter capability; if the determination is no, then the wafer to be screened is marked as another wafer.

[0032] Thus, the screening method provided in this disclosure effectively utilizes the intrinsic defect structure of the intrinsic gettering capability, i.e. the inherent property of the material itself, to suppress the migration of copper to the surface without actively introducing additional process defects or significantly increasing process complexity. This solves the problems of high complexity and potential introduction of secondary defects brought about by traditional active gettering processes, and achieves a simple, efficient and reliable technical effect of pollution control from the material source.

[0033] A detailed analysis of the physical mechanism, process integration, and implementation effect reveals that the screening method disclosed herein provides a simple, reliable, and source-controlled copper contamination suppression solution by utilizing the inherent intrinsic gettering capability of wafers. The specific details are as follows.

[0034] From a physical perspective, this method considers and utilizes the ability of intrinsic defect structures naturally formed during crystal growth to bind copper impurities. Therefore, it does not rely on the intrinsic or artificially introduced defects that are inherently mismatched with the crystal lattice, which are necessary for traditional gettering techniques, thus avoiding the inherent disturbance to crystal integrity caused by the defect introduction process.

[0035] From a process integration perspective, this method replaces the traditional, separate getter process module with a pre-selection step. This selection step can be completed quickly based on wafer traceability information, without the need for additional heat treatment or defect manufacturing processes. This significantly simplifies the process flow, reduces integration complexity and production cycle time, and minimizes process variables introduced by additional steps.

[0036] In terms of implementation effectiveness, this method ensures the originality and naturalness of the intrinsic defect structures utilized through screening. Their distribution and characteristics are determined by the growth process, thus avoiding the difficulties in controlling the density, distribution, and stability of artificially introduced defects. This fundamentally eliminates performance fluctuations caused by inhomogeneous or uncontrollable getter layers, as well as the risk of secondary defect generation. While achieving efficient suppression of copper diffusion, it also ensures the intrinsic high quality of the wafer material.

[0037] The following describes, with reference to the accompanying drawings, a screening method, a processing method, a wafer, a screening apparatus, a device, and a medium according to at least one embodiment of the present disclosure.

[0038] In the wafer screening method provided in at least one embodiment of this disclosure, such as Figure 1 As shown, the screening method includes the following steps S100 to S220.

[0039] Step S100: Obtain wafer traceability information for the wafers to be screened.

[0040] Specifically, wafer traceability information refers to a set of information used to determine or infer the growth history, location, and key intrinsic material properties of a semiconductor wafer to be screened in the original ingot. This information is used to objectively determine that the wafer to be screened has intrinsic defect structures that originate from itself and that can be known to have copper impurities thermally diffused to its surface.

[0041] Step S200: Based on wafer traceability information and preset getter capability judgment criteria, determine whether the wafer to be screened has intrinsic getter capability. Intrinsic getter capability refers to the ability of the wafer to be screened to use the intrinsic defect structure naturally formed during its growth process to bind copper impurities.

[0042] Specifically, the gettering capability judgment standard refers to a set of pre-set logical rules or models used to systematically evaluate wafer traceability information and determine whether it has intrinsic gettering capability. Its core function is to identify whether the wafer has intrinsic defect structures that bind copper impurities.

[0043] Intrinsic getter capability refers to the inherent property of semiconductor wafers to effectively capture, bind, and suppress the migration of copper impurities from the bulk to the active regions on the wafer surface during subsequent heat treatment, utilizing the intrinsic defect structures naturally formed and inherent during the crystal growth stage, such as the vacancies and oxygen-vacancy complexes abundant in the V-Rich region mentioned below. This capability is different from getter capability obtained by actively introducing non-intrinsic defects through subsequent processes.

[0044] Step S210: If the determination is yes, then mark the wafer to be screened as a wafer with intrinsic gettering capability.

[0045] Specifically, the marking in step S210 is an operation of assigning a status identifier to the wafer to be screened. This status identifier can be manifested by physical marking on the surface of the wafer to be screened, such as laser marking, attaching a label to the wafer carrier, such as a Cassette, or updating the status attributes of the wafer to be screened in a database such as a manufacturing execution system.

[0046] Wafers labeled as "intrinsic getter wafers" are identified as materials that can use their intrinsic defect structures to suppress copper diffusion by trapping copper impurities. These wafers are suitable for manufacturing high-end devices sensitive to copper contamination, or for simplifying subsequent processes.

[0047] Step S220: If the determination is negative, mark the wafer to be screened as another wafer.

[0048] Specifically, other wafers refer to wafers that are deemed to lack intrinsic getter capability based on getter capability criteria. These wafers require different subsequent process paths, such as traditional getter processes or applications with high tolerance for copper contamination.

[0049] Therefore, step S100, as the data preparation and input link of the entire screening process, provides factual evidence about the wafer growth history and intrinsic material properties in order to make an objective judgment on the intrinsic copper contamination resistance potential of the wafer to be screened. This is the first step to ensure the scientific nature and accuracy of the screening.

[0050] Step S200 serves as the core logical judgment and decision-making step in the entire screening method. Its function is to systematically compare and analyze the raw data obtained in step S100—the wafer traceability information—with the pre-set getter capability judgment criteria. This step transforms "data" into "conclusion," and its core is to execute a binary classification decision: determining whether the wafer possesses the intrinsic getter capability to confine copper diffusion using its intrinsic defect structure. The accuracy of this step directly determines the effectiveness of the entire screening scheme.

[0051] Step S210 serves as a positive execution and resource optimization step for the screening results. When step S200 makes a positive judgment, this step performs the corresponding operation, marking the wafers to be screened as "wafers with intrinsic getter capability". This marking is the basis for subsequent differentiated processing, meaning that such wafers can be preferentially used for the manufacture of high-performance devices sensitive to copper contamination, or the traditional external getter process can be simplified or even omitted in subsequent processes, thereby simplifying the process flow and optimizing the allocation of production resources.

[0052] Step S220 serves as a negative execution and path diversion step for the screening results. When step S200 makes a negative judgment, this step performs the corresponding operation, marking the wafer to be screened as "other wafers." This marking is equally crucial, as it clarifies that this type of wafer does not possess sufficient intrinsic resistance to copper diffusion and therefore may need to be directed to different process paths, such as being processed using traditional active getter processes or applied to products with higher tolerance for copper contamination. This ensures that all wafers receive the most suitable processing according to their own characteristics, achieving refined management of the manufacturing process.

[0053] In steps S203 and S204, the wafer is marked according to the judgment result.

[0054] It should be noted that the embodiments disclosed herein do not limit the means of obtaining wafer traceability information. For example, it may include, but is not limited to: directly acquiring and integrating the raw data streams of location, process conditions, and oxygen concentration; or acquiring a comprehensive feature vector that has already encapsulated the above information; or extracting feature parameters from a spectrum reflecting the distribution of crystal defects as part of the traceability information. All of these can be selected and designed according to actual needs, and will not be elaborated here.

[0055] In at least one embodiment of this disclosure, the intrinsic defect structure capable of binding copper impurities is a specific defect composite structure that is stabilized by a high vacancy concentration and a high interstitial oxygen concentration and is not compensated by nitrogen impurities. Specifically, it is a high-concentration oxygen-vacancy composite defect system that is not passivated by nitrogen.

[0056] For example, the high-concentration oxygen-vacancy composite defect system that is not nitrogen passivated exhibits the following three characteristics: First, in the region rich in vacancy-type primary defects, there are defect structures in the wafer that originate from the supersaturation aggregation of vacancy during crystal growth, characterized by high vacancy density. Secondly, there is the complex of high-concentration interstitial oxygen atoms and vacancies. The high vacancy defects interact with the interstitial oxygen atoms to form oxygen-vacancy complexes, which constitute stable and highly active impurity trapping sites.

[0057] Thirdly, the defect states that are not passivated by nitrogen impurities: the oxygen-vacancy complexes mentioned above have not undergone nitrogen doping during the ingot growth process, thereby avoiding the passivation effect of nitrogen atoms on vacancies or oxygen-vacancy complexes, and ensuring that their inherent strong chemical binding ability against copper impurities is maintained.

[0058] Therefore, judging whether an intrinsic defect structure exists requires a comprehensive assessment based on parameters such as wafer traceability information and wafer quality information, depending on the specific manifestation of the intrinsic defect structure. Thus, in order to effectively screen the aforementioned intrinsic defect structure composed of high vacancy concentration, high interstitial oxygen concentration, and lack of nitrogen passivation—that is, the high-concentration oxygen-vacancy composite defect system that has not been nitrogen passivated—this disclosure further defines the preset gettering capability judgment criteria, as detailed below.

[0059] In at least one embodiment of this disclosure, step S100, obtaining wafer traceability information of the wafer to be screened includes obtaining wafer origin information and wafer quality information. The wafer origin information includes at least the axial position distance of the wafer to be screened on the ingot and the process growth conditions of the ingot corresponding to the wafer to be screened. The wafer quality information includes at least the interstitial oxygen concentration of the wafer to be screened.

[0060] Specifically, the axial distance refers to the straight-line distance from the center point of the wafer to be screened along the ingot growth axis to the crystal tip, i.e., the end face where crystal growth begins. This parameter is a key geometric basis for determining whether the wafer is taken from a specific region of the ingot, such as the V-Rich region at the head. The essential characteristic of the V-Rich region is that it has a high concentration of vacancies caused by the rapid cooling process.

[0061] The V-Rich region mentioned above, also known as the vacancy-rich region, is a characteristic region formed during semiconductor wafer fabrication. Its core is a region where the vacancy (Va) concentration within the wafer is above saturation and vacancies dominate. It primarily forms during the fabrication of Czochralski single-crystal silicon (CZ silicon). The formation of the V-Rich region is closely related to the ratio of the single-crystal pulling speed V to the internal temperature gradient G, i.e., V / G. When V / G reaches a critical point or higher, the vacancies within the wafer become supersaturated, leading to the aggregation and formation of primary defects such as crystal origin defects and fluid pattern defects. This region, characterized by vacancy enrichment and accompanying primary defects, is the V-Rich region.

[0062] Interstitial oxygen concentration refers to the concentration of oxygen dissolved in the crystal lattice of a wafer as interstitial atoms, typically expressed in ppm (parts per million). This parameter is a key indicator for evaluating the stability and activity of intrinsic defect structures such as oxygen-vacancy complexes within a wafer. Therefore, wafer quality information must include at least the interstitial oxygen concentration of the wafer to be screened, as it serves as a basis for determining whether the wafer originating from the V-Rich region can convert the potential of "high vacancy concentration" into a defect complex structure with binding function.

[0063] Process growth conditions refer to the key process parameters or doping conditions used during ingot pulling that may affect the formation of intrinsic defects. For example, whether the ingot is grown using a non-nitrogen-doped process.

[0064] Therefore, the purpose of step S100 is to systematically collect and structure two types of key information: wafer traceability information and wafer quality information. By obtaining the axial position distance of the wafer to be screened on the corresponding ingot and the process growth conditions, it can be used as a basis to determine whether the wafer originates from the spatial and chemical environmental conditions that easily form V-Rich regions. By obtaining the interstitial oxygen concentration, it can be used as a decisive chemical prerequisite for assessing whether the high concentration of vacancies in the V-Rich region that can form intrinsic defect structures with bound copper impurities can evolve into stable and effective oxygen-vacancy complexes, i.e., intrinsic defect structures. This method of dividing wafer traceability information into two categories ensures that the assessment of the intrinsic gettering ability of the wafer to be screened is based on comprehensive and logically clear objective data. It provides an essential and standardized input for the subsequent precise logical judgment, i.e., step S200, and is the first step to ensure the scientific nature, repeatability, and accuracy of the entire screening process.

[0065] In at least one embodiment of this disclosure, in step S200, the getter capability judgment criteria include a traceability matching criterion and a quality judgment criterion; wherein, the traceability matching criterion is the basis for comparing and matching with wafer traceability information; and the quality judgment criterion is the basis for judging by comparing and judging with wafer quality information.

[0066] In at least one embodiment of this disclosure, in step S200, the traceability matching criteria include that the axial position distance of the wafer to be screened from the lead end on the ingot is less than or equal to a first preset threshold, and the growth process conditions of the ingot corresponding to the wafer to be screened include non-nitrogen-doped process conditions; the quality judgment criteria include that the interstitial oxygen concentration of the wafer to be screened is greater than or equal to a second preset threshold.

[0067] Specifically, the traceability matching standard is used to determine whether the material source and growth history of the wafer to be screened possess the physical and technological basis for forming the oxygen-vacancy complex defect system. This standard must simultaneously meet the following two core conditions: One factor is spatial conditions. The wafers to be screened are taken from a specific axial distance range from the head of the ingot, such as the axial position of the wafer to be screened on the ingot being less than or equal to the lead end. This is the source of its high vacancy density.

[0068] Secondly, the chemical environment conditions are crucial. The ingot growth process corresponding to the wafer to be screened is a non-nitrogen-doped process, which is the key to ensuring that vacancies and oxygen-vacancy complexes are not passivated by nitrogen atoms and to maintain their chemical activity.

[0069] Specifically, non-nitrogen-doped processes refer to processes in which nitrogen is not introduced for doping during the preparation of the wafer to be screened, including the corresponding ingot growth and other process steps. This avoids the ability of nitrogen impurities to suppress or interfere with the ability of the wafer to bind copper impurities due to potential intrinsic defects.

[0070] Quality Judgment Criteria: This criterion is the core basis for comparing with wafer quality information. It is used to determine the decisive chemical prerequisite for the evolution of the aforementioned high vacancy sites into stable and effective oxygen-vacancy complexes based on the current material properties. It is the core quality criterion for determining whether this intrinsic defect structure can be realized. The interstitial oxygen concentration must be greater than a second preset threshold, which defines a high oxygen concentration level that is conducive to the formation of effective gettering centers such as stable oxygen-vacancy complexes.

[0071] Thus, the two standards form a complete logical chain: the traceability matching standard judges "whether it is possible to manufacture" (high vacancy, no interference), while the quality judgment standard judges "whether the key raw materials are sufficient", that is, whether the oxygen concentration meets the standard. Only by combining the two can we reliably determine whether the wafer to be screened has intrinsic defect structure.

[0072] In at least one embodiment of this disclosure, the gettering capability judgment criteria defined in step S200 include threshold values ​​for key parameters. Specifically, the first preset threshold corresponds to the axial position distance of the wafer to be screened on the corresponding ingot, and its value is less than or equal to 10 cm; the second preset threshold corresponds to the interstitial oxygen concentration of the wafer to be screened, for example, measured using the ASTM F121 standard, and its value is greater than or equal to 14 ppm.

[0073] In the embodiments provided in this disclosure, the term "satisfy" may include, in the context of numerical comparison, the case of being equal to a threshold, or may be strictly limited to being greater than or less than, depending on the actual definition.

[0074] For example, the axial distance between the wafer to be screened and the corresponding ingot is any one of 10 cm, 9.5 cm, 9 cm, 8.5 cm, 8 cm, 7.5 cm, 7 cm, 6.5 cm, 6 cm, 5.5 cm, 5 cm, 4.5 cm, 3 cm, 2.5 cm, 2 cm, 1.5 cm, 1 cm, 0.5 cm, etc.

[0075] For example, the interstitial oxygen concentration of the wafer to be screened, measured according to ASTM F121 standard, is any one of 14ppm, 14.5ppm, 15ppm, 15.5ppm, 16ppm, 16.5ppm, 17ppm, 17.5ppm, 18ppm, 18.5ppm, 19ppm, 19.5ppm, 20ppm, etc.

[0076] These threshold definitions determine that the wafers to be screened originate from the V-Rich region, i.e., have high vacancy rates (also known as high vacancy concentrations). Under interstitial oxygen concentrations that meet a second preset threshold, oxygen-vacancy complexes are formed. Furthermore, under non-nitrogen growth processes, the ability of these oxygen-vacancy complexes to confine impurities remains unaffected; they possess the ability to confine copper impurities. For example, in the heat treatment process mentioned later, they can chemically interact with copper impurities, such as forming copper silicides, effectively confining the copper impurities within the wafer and thus significantly suppressing the thermally induced diffusion of copper impurities to the surface active regions.

[0077] It should be noted that the first and second preset thresholds mentioned above in the embodiments of this disclosure are preferred values ​​verified by experiments, and they have a certain degree of adjustability in practical applications. For example, the first preset threshold can be explored and optimized within a first range, such as 8 cm to 15 cm, based on specific growth conditions such as ingot diameter and cooling curve. The second preset threshold is based on a specific measurement standard, and its equivalent value may fluctuate slightly if the calibration method is different. Its core is to define a "relatively high" oxygen concentration level, and the equivalent range can be within a second range, such as 13 ppm to 16 ppm. In addition, the quality judgment criteria may also include other parameter standards, such as the minority carrier lifetime of the wafer to be screened being lower than a third preset threshold, such as 10 microseconds, or the density of crystal native particle defects of a preset size within a preset range. For example, the density of crystal native particle defects with a size between 17 nanometers and 60 nanometers is within 2 × 10⁻⁶. 7 cm -3 Up to 2.5×10 8 cm -3Within this range. All of the above can be designed according to actual needs, and will not be elaborated upon here.

[0078] In order to optimize the logical rigor and execution efficiency of the judgment process, the following embodiments of this disclosure adopt a hierarchical judgment logic for the judgment of step S200.

[0079] For example, in at least one embodiment of this disclosure, in step S200, based on wafer traceability information and a preset getter capability judgment standard, it is determined whether the wafer to be screened possesses intrinsic getter capability, such as... Figure 2 As shown, it includes the following steps S201 to S201d.

[0080] Step S201: Compare the wafer traceability information with the traceability matching standard to determine whether the wafer to be screened meets the traceability matching standard.

[0081] Specifically, the comparison in step S201 refers to performing a logical OR operation, that is, comparing the axial position distance and process growth conditions in the obtained wafer traceability information with the preset thresholds and conditions in the traceability matching criteria. To meet the traceability matching criteria, the following must be met simultaneously: 1) The axial position distance of the wafer to be screened is less than or equal to the first preset threshold, for example, 10 cm; 2) The ingot corresponding to the wafer to be screened is grown using a non-nitrogen-doped process.

[0082] Step S201a: If the condition is not met, it is determined that the wafer to be screened does not have intrinsic gettering capability.

[0083] Specifically, lacking intrinsic gettering capability refers to a negative conclusion drawn based on the current judgment logic. This means that the growth history of the wafer to be screened, such as an axial position distance exceeding a first preset threshold or originating from at least one of nitrogen-doped ingots, does not meet the basis for forming an intrinsic defect structure with effective copper binding capability.

[0084] Step S201b: If satisfied, compare the wafer traceability information with the quality judgment criteria to determine whether the wafer to be screened meets the quality judgment criteria.

[0085] Specifically, this step is the next layer of judgment logic initiated after a positive conclusion is reached in step S201. The core of this comparison operation is to compare the interstitial oxygen concentration in the wafer traceability information with the quality judgment standard to determine whether the interstitial oxygen concentration of the wafer to be screened is greater than the second preset threshold.

[0086] Step S201c: If the condition is not met, it is determined that the wafer to be screened does not have intrinsic gettering capability.

[0087] Specifically, failing to meet the quality judgment criteria means that the interstitial oxygen concentration of the wafer to be screened is not greater than or equal to the second preset threshold. This indicates that even if the wafer to be screened meets the traceability matching criteria, its current material state does not support the formation of stable, active oxygen-vacancy complexes or other effective gettering centers. Specifically, it is determined whether its interstitial oxygen concentration is greater than or equal to 14 ppm.

[0088] Step S201d: If the condition is met, then the wafer to be screened is determined to have intrinsic gettering capability.

[0089] Therefore, steps S201 to S201d constitute a rigorous collaborative judgment chain. The comprehensive traceability information obtained in step S201 provides precise input for subsequent judgments, and its cooperation with step S201a achieves efficient front-end filtering. It serves as a rapid termination and output stage for wafers that do not meet the traceability matching criteria, thus achieving logic short-circuit optimization and avoiding unnecessary subsequent processing of obviously unqualified wafers, thereby significantly improving the average efficiency of large-scale screening. Steps S201b and S201c then perform precise verification of key material properties. Finally, step S201d confirms the wafers that have passed all verifications.

[0090] Thus, this design enables the screening method provided in this disclosure to efficiently and accurately identify wafers from the wafer population to be screened that are rich in specific intrinsic defect structures due to their special growth history and inherent high oxygen characteristics. This lays the foundation for subsequently using their intrinsic characteristics to suppress copper diffusion, and together achieves the technical effect of replacing the traditional complex gettering process.

[0091] Based on the above embodiments, at least one embodiment of this disclosure provides a wafer screening method, such as... Figure 3 As shown, the method includes steps S10 to S20d.

[0092] Step S10: Obtain the wafer traceability information and preset getter capability judgment criteria for the wafers to be screened. The wafer traceability information includes wafer source information and wafer quality information, and the getter capability judgment criteria include source matching criteria and quality judgment criteria.

[0093] Step S20: Compare the wafer traceability information with the traceability matching criteria to determine whether the wafer to be screened meets the traceability matching criteria.

[0094] Step S20a: If the condition is not met, it is determined that the wafer to be screened does not have intrinsic gettering capability.

[0095] Step S20b: If the criteria are met, compare the wafer traceability information with the quality judgment criteria to determine whether the wafer to be screened meets the quality judgment criteria.

[0096] Step S20c: If the condition is not met, it is determined that the wafer to be screened does not have intrinsic gettering capability.

[0097] Step S20d: If the condition is met, then the wafer to be screened is determined to have intrinsic gettering capability.

[0098] It should be noted that the logical order of comparing the wafer traceability information of the wafer to be screened with different judgment criteria in the above method can be adjusted according to actual needs. The specific implementation of steps S10 to S20d can be referred to the above embodiments, and will not be repeated here.

[0099] Based on the above embodiments, at least one embodiment of this disclosure provides a wafer screening method, such as... Figure 4 As shown, the method includes steps S010 to S030d.

[0100] Step S010: Obtain the axial position distance of the wafer to be screened on the corresponding ingot, the process growth conditions of the ingot corresponding to the wafer to be screened, and the interstitial oxygen concentration of the wafer to be screened.

[0101] Step S020: Determine whether the axial distance between the wafer to be screened and the corresponding ingot is less than or equal to the first preset threshold.

[0102] Step S020a: If not, then determine that the wafer to be screened does not have intrinsic gettering capability.

[0103] Step S020b: If yes, determine whether the process growth conditions of the ingot corresponding to the wafer to be screened are non-nitrogen-doped process conditions.

[0104] Step S020c: If not, then determine that the wafer to be screened does not have intrinsic gettering capability.

[0105] Step S020d: If so, determine whether the interstitial oxygen concentration of the wafer to be screened is greater than or equal to the second preset threshold.

[0106] Step S020e: If not, then determine that the wafer to be screened does not have intrinsic gettering capability.

[0107] Step S020f: If yes, then determine that the wafer to be screened has intrinsic gettering capability.

[0108] It should be noted that the logical order between different judgment steps corresponding to different wafer traceability information of the wafer to be screened in the above method can be adjusted according to actual needs. The specific implementation of steps S010 to S020f can be referred to the above embodiments, and will not be repeated here.

[0109] Those skilled in the art can easily combine the hierarchical judgment process in this embodiment with the aforementioned specific threshold standards. This combination can simultaneously achieve high accuracy, high robustness, and high efficiency in screening, which should also fall within the protection scope of this invention.

[0110] In at least one embodiment of the wafer processing method provided in this disclosure, such as Figure 5 As shown, the processing method includes the following steps S01 to S02.

[0111] Step S01: Obtain the wafer to be processed, wherein the wafer to be processed is a wafer with intrinsic gettering capability obtained by the screening method in the first aspect described above.

[0112] Specifically, the wafer to be processed in this step refers to a wafer that has been identified and marked as having intrinsic gettering capability by the screening method in the aforementioned embodiments. This means that the wafer has been confirmed to originate from the head region of an ingot grown using a non-nitrogen-doped process (axial position less than or equal to a first preset threshold, such as 10 cm, and its interstitial oxygen concentration greater than or equal to a second preset threshold, such as 14 ppm).

[0113] Step S02: Based on preset conditions, perform heat treatment on the wafer to be processed, wherein the heat treatment is configured to activate the intrinsic defect structure of the wafer to be processed to bind copper impurities.

[0114] Specifically, the heat treatment in step S02 refers to the process of heating the wafer to be processed to a specific temperature and holding it for a certain period of time in a controlled atmosphere, such as an inert gas or a vacuum. Its purpose is not to introduce new defects, but to provide the necessary energy for the specific physicochemical processes already existing within the wafer—that is, the intrinsic defect structures that bind copper impurities.

[0115] Limiting the preset conditions for heat treatment is to ensure that the intrinsic defect structure of the wafer to be treated has sufficient migration activity to form a stable composite structure such as a vacancy-copper complex with copper impurities, while also avoiding excessive temperature that could lead to the dissociation of the vacancy-copper complex or changes in the crystal structure.

[0116] Therefore, step S01 serves as the "object preparation and qualification verification" stage in the entire processing flow. The core purpose of this step is to ensure that the objects of subsequent functional processing are scientifically identified wafer groups possessing intrinsic gettering capabilities. Through this step, a precise connection is achieved from "screening and classification" to "targeted processing," laying the necessary material foundation for subsequent steps to effectively activate and utilize the intrinsic gettering characteristics of the wafers themselves.

[0117] Step S02 is the core step in "functional activation and performance realization." The technical principle of this step is that, within an optimized temperature-time window, heat treatment provides sufficient migration kinetic energy for copper impurities, allowing them to move within the crystal lattice; simultaneously, it enhances the reactivity of intrinsic defect structures in the wafer to be treated. The combination of these two factors significantly increases the probability of copper impurities being captured and firmly bound by defects. For example, intrinsic defect structures in the wafer to be treated, such as the oxygen-vacancy complex mentioned above, interact with copper impurities, forming copper silicides, thereby capturing and fixing them within the wafer, preventing their migration to the surface, and thus binding the copper impurities. By performing this step, the wafer to be treated exhibits a significantly reduced surface copper impurity concentration in subsequent processes, achieving the technical effect of efficiently suppressing copper contamination without introducing an additional defect layer.

[0118] Furthermore, compared to existing getter technologies that require additional high-temperature process steps to actively construct defect trap layers, resulting in high thermal budgets, the processing method provided in this disclosure eliminates all thermal process steps for constructing trap layers by directly screening and utilizing the intrinsic defect structure of the wafer. Only a relatively mild thermal treatment, such as the 550°C to 620°C range mentioned below, is required on the selected wafers to activate their intrinsic getter capabilities. This significantly reduces the overall thermal budget of the manufacturing process, aligning better with the trend of reducing thermal history and thermal damage in advanced semiconductor manufacturing.

[0119] In at least one embodiment of this disclosure, the preset conditions include a heat treatment temperature in the range of 550°C to 620°C and a treatment time in the range of 1 hour to 4 hours.

[0120] For example, the heat treatment temperature is any one of 550°C, 560°C, 570°C, 580°C, 590°C, 600°C, 610°C, 620°C, etc.

[0121] For example, the heat treatment time is any one of 1 hour, 1.5 hours, 2 hours, 2.5 hours, 3 hours, 3.5 hours, 4 hours, etc.

[0122] For example, the heat treatment temperature and time range can be selected and adapted according to specific production requirements, equipment capabilities, and thermal budget requirements. For instance, in scenarios where the thermal budget needs to be minimized, a temperature close to 550°C can be selected with a correspondingly extended processing time; while in scenarios requiring rapid processing, a temperature close to 620°C can be selected with a shorter time. Regardless of the specific parameter combination used within this range, the core principle is to provide adequate thermal energy to activate and utilize the wafer's intrinsic gettering ability, thereby suppressing the diffusion of copper impurities to the surface.

[0123] To clearly demonstrate the correspondence between different heat treatment process conditions, expected effects, applicable scenarios, and consideration factors, the following Table 1 can be used for explanation.

[0124] Table 1 Examples of Heat Treatment Process Parameters and Effects As illustrated in the examples above, by adjusting the combination of heat treatment temperature and time within the process window established in this disclosure embodiment, different production needs such as "low thermal budget," "high efficiency," or "rapid processing" can be flexibly addressed. This allows for targeted process optimization while ensuring the core functions of activating the intrinsic getter capability of the wafer and effectively suppressing copper impurities. This demonstrates that the processing method provided by this disclosure embodiment possesses both clear technical principles and good engineering adaptability.

[0125] It should be noted that the parameters in Table 1 above are all based on experimental verification and are intended to illustrate how to optimize the selection within the process window disclosed in this embodiment to adapt to different production needs and constraints. Those skilled in the art should understand that these specific examples are not intended to limit the scope of protection, but rather to further illustrate the operability of the aforementioned process range.

[0126] This disclosure also provides a wafer obtained by the processing method described in the above embodiments, wherein the surface copper impurity concentration of the wafer is 1.0 × 10⁻⁶. 7 atoms / cm 2 Up to 1.5×10 8 atoms / cm 2 Within the range.

[0127] Thus, the wafer has undergone the screening and processing methods provided in this disclosure, specifically screening out wafers with intrinsic gettering capabilities and performing targeted heat treatment to activate the wafer, so that the intrinsic defect structure in the wafer binds the copper impurities in the wafer, thereby effectively suppressing the surface copper impurity concentration of the wafer.

[0128] Furthermore, the features of the wafers provided in this disclosure are a direct result and manifestation of their special screening and processing methods, distinguishing them from wafers prepared by conventional active getter processes, as well as from ordinary wafers that have not undergone screening and processing. Such wafers can provide higher intrinsic reliability when used in the manufacture of advanced semiconductor devices sensitive to copper contamination.

[0129] For example, the surface copper impurity concentration of the wafer is 1.0 × 10⁻⁶. 7 atoms / cm 2 2.0×10 7 atoms / cm 2 3.0×107 atoms / cm 2 4.37×10 7 atoms / cm 2 5.0×10 7 atoms / cm 2 6.82×10 7 atoms / cm 2 8.0×10 7 atoms / cm 2 9.57×10 7 atoms / cm2, 1.0×10 8 atoms / cm 2 1.1×10 8 atoms / cm 2 1.3×10 8 atoms / cm 2 1.44×10 8 atoms / cm 2 1.5×10 8 atoms / cm 2 Any one of them.

[0130] In at least one embodiment of this disclosure, the surface copper impurity concentration of the heat-treated wafer is 1.0 × 10⁻⁶. 7 atoms / cm 2 Up to 1.0×10 8 atoms / cm 2 Within the range.

[0131] To verify and fully disclose the correctness, repeatability, and technical effectiveness of the wafer screening method provided in the embodiments of this disclosure, a detailed description is provided below in conjunction with specific experimental data. All embodiments and comparative examples are based on actual semiconductor wafer manufacturing processes, and the conditions, parameters, and results described can be reproduced and verified by those skilled in the art.

[0132] Example 1: The purpose is to verify that only wafers that meet the gettering ability judgment criteria corresponding to the screening method can exhibit copper diffusion suppression ability after being processed by the methods in the above-mentioned embodiment set.

[0133] Sample selection: A polished wafer from the head of a single-crystal silicon ingot grown using a non-nitrogen-doped process was selected as the object to be screened and processed.

[0134] Specifically, the axial distance of the wafer on the corresponding ingot, i.e., from the lead end, is 8.66 cm, which is less than the first preset threshold of 10 cm. The crystal region of the wafer is identified as "P-band (Near V-Rich)" by microwave photoconductivity attenuation spectrum analysis, i.e., close to the V-Rich region.

[0135] Using Fourier transform infrared spectroscopy, specifically according to ASTM F121 standard, the interstitial oxygen concentration of the wafer was measured to be 14.60 ppm.

[0136] The resistivity of the corresponding sister wafers, i.e. wafers from the same ingot location, was measured to be 20.27 Ω·cm.

[0137] Screening and verification process: First, obtain the wafer traceability information of the wafer, which includes wafer origin information and wafer quality information. The wafer origin information includes the axial position distance of the wafer on the corresponding ingot, such as 8.66 cm and the growth process, i.e., non-nitrogen doped. The wafer quality information includes the interstitial oxygen concentration of the wafer, i.e., 14.60 ppm.

[0138] Then, the wafer traceability information is compared with the preset getter capability judgment criteria. Since it meets the following criteria: axial position < first preset threshold 10 cm satisfies the traceability matching standard, and interstitial oxygen concentration > second preset threshold 14 ppm satisfies the quality judgment standard, the wafer is judged to have intrinsic getter capability and is marked as a wafer with intrinsic getter capability.

[0139] Then, the wafers marked as having intrinsic getter capability are subjected to heat treatment. The process conditions are: temperature 580℃, time 2 hours.

[0140] After heat treatment, the results are tested. Specifically, the copper concentration on the wafer surface, i.e. the copper impurities diffused to the surface, is determined by acid pickling-inductively coupled plasma mass spectrometry.

[0141] Data Results: After heat treatment, the surface diffusion copper impurity concentration of the wafer was 6.82 × 10⁻⁶. 7 atoms / cm 2 The calculated concentration of copper impurities diffused from the body was 1.77 × 10⁻⁶. 9 atoms / cm 2 After cleaning, the concentration of copper impurities in the body was 1.51 × 10⁻⁶. 8 atoms / cm 2 The overall copper impurity concentration was 1.92 × 10⁻⁶. 9 atoms / cm 2 .

[0142] Therefore, this embodiment demonstrates that wafers identified as having intrinsic getter capability by the screening method of this application exhibit extremely low copper diffusion on their surface after heat treatment at 580℃ for 2 hours, specifically within 10%. 7 atoms / cm 2 The magnitude of the sample effectively verifies that the wafers selected by this method with intrinsic gettering ability can indeed use their intrinsic defect structure to suppress the diffusion of copper impurities to their surface, and that the selection method is correct and effective.

[0143] Example 2: This embodiment aims to repeatedly verify the conclusions of Example 1 using multiple samples, demonstrating the repeatability and universality of the corresponding screening criteria, namely the traceability matching criteria and the quality judgment criteria.

[0144] Sample selection: Three polished wafers from the V-Rich region of the ingot, all clearly derived from non-nitrogen-doped growth processes, were selected. Their specific wafer traceability information is as follows: Sample A: Axial position 8.87 cm, interstitial oxygen concentration 14.53 ppm, resistivity 11.29 Ω·cm.

[0145] Sample B: Axial position 7.72 cm, interstitial oxygen concentration 14.33 ppm, resistivity 11.40 Ω·cm.

[0146] Sample C: Axial position 8.87 cm, interstitial oxygen concentration 14.05 ppm, resistivity 11.28 Ω·cm.

[0147] Screening and verification process: The specific process is the same as in Example 1. All three wafers are determined to have intrinsic gettering capability based on their traceability information, that is, they all meet the non-nitrogen growth conditions, axial position <10cm and interstitial oxygen concentration >14ppm, and all are subjected to heat treatment under preset conditions of 580℃ / 2h.

[0148] Data Results: After heat treatment, the surface diffusion copper concentrations of the three wafers, sample A, sample B, and sample C, were 9.57 × 10⁻⁶ and 9.57 × 10⁻⁶, respectively. 7 atoms / cm 2 4.37×10 7 atoms / cm 2 1.44×10 8 atoms / cm 2 The corresponding copper impurity concentrations in its sister wafers are 2.75 × 10⁻⁶. 9 atoms / cm 2 1.50E×10 9atoms / cm 2 3.58E×10 9 atoms / cm 2 That is, the total copper content in the corresponding sister films is also at 10. 9 atoms / cm 2 Magnitude.

[0149] Therefore, it can be seen that the three groups of wafers, located at different positions but all meeting the screening criteria of this application (i.e., the traceability matching criteria and the quality judgment criteria), originating from the V-Rich region, all exhibited stable and low surface copper diffusion levels after the same heat treatment, specifically at 10 7 ~10 8 atoms / cm 2 The magnitude of this demonstrates that the screening criteria used in this application, namely the getter capability judgment criteria, are repeatable and universal, and can reliably identify wafers with intrinsic getter capability.

[0150] Example 3: This example serves as a comparative example, aiming to highlight the unique advantages of V-Rich regions in suppressing copper diffusion by comparing it with Examples 1 and 2, using wafers originating from non-V-Rich regions as a control, thereby demonstrating the necessity of screening.

[0151] Sample selection: Three polished wafers, labeled as non-V-Rich regions (e.g., P-band, PV, and PI regions respectively), were selected as controls.

[0152] The wafer traceability information shows that although they may meet the non-nitrogen-doped conditions, the corresponding axial distances are all much greater than the first preset threshold of 10 cm, and the interstitial oxygen concentrations are all lower than the second preset threshold of 14 ppm. The specific information is as follows: P-band region sample: axial position 207.87 cm, interstitial oxygen concentration 11.16 ppm, resistivity 11.56 Ω / cm -3 .

[0153] PV region sample: axial position 88.79 cm, interstitial oxygen concentration 10.38 ppm, resistivity 10.38 Ω / cm -3 .

[0154] PI region sample: axial position 169.31 cm, interstitial oxygen concentration 10.84 ppm, resistivity 10.84 Ω / cm -3 .

[0155] Processing flow: All three wafers were subjected to the same heat treatment at 580°C for 2 hours, as described in Example 1, and will not be repeated here.

[0156] Data Results: After heat treatment, the surface diffusion copper concentrations of the three control wafers (P-band, PV, and PI regions) reached as high as 8.57 × 10⁻⁶. 8 atoms / cm 2 3.49×10 8 atoms / cm 2 2.01×10 9 atoms / cm 2 The corresponding sister films had copper impurity concentrations as high as 3.62 × 10⁻⁶. 10 atoms / cm 2 9.76×10 9 atoms / cm 2 6.70×10 10 atoms / cm 2 That is, the total amount of copper in its body is as high as 10. 10 atoms / cm 2 Magnitude.

[0157] Therefore, compared with the wafers with intrinsic gettering ability originating from the V-Rich region selected in Examples 1 and 2, these wafers originating from non-V-Rich regions, which do not meet the screening criteria (i.e., the gettering ability judgment criteria), especially those with substandard axial distance and interstitial oxygen concentration on the corresponding ingots, exhibit a 1 to 2 order of magnitude higher surface copper impurity diffusion after heat treatment. This comparative data directly demonstrates quantitatively that without the screening method provided in this disclosure, conventional wafers have a much higher risk of copper contamination after heat treatment, thus highlighting the value and correctness of the screening method of this disclosure in identifying high-quality anti-contamination materials.

[0158] Example 4: This example serves as a comparative example, aiming to verify the necessity of the "non-nitrogen-doped process" condition in the traceability matching standard, and to demonstrate that the nitrogen-doped process would disrupt the consistent effect of the wafer originating from the V-Rich region and meeting the requirements for interstitial oxygen concentration on copper impurities.

[0159] Sample selection: Select a wafer marked as grown using a nitrogen-doped process, with an axial distance of 5.52 cm (<10 cm) at the head of the ingot.

[0160] Screening and verification process: The specific process is the same as in Example 1. If the screening method of this application is applied, since the process growth conditions of this wafer are "nitrogen doping", it does not meet the traceability matching standard, so it should be judged as not having intrinsic gettering ability and marked as other wafers.

[0161] The wafer was subjected to a heat treatment at 580°C for 2 hours, as described in Example 1, and will not be repeated here.

[0162] Data Results: After heat treatment, the surface diffusion copper concentration of this nitrogen-doped wafer reached as high as 1.52 × 10⁻⁶. 9 atoms / cm 2 The total internal copper content is as high as 4.95 × 10⁻⁶. 10 atoms / cm 2 This is one of the highest values ​​among all samples.

[0163] Therefore, even if the wafer is taken from the head of the ingot and the interstitial oxygen concentration meets the requirements, its resistance to copper diffusion is completely ineffective because it originates from a nitrogen-doped ingot. The surface copper concentration is even higher than that of many samples in non-V-Rich regions. This embodiment conclusively proves that "non-nitrogen-doped process" is a key prerequisite for the existence of intrinsic gettering ability, thereby verifying the correctness and necessity of using "non-nitrogen-doped" as one of the core conditions for traceability matching in the screening method of this application.

[0164] Example 5: This embodiment aims to analyze and demonstrate that the effect discovered by the present invention is independent of "high resistivity," a common factor that may lead to low copper content, and is an independent verification of excluding high resistivity factors.

[0165] Phenomena and Data Analysis: In Examples 1 and 2, the selected wafers with characterization capabilities exhibited high resistivity, specifically 20.27 Ω·cm in Example 1 and 11.29 Ω·cm - 11.40 Ω·cm in Example 2. It is known that high-resistivity silicon materials may inherently have low initial metallic impurity content.

[0166] However, the surface copper diffusion data of Examples 1 and 2, specifically in 10 7 -10 8 atoms / cm 2 The magnitude is similar to that of the wafer in Example 3, which also has high resistivity but is located in the non-V-Rich region, specifically in 10 8 -10 9 atoms / cm 2 A comparison of magnitudes revealed that the latter exhibited significantly higher surface copper diffusion.

[0167] Therefore, the screening method provided in this disclosure, which identifies wafers with intrinsic gettering capabilities originating from the V-Rich region, demonstrates an enhanced ability to suppress copper impurity diffusion. This ability is a further enhancement of the generally low background copper content of high-resistivity wafers. This screening method can identify individuals with even stronger copper binding capabilities within high-resistivity materials, thus providing a more refined and effective control dimension than simply relying on high resistivity. This demonstrates the independence and advancement of the screening method provided in this disclosure.

[0168] In summary, the above series of embodiments fully and clearly disclose the implementation steps, specific parameters, and verification results of the screening and processing methods provided in this disclosure. Embodiments 1 and 2 demonstrate the effectiveness of the above methods with positive data; Embodiments 3 and 4, as key comparative examples, reveal the consequences of not meeting the getter-attracting ability judgment criteria, especially axial position distance, interstitial oxygen concentration, and non-nitrogen-doped conditions, through comparative data, thus confirming the scientific nature of the getter-attracting ability judgment criteria in this screening method; Embodiment 5 identifies and confirms the independence of the above method effects. All embodiments together constitute the technical factual basis supporting the claims, and those skilled in the art can reproduce and verify the technical effects of the present invention without creative effort based on the description therein.

[0169] This disclosure also provides a wafer screening device, such as... Figure 6 As shown, the screening device 100 includes an acquisition module 110, a judgment module 120, and an execution module 130. The acquisition module 110 is configured to acquire wafer traceability information of the wafer to be screened; the judgment module 120 is configured to determine whether the wafer to be screened has intrinsic getter capability based on the wafer traceability information and a preset getter capability judgment standard, wherein intrinsic getter capability refers to the ability of the wafer to be screened to use the intrinsic defect structure naturally formed during its growth process to bind copper impurities; the execution module 130 is configured to mark the wafer to be screened as a wafer with intrinsic getter capability if the judgment is yes, and mark the wafer to be screened as another wafer if the judgment is no.

[0170] In at least one embodiment of this disclosure, the judgment module 120 is configured to compare the wafer traceability information with the traceability matching standard to determine whether the wafer to be screened meets the traceability matching standard.

[0171] In at least one embodiment of this disclosure, the execution module 130 is configured to: if the condition is not met, determine that the wafer to be screened does not have intrinsic getter capability; if the condition is met, compare the wafer traceability information with the quality judgment standard to determine whether the wafer to be screened meets the quality judgment standard; if the condition is not met, determine that the wafer to be screened does not have intrinsic getter capability; if the condition is met, determine that the wafer to be screened has intrinsic getter capability.

[0172] Specifically, in the software implementation, this is manifested as a nested conditional judgment structure. The judgment module 120 first extracts the axial position distance and process growth condition fields from the traceability information and compares them with preset traceability matching standards, such as axial position distance ≤ a first preset threshold and the process being non-nitrogen-doped. If the comparison result is false, it immediately returns an instruction "Does not possess intrinsic gettering capability" to the execution module 130. Only when the comparison result is true will it continue to extract the interstitial oxygen concentration field and compare it with the quality judgment standard, i.e., interstitial oxygen concentration ≥ a second preset threshold, and return the final instruction based on the result. Those skilled in the art will understand that in some implementations, if all traceability information has been pre-acquired and stored, this process mainly optimizes the logical sequence; if some information, such as interstitial oxygen concentration, requires time-consuming measurement, this process can save actual measurement time and cost.

[0173] Therefore, this device can automate and standardize the screening process, ensuring consistency and efficiency in judgment. Furthermore, the functions of each module correspond to the aforementioned method steps, and will not be repeated here.

[0174] To more clearly demonstrate how the screening methods provided in this disclosure operate and create value in a real-world industrial environment, the following dynamic description is provided using epitaxial substrate wafer shipment inspection as a specific scenario.

[0175] On a certain high-voltage device production line, gate oxide integrity is extremely sensitive to metal contamination. In the traditional process, all wafers used as inputs to the current process require an additional back-side argon ion implantation and annealing process to form a getter layer. This step requires a dedicated ion implantation machine, takes approximately 30 minutes per batch, and adds about 800°C / 1 hour to the thermal budget.

[0176] The process was optimized by introducing the screening method provided by Benbenkai. Firstly, in the wafer incoming inspection stage, integrated technologies such as... Figure 6The screening device shown has an automatic screening system. The system reads the ID of each wafer and obtains its wafer traceability information from the extended data package provided by the supplier, specifically including "axial position distance", "growth process (nitrogen doping status)" and "interstitial oxygen concentration" data. The system's built-in judgment logic runs automatically: for wafers with an axial position distance greater than a first preset threshold, such as 10 cm, or marked as nitrogen-doped, the system directly marks them as "other wafers" or "conventional wafers" and directs them to the original back-side getter process branch. For wafers with an axial position distance less than or equal to the first preset threshold, such as 10 cm, and not nitrogen-doped, the system further checks their interstitial oxygen concentration. If it is greater than or equal to a second preset threshold, such as 14 ppm, it is marked as "intrinsic getter wafer"; otherwise, it is also marked as "other wafers" or "conventional wafer".

[0177] For wafers labeled as "intrinsic getter wafers," the subsequent processing flow is simplified. They skip the expensive backside ion implantation step and proceed directly to the conventional cleaning and gate oxide growth sequence. During the preheating stage before gate oxide growth or during a mid-field heat treatment stage (e.g., at a heat treatment temperature of 580°C for 2 hours), the pre-existing intrinsic defect structures originating from the V-Rich region within the wafer are activated, effectively confining any copper impurities that may be present within the wafer.

[0178] In this scenario, the screening method provided in this disclosure brings quantifiable improvements: First, for the "intrinsic getter wafers" that account for approximately 15%-20% of the incoming materials, the back-side getter process is completely eliminated, saving corresponding machine time, energy consumption, and material costs such as argon. Second, by avoiding back-side damage, particle contamination, and thermal stress that may be caused by ion implantation, the overall quality baseline of this batch of wafers is more uniform. In subsequent gate oxide integrity testing, the distribution of their collapse charge density shows better tail-end characteristics, and the yield is expected to improve by 0.5%-1%. Finally, from the perspective of product reliability, using the intrinsic defects of the wafer itself for gettering avoids the risk of externally introduced defects evolving under long-term use or stress testing, which helps to improve the long-term reliability of the device.

[0179] This disclosure also provides a computing device, such as... Figure 7 As shown, the computing device 200 includes a processor 210 and a memory 220. The processor 210 is used to execute instructions, such as applications, stored in the memory 220 to implement the filtering method in the above embodiments.

[0180] In at least one embodiment of this invention, the computing device 200 includes one or more processors 210. The application program stored in the memory 220 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processors 210 are configured to execute instructions to perform the filtering method described in the above embodiments.

[0181] In at least one embodiment of this invention, the computing device 200 may further include a power supply component configured to perform power management of the computing device 200, a wired or wireless network interface configured to connect the computing device 200 to a network, and an input / output (I / O) interface. The computing device 200 may operate on an operating system stored in memory 220, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, or similar.

[0182] This disclosure provides a computer storage medium storing at least one instruction, which is executed by the processor 210 of the computing device 200 to implement the filtering method described in the above embodiments.

[0183] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0184] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0185] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0186] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0187] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0188] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program verification codes, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0189] Furthermore, it should be noted that the combination of the various technical features in this case is not limited to the combination methods described in the claims of this case or the combination methods described in the specific embodiments. All technical features described in this case can be freely combined or combined in any way, unless they contradict each other.

[0190] It should be noted that the above examples are merely specific embodiments of the present invention, and the present invention is obviously not limited to the above embodiments, with many similar variations. All modifications that can be directly derived or conceived by those skilled in the art from the content disclosed in this invention should fall within the protection scope of this invention.

[0191] It should be understood that the terms "first," "second," etc., mentioned in the embodiments of the present invention are merely for the purpose of more clearly describing the use of the technical solutions in the embodiments of the present invention, and are not intended to limit the scope of protection of the present invention.

[0192] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications or equivalent substitutions made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for screening wafers, characterized in that, include: Obtain wafer traceability information for the wafers to be screened; Based on the wafer traceability information and the preset getter capability judgment criteria, it is determined whether the wafer to be screened has intrinsic getter capability, wherein the intrinsic getter capability refers to the ability of the wafer to be screened to use the intrinsic defect structure naturally formed during its growth process to bind copper impurities. If the determination is yes, then the wafer to be screened is marked as a wafer with intrinsic gettering capability; If the determination is negative, the wafer to be screened is marked as another wafer.

2. The screening method according to claim 1, characterized in that, The wafer traceability information includes wafer origination information and wafer quality information; The wafer traceability information includes at least the axial position distance of the wafer to be screened on the corresponding ingot and the process growth conditions of the ingot corresponding to the wafer to be screened. The wafer quality information includes at least the interstitial oxygen concentration of the wafer to be screened.

3. The screening method according to claim 1 or 2, characterized in that, The criteria for judging gettering ability include traceability matching criteria and quality judgment criteria; The traceability matching standard is used as the basis for comparing and matching with the wafer traceability information, and the quality judgment standard is used as the basis for judging by comparing and judging with the wafer quality information.

4. The screening method according to claim 3, characterized in that, The traceability matching criteria include that the axial position of the wafer to be screened on the corresponding ingot is less than or equal to a first preset threshold, and the growth process conditions of the ingot corresponding to the wafer to be screened include non-nitrogen-doped process conditions. The quality judgment criteria include that the interstitial oxygen concentration of the wafer to be screened is greater than or equal to a second preset threshold.

5. The screening method according to claim 4, characterized in that, The first preset threshold is less than or equal to 10 cm, and the second preset threshold is greater than or equal to 14 ppm.

6. The screening method according to claim 3, characterized in that, The determination of whether the wafer to be screened possesses intrinsic getter capability based on the wafer traceability information and a preset getter capability judgment standard includes: The wafer traceability information is compared with the traceability matching criteria to determine whether the wafer to be screened meets the traceability matching criteria. If the conditions are not met, the wafer to be screened is determined to lack intrinsic gettering capability. If the criteria are met, the wafer traceability information is compared with the quality judgment criteria to determine whether the wafer to be screened meets the quality judgment criteria. If the conditions are not met, the wafer to be screened is determined to lack intrinsic gettering capability. If the conditions are met, the wafer to be screened is determined to have intrinsic gettering capability.

7. A method for processing a wafer, characterized in that, include: Obtain a wafer to be processed, wherein the wafer to be processed is a wafer with intrinsic gettering capability obtained by screening using the screening method according to any one of claims 1 to 6; Based on preset conditions, the wafer to be processed is subjected to heat treatment, wherein the heat treatment is configured to activate the intrinsic defect structure of the wafer to be processed to bind copper impurities.

8. A wafer, characterized in that, The wafer is obtained by the processing method of claim 7, wherein the wafer has a surface copper impurity concentration in the range of 1.0 x 10 7 atoms / cm 2 - 1.0 x 10 8 atoms / cm 2 .

9. A wafer screening device, characterized in that, include: The acquisition module is configured to acquire wafer traceability information of the wafers to be screened; The judgment module is configured to determine whether the wafer to be screened has intrinsic getter capability based on the wafer traceability information and the preset getter capability judgment criteria. The intrinsic getter capability refers to the ability of the wafer to be screened to use the intrinsic defect structure naturally formed during its growth process to bind copper impurities. The execution module is configured to mark the wafer to be screened as a wafer with intrinsic getter capability if the determination is yes, and to mark the wafer to be screened as another wafer if the determination is no.

10. A computing device, characterized in that, It includes a processor and a memory, the processor being configured to execute instructions stored in the memory to implement the screening method as described in any one of claims 1 to 6.

11. A computer storage medium, characterized in that, The storage medium stores at least one instruction, which is executed by a processor to implement the filtering method as described in any one of claims 1 to 6.

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