Electronic component manufacturing method using plasma etching to remove blind via residue
By employing a multi-stage plasma etching method, combining strong and weak etching steps, the problems of over-etching of metal pads and damage to the insulating layer during the removal of blind via residues were solved, thereby improving product performance and yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- LINCO TECH CO LTD
- Filing Date
- 2024-12-18
- Publication Date
- 2026-06-23
AI Technical Summary
Existing plasma etching methods can easily lead to over-etching of metal pads, thermal damage or cracking of the insulation layer when removing blind via residues, affecting product yield.
A multi-stage plasma etching method is adopted, including strong etching and weak etching steps, which are performed by inductively coupled plasma reactive ion etching or ion source, respectively. Strong etching removes metal oxide residues, and weak etching removes oxide residues. The etching power and vacuum level are controlled to avoid damage.
It effectively removes blind hole residue, avoids over-corrosion of metal pads, heat damage or cracks in the insulation layer, and improves product performance and yield.
Smart Images
Figure CN122270133A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a method for manufacturing a semiconductor, and more particularly to a method for manufacturing electronic components using plasma etching to remove residues from blind vias. Background Technology
[0002] The rewiring process, which involves bringing the metal contacts of a chip or IC substrate outward, can change the contact position of the originally designed metal pads to suit different packaging forms or integrate them into a multi-chip package.
[0003] In the redistribution process, lasers are used to drill holes in the dielectric layer to form blind vias that allow communication between different circuit layers. However, since there are residues in the blind vias after laser drilling, plasma etching is used to clean up the residues.
[0004] Existing plasma etching methods use high-power, continuous bombardment of blind vias to completely remove residues, which can cause problems such as over-etching of metal pads, thermal damage to the insulation layer, or cracks, resulting in a decrease in product yield and urgently requiring improvement. Summary of the Invention
[0005] The purpose of this invention is to provide a multi-stage method for manufacturing electronic components by using plasma etching to remove residues from blind vias.
[0006] The present invention provides an electronic component manufacturing method for removing residues from blind vias using plasma etching. This method is applicable to processing workpieces having a patterned metal layer and an insulating layer covering the patterned metal layer. The insulating layer has a plurality of blind vias. The electronic component manufacturing method includes the following steps:
[0007] First with a high etching rate The blind via is subjected to a plasma etching step to remove residual metal oxides on the patterned metal layer. The plasma etching step employs inductively coupled plasma reactive ion etching, reactive ion etching, or an ion source.
[0008] Then with a low etching rate The blind vias are subjected to a weak plasma etching step to remove oxide residues left after the strong plasma etching step. This weak plasma etching step employs inductively coupled plasma reactive ion etching, reactive ion etching, or an ion source. Furthermore, the power used in the weak plasma etching step is lower than that used in the strong plasma etching step.
[0009] Another method for manufacturing electronic components using plasma etching to remove residue from blind vias includes:
[0010] An insulating layer is formed on a patterned metal layer on the workpiece.
[0011] The insulating layer is laser-drilled to form multiple blind holes.
[0012] With high etching rate The blind via is subjected to a plasma etching step to remove residual metal oxides within it. The plasma etching step employs inductively coupled plasma reactive ion etching, reactive ion etching, or an ion source.
[0013] Then with a low etching rate The blind vias are subjected to a weak plasma etching step to remove oxide residues left after the strong plasma etching step. This weak plasma etching step employs inductively coupled plasma reactive ion etching, reactive ion etching, or an ion source. Furthermore, the power used in the weak plasma etching step is lower than that used in the strong plasma etching step.
[0014] Following the plasma weak etching step, a patterned seed layer is deposited over the insulating layer along with the blind vias.
[0015] A patterned metal wire layer is coated on the seed layer.
[0016] The electronic component manufacturing method of the present invention uses plasma etching to remove residues from blind holes, wherein gas is intermittently blown in during either the strong plasma etching step or the weak plasma etching step.
[0017] The present invention relates to an electronic component manufacturing method that uses plasma etching to remove residues from blind holes, wherein the strong plasma etching step and the weak plasma etching step are performed in the same cavity.
[0018] The present invention relates to an electronic component manufacturing method that uses plasma etching to remove residues from blind holes, wherein the strong plasma etching step and the weak plasma etching step are performed in different cavities.
[0019] The present invention discloses an electronic component manufacturing method for removing residues from blind vias using plasma etching. The plasma strong etching step includes a first strong etching sub-step and a second strong etching sub-step, wherein the etching rate of the second strong etching sub-step is different from the etching rate of the first strong etching step.
[0020] The present invention discloses an electronic component manufacturing method for removing residues from blind vias using plasma etching. The plasma weak etching step includes a first weak etching sub-step and a second weak etching sub-step, wherein the etching rate of the second weak etching sub-step is different from the etching rate of the first weak etching step.
[0021] The present invention relates to an electronic component manufacturing method that uses plasma etching to remove residues from blind holes, wherein the second weak etching sub-step is performed in a different cavity than the first weak etching step.
[0022] The present invention relates to an electronic component manufacturing method that uses plasma etching to remove residues from blind vias, wherein the power density of the upper electrode (source) in the plasma high-intensity etching step is 0.468 W / cm². 2 The upper electrode power density of the plasma weak etching step is 0.1–0.3 W / cm². 2 .
[0023] The present invention relates to an electronic component manufacturing method that uses plasma etching to remove residues from blind vias, wherein the vacuum degree of the strong plasma etching step is 0.5 to 5 mTorr, and the vacuum degree of the weak plasma etching step is 5 to 10 mTorr.
[0024] The present invention relates to an electronic component manufacturing method that uses plasma etching to remove residues from blind vias, wherein the lower electrode (bias) power of the strong plasma etching step is greater than the lower electrode power of the weak plasma etching step.
[0025] The present invention relates to an electronic component manufacturing method that uses plasma etching to remove residues from blind vias, wherein the thickness of the oxide residues left after the plasma etching step is less than 10 μm.
[0026] The present invention relates to an electronic component manufacturing method that uses plasma etching to remove residues from blind vias, wherein the plasma high etching step has a high etching rate. The weak etching rate of the plasma weak etching step is between to between.
[0027] The present invention relates to an electronic component manufacturing method that uses plasma etching to remove residues from blind vias. In the strong plasma etching step, the metal oxide residue to be removed is aluminum oxide, and in the weak plasma etching step, the oxide residue to be removed is silicon or aluminum oxide.
[0028] The present invention relates to an electronic component manufacturing method that uses plasma etching to remove residues from blind holes, wherein the workpiece is a wafer, an IC substrate, or a printed circuit board.
[0029] The present invention relates to an electronic component manufacturing method that uses plasma etching to remove residues from blind holes, wherein the material of the patterned metal layer is one of titanium, aluminum, copper, nickel, gold, or an alloy thereof.
[0030] The beneficial effects of the present invention are as follows: by using a multi-stage etching process of strong plasma etching and weak plasma etching, the residue of the blind hole can be effectively removed, resulting in a cleaner blind hole, and avoiding problems such as over-etching of the patterned metal layer, thermal damage or cracks in the insulating layer. In subsequent processes, the contact resistance between the patterned metal layer and the blind hole can be reduced, thereby improving its conductivity and thus improving product performance and yield. Attached Figure Description
[0031] Other features and effects of the present invention will be clearly presented in the embodiments with reference to the accompanying drawings, wherein:
[0032] Figure 1 This is a flowchart of the electronic component manufacturing method of the present invention, which uses plasma etching to remove residues from blind vias; and
[0033] Figures 2 to 7 This is a schematic diagram of the structure corresponding to each step of the method. Detailed Implementation
[0034] Figure 1 This is a flowchart of an electronic component manufacturing method for removing residues from blind vias using plasma etching, as per the present invention. The electronic component manufacturing method is applicable to processing a workpiece 2, for example, but not limited to, creating a redistribution layer (RDL) on the workpiece 2. The method includes the following steps:
[0035] Step 11, in conjunction with Figure 2 An insulating buildup film 3 is applied to a patterned metal layer 21 on the workpiece 2 to form an insulating layer 31. In this embodiment, the workpiece 2 is a wafer that has undergone semiconductor wafer manufacturing and has been individually diced and transferred onto a rectangular carrier. The patterned metal layer 21 is a collection of metal pads on the wafer used as connection points, such as aluminum pads (Al pads) or copper pads (Cu pads). However, in other embodiments, the workpiece 2 can also be an IC carrier board or a printed circuit board; therefore, the material of the patterned metal layer 21 can be one of titanium, aluminum, copper, nickel, gold, or an alloy thereof. The insulating buildup film 3 is ABF (Ajinomoto Buildup Film), which mainly contains epoxy resin and inorganic fillers such as, but not limited to, silicon dioxide (SiO2) filler particles. In some variations, the insulating layer 31 can be made of materials other than the insulating buildup film 3, such as epoxy molding compound (EMC).
[0036] Step 12, in conjunction with Figure 3The insulating layer 31 is laser-drilled to form multiple blind holes 32. The bottom of each blind hole 32 is the patterned metal layer 21. When the patterned metal layer 21 comes into contact with air, it undergoes an oxidation reaction, resulting in the formation of metal oxide residues 33, such as aluminum oxide (Al2O3), at the bottom of the blind holes 32. The thickness of these metal oxide residues 33 is typically 15–30 nm.
[0037] Step 13, in conjunction with Figure 4 With a high hard etching rate Plasma etching is performed on the blind via 32 to remove the metal oxide residue 33 at the bottom of the blind via 32. Simultaneously, it etches the uneven sidewalls of the blind via 32, removing as much of the protruding silicon dioxide filler particles within the insulating reinforcement film 3 as possible. The gaps between the silicon dioxide filler particles are then replaced with other materials from the insulating reinforcement film 3 and cut flush with the sidewalls of the via, resulting in a blind via 32 with a relatively flat shape. The preferred etching rate in the plasma etching step 13 is [insert value here]. The plasma high etching step 13 can be performed using inductively coupled plasma reactive ion etching (ICP-RIE), reactive ion etching (RIE), or an ion source with a high etching rate.
[0038] The vacuum range for strong etching using ICP-RIE is 0.5–5 mTorr, and argon (Ar), helium (He), or hydrogen (H2) gas can be introduced. Under the conditions of argon introduction, a vacuum of 1 mTorr, an upper electrode (source) power of 2 kW, and a lower electrode (bias) power of 2.7 kW, the obtained etching rate is... The power density of the upper electrode is 0.468 W / cm². 2 The power density of the lower electrode is 0.632 W / cm². 2 Since the etching rate varies depending on the material of the object being etched, the etching rate referred to in this article is obtained by plasma etching and measurement of a standard test piece. The standard test piece consists of multiple silicon wafers with silicon dioxide (SiO2) surfaces attached to a glass substrate, and a PI film, such as a polyimide film, is attached to a portion of the silicon wafers to form a shielding area and an etching area. After a period of plasma etching, the thickness difference of silicon dioxide in the shielding area and the etching area of each silicon wafer is measured, and the etching rate is obtained by dividing the thickness difference by the time.
[0039] In some embodiments, etching can be performed intermittently during the intense plasma etching process to achieve better temperature control. In some embodiments, during the intense plasma etching process, the workpiece 2 can be intermittently purged with gases such as argon or helium (He), or a sequence of steps can be performed, including pausing vacuuming, purging the workpiece 2 with argon or helium, resuming vacuuming, and performing plasma etching. This is to accelerate the removal of byproducts such as CO from the plasma etching reaction by the gas extraction system, thereby reducing the amount of new material generated during the etching process.
[0040] In some embodiments, the plasma strong etching step 13 can be performed in stages to ensure a better strong etching effect. For example, the plasma strong etching step 13 has a first strong etching sub-step 131 and a second strong etching sub-step 132. The etching rate of the second strong etching sub-step 132 is different from the etching rate of the first strong etching sub-step 131. Of course, a third, fourth, or more strong etching sub-steps can also be performed as needed.
[0041] In addition to the etching reaction mechanism, a coating reaction mechanism is also generated during the plasma intense etching process. The main reason is that when energy is applied to the metal oxide residue 33 during the etching reaction, the metal oxide residue 33 may be re-sputtered and dissociated into oxygen free radicals or oxygen atoms. These oxygen free radicals or oxygen atoms may then combine with free silicon atoms from the insulating layer 3 or metal atoms from the metal oxide residue 33 to generate new oxide residue 34, such as new silicon oxide (SiO2). x and aluminum oxide Al x O y Therefore, while removing the original metal oxide residue 33, new oxide residue 34 will continue to be generated stably. However, the thickness of these newly generated oxide residues 34 is usually less than 10 μm.
[0042] Step 14, in conjunction with Figure 4 and Figure 5 To remove the oxide residue 34 after the plasma strong etching step 13, a soft etching rate will be used. The blind via 32 is subjected to weak plasma etching. Compared to strong plasma etching, the weak plasma etching step 14 uses low power, low plasma density, and low etching rate parameters to remove the oxide residue 34. Therefore, the power used in the weak plasma etching step is lower than that used in the strong plasma etching step. The weak plasma etching step 14 can employ inductively coupled plasma reactive ion etching, reactive ion etching, or an ion source.
[0043] The vacuum range for weak etching using ICP-RIE is 5–10 mTorr, and argon (Ar), helium (He), or hydrogen (H2) gas can be introduced. Under the conditions of argon (Ar) gas introduction, and with an upper electrode (source) power of 1 kW and a lower electrode (bias) power of 0.5–2 kW, the resulting etching rate is... The power density of the upper electrode ranges from 0.1 to 0.3 W / cm². 2 The lower electrode power density ranges from 0.2 to 0.6 W / cm². 2 .
[0044] In some embodiments, the etching process can be intermittent during the weak plasma etching to achieve better temperature control. In other embodiments, during the weak plasma etching, the workpiece 2 can be intermittently purged with gases such as argon or helium, or the process can involve sequentially pausing vacuuming, purging the workpiece 2 with gases such as argon or helium, resuming vacuuming, and performing plasma etching. This is to accelerate the removal of byproducts from the plasma etching reaction by the gas extraction system, thereby reducing the amount of new material generated during the etching process.
[0045] In some embodiments, the plasma strong etching step 13 and the plasma weak etching step 14 are performed in different cavities, but in some embodiments they can also be performed in the same cavity. The operator can decide whether to perform them in the same cavity or different cavities depending on the production cycle.
[0046] In some embodiments, the plasma weak etching step 14 can be performed in stages to ensure a better weak etching effect. For example, the plasma weak etching step 14 has a first weak etching sub-step 141 and a second weak etching sub-step 142, where the etching rate of the second weak etching sub-step 142 is different from that of the first weak etching sub-step 141. Of course, a third, fourth, or more weak etching sub-steps can also be performed as needed. Considering the long operation time required for weak etching, the second weak etching sub-step 142 and the first weak etching step 141 can be performed in different cavities.
[0047] If reactive ion etching is used in the plasma weak etching step 14, the lower electrode power is 1–2.7 kW. If an ion source is used in the plasma weak etching step 14, the voltage is 2–5 KV and the vacuum level is 0.5–3 mTorr.
[0048] Step 15, in conjunction with Figure 6Following the plasma weak etching step 14, a patterned seed layer 4 is deposited over the insulating layer 31 and the blind via 32. The seed layer 4 is formed by sequentially sputtering or depositing a titanium layer and a copper layer.
[0049] Step 16, in conjunction with Figure 7 A patterned metal conductor layer 5 is deposited on the seed layer 4. The metal conductor layer 5 is formed of a metal, such as copper, through electroplating or deposition, and can be patterned using photolithography and etching techniques. The metal of the metal conductor layer 5 fills the blind vias 32 to electrically connect to the patterned metal layer 21.
[0050] The above steps complete a single-layer RDL. If you need to build up more layers of RDL, simply repeat steps 11 to 16.
[0051] This invention employs a multi-stage process of strong and weak plasma etching, effectively removing residues from the blind vias 32 and obtaining cleaner blind vias 32. This avoids problems such as over-etching, thermal damage, or cracking of the metal pads in the patterned metal layer 21, thereby reducing the contact resistance (Rc) between the metal conductor layer 5 and the patterned metal layer 21, thus improving conductivity and enhancing product performance and yield. Therefore, the objective of this invention is indeed achieved.
[0052] The above description is merely an embodiment of the present invention and should not be construed as limiting the scope of the present invention. Any simple equivalent changes and modifications made in accordance with the claims and description of the present invention shall still fall within the scope of the present invention.
Claims
1. A method for manufacturing electronic components using plasma etching to remove residue from blind vias, suitable for processing workpieces having a patterned metal layer and an insulating layer covering the patterned metal layer, the insulating layer having a plurality of blind vias, characterized in that: The method for manufacturing electronic components by removing residues from blind vias using plasma etching includes the following steps: First with a high etching rate The blind vias are subjected to a plasma high-intensity etching step to remove residual metal oxides in the patterned metal layer. This plasma high-intensity etching step employs inductively coupled plasma reactive ion etching, reactive ion etching, or an ion source. Then with a low etching rate The blind via is subjected to a weak plasma etching step to remove oxide residues after the strong plasma etching step. The weak plasma etching step employs inductively coupled plasma reactive ion etching, reactive ion etching, or an ion source, and the power used in the weak plasma etching step is lower than that used in the strong plasma etching step.
2. The method for manufacturing electronic components by plasma etching to remove residues from blind vias according to claim 1, characterized in that: Gas is intermittently blown in during either the strong plasma etching step or the weak plasma etching step.
3. The method for manufacturing electronic components by plasma etching to remove residues from blind vias according to claim 1, characterized in that: The plasma strong etching step and the plasma weak etching step are performed in the same cavity.
4. The method for manufacturing electronic components by plasma etching to remove residues from blind vias according to claim 1, characterized in that: The strong plasma etching step and the weak plasma etching step are performed in different cavities.
5. The method for manufacturing electronic components by plasma etching to remove residues from blind vias according to claim 1, characterized in that: The plasma high-intensity etching step includes a first high-intensity etching sub-step and a second high-intensity etching sub-step, wherein the etching rate of the second high-intensity etching sub-step is different from the etching rate of the first high-intensity etching sub-step.
6. The method for manufacturing electronic components by plasma etching to remove residues from blind vias according to claim 1, characterized in that: The plasma weak etching step includes a first weak etching sub-step and a second weak etching sub-step, wherein the etching rate of the second weak etching sub-step is different from the etching rate of the first weak etching step.
7. The method for manufacturing electronic components by plasma etching to remove residues from blind vias according to claim 6, characterized in that: The second weak etching step is performed in a different cavity than the first weak etching step.
8. The method for manufacturing electronic components by removing residues from blind vias using plasma etching according to claim 1, characterized in that: The upper electrode power density in the plasma high-intensity etching step is 0.468 W / cm². 2 The upper electrode power density of the plasma weak etching step is 0.1–0.3 W / cm². 2 .
9. The method for manufacturing electronic components by plasma etching to remove residues from blind vias according to claim 1, characterized in that: The vacuum degree of the plasma strong etching step is 0.5 to 5 mTorr, and the vacuum degree of the plasma weak etching step is 5 to 10 mTorr.
10. The method for manufacturing electronic components by plasma etching to remove residues from blind vias according to claim 1, characterized in that: The lower electrode power in the plasma strong etching step is greater than the lower electrode power in the plasma weak etching step.
11. The method for manufacturing electronic components by plasma etching to remove residues from blind vias according to claim 1, characterized in that: The thickness of the oxide residue left after the plasma etching step is less than 10 μm.
12. The method for manufacturing electronic components by plasma etching to remove residues from blind vias according to claim 1, characterized in that: The high etching rate of the plasma high etching step The weak etching rate of the plasma weak etching step is between to between.
13. The method for manufacturing electronic components by plasma etching to remove residues from blind vias according to claim 1, characterized in that: The metal oxide residue to be removed in the plasma strong etching step is aluminum oxide, and the oxide residue to be removed in the plasma weak etching step is silicon or aluminum oxide.
14. A method for manufacturing electronic components using plasma etching to remove residue from blind vias, characterized in that: Includes the following steps: An insulating layer is formed on a patterned metal layer on the workpiece; The insulating layer is laser-drilled to form multiple blind holes; With high etching rate The blind via is subjected to a plasma etching step to remove residual metal oxides inside the blind via. The plasma etching step employs inductively coupled plasma reactive ion etching, reactive ion etching, or an ion source. Then with a low etching rate The blind via is subjected to a weak plasma etching step to remove oxide residues after the strong plasma etching step. The weak plasma etching step employs inductively coupled plasma reactive ion etching, reactive ion etching, or an ion source, and the power used in the weak plasma etching step is lower than that used in the strong plasma etching step. After the plasma weak etching step, a patterned seed layer is deposited over the insulating layer and the blind holes; and A patterned metal wire layer is coated on the seed layer.
15. The method for manufacturing electronic components by plasma etching to remove residues from blind vias according to claim 14, characterized in that: The workpiece is a wafer, IC substrate, or printed circuit board.
16. The method for manufacturing electronic components by plasma etching to remove residues from blind vias according to claim 14, characterized in that: The patterned metal layer is made of one of titanium, aluminum, copper, nickel, gold, or an alloy thereof.