A time extraction method, system and application of digital pulse signal
By employing a thresholdless digital constant ratio timing method, the problem of low efficiency in low-energy signal processing of existing CFD systems is solved, achieving 100% detection efficiency and time measurement accuracy, and is applicable to radiation detectors and radar signal processing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-03-20
- Publication Date
- 2026-06-26
AI Technical Summary
Existing digital CFD systems suffer from low efficiency and event loss when processing low-energy signals. In particular, when a small attenuation factor is set, the amplitude of the synthesized CFD signal is extremely low, causing valid low-energy physical events to be discarded, which affects detection efficiency and coincidence measurement capability.
A trigger-guided thresholdless digital constant ratio timing method is adopted. By using a fast trapezoidal filter trigger signal, the zero-crossing point search within the time window is dynamically adjusted without amplitude threshold, and the fine interpolation calculation is transferred to the offline stage to ensure 100% detection efficiency and time measurement accuracy.
It maximizes timing efficiency across the entire energy spectrum, eliminates low-energy-efficiency truncation, optimizes hardware resource utilization, and provides picosecond-level time accuracy and data integrity, making it suitable for radiation detectors and radar signal processing.
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Figure CN122284256A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of nuclear electronics and nuclear detection technology, specifically relating to a method, system and application for time extraction of digital pulse signals. Background Technology
[0002] In nuclear physics experiments, nuclear medicine imaging (such as PET), and environmental radiation monitoring, accurate extraction of particle incident time information is crucial. With the development of technology, digital pulse processing systems based on high-speed analog-to-digital converters (ADCs) and field-programmable gate arrays (FPGAs) have gradually replaced traditional analog electronics modules.
[0003] Currently, the mainstream digital time extraction algorithms are mainly of the following two types:
[0004] 1) Leading Edge (LE): This method is simple and has high detection efficiency (limited only by the signal-to-noise ratio). However, it suffers from a severe amplitude-time walk effect, meaning that signals with the same rise time but different amplitudes are triggered at different times. Furthermore, for detectors such as high-purity germanium (HPGe), the rise time walk effect also affects the time resolution, resulting in poor time resolution.
[0005] 2) Digital Constant Ratio Timing (Digital CFD): By using the algorithm y[i]=f·x[i]-x[iD] to synthesize a bipolar signal and find the zero-crossing point, the amplitude fluctuation can theoretically be eliminated.
[0006] Existing commercial digital CFD systems (such as XIA Pixie-16) typically employ a "dual threshold" logic: requiring the fast-forming signal to exceed a trigger threshold, and also requiring the amplitude of the synthesized CFD signal (y[i]) to exceed a set "CFD Validation Threshold" to suppress spurious zero-crossings caused by baseline noise.
[0007] However, when processing low-energy signals (small amplitude) or setting a small attenuation factor (Fraction f, such as 20%) to achieve optimal time resolution, the synthesized CFD signal amplitude is extremely low. This results in many valid low-energy physical events, although triggering the fast prototyping channel, being discarded because the CFD signal amplitude does not reach the "CFD effective threshold," or the CFD time cannot be obtained. This "efficiency truncation" phenomenon severely affects the detection efficiency and coincidence measurement capability in the low-energy region. Summary of the Invention
[0008] The purpose of this invention is to address the problems existing in the prior art by providing a method, system, and application for time extraction of digital pulse signals, particularly a digital constant ratio timing (CFD) method for small amplitude signals. This method eliminates the low energy efficiency truncation phenomenon of the CFD method and achieves 100% detection efficiency consistent with leading-edge timing while ensuring time measurement accuracy.
[0009] To achieve the above objectives, in one aspect, embodiments of the present invention provide a method for time extraction of digital pulse signals, comprising:
[0010] S1) Acquire the detector signal and perform analog-to-digital conversion;
[0011] S2) Generate a trigger signal according to the set fast trigger threshold, and simultaneously perform digital constant ratio timing filtering and synthesis;
[0012] S3) In response to the trigger signal, open a search time window;
[0013] S4) Within the time window, a zero-crossing search is performed on the digital constant ratio timing filter result, independent of the amplitude threshold, to detect the zero-crossing point where the synthesized digital constant ratio timing signal y[n] changes from positive to negative;
[0014] S5) Pack the raw data before and after the zero point and transmit it to the host computer for timed calculation.
[0015] Furthermore, in a specific embodiment, in the digital pulse signal time extraction method described above, in step S1), the analog signal of the detector is sampled by an analog-to-digital converter to obtain a digital signal sequence S[n].
[0016] Furthermore, in a specific embodiment, in the digital pulse signal time extraction method described above, in step S2), the digital signal is subjected to fast trapezoidal filtering to obtain the processed digital signal sequence x[n], and a fast trigger threshold Th is set. fast When x[n] exceeds Th fast When this occurs, a trigger signal is generated.
[0017] Furthermore, in step S2), a coarse timestamp T is recorded based on the sampling point that generates the trigger signal. trig .
[0018] Furthermore, in step S2), the digital constant-ratio timing filter synthesis algorithm is as follows:
[0019] y[n]=f·x[n]-x[nD]
[0020] Where y[n] is the synthesized digital constant ratio timing signal, x[n] is the digital signal sequence after fast trapezoidal filtering, f is the attenuation factor, D is the delay parameter, and n is the sampling point number.
[0021] Furthermore, in a specific embodiment, in the digital pulse signal time extraction method described above, in step S3), the start time of the time window is dynamically adjusted according to the delay parameter D.
[0022] Furthermore, in a specific implementation, in the digital pulse signal time extraction method described above, in step S4), within the time window, the sign bit of y[n] is monitored in real time to find the zero-crossing index i that satisfies y[i]≥0 and y[i+1]<0; if a zero-crossing is found within the time window, the flag bit Flag=1 is set; if no zero-crossing is found within the time window, the flag bit Flag=0 is set.
[0023] Furthermore, in step S4), if a zero-crossing point is found within the time window, the original values y[i] and y[i+1] before and after the zero-crossing point are latched, and the integer clock cycle difference ΔT between the trigger time and the zero-crossing time is calculated. int .
[0024] Furthermore, in a specific implementation, in the digital pulse signal time extraction method described above, in step S5), if a zero-crossing point is found within the time window, the original data before and after the zero-crossing point includes at least: a coarse timestamp T of the trigger signal sampling point. trig , Flag bit, Integer clock cycle difference ΔT from trigger time to zero crossing time int , and the original values y[i] and y[i+1] before and after the zero point.
[0025] Furthermore, in step S5), if no zero-crossing point is found within the time window, the flag bit Flag=0 is set, the event is retained, and only the coarse timestamp T of the sampling point that generated the trigger signal is output. trig .
[0026] Furthermore, in step S5), the host computer receives data packets and performs offline timing calculations. For events with Flag=1, interpolation calculations are performed using the original sampling point values to obtain sub-sampling times with picosecond precision. For events with Flag=0, offline time-walking correction is performed using energy information.
[0027] Furthermore, in step S5), for events with Flag=1, the formula for interpolation calculation using the original sample point values is as follows:
[0028] ΔT fine =(ΔT int +y[i] / (y[i]-y[i+1]))×T clk
[0029] Where, ΔTfine For sub-sampling time, ΔT int T is the integer clock cycle difference between the trigger time and the zero-crossing time, y[i] and y[i+1] are the original values before and after the zero-crossing point, and T is the integer clock cycle difference between the trigger time and the zero-crossing time. clk The sampling clock period.
[0030] Furthermore, in step S5), the zero-crossing slope is calculated using y[i]-y[i+1]. If the slope is lower than the preset noise slope threshold, it is marked as noise zero crossing, and the leading edge timing mode is used for correction.
[0031] On the other hand, embodiments of the present invention provide a time extraction system for digital pulse signals, comprising:
[0032] The signal sampling module is used to acquire detector signals and perform analog-to-digital conversion;
[0033] The triggering module is used to perform fast trapezoidal filtering on digital signals and generate trigger signals according to the set fast trigger threshold.
[0034] The CFD filter synthesis module is used to perform digital constant ratio timing filter synthesis on digital signal sequences processed by fast trapezoidal filtering.
[0035] The windowed zero-crossing search module is used to open a search time window according to the trigger signal. Within the time window, the zero-crossing point search is performed on the digital constant ratio timing filter result without relying on the amplitude threshold, and the zero-crossing point of the synthesized digital constant ratio timing signal y[n] changing from positive to negative is detected.
[0036] The data transmission module is used to package and transmit the raw data before and after the zero crossing to the host computer.
[0037] The timing calculation module uses the original sampling point values to perform interpolation calculations to obtain sub-sampling times with picosecond-level precision.
[0038] Furthermore, in the digital pulse signal time extraction system described above, if no zero-crossing point is found within the time window, the data transmission module only outputs a coarse timestamp T of the sampling point that generated the trigger signal. trig .
[0039] Furthermore, the digital pulse signal time extraction system described above also includes a zero-crossing slope judgment module, which calculates the zero-crossing slope using the original values y[i]-y[i+1] before and after the zero-crossing point. If the slope is lower than a preset noise slope threshold, it is marked as noise zero crossing, and the system switches to leading-edge timing mode for time correction.
[0040] The digital pulse signal time extraction method and system provided in the embodiments of the present invention can be used for radiation detector signal processing or radar signal processing.
[0041] The beneficial effects of this invention are as follows:
[0042] (1) Elimination of low energy efficiency truncation: The timing method provided by the present invention eliminates the amplitude threshold of the CFD branch, so that even signals with very small amplitudes (as long as they can be triggered by a fast filter) can obtain CFD time, thereby maximizing the timing efficiency of the full spectrum.
[0043] (2) Resource optimization (FPGA Friendly): This method moves the complex floating-point division operation (interpolation) to the offline CPU, avoiding the consumption of a large amount of DSP resources and divider IP cores inside the FPGA, and reducing firmware latency.
[0044] (3) Data integrity: Even if the timing method provided by this invention fails to search past zero within the time window, the system will fall back to LE mode to record the event, thus preventing data loss.
[0045] (4) Advanced analysis capabilities: This method outputs the original sampled values near the zero crossing point, allowing users to eliminate noisy zero crossings by judging the slope in offline analysis, or to use more advanced fitting algorithms (such as cubic splines) to further improve the time accuracy, which is especially important for slow signal detectors such as HPGe. Attached Figure Description
[0046] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0047] Figure 1 This is a logic block diagram of a thresholdless digital constant ratio timing method based on trigger guidance in a specific embodiment of the present invention.
[0048] Figure 2 This is a structural diagram of a thresholdless digital constant ratio timing system based on trigger guidance in a specific embodiment of the present invention.
[0049] Figure 3 This is a schematic diagram of timing waveforms in a specific embodiment of the present invention. Detailed Implementation
[0050] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0051] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains.
[0052] The terms “comprising”, “including”, etc., as used herein indicate the presence of the steps, features, operations, or components, but do not preclude the addition of one or more other steps, features, operations, or components.
[0053] Traditional Digital Constant Ratio Timing (Digital CFD) methods first digitize the signal, then the digital information is analyzed and processed by a digital signal processor (DSP). Depending on the testing objective, relevant information (such as amplitude and time) is extracted from the sampled signal. Online baseline drift elimination, peak finding, and waveform reconstruction at the sampling points are then performed. Based on the reconstructed waveform, the signal amplitude is determined, a constant trigger ratio is set, and the waveform is attenuated, delayed, and shaped to a constant ratio to find the constant ratio timing point. Since the constant ratio value generally falls between two sampling points, an interpolation algorithm is needed to obtain an accurate solution.
[0054] Existing commercial digital CFD systems typically employ a "dual threshold" logic: requiring the fast prototyping signal to exceed a trigger threshold, and also mandating that the amplitude of the synthesized CFD signal (y[i]) must exceed a set "CFD validation threshold" to suppress spurious zero-crossings caused by baseline noise. However, when processing low-energy signals (small amplitudes) or setting a small attenuation factor (Fraction f, such as 20%) to achieve optimal time resolution, the synthesized CFD signal amplitude is extremely low. This results in many valid low-energy physical events triggering the fast prototyping channel being discarded because the CFD signal amplitude does not reach the "CFD validation threshold," or the CFD time cannot be obtained. This "efficiency truncation" phenomenon severely impacts the detection efficiency and coincidence measurement capabilities in the low-energy region.
[0055] This invention aims to address the problems of low efficiency and event loss in existing digital CFD technology when processing small-amplitude signals, and provides a thresholdless digital constant-ratio timing method that decouples triggering logic from timing logic. This method achieves 100% detection efficiency consistent with leading-edge triggering while maintaining time measurement accuracy.
[0056] This invention proposes a time extraction method for digital pulse signals, which is essentially a trigger-guided thresholdless digital constant-ratio timing method. Its core lies in: using fast trapezoidal filtering results for event triggering; within a specific time window after triggering, performing thresholdless zero-crossing point search on the CFD signal; and transferring fine interpolation calculations to an offline stage to save hardware resources.
[0057] In some specific embodiments, the method provided by the present invention is as follows: Figure 1 As shown, it includes the following steps:
[0058] S1) Acquire the detector signal and perform analog-to-digital conversion;
[0059] S2) Generate a trigger signal according to the set fast trigger threshold, and simultaneously perform digital constant ratio timing filtering and synthesis;
[0060] S3) In response to the trigger signal, open a search time window;
[0061] S4) Within the time window, a zero-crossing search is performed on the digital constant ratio timing filter result, independent of the amplitude threshold, to detect the zero-crossing point where the synthesized digital constant ratio timing signal y[n] changes from positive to negative;
[0062] S5) Pack the raw data before and after the zero point and transmit it to the host computer for timed calculation.
[0063] In some specific embodiments, a high-speed analog-to-digital converter (ADC) is used to digitize the analog signal output by the detector and sample it to obtain a digital signal sequence S[n].
[0064] In some specific embodiments, two parallel processing paths are constructed within the field-programmable gate array (FPGA):
[0065] Path A (trigger path): The digital signal sequence S[n] is subjected to fast trapezoidal filtering to obtain the processed digital signal sequence x[n].
[0066] Path B (Timing Path): The processed digital signal sequence x[n] is subjected to CFD filtering and synthesized to obtain a digital constant ratio timing signal. The algorithm is y[n]=f·x[n]-x[nD], where f is the attenuation factor and D is the delay parameter.
[0067] In some specific embodiments, a fast trigger threshold Th is set. fast When the digital signal sequence x[n] after fast trapezoidal filtering of path A exceeds Th fast When a trigger signal is generated, a coarse timestamp T of the trigger moment is recorded. trig .
[0068] This invention constructs two parallel processing paths, where the validity of an event is determined solely by path A, and path B does not have an amplitude threshold. This allows even signals with extremely small amplitudes (as long as they can be triggered by a fast filter) to undergo CFD filtering and synthesis, thus obtaining CFD time.
[0069] In some specific embodiments, once the trigger path generates a trigger signal, the logic circuit immediately opens a search time window W. The start time of the time window is dynamically adjusted according to the delay parameter D.
[0070] Within the time window W, the sign bit of the synthesized digital constant ratio timing signal y[n] is monitored in real time, and the zero-crossing index i that satisfies y[i]≥0 and y[i+1]<0 is searched.
[0071] In some specific embodiments, if a zero-crossing point is found within the time window, the flag bit Flag=1 is set; if no zero-crossing point is found within the time window, the flag bit Flag=0 is set.
[0072] In some specific embodiments, if a zero-crossing point is found within the time window, the original values y[i] and y[i+1] of the digital constant ratio timing signal before and after the zero-crossing point are latched, and the integer clock cycle difference ΔT from the trigger time to the zero-crossing time is calculated. int .
[0073] If no zero point is found within the time window, the flag bit Flag=0 is set, the event is retained, and only the approximate timestamp T of the trigger time is output. trig .
[0074] In some specific embodiments, the raw data before and after the zero-crossing point is packaged and transmitted to the host computer for offline timing calculations to save hardware resources. The data packaged and output by the FPGA includes at least: a coarse timestamp T. trig , Flag bit, Integer clock cycle difference ΔT from trigger time to zero crossing time int The output includes the original values y[i] and y[i+1] before and after the zero point. If needed, y[i-1] and y[i+2] can also be output.
[0075] In some specific embodiments, the host computer (CPU) receives data packets and performs offline fine-grained timing calculations. For events with Flag=1, interpolation calculations (such as linear interpolation or spline interpolation) are performed using the original sampling point values to obtain sub-sampling times with picosecond-level precision.
[0076] ΔT fine =(ΔT int +y[i] / (y[i]-y[i+1]))×T clk
[0077] Where, ΔT fine For sub-sampling time, ΔT int T is the integer clock cycle difference between the trigger time and the zero-crossing time, y[i] and y[i+1] are the original values before and after the zero-crossing point, and T is the integer clock cycle difference between the trigger time and the zero-crossing time. clk The sampling clock period.
[0078] For events with Flag=0, offline time travel correction can be performed using energy information.
[0079] In some specific embodiments, noise zero-crossings can be eliminated in offline analysis by judging the slope. Specifically, the zero-crossing slope can be calculated using the original values y[i]-y[i+1] of the digital constant ratio timing signal before and after the zero-crossing point. If the slope is lower than a preset noise slope threshold, it is marked as a noise zero-crossing, and the system switches to the leading-edge timing mode for correction.
[0080] To implement the above method, this invention further provides a digital pulse signal time extraction system, specifically a digital pulse processing system based on a high-speed analog-to-digital converter (ADC) and a field-programmable gate array (FPGA), to realize the trigger-guided thresholdless digital constant-ratio timing method of this invention. The system's structure is as follows: Figure 2 As shown, it specifically includes:
[0081] The signal sampling module is used to acquire detector signals and perform analog-to-digital conversion;
[0082] The triggering module is used to perform fast trapezoidal filtering on digital signals and generate trigger signals according to the set fast trigger threshold.
[0083] The CFD filter synthesis module is used to perform digital constant ratio timing filter synthesis on digital signal sequences processed by fast trapezoidal filtering.
[0084] The windowed zero-crossing search module is used to open a search time window according to the trigger signal. Within the time window, the zero-crossing point search is performed on the digital constant ratio timing filter result without relying on the amplitude threshold, and the zero-crossing point of the synthesized digital constant ratio timing signal y[n] changing from positive to negative is detected.
[0085] The data transmission module is used to package and transmit the raw data before and after the zero crossing to the host computer.
[0086] The timing calculation module uses the original sampling point values to perform interpolation calculations to obtain sub-sampling times with picosecond-level precision.
[0087] In some specific embodiments, the windowed zero-crossing search module of this system may encounter two scenarios: finding a zero-crossing point within the time window or not finding one. If a zero-crossing point is found within the time window, the flag bit Flag=1 is set, the original values y[i] and y[i+1] of the digital constant ratio timing signal before and after the zero-crossing point are latched, and the integer clock cycle difference ΔT from the trigger time to the zero-crossing time is calculated. int The data packaged and output by the data transmission module should include at least: a rough timestamp T. trig, Flag bit, Integer clock cycle difference ΔT from trigger time to zero crossing time int And the original values y[i] and y[i+1] before and after the zero point.
[0088] If no zero-crossing point is found within the time window, the flag bit Flag=0 is set, the event is retained, and the data transmission module only outputs a rough timestamp T of the trigger time. trig .
[0089] In some specific embodiments, the system also includes a zero-crossing slope judgment module, which calculates the zero-crossing slope using the original values y[i]-y[i+1] of the digital constant ratio timing signal before and after the zero-crossing point. If the slope is lower than a preset noise slope threshold, it is marked as noise zero crossing, and the system switches to leading-edge timing mode and corrects accordingly.
[0090] Both the timing calculation module and the zero-crossing slope judgment module are located on the host computer, and the host computer (CPU) performs offline calculations, which avoids consuming a lot of DSP resources and divider IP cores inside the FPGA, thus achieving optimization and efficient utilization of hardware resources.
[0091] Example
[0092] This embodiment provides a timing system for a high-purity germanium (HPGe) detector based on a CAEN V2745 digitizer.
[0093] Hardware platform: CAEN V2745 digitizer (125 MS / s, 16-bit) and high-purity germanium (HPGe) detector with a relative efficiency of 70%.
[0094] The CAEN V2745 digitizer features high-speed acquisition, a multi-channel ADC, local memory, and an FPGA, enabling real-time data processing.
[0095] FPGA logic configuration:
[0096] Fast filter parameters: rise time 96 ns, flat top 96 ns.
[0097] CFD parameters: Delay D = 40 ns (adjusted according to detector rise time), attenuation factor f = 0.25.
[0098] Search time window: set width W = 200 ns, starting position relative to the approximate timestamp T of the trigger time. trig Offset by D clock cycles.
[0099] The thresholdless digital constant ratio timing method of this system is as follows:
[0100] 1) When γ-rays interact with the HPGe detector, the preamplifier signal enters the high-speed analog-to-digital converter (ADC) of the digitizer. The ADC digitizes the analog signal output by the detector and samples it to obtain a digital signal sequence S[n].
[0101] 2) The fast trapezoidal filter inside the FPGA of the digitizer detects the digital signal and performs fast trapezoidal filtering to obtain the processed digital signal sequence x[n]. When the digital signal sequence x[n] exceeds the preset fast trigger threshold Th... fast At that time, a trigger signal is generated, and a rough timestamp T of the trigger moment is recorded. trig .
[0102] 3) Simultaneously, the FPGA performs CFD filtering on the processed digital signal sequence x[n] to synthesize a digital constant-ratio timing signal y[n]. The algorithm is y[n] = f·x[n] - x[nD], where f is the attenuation factor and D is the delay parameter. Due to the small signal amplitude, the peak value of y[n] may only have a few LSBs (least significant bits). The timing waveforms of S[n], x[n], and y[n] are as follows: Figure 3 As shown.
[0103] 4) In response to the trigger signal, start the counter and open a search time window with a window width W = 200 ns and a starting position relative to the approximate timestamp T of the trigger time. trig Offset by D clock cycles. For example... Figure 3 As shown, the digital signal sequence x[n] exceeds the preset fast trigger threshold Th. fast At that time, open the search time window.
[0104] 5) Monitor the sign bit of the synthesized digital constant-ratio timing signal y[n] in real time and find the zero-crossing index i that satisfies y[i]≥0 and y[i+1]<0. When y[n] is detected to change from positive to negative within the time window (see... Figure 3 T passing zero point ZC The FPGA immediately latches the original values y[i] and y[i+1] of the current digital constant-ratio timing signal, as well as the integer clock cycle difference ΔT from the trigger time to the zero-crossing time. int .
[0105] 6) Set the coarse timestamp T trig , Flag bit, Integer clock cycle difference ΔT from trigger time to zero crossing time int The original values y[i] and y[i+1] before and after the zero point are packaged and transmitted to the PC.
[0106] 7) The PC software reads the data packet. If the flag is set to 1, the sub-sampling time ΔT is calculated using the formula.fine ΔT fine =(ΔT int +y[i] / (y[i]-y[i+1]))×T clk .
[0107] Where, ΔT fine For sub-sampling time, ΔT int T is the integer clock cycle difference between the trigger time and the zero-crossing time, y[i] and y[i+1] are the original values before and after the zero-crossing point, and T is the integer clock cycle difference between the trigger time and the zero-crossing time. clk The sampling clock period.
[0108] If Flag=0, the event time is marked with low precision.
[0109] Meanwhile, the zero-crossing slope is calculated using y[i]-y[i+1]. If the slope is lower than the preset noise slope threshold, it is marked as a pseudo-zero crossing at the software level, and LE time is used for correction.
[0110] Those skilled in the art will understand that the specific order of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order of steps in the process can be rearranged without departing from the scope of the invention. The appended methods provide elements of various steps in an exemplary order and are not intended to be limited to the specific order or hierarchy described.
[0111] Although the technical solution of this embodiment is designed for a timing system of an HPGe detector, those skilled in the art should understand and realize that this method is also applicable to signal processing of other detectors such as LaBr3 and liquid scintillators, as well as to PET or radar signal processing. Any detector and application involving the use of CFD methods to extract subsampling point time accuracy is applicable to this invention.
[0112] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. Thus, the invention also intends to include such variations and adaptations if they fall within the scope of the claims and their equivalents.
[0113] The above embodiments are merely illustrative examples of the present invention. The present invention may also be implemented in other specific ways or forms without departing from its spirit or essential characteristics. Therefore, the described embodiments should be considered illustrative rather than limiting in any respect. The scope of protection of the present invention should be defined by the claims, and any variations equivalent to the intent and scope of the claims should also be included within the scope of the present invention.
Claims
1. A method for time extraction of digital pulse signals, characterized in that, include: S1) Acquire the detector signal and perform analog-to-digital conversion; S2) Generate a trigger signal according to the set fast trigger threshold, and simultaneously perform digital constant ratio timing filtering and synthesis; S3) In response to the trigger signal, open a search time window; S4) Within the time window, a zero-crossing search is performed on the digital constant ratio timing filter result, independent of the amplitude threshold, to detect the zero-crossing point where the synthesized digital constant ratio timing signal y[n] changes from positive to negative; S5) Pack the raw data before and after the zero point and transmit it to the host computer for timed calculation.
2. The method for time extraction of digital pulse signals as described in claim 1, characterized in that, In step S1), the analog signal of the detector is sampled by an analog-to-digital converter to obtain a digital signal sequence S[n].
3. The method for time extraction of digital pulse signals as described in claim 1, characterized in that, In step S2), the digital signal is subjected to fast trapezoidal filtering to obtain the processed digital signal sequence x[n], and the fast trigger threshold Th is set. fast When x[n] exceeds Th fast When this occurs, a trigger signal is generated.
4. The method for time extraction of digital pulse signals as described in claim 1, characterized in that, In step S2), a coarse timestamp T is recorded based on the sampling point that generates the trigger signal. trig .
5. The method for time extraction of digital pulse signals as described in claim 1, characterized in that, In step S2), the digital constant-ratio timing filter synthesis algorithm is as follows: y[n]=f·x[n]-x[nD] Where y[n] is the synthesized digital constant ratio timing signal, x[n] is the digital signal sequence after fast trapezoidal filtering, f is the attenuation factor, D is the delay parameter, and n is the sampling point number.
6. The method for time extraction of digital pulse signals as described in claim 5, characterized in that, In step S3), the start time of the time window is dynamically adjusted according to the delay parameter D.
7. The method for time extraction of digital pulse signals as described in claim 1, characterized in that, In step S4), within the time window, the sign bit of y[n] is monitored in real time to find the zero-crossing index i that satisfies y[i]≥0 and y[i+1]<0; if a zero-crossing is found within the time window, the flag bit Flag=1 is set; if no zero-crossing is found within the time window, the flag bit Flag=0 is set.
8. The method for time extraction of digital pulse signals as described in claim 7, characterized in that, In step S4), if a zero-crossing point is found within the time window, the original values y[i] and y[i+1] before and after the zero-crossing point are latched, and the integer clock cycle difference ΔT between the trigger time and the zero-crossing time is calculated. int .
9. The method for time extraction of digital pulse signals as described in claim 1, characterized in that, In step S5), if a zero-crossing point is found within the time window, the original data before and after the zero-crossing point shall include at least: a coarse timestamp T of the trigger signal sampling point. trig , Flag bit, Integer clock cycle difference ΔT from trigger time to zero crossing time int , and the original values y[i] and y[i+1] before and after the zero point.
10. The method for time extraction of a digital pulse signal as described in claim 1, characterized in that, In step S5), if no zero-crossing point is found within the time window, the flag bit Flag=0 is set, the event is retained, and only the coarse timestamp T of the sampling point that generated the trigger signal is output. trig .
11. The method for time extraction of digital pulse signals as described in claim 7, characterized in that, In step S5), the host computer receives data packets and performs offline timing calculations. For events where the flag is set to 1, interpolation calculations are performed using the original sampling point values to obtain sub-sampling times with picosecond precision. For events where the flag is set to 0, offline time-walking correction is performed using energy information.
12. The method for time extraction of digital pulse signals as described in claim 11, characterized in that, In step S5), for events with Flag=1, the formula for interpolation calculation using the original sample point values is as follows: ΔT fine =(ΔT int + y[i] / (y[i]-y[i+1]))×T clk Where, ΔT fine For sub-sampling time, ΔT int T is the integer clock cycle difference between the trigger time and the zero-crossing time, y[i] and y[i+1] are the original values before and after the zero-crossing point, and T is the integer clock cycle difference between the trigger time and the zero-crossing time. clk The sampling clock period.
13. The method for time extraction of digital pulse signals as described in claim 12, characterized in that, In step S5), the zero-crossing slope is calculated using y[i]-y[i+1]. If the slope is lower than the preset noise slope threshold, it is marked as noise zero crossing, and the system switches to leading-edge timing mode and corrects the time.
14. A system for implementing the time extraction method for digital pulse signals according to any one of claims 1-13, characterized in that, include: The signal sampling module is used to acquire detector signals and perform analog-to-digital conversion; The triggering module is used to perform fast trapezoidal filtering on digital signals and generate trigger signals according to the set fast trigger threshold. The CFD filter synthesis module is used to perform digital constant ratio timing filter synthesis on digital signal sequences processed by fast trapezoidal filtering. The windowed zero-crossing search module is used to open a search time window according to the trigger signal. Within the time window, the zero-crossing point search is performed on the digital constant ratio timing filter result without relying on the amplitude threshold, and the zero-crossing point of the synthesized digital constant ratio timing signal y[n] changing from positive to negative is detected. The data transmission module is used to package and transmit the raw data before and after the zero crossing to the host computer. The timing calculation module uses the original sampling point values to perform interpolation calculations to obtain sub-sampling times with picosecond-level precision.
15. The system as described in claim 14, characterized in that, If no zero-crossing point is found within the time window, the data transmission module only outputs a coarse timestamp T of the sampling point that generated the trigger signal. trig .
16. The system as described in claim 14, characterized in that, It also includes a zero-crossing slope judgment module, which calculates the zero-crossing slope using the original values y[i]-y[i+1] before and after the zero-crossing point. If the slope is lower than the preset noise slope threshold, it is marked as noise zero crossing, and the system switches to leading-edge timing mode and corrects the time.
17. An application of the time extraction method for a digital pulse signal according to any one of claims 1-13, characterized in that, It can be used for radiation detector signal processing or radar signal processing.