A feedback signal monitoring function block for use in a safety control system
By combining design logic and modules, numerical comparison modules, and other components, a complex design for the feedback signal monitoring function block in a domestically developed safety control system was achieved, ensuring the reliability and security of the output signal and improving the maintainability and scalability of the system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CGN DIGITAL TECH CO LTD
- Filing Date
- 2026-04-10
- Publication Date
- 2026-06-26
AI Technical Summary
The design of the feedback signal monitoring function block in existing domestic safety control systems is insufficient, which cannot meet the complex signal monitoring requirements, resulting in insufficient system reliability and security.
A feedback signal monitoring function block was designed, which includes a combination of various basic function modules such as a logic AND module, a numerical comparison module, an open delay module, an RS flip-flop module, and a logic OR module. By performing numerical comparison, delay processing, and logical operations on the readback signal and the actual output signal, the reliability and security of the output signal are ensured.
It improves the reliability and security of critical output signals of the safety system, and enhances the maintainability and scalability of the system.
Smart Images
Figure CN122284472A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of safety control system technology, and specifically relates to a feedback signal monitoring function block applied to a safety control system. Background Technology
[0002] Proton therapy, a high-precision radiotherapy technique, utilizes the physical properties of proton particles to achieve precise tumor localization and treatment while significantly reducing damage to surrounding healthy tissues. In a proton therapy system, the treatment safety system is the core equipment ensuring patient safety and treatment effectiveness. Its functions encompass accurate proton beam positioning and adjustment, dose monitoring and control, and patient safety education and training. With the widespread application and continuous development of proton therapy technology, proton therapy safety systems have become a research hotspot in the medical field.
[0003] During the operation of a proton therapy system, the safety control system is a crucial component ensuring the safety of equipment and personnel in the treatment center, effectively preventing and avoiding potential personal injury accidents. The feedback signal monitoring function is an important part of the safety control system, primarily responsible for monitoring the readback signals of the output signal relays (obtained through the input module). It confirms that the relays corresponding to the required system output signals have operated correctly as required, thereby ensuring the reliability and safety of the system's critical output signals.
[0004] Currently, most mainstream safety control systems on the market rely on imported equipment, and the function block library of domestically produced safety systems still suffers from significant deficiencies in richness. Therefore, how to design complex feedback signal monitoring function blocks based on the basic function modules of domestically produced safety systems has become an urgent problem to be solved. Summary of the Invention
[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a feedback signal monitoring function block for use in a safety control system, and to implement the design of a complex feedback signal monitoring function block based on the basic functional modules of a domestic safety system.
[0006] This invention provides a feedback signal monitoring function block for a safety control system, comprising:
[0007] The system includes several logic AND modules, a numerical comparison module, an open delay module, an RS flip-flop module, and a logic OR module, wherein the several logic AND modules include a first logic AND module, a second logic AND module, and a third logic AND module. The numerical comparison module is used to compare the readback signal and the actual output signal of the module to output a readback monitoring signal. The first logic AND module is used to perform an AND operation on the quality code signal corresponding to the readback signal and the inverted signal of the readback monitoring signal to output a feedback and output difference comparison signal; The open delay module is used to compare the feedback and output difference comparison signal and the difference time period number signal to output a pre-alarm signal. The logic OR module is used to perform an OR operation based on the inverted signals of the manual reset signal and the automatic reset signal to output a reset alarm signal. The RS trigger module is used to retain alarm information based on the pre-alarm signal and the reset alarm signal, so as to output a status warning signal. The second logic AND module is used to perform an AND operation on the status warning signal to output the actual alarm signal and the alarm confirmation signal; The third logic AND module is used to perform an AND operation on the inverted signal of the actual alarm signal, the module pre-output signal, and the quality code signal corresponding to the readback signal, so as to output the actual output signal of the module.
[0008] In one embodiment of the present invention, the numerical comparison module includes a first data input pin, a second data input pin, and an equal result output pin; The first data input pin of the numerical comparison module is connected to the actual output signal of the module, the second data input pin of the numerical comparison module is connected to the readback signal, and the equal result output pin is connected to the data output pin of the first logic AND module. When the actual output signal of the module is different from the readback signal, the equal result output pin of the numerical comparison module outputs a low-level signal as the readback monitoring signal.
[0009] In one embodiment of the present invention, the first logic AND module includes a first control signal input pin, a second control signal input pin, and a data output pin; The first control signal input pin of the first logic AND module is connected to the quality code signal corresponding to the readback signal, and the second control signal input pin of the first logic AND module is connected to the inverted signal of the readback monitoring signal; When the quality code signal corresponding to the readback signal is a high-level signal and the readback monitoring signal is a low-level signal, the data output pin of the first logic AND module outputs a high-level signal as a feedback and output difference comparison signal.
[0010] In one embodiment of the present invention, the delay module includes a trigger signal input pin, a preset time input pin, and a status output pin; The trigger signal input pin of the open delay module is connected to the feedback and output difference comparison signal, the preset time input pin of the open delay module is connected to the difference time cycle number signal, and the status output pin of the open delay module is connected to the set pin of the RS trigger module. When the continuous trigger duration of the feedback and output difference comparison signal output by the first logic AND module is greater than the duration of the difference time cycle number signal, the status output pin of the open delay module outputs a high-level signal as the pre-alarm signal.
[0011] In one embodiment of the present invention, it further includes: a first multi-multiplication addition module and a second multi-multiplication addition module; The first multi-multiplication addition module is used to multiply and sum the preset number of cycles and the cycle coefficient to output the difference time cycle number signal; The second multi-multiplication adder module is used to multiply and sum the difference time period number signal and the scan period duration to output the actual difference duration.
[0012] In one embodiment of the present invention, the logic OR module includes a first control signal input pin, a second control signal input pin, and a data output pin; The first control signal input pin of the logic OR module is connected to the manual reset signal, the second control signal input pin of the logic OR module is connected to the inverted signal of the automatic reset signal, and the data output pin of the logic OR module is connected to the reset pin of the RS flip-flop module. When either the manual reset signal or the inverted signal of the automatic reset signal is a high-level signal, the data output pin of the logic OR module outputs a high-level signal.
[0013] In one embodiment of the present invention, the RS trigger module includes a set pin, a reset pin, and a set-priority output pin; The set pin of the RS trigger module is connected to the pre-alarm signal, the reset pin of the RS trigger module is connected to the reset alarm signal, and the set priority output pin of the RS trigger module is connected to the control signal input pin of the second logic AND module. When the reset alarm signal is a low-level signal and the pre-alarm signal is a high-level signal, the set priority output pin outputs a status warning signal that is a high-level signal. When the reset alarm signal is a high-level signal and the pre-alarm signal is a low-level signal, the set priority output pin outputs a status warning signal that is a low-level signal. When the reset alarm signal is a low-level signal and the pre-alarm signal is a low-level signal, the status warning signal output by the set priority output pin remains unchanged; When the reset alarm signal is a high-level signal and the pre-alarm signal is a high-level signal, the set priority output pin outputs a status warning signal that is a low-level signal.
[0014] In one embodiment of the present invention, the second logic AND module includes a first logic AND submodule, the first logic AND submodule including a control signal input pin and a data output pin; The set priority output pin of the RS trigger module and the equal result output pin of the numerical comparison module are respectively connected to the control signal input pin of the second logic AND submodule, and the data output pin of the second logic AND submodule is connected to the alarm confirmation signal. When the status warning signal and the readback monitoring signal are both high-level signals, the second logic AND submodule outputs an alarm confirmation signal that is also high-level.
[0015] In one embodiment of the present invention, the second logic AND module includes a second logic AND submodule, the second logic AND submodule including a control signal input pin and a data output pin; The set priority output pin of the RS trigger module and the equal result output pin of the numerical comparison module are respectively connected to the control signal input pin of the second logic AND submodule, and the data output pin of the second logic AND submodule is connected to the alarm confirmation signal. When the status warning signal and the readback monitoring signal are both high-level signals, the second logic AND submodule outputs an alarm confirmation signal that is also high-level.
[0016] In one embodiment of the present invention, the third logic AND module includes a first control signal input pin, a second control signal input pin, a third control signal input pin, and a data output pin; The first control signal input pin of the third logic AND module is connected to the module's pre-output signal, the second control signal input pin of the third logic AND module is connected to the inverted signal of the actual alarm signal, and the third control signal input pin of the third logic AND module is connected to the quality code signal corresponding to the readback signal. When the module's pre-output signal is a high-level signal, the actual alarm signal is a low-level signal, and the quality code signal corresponding to the readback signal is a high-level signal, an AND operation is performed, and the data output pin of the third logic AND module outputs the actual output signal of the module as a high-level signal.
[0017] The beneficial effects of this invention are as follows: This invention, through the design and combination of various basic functional modules such as the AND module, numerical comparison module, open delay module, RS flip-flop module, and OR module, monitors the readback signal of the output signal relay (obtained through the input module) and confirms whether the relay corresponding to the signal required by the safety system has acted correctly as required, thereby ensuring the reliability and safety of the key output signals of the safety system. Furthermore, the combination design of basic functional modules improves the maintainability and scalability of the system. Attached Figure Description
[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0019] Figure 1 This is a schematic diagram of the structure of a feedback signal monitoring function block applied to a safety control system according to an embodiment of the present invention; Among them, 100 is the numerical comparison module; 201 is the first logic AND module; 202 is the first logic AND submodule of the second logic AND module; 203 is the second logic AND submodule of the second logic AND module; 204 is the third logic AND module; 301 is the first multi-multiplication addition module; 302 is the second multi-multiplication addition module; 400 is the open delay module; 500 is the logic OR module; and 600 is the RS flip-flop module. Detailed Implementation
[0020] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0022] It is understood that the terms "first," "second," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.
[0023] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.
[0024] It is understandable that "at least one" refers to one or more, and "multiple" refers to two or more. "At least a part of an element" refers to part or all of an element.
[0025] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.
[0026] Please see Figure 1 As shown, a feedback signal monitoring function block applied to a safety control system includes: several AND modules (AND6), a numerical comparison module 100 (CMPR), an on-delay module 400 (TON), an OR module 500 (OR6), an RS flip-flop module 600 (LTCH), a first multi-multiply adder module 301 (MULADD), and a second multi-multiply adder module 302 (MULADD). In the following description of this invention, a pin output of 1 indicates a high-level output signal, and a pin output of 0 indicates a low-level output signal.
[0027] The numerical comparison module 100 is used to compare the readback signal and the actual output signal of the module to output a readback monitoring signal. The first logic AND module 201 is used to perform an AND operation on the quality code signal corresponding to the readback signal and the inverted signal of the readback monitoring signal to output a feedback and output difference comparison signal; The first multi-multiplication addition module 301 is used to multiply and sum the preset number of cycles and the cycle coefficient to output the difference time cycle number signal; The second multi-multiplication adder module 302 is used to multiply and sum the difference time cycle number signal and the scan cycle duration to output the actual difference duration; The delay module 400 is used to compare the feedback and output difference comparison signal and the difference time period number signal to output a pre-alarm signal. The logic OR module 500 is used to perform an OR operation based on the inverted signals of the manual reset signal and the automatic reset signal to output a reset alarm signal. The RS trigger module 600 is used to retain alarm information based on the pre-alarm signal and the reset alarm signal, so as to output a status warning signal. The second logic AND module is used to perform an AND operation on the status warning signal to output the actual alarm signal and the alarm confirmation signal; The third logic AND module 204 is used to perform an AND operation on the inverted signal of the actual alarm signal, the module pre-output signal, and the quality code signal corresponding to the readback signal, so as to output the actual output signal of the module.
[0028] In this embodiment of the invention, the numerical comparison module 100 compares the states of two signals; the module has two input variables, namely the first data input pin and the second data input pin, and five state output variables, namely the output pin greater than the result, the output pin greater than or equal to the result, the output pin equal to the result, the output pin less than or equal to the result, and the output pin less than the result.
[0029] Wherein, the first data input pin of the numerical comparison module 100 is connected to the actual output signal of the module (FDBACK_FDB_Q.AV), the readback signal (FDBACK_FEEDBACK_Q.AV) of the numerical comparison module 100, and the equal result output pin are respectively connected to the data output pins of the second logic AND submodule in the first logic AND module 201 and the second logic AND module.
[0030] Specifically, the actual output signal of the module is a reliable signal value output after diagnosis by the feedback signal monitoring function block. When the module's pre-output signal (FDBACK_ON.AV) and the readback signal do not change synchronously within the difference time and the alarm is not confirmed, or when the quality code signal (FDBACK_QBAD_FIO.AV) corresponding to the readback signal is 0, the actual output signal of the module will always be 0.
[0031] Wherein, when the quality code signal corresponding to the readback signal is 1, it indicates that the signal is normal and without fault, and when the quality code is 0, it indicates that the signal is faulty; the module pre-output signal is the signal output by the feedback signal monitoring function block required by the safety system (which has not yet been monitored and judged by the feedback signal monitoring function block), and the readback signal is the signal that is finally applied to the corresponding output relay after being judged by the feedback signal monitoring function block.
[0032] like Figure 1 As shown, in the numerical comparison module 100, EN is the enable control pin, IN1 and IN2 are the first data input pin and the second data input pin, respectively. The normally closed contact signal in the mutual exclusion contact signal is used as the comparison value. GT, GE, EQ, LE, and LT are respectively greater than the result output pin, greater than or equal to the result output pin, equal to the result output pin, less than or equal to the result output pin, and less than the result output pin. When IN1 is greater than, greater than or equal to, equal to, less than or equal to, and less than the value of IN2, the five output pins output 1 respectively.
[0033] In this embodiment of the invention, when the actual output signal of the module and the readback signal are different, the equal result output pin of the numerical comparison module 100 outputs a low-level signal as the readback monitoring signal. The inverted readback monitoring signal is input to the second control signal input pin of the first logic AND module 201.
[0034] In this embodiment of the invention, the logical AND module implements a logical AND operation on six digital input variables. The module has six digital input variables and one digital output variable; IN1~IN6 are input values, and Q is the output; the output is 1 if and only if all input values are 1; the output is 0 if any input value is 0. Specifically, the first logic AND module 201 includes a first control signal input pin, a second control signal input pin, and a data output pin; such as Figure 1 As shown, IN1 is the first control signal input pin, IN2 is the second control signal input pin, Q is the data output pin, EN is the enable control pin, and IN3~IN6 are set to 1.
[0035] In this embodiment of the invention, the first control signal input pin of the first logic AND module 201 is connected to the quality code signal (FDBACK_QBAD_FIO.AV) corresponding to the readback signal, and the second control signal input pin of the first logic AND module 201 is connected to the inverted signal of the readback monitoring signal; When the quality code signal corresponding to the readback signal is a high-level signal and the readback monitoring signal is a low-level signal, the data output pin of the first logic AND module 201 outputs a high-level signal as a feedback and output difference comparison signal, indicating that the quality code signal corresponding to the readback signal is normal and the readback signal and the actual output signal of the module are out of sync, requiring further monitoring and feedback.
[0036] In this embodiment of the invention, the multi-multiplication addition module realizes the multiplication and summation of three sets of variable inputs; the module has 6 variable inputs and 1 variable output, that is, the multi-multiplication addition module includes three data input pins, three coefficient input pins and a data output pin; the three data input pins are the first data input pin, the second data input pin and the third data input pin, and the three coefficient input pins are the first coefficient input pin, the second coefficient input pin and the third coefficient input pin.
[0037] like Figure 1 As shown, in the multi-multiply-add module, K1 is the first data input pin, X1 is the first coefficient input pin, K2 is the second data input pin, X2 is the second coefficient input pin, K3 is the third data input pin, X3 is the first coefficient input pin, and Q is the data output pin, where Q=K1. X1+K2 X2+K3 X3, the default value for the unlinked data output pin is 0.0.
[0038] In this embodiment of the invention, the first data input pin of the first multi-multiplication addition module 301 is connected to a preset number of cycles (e.g., 20), the first coefficient input pin of the first multi-multiplication addition module 301 is connected to a cycle coefficient (e.g., 1), and the remaining data input pins and coefficient input pins are all set to 0. The first multi-multiplication addition module 301 performs multiplication and summation to obtain a difference time of 20 cycles. The data output pin of the first multi-multiplication addition module 301 outputs a difference time cycle number signal to represent 20 controller scan cycles, so as to realize the preset time of the open delay signal. In the second multi-multiply adder module 302, the first data input pin is connected to the difference time cycle number signal (e.g., 20). In the first multi-multiply adder module 301, the first coefficient input pin is connected to the scan cycle duration (e.g., 50, unit set to ms). All other data input pins and coefficient input pins are set to 0. The second multi-multiply adder module 302 performs multiplication and summation to obtain a difference time of 1000ms. The data output pin of the second multi-multiply adder module 302 outputs the actual difference duration (FDBACK_FDB_TIME.AV) as 1000ms.
[0039] In this embodiment of the invention, the delay module 400 includes a trigger signal input pin, a preset time input pin, and a status output pin; The trigger signal input pin of the open delay module 400 is connected to the feedback and output difference comparison signal, the preset time input pin of the open delay module 400 is connected to the data output pin of the first multi-multiply-add module 301, and the status output pin of the open delay module 400 is connected to the set pin of the RS trigger module 600.
[0040] like Figure 1 As shown, in the open delay module 400, EN is the enable control pin, IN is the trigger signal input pin for timing control pulse, PT is the preset time input pin, Q is the elapsed time output pin, and ET is the status output pin. The open delay module 400 implements the following: when IN is 1, the delay count takes effect, and 1 is output after a delay of PT. At this time, ET = ET + 1 per cycle. When IN is 0 at any time, Q and ET are simultaneously cleared to zero. The integer input variable PT is the delay difference time; the digital output variable Q is the timing output. When Q = 1, the delay count ends; the integer output variable ET is the current timing value. When ET = PT, Q output is 1.
[0041] In a practical application scenario of this invention, the delay time of the PT in the delay module 400 is calculated based on the number of scan cycles, rather than the PT delay time being directly input in some systems. For example, if the delay module 400 needs to output 1 when the input is a high-level signal for more than 500ms, then when the logic page scan cycle length is set to 50ms, 10 needs to be input on the PT pin, representing that the output is 1 after 10 scan cycles. Similarly, when the page scan cycle length is 100ms, if a delay of 500ms is required (i.e., the actual difference time is 500ms), 500 / 100=5 needs to be input on the PT pin, and so on.
[0042] In this embodiment of the invention, the feedback signal monitoring function block determines whether the actual output signal of the module is faulty based on the following: when the actual output signal of the module changes, the corresponding output relay readback signal needs to change to the same value within the set signal difference time (i.e., FDBACK_FDB_TIME.AV), otherwise a pre-alarm signal will be output.
[0043] Therefore, when the continuous trigger duration of the feedback and output difference comparison signal output by the first logic AND module 201 is greater than the duration of the difference time cycle number signal, the status output pin of the open delay module 400 outputs a high-level signal as the pre-alarm signal.
[0044] In this embodiment of the invention, the logic OR module 500 implements a logic OR operation on 6 digital input variables; the module has 6 digital input variables and 1 digital output variable; IN1~IN6 are input values, and Q is the output; the output is 0 if and only if all input values are 0; the output is 1 if any input value is 1.
[0045] like Figure 1 As shown, in the logic OR module 500, IN1 is the first control signal input pin, IN2 is the second control signal input pin, Q is the data output pin, EN is the enable control pin, FDBACK_Acksum.AV is the manual reset signal, and FDBACK_ACK_NEC.AV is the automatic reset signal.
[0046] In this embodiment of the invention, the first control signal input pin of the logic OR module 500 is connected to a manual reset signal, the second control signal input pin of the logic OR module 500 is connected to the inverted signal of the automatic reset signal, and the data output pin of the logic OR module 500 is connected to the reset pin of the RS flip-flop module 600.
[0047] In this embodiment of the invention, when either the manual reset signal or the inverted signal of the automatic reset signal is 1, the data output pin of the logic OR module 500 outputs 1.
[0048] When FDBACK_ACK_NEC.AV is 1, it means that manual confirmation is required, and 0 means that the safety system automatically confirms the alarm. When FDBACK_Acksum.AV is 1, it means that a high-level short pulse is given to IN2 of the logic OR module 500 to confirm the alarm, and then the pin that sends the actual alarm signal (FDBACK_FDB_ERROR.AV) is reset to 0.
[0049] In this embodiment of the invention, the RS trigger module 600 has two digital input variables and two digital output variables. EN is the enable control pin, S is the set pin, R is the reset pin, Q_RS is the reset priority output pin, and Q_SR is the set priority output pin.
[0050] Specifically, the set pin of the RS trigger module 600 is connected to the pre-alarm signal, the reset pin of the RS trigger module 600 is connected to the reset alarm signal, and the set priority output pin of the RS trigger module 600 is connected to the control signal input pin of the second logic AND module.
[0051] When the actual output signal of the module changes, if the corresponding output relay readback signal does not change to the same value within the time difference, the output pre-alarm signal is sent to the set pin of the RS trigger module 600 to trigger the status warning.
[0052] When the reset alarm signal is 0 and the pre-alarm signal is 1, the set priority output pin outputs 1; When the reset alarm signal is 1 and the pre-alarm signal is 0, the set priority output pin outputs 0 and the set priority output pin outputs 0. When the reset alarm signal is 0 and the pre-alarm signal is 0, the output of the set priority output pin and the output of the set priority output pin remain unchanged. When the reset alarm signal is 1 and the pre-alarm signal is 1, the set priority output pin outputs 0 and the set priority output pin outputs 1.
[0053] In this embodiment of the invention, the second logic AND module includes a first logic AND submodule 202 and a second logic AND submodule 203, wherein the first logic AND submodule 202 and the second logic AND submodule 203 respectively include a control signal input pin and a data output pin.
[0054] like Figure 1 As shown, in the first logic AND submodule 202, IN1 is the control signal input pin, EN is the enable control pin, Q is the data output pin, IN2~IN6 are set to 1, and FDBACK_FDB_ERROR.AV is the actual alarm signal; In the second logic AND submodule 203, IN1 is the control signal input pin, EN is the enable control pin, Q is the data output pin, IN2~IN6 are set to 1, and FDBACK_FDB_ACK_REQ.AV is the alarm confirmation signal.
[0055] In this embodiment of the invention, the set-priority output pin of the RS trigger module 600 is connected to the control signal input pins of the first logic AND submodule 202 and the second logic AND submodule 203, respectively. The data output pin of the first logic AND submodule 202 is connected to the actual alarm signal, and the data output pin of the second logic AND submodule 203 is connected to the alarm confirmation signal.
[0056] When the status warning signal and the readback monitoring signal are both 1, the first logic AND submodule 202 outputs an actual alarm signal of 1, and the other level signal combinations of the status warning signal and the readback monitoring signal, and the corresponding alarm confirmation signals are all 0.
[0057] Specifically, the actual alarm signal serves as the alarm output of the feedback monitoring module. When the module's pre-output signal and the readback signal do not change synchronously within the time difference, the actual alarm signal will be output as 1.
[0058] When the actual alarm signal is 1 and the feedback and output difference comparison signal returns to 0, the alarm confirmation signal also becomes 1, indicating that an alarm has occurred and needs to be confirmed. When the actual alarm signal is manually or automatically confirmed and reset, or when the actual alarm signal is not confirmed and the feedback and output difference comparison signal is still 1, the alarm confirmation signal automatically returns to 0.
[0059] When the module's pre-output signal and readback signal are synchronized, this alarm can be confirmed: a short high-level pulse is given to the IN1 pin of the logic OR module 500 to generate a manual reset signal for alarm confirmation, after which the actual alarm signal is restored to 0.
[0060] In this embodiment of the invention, the third logic AND module 204 includes a first control signal input pin, a second control signal input pin, a third control signal input pin, and a data output pin.
[0061] like Figure 1 As shown, IN1 is the first control signal input pin, IN2 is the second control signal input pin, IN3 is the third control signal input pin, Q is the data output pin, EN is the enable control pin, FDBACK_ON.AV is the module pre-output signal, FDBACK_QBAD_FIO.AV is the quality code signal corresponding to the readback signal, and FDBACK_FDB_Q.AV is the module actual output signal.
[0062] In this embodiment of the invention, the first control signal input pin of the third logic AND module 204 is connected to the module pre-output signal, the second control signal input pin of the third logic AND module 204 is connected to the inverted signal of the actual alarm signal, and the third control signal input pin of the third logic AND module 204 is connected to the quality code signal corresponding to the readback signal.
[0063] When the module pre-output signal is a high-level signal, the actual alarm signal is a low-level signal, and the quality code signal corresponding to the readback signal is a high-level signal, an AND operation is performed, and the data output pin of the third logic AND module 204 outputs the actual output signal of the module as a high-level signal; The remaining level signal combinations of the quality code signals corresponding to the module pre-output signal, the actual alarm signal, and the readback signal, and the actual output signal of the data output pin of the third logic AND module 204 are all low-level signals. Specifically, the actual output signal of the module output by the third logic AND module 204 is a trustworthy signal value output after diagnosis by the feedback signal monitoring function block. The feedback signal monitoring function block outputs a trustworthy value of 1 only when the module pre-output signal is 1, the module does not alarm (i.e., the actual alarm signal is 0), and the quality code signal corresponding to the readback signal is 1 (i.e., the quality code is normal).
[0064] In summary, this invention, through the design and combination of various basic functional modules such as the AND module, numerical comparison module, open delay module, RS flip-flop module, and OR module, monitors the readback signal of the output signal relay (obtained through the input module) and confirms whether the relay corresponding to the signal required by the safety system has acted correctly as required. This ensures the reliability and security of the key output signals of the safety system, and improves the maintainability and scalability of the system through the combined design of basic functional modules.
[0065] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A feedback signal monitoring function block applied to a safety control system, characterized in that, include: The system includes several logic AND modules, a numerical comparison module, an open delay module, an RS flip-flop module, and a logic OR module, wherein the several logic AND modules include a first logic AND module, a second logic AND module, and a third logic AND module. The numerical comparison module is used to compare the readback signal and the actual output signal of the module to output a readback monitoring signal. The first logic AND module is used to perform an AND operation on the quality code signal corresponding to the readback signal and the inverted signal of the readback monitoring signal to output a feedback and output difference comparison signal; The open delay module is used to compare the feedback and output difference comparison signal and the difference time period number signal to output a pre-alarm signal. The logic OR module is used to perform an OR operation based on the inverted signals of the manual reset signal and the automatic reset signal to output a reset alarm signal. The RS trigger module is used to retain alarm information based on the pre-alarm signal and the reset alarm signal, so as to output a status warning signal. The second logic AND module is used to perform an AND operation on the status warning signal to output the actual alarm signal and the alarm confirmation signal; The third logic AND module is used to perform an AND operation on the inverted signal of the actual alarm signal, the module pre-output signal, and the quality code signal corresponding to the readback signal, so as to output the actual output signal of the module.
2. The feedback signal monitoring function block for a safety control system according to claim 1, characterized in that, The numerical comparison module includes a first data input pin, a second data input pin, and an equal result output pin; The first data input pin of the numerical comparison module is connected to the actual output signal of the module, the second data input pin of the numerical comparison module is connected to the readback signal, and the equal result output pin is connected to the data output pin of the first logic AND module. When the actual output signal of the module is different from the readback signal, the equal result output pin of the numerical comparison module outputs a low-level signal as the readback monitoring signal.
3. The feedback signal monitoring function block for a safety control system according to claim 1, characterized in that, The first logic AND module includes a first control signal input pin, a second control signal input pin, and a data output pin; The first control signal input pin of the first logic AND module is connected to the quality code signal corresponding to the readback signal, and the second control signal input pin of the first logic AND module is connected to the inverted signal of the readback monitoring signal; When the quality code signal corresponding to the readback signal is a high-level signal and the readback monitoring signal is a low-level signal, the data output pin of the first logic AND module outputs a high-level signal as a feedback and output difference comparison signal.
4. The feedback signal monitoring function block for a safety control system according to claim 1, characterized in that, The delay module includes a trigger signal input pin, a preset time input pin, and a status output pin. The trigger signal input pin of the open delay module is connected to the feedback and output difference comparison signal, the preset time input pin of the open delay module is connected to the difference time cycle number signal, and the status output pin of the open delay module is connected to the set pin of the RS trigger module. When the continuous trigger duration of the feedback and output difference comparison signal output by the first logic AND module is greater than the duration of the difference time cycle number signal, the status output pin of the open delay module outputs a high-level signal as the pre-alarm signal.
5. The feedback signal monitoring function block for a safety control system according to claim 1, characterized in that, Also includes: First multi-multiplication addition module and second multi-multiplication addition module; The first multi-multiplication addition module is used to multiply and sum the preset number of cycles and the cycle coefficient to output the difference time cycle number signal; The second multi-multiplication adder module is used to multiply and sum the difference time period number signal and the scan period duration to output the actual difference duration.
6. The feedback signal monitoring function block for a safety control system according to claim 1, characterized in that, The logic or module includes a first control signal input pin, a second control signal input pin, and a data output pin; The first control signal input pin of the logic OR module is connected to the manual reset signal, the second control signal input pin of the logic OR module is connected to the inverted signal of the automatic reset signal, and the data output pin of the logic OR module is connected to the reset pin of the RS flip-flop module. When either the manual reset signal or the inverted signal of the automatic reset signal is a high-level signal, the data output pin of the logic OR module outputs a high-level signal.
7. The feedback signal monitoring function block for a safety control system according to claim 1, characterized in that, The RS flip-flop module includes a set pin, a reset pin, and a set-priority output pin. The set pin of the RS trigger module is connected to the pre-alarm signal, the reset pin of the RS trigger module is connected to the reset alarm signal, and the set priority output pin of the RS trigger module is connected to the control signal input pin of the second logic AND module. When the reset alarm signal is a low-level signal and the pre-alarm signal is a high-level signal, the set priority output pin outputs a status warning signal that is a high-level signal. When the reset alarm signal is a high-level signal and the pre-alarm signal is a low-level signal, the set priority output pin outputs a status warning signal that is a low-level signal. When the reset alarm signal is a low-level signal and the pre-alarm signal is a low-level signal, the status warning signal output by the set priority output pin remains unchanged; When the reset alarm signal is a high-level signal and the pre-alarm signal is a high-level signal, the set priority output pin outputs a status warning signal that is a low-level signal.
8. The feedback signal monitoring function block for a safety control system according to claim 1, characterized in that, The second logic AND module includes a first logic AND submodule, which includes a control signal input pin and a data output pin. The set-priority output pin of the RS trigger module is connected to the control signal input pin of the first logic AND submodule, and the data output pin of the first logic AND submodule is connected to the actual alarm signal. When the status warning signal is a high-level signal, the first logic AND submodule outputs an actual alarm signal as a high-level signal. When the status warning signal is a low-level signal, the first logic AND submodule outputs an actual alarm signal that is a low-level signal.
9. The feedback signal monitoring function block for a safety control system according to claim 1, characterized in that, The second logic AND module includes a second logic AND submodule, which includes control signal input pins and data output pins; The set priority output pin of the RS trigger module and the equal result output pin of the numerical comparison module are respectively connected to the control signal input pin of the second logic AND submodule, and the data output pin of the second logic AND submodule is connected to the alarm confirmation signal. When the status warning signal and the readback monitoring signal are both high-level signals, the second logic AND submodule outputs an alarm confirmation signal that is also high-level.
10. The feedback signal monitoring function block for a safety control system according to claim 1, characterized in that, The third logic AND module includes a first control signal input pin, a second control signal input pin, a third control signal input pin, and a data output pin; The first control signal input pin of the third logic AND module is connected to the module's pre-output signal, the second control signal input pin of the third logic AND module is connected to the inverted signal of the actual alarm signal, and the third control signal input pin of the third logic AND module is connected to the quality code signal corresponding to the readback signal. When the module's pre-output signal is a high-level signal, the actual alarm signal is a low-level signal, and the quality code signal corresponding to the readback signal is a high-level signal, an AND operation is performed, and the data output pin of the third logic AND module outputs the actual output signal of the module as a high-level signal.