A method and system for hardware fault control based on motor controller

Abstract

This invention discloses a hardware fault control method and system based on a motor controller. The method includes configuring a hardware fault signal as an interrupt trigger input for the microcontroller; after system power-on initialization, resetting the driver chip and then enabling the hardware latch circuit, which latches the hardware fault signal and outputs a total hardware fault signal; monitoring the hardware fault signal, and when the trigger edge of the hardware fault pin is interrupted, determining whether the current motor state meets preset conditions; if the conditions are met, setting the corresponding software fault flag; acquiring the software fault flag and the total hardware fault signal output by the hardware latch circuit, and combining this with whether the motor is currently under high-voltage power-on, performing fault diagnosis and corresponding protection and recovery operations. This invention solves the technical problems of slow hardware fault diagnosis response speed, easy false alarms during power-on, and limited fault recovery strategies in existing technologies.

Description

Technical Field

[0001] This invention relates to the field of new energy motor controller technology, and in particular to a hardware fault control method and system based on a motor controller. Background Technology

[0002] In recent years, with the deepening demands of the automotive industry, automotive system control schemes have become more complex, and electrical systems are constantly being updated. As a core component of the motor system, the motor controller (MCU) has a significant impact on the performance and efficiency of the motor. With continuous technological advancements and increasing application demands, the motor controller industry is also constantly evolving and transforming. The controller needs to process critical hardware signals such as bus voltage, phase current, and drive chip status in real time. Any hardware fault must be quickly and accurately diagnosed and protected against to prevent catastrophic consequences.

[0003] Currently, the mainstream solutions for hardware fault diagnosis of motor controllers can be divided into two categories: one is a pure software diagnostic solution, which captures the state of faulty pins through periodic sampling or interrupts of the microcontroller; the other is a pure hardware latching solution, which directly latches the fault and shuts down the power transistor through logic circuits. However, both solutions have inherent drawbacks: the response speed of the pure software solution is affected by software loops and interrupt priorities, resulting in delays, and may not provide sufficiently fast protection under extreme fault conditions; at the same time, the software is susceptible to electromagnetic interference or program crashes, posing a reliability risk; while the pure hardware solution responds quickly, once latched, it usually requires a complete system power-down to reset, lacking flexibility. Especially during the system power-on initialization phase, the states of various chips and circuits are not yet stable, and the hardware latching circuit is prone to false latches due to timing competition, causing the system to fail to start normally. In addition, the fault recovery mechanisms of existing solutions are often simplistic, failing to distinguish whether the fault occurs in the system's high-voltage operating state or low-voltage standby state, which may lead to unnecessary system power-downs in non-dangerous conditions, reducing system availability.

[0004] Therefore, how to design a method for diagnosing and protecting motor controller hardware faults that is fast and accurate, has strong resistance to false alarms, and can intelligently recover based on the system status has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] To address the aforementioned shortcomings of existing technologies, this invention provides a hardware fault control method and system based on a motor controller. By employing dual diagnosis through software and hardware collaboration, power-on initialization timing, and differentiated recovery based on high-voltage conditions, it solves the technical problems of slow hardware fault diagnosis response speed, susceptibility to false alarms during power-on, and limited fault recovery strategies in existing technologies.

[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0007] A hardware fault control method based on a motor controller includes the following steps:

[0008] S1. Configure the hardware fault signal as an interrupt trigger input for the microcontroller;

[0009] S2. After the system is powered on and initialized, the driver chip is reset first, and then the hardware latch circuit is enabled so that the hardware latch circuit enters the fault detection state; the hardware latch circuit is used to latch the hardware fault signal and output the hardware total fault signal.

[0010] S3. Monitor the hardware fault signal. When the hardware fault pin triggers an edge interruption, determine whether the current motor state meets the preset conditions. If the conditions are met, set the corresponding software fault flag.

[0011] S4. Obtain the software fault flag and the hardware total fault signal output by the hardware latch circuit.

[0012] S5. Based on the obtained software fault flags and hardware total fault signals, and considering whether the motor is currently under high voltage, perform fault diagnosis and corresponding protection and recovery operations.

[0013] As a preferred embodiment, in step S1, the hardware fault signal configuration is executed in the control abstraction layer of the basic software layer, specifically including:

[0014] Configure the PORT module, set the hardware fault pin as the input direction, and initialize the level and pull-up / pull-down mode;

[0015] Configure the ICU module, assign an input capture unit to the hardware fault pin, and set the edge-triggered mode;

[0016] Configure the IRQ module to allocate interrupt resources for hardware fault pins, including interrupt source, interrupt type and interrupt priority.

[0017] As a preferred embodiment, in step S2, the enabling hardware latch circuit includes: after the driver chip is successfully reset, delaying for a preset time, and then switching the hardware latch circuit from the reset state to the enable state; the hardware latch circuit has a reset enable terminal FLTRST pin; the FLTRST pin is at a high level in the reset state and at a low level in the enable state.

[0018] As a preferred embodiment, in step S3, the preset condition is: the motor is not in a dormant state and has not entered an active short-circuit state.

[0019] As a preferred embodiment, in step S3, the software fault flag corresponding to the setting specifically includes: setting independent software fault flag bits for hardware overcurrent fault, hardware overvoltage fault and driver chip fault respectively, and setting them in the corresponding interrupt service function respectively.

[0020] As a preferred embodiment, in step S4, the acquisition of the software fault flag and the total hardware fault signal is achieved by transmitting the software fault flag and the total hardware fault signal from the basic software layer to the application software layer through the runtime environment interface.

[0021] As a preferred embodiment, step S5, specifically the processing of performing fault diagnosis and corresponding protection and recovery operations, includes:

[0022] When the motor is under high voltage, permanent shutdown protection is implemented until the system is powered off.

[0023] When the motor is not under high voltage, a temporary shutdown protection is executed, and the system is reset.

[0024] As a preferred embodiment, the execution of temporary shutdown protection and triggering system reset specifically includes: within a preset number of consecutive resets, if the fault disappears after the reset, the system resumes normal operation; if the fault still exists after the preset number of resets, permanent shutdown protection is executed until the system is powered down.

[0025] A hardware fault control system based on a motor controller, characterized in that, for implementing the aforementioned hardware fault control method based on a motor controller, it includes:

[0026] The hardware latch circuit has a reset enable terminal, which is used to latch hardware fault signals and output a total hardware fault signal.

[0027] A microcontroller, connected to the hardware fault signal source and the hardware latch circuit, is used to execute the steps of the hardware fault control method based on the motor controller described above.

[0028] Compared with the prior art, the present invention has the following technical effects:

[0029] 1. This invention uses a hardware latching circuit to monitor and latch hardware fault signals such as overcurrent, overvoltage, and driver chip failure. Once a valid fault is detected, the hardware latching circuit can directly trigger an emergency shutdown, improving the protection response speed. At the same time, the microcontroller captures the same fault signal through an interrupt and sets a software fault flag when preset conditions are met for subsequent fault diagnosis and status recording. In this way, the hardware circuit and software interrupt work in parallel, which not only ensures the real-time fault response but also avoids the risk caused by the failure of a single mechanism, significantly improving the safety and reliability of the system.

[0030] 2. After the system is powered on and initialized, the present invention first resets the driver chip to clear any transient abnormal states that may have occurred during the initialization process, and then enables the hardware latch circuit to enter the fault detection state. This timing design avoids the hardware latch circuit from mistakenly capturing other fault signals and generating false fault latches when the driver chip is not stable, thus solving the problem in the prior art where the motor controller cannot start normally due to false alarms upon power-on.

[0031] 3. This invention differentiates the recovery operation after a fault based on whether the motor is under high voltage: when the fault occurs during high-voltage operation, the system performs permanent shutdown protection until the entire vehicle is powered off, ensuring absolute safety under extreme conditions; when the fault occurs during non-high-voltage operation (such as pre-charging or standby), the system attempts to recover by resetting after performing shutdown protection, and switches to permanent protection only if the fault persists after a preset number of consecutive resets; thus, it ensures safety during high-voltage operation and avoids permanent system failure due to a single fault in non-dangerous conditions, improving the system's fault tolerance and availability. Attached Figure Description

[0032] To make the objectives, technical solutions, and advantages of the invention clearer, the invention will now be described in further detail with reference to the accompanying drawings, wherein:

[0033] Figure 1 This is a flowchart of a hardware fault control method based on a motor controller disclosed in this invention;

[0034] Figure 2 This is a flowchart of a hardware fault control method based on a motor controller in an embodiment of the present invention. Detailed Implementation

[0035] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to represent selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0037] It should be noted that similar reference numerals and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the figures, or the orientation or positional relationship commonly used when the product is in use. They are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance. In addition, the terms "horizontal," "vertical," etc., do not indicate that the component is required to be absolutely horizontal or suspended, but can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted. In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0038] Example 1:

[0039] With the rapid development of the new energy vehicle industry, the motor controller, as a core component of the electric drive system, directly affects the safety and reliability of the entire vehicle. Currently, there are two main approaches to hardware fault diagnosis for motor controllers: pure software diagnostics and pure hardware latching. However, both approaches have inherent drawbacks: the response speed of pure software solutions is affected by software task scheduling and interrupt priorities, posing a risk of protection delays under extreme fault conditions; while pure hardware solutions offer rapid response, once latched, they typically require a complete system power-down to reset, lacking flexibility. Furthermore, hardware latching circuits are highly susceptible to false latches due to timing races, preventing the system from starting normally. In addition, existing fault recovery mechanisms are often simplistic, failing to distinguish between high-voltage operation and low-voltage standby states, potentially leading to unnecessary system power-downs in non-hazardous conditions and reducing system availability.

[0040] Therefore, in response to the above-mentioned problems, this invention proposes a hardware fault control method based on a motor controller. This method aims to achieve rapid and reliable fault response, effectively avoid false alarms during startup, and intelligently execute recovery operations according to the actual operating status of the system, thereby comprehensively improving the safety, availability, and fault tolerance of the motor controller.

[0041] Specifically, the hardware fault control method based on a motor controller proposed in this invention, such as... Figure 1 and Figure 2 As shown, it includes the following steps:

[0042] S1. Configure the hardware fault signal as an interrupt trigger input for the microcontroller;

[0043] Furthermore, the hardware fault signal configuration is executed in the Control Abstraction Layer (MCAL) of the Basic Software (BSW) layer. The MCAL configuration specifically includes: configuring the hardware overcurrent fault pin, hardware overvoltage fault pin, and driver chip fault pin as input directions through the PORT module, and setting the initial level and pull-up / pull-down mode; allocating input capture units to the above-mentioned hardware fault pins through the ICU module, and setting the falling edge trigger mode; and configuring interrupt resources for the above-mentioned hardware fault pins through the IRQ module, including interrupt source, interrupt type, and interrupt priority.

[0044] In this embodiment, the MCAL configuration tool based on the AUTOSAR architecture is used to configure the microcontroller abstraction layer, specifically including parameter settings for the PORT module, ICU module, and IRQ module.

[0045] (1) PORT Module Configuration: The PORT module configuration tool is used to set the direction, level, and mode of the hardware fault-related pins. The pins involved in this embodiment include: hardware overcurrent fault pin (named OCP), hardware overvoltage fault pin (named OVP), driver chip fault pin (named DRV), latch circuit reset pin (named FLTRST), and hardware general fault pin (named FAULT). The configuration parameters for each pin are shown in Table 1:

[0046] Table 1 Configuration parameters for each pin

[0047]

[0048] After the above configuration is completed, the OVP, OCP, and DRV pins are set to the input direction and internal pull-up resistors are enabled to ensure that the pins remain high in a fault-free state; the FLTRST pin is set to the output direction and initialized to high-level output; the FAULT pin is set to the input direction and internal pull-up resistors are enabled.

[0049] (2) ICU Module Configuration: Using the ICU module configuration tool, assign input capture units to the three hardware fault pins: OVP, OCP, and DRV. Specifically, associate the three pins with the ERU (Event Response Unit) channel, set the trigger edge to falling edge trigger (ICU_FALLING_EDGE), and assign a corresponding ERU channel pin number to each pin. This configuration enables the corresponding event response to be triggered when any hardware fault pin detects a falling edge signal.

[0050] (3) IRQ Configuration: Configure interrupt resources for the three hardware fault pins, OVP, OCP, and DRV, using the IRQ module configuration tool. Specifically, set the interrupt mode to Scu interrupt mode, assign the interrupt source to CPU0, set the interrupt type to CAT1, and set the interrupt priorities to 61, 62, and 63 respectively (adjustable according to system requirements). This configuration ensures that when a hardware fault is triggered, the CPU can respond promptly and execute the corresponding interrupt service function.

[0051] S2. After the system is powered on and initialized, the driver chip is reset first, and then the hardware latch circuit is enabled so that the hardware latch circuit enters the fault detection state; the hardware latch circuit is used to latch the hardware fault signal and output the hardware total fault signal.

[0052] Furthermore, the enabling hardware latch circuit includes: after the driver chip is successfully reset, a preset time is delayed before switching the hardware latch circuit from the reset state to the enabled state; the hardware latch circuit has a reset enable terminal FLTRST pin; the FLTRST pin is at a high level in the reset state and at a low level in the enabled state.

[0053] (1) Software and hardware initialization: After the system is powered on, software and hardware initialization is performed first. Software initialization includes the initialization of the MCU driver module, specifically involving the driver initialization of the GTM module, PORT module, ICU module, IRQ module, etc., as well as the initialization configuration of all peripheral chips (including driver chips). Hardware initialization includes the initial state establishment of the hardware fault detection circuit and the hardware latch circuit. After initialization, the state of each pin is as follows: OVP, OCP and DRV pins are at high level by default (no fault), FLTRST pin is at high level by default (reset and clear), and FAULT pin is at low level by default (no fault).

[0054] (2) Reset of driver chip: Based on the initialization of the vehicle power-on software and the initial timing of the hardware circuit, it is possible that after the software initialization is completed, the fault diagnosis will begin. At this time, the fault pin (DRV) of the hardware driver chip is not completed and the level is low. At the same time, the driver chip itself has a fault latching function, and the software will falsely report a driver chip fault. Therefore, after the software initialization is completed, the driver chip is reset through the pin or register (according to the driver chip mechanism) to clear the driver chip output fault during the initialization phase.

[0055] (3) Latch circuit reset: The hardware latch circuit used in this embodiment has the following logic functions: When the latch circuit is in a valid detection state (i.e., the latch reset pin is low level), if any of the pins of OVP, OCP and DRV is low level (fault), the latch circuit immediately latches the fault state and sets the output of the hardware total fault pin (FAULT) to high level (fault); if all fault pins are high level (no fault), the FAULT pin remains low level.

[0056] Based on the above circuit logic and considering the timing requirements of the component logic gates, the hardware latch circuit can only enter the fault detection state after software initialization and driver chip reset are both completed. The specific operation is as follows:

[0057] After software initialization, the FLTRST pin remains high by default, and the hardware latch circuit is in a reset state, not responding to any fault input. After the driver chip is successfully reset and the FLTRST pin remains high for a preset time (20ms in this embodiment), the FLTRST pin is pulled low. After the FLTRST pin is pulled low, the hardware latch circuit enters an effective detection state, starts to monitor the input signals of the OVP, OCP and DRV pins in real time, and latches faults. At the same time, the MCU emergency shutdown register is cleared to ensure that subsequent hardware faults can trigger the MCU's emergency shutdown protection.

[0058] At this point, the hardware latch circuit enters normal operating mode, and the system has the capability for hardware-level fault detection and rapid protection.

[0059] S3. Monitor the hardware fault signal. When the hardware fault pin triggers an edge interruption, determine whether the current motor state meets the preset conditions. If the conditions are met, set the corresponding software fault flag.

[0060] Furthermore, the preset conditions are: the motor is not in a sleep state and has not entered an active short-circuit state.

[0061] In this embodiment, corresponding interrupt service functions are defined for the three hardware fault pins: OVP, OCP, and DRV, named ISR_OVP, ISR_OCP, and ISR_DRV, respectively. When a falling edge signal is detected on any hardware fault pin, the corresponding interrupt is triggered, and the CPU immediately executes the corresponding interrupt service function.

[0062] In the interrupt service routine, to avoid false hardware fault reports under specific operating conditions, the following judgment conditions are set:

[0063] Determine whether the current motor operating state is in sleep mode (OperMod != SleepMod);

[0064] Determine if the current state is an active short circuit (ASC_State != 1);

[0065] When both of the above conditions are met simultaneously—that is, the motor is not in sleep mode and has not entered an active short-circuit state—the corresponding fault flag is set to 1, indicating that a valid fault has been detected; otherwise, the fault flag is set to 0, indicating that the current fault is an invalid trigger or a false alarm. Specifically: in ISR_OVP, if the condition is met, OVP_State = 1 (hardware overvoltage fault); in ISR_OCP, if the condition is met, OCP_State = 1 (hardware overcurrent fault); in ISR_DRV, if the condition is met, DRV_State = 1 (driver chip fault). Through the above judgment logic, this embodiment implements software-level fault latching, while effectively avoiding false alarms in sleep mode or active short-circuit conditions.

[0066] S4. Obtain the software fault flag and the hardware total fault signal output by the hardware latch circuit.

[0067] Furthermore, the software fault flags corresponding to the settings specifically include: setting independent software fault flag bits for hardware overcurrent faults, hardware overvoltage faults, and driver chip faults, and setting them respectively in the corresponding interrupt service functions.

[0068] Furthermore, the acquisition of the software fault flag and the total hardware fault signal is achieved by transmitting the software fault flag and the total hardware fault signal from the base software layer (BSW) to the application software layer (ASW) through the runtime environment (RTE) interface.

[0069] Specifically, through the write operation of the RTE interface, the fault flag bits (OVP_State, OCP_State, DRV_State) latched in step S3 and the hardware total fault pin level (FAULT) output by the hardware latching circuit are transmitted from the BSW layer to the RTE layer. The fault diagnosis module of the ASW layer obtains the above fault flag bits and hardware total fault level signals in real time through the read operation of the RTE interface, providing a data basis for subsequent fault diagnosis and processing.

[0070] S5. Based on the obtained software fault flags and hardware total fault signals, and considering whether the motor is currently under high voltage, perform fault diagnosis and corresponding protection and recovery operations.

[0071] Furthermore, the specific processing for performing fault diagnosis and corresponding protection and recovery operations includes:

[0072] When the motor is under high voltage, permanent shutdown protection is implemented until the system is powered off.

[0073] When the motor is not under high voltage, a temporary shutdown protection is executed, and the system is reset.

[0074] In this embodiment, the fault diagnosis module of the ASW layer reads OVP_State, OCP_State, DRV_State, and FAUL through the RTE interface. When the flag bit is 1 and the motor state is high voltage, it reports three levels of hardware overvoltage fault codes, hardware overcurrent fault codes, driver chip fault codes, and hardware total fault codes (as required). The software operation register shuts down the PWM and the MCU hardware shuts down urgently. At this time, the fault can only be recovered by power-down. When the fault state is 1 and the motor state is not high voltage, the fault code is not reported for the time being. The software operation register shuts down the PWM and the MCU hardware shuts down urgently. Then, the watchdog timer is used to perform a hard reset on the MCU PWR_REST pin (the software latch, hardware latch, and emergency shutdown register are all reset and cleared). After 5 consecutive resets (as required), if the fault state is still 1, the fault code is immediately reported and protection measures are executed. The fault can only be recovered by power-down. Through the above-mentioned graded protection and recovery mechanism, this embodiment realizes differentiated fault handling under different system states: under high voltage state, safety is given priority and non-automatic recovery latch protection is adopted; under non-high voltage state, automatic recovery is attempted first to improve the availability and robustness of the system.

[0075] Example 2:

[0076] Accordingly, this embodiment also provides a hardware fault control system based on a motor controller, used to implement the above-described hardware fault control method based on a motor controller, including:

[0077] The hardware latch circuit has a reset enable terminal, which is used to latch hardware fault signals and output a total hardware fault signal.

[0078] In this embodiment, the input terminal of the hardware latch circuit is connected to the hardware fault signal source, its reset enable terminal is connected to the first output pin of the microcontroller, and its output terminal is used to output the hardware total fault signal.

[0079] A microcontroller, connected to the hardware fault signal source and the hardware latch circuit, has its first output pin connected to the reset enable terminal of the hardware latch circuit, and its second input pin connected to the output terminal of the hardware latch circuit. The microcontroller is configured to perform the following operations: configure the hardware fault signal as an interrupt trigger input; after the system power-on initialization is completed, first reset the driver chip, and then enable the hardware latch circuit; monitor the hardware fault signal, and when the hardware fault pin trigger edge is interrupted and the current motor state meets the preset conditions, set the corresponding software fault flag; acquire the software fault flag and the hardware total fault signal; and, based on the acquired software fault flag and hardware total fault signal, and in conjunction with whether the motor is currently under high voltage power-on, perform fault diagnosis and corresponding protection and recovery operations.

[0080] In summary, the hardware fault control method and system based on the motor controller proposed in this embodiment have the following technical advantages compared with the prior art:

[0081] This invention uses a hardware latching circuit to monitor and latch hardware fault signals such as overcurrent, overvoltage, and driver chip failure. Once a valid fault is detected, the hardware latching circuit can directly trigger an emergency shutdown, improving the protection response speed. At the same time, the microcontroller captures the same fault signal via an interrupt and sets a software fault flag when preset conditions are met for subsequent fault diagnosis and status recording. In this way, the hardware circuit and software interrupt work in parallel, which not only ensures the real-time fault response but also avoids the risk caused by the failure of a single mechanism, significantly improving the safety and reliability of the system.

[0082] After the system is powered on and initialized, the present invention first resets the driver chip to clear any transient abnormal states that may have occurred during the initialization process, and then enables the hardware latch circuit to enter the fault detection state. This timing design avoids the hardware latch circuit from mistakenly capturing other fault signals and generating false fault latches when the driver chip is not stable, thus solving the problem in the prior art where the motor controller cannot start normally due to false alarms upon power-on.

[0083] This invention differentiates the recovery operation after a fault based on whether the motor is under high voltage: when the fault occurs during high-voltage operation, the system performs permanent shutdown protection until the entire vehicle is powered off, ensuring absolute safety under extreme conditions; when the fault occurs in a non-high-voltage state (such as pre-charging or standby), the system attempts to recover by resetting after performing shutdown protection, and switches to permanent protection only if the fault persists after a preset number of consecutive resets. In this way, safety during high-voltage operation is ensured, and permanent system failure due to a single fault in non-dangerous conditions is avoided, improving the system's fault tolerance and availability.

[0084] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit the technical solutions. Those skilled in the art should understand that any modifications or equivalent substitutions to the technical solutions of the present invention without departing from the spirit and scope of the present invention should be covered within the scope of the claims of the present invention.

Claims

1. A hardware fault control method based on a motor controller, characterized in that, Includes the following steps: S1. Configure the hardware fault signal as an interrupt trigger input for the microcontroller; S2. After the system is powered on and initialized, the driver chip is reset first, and then the hardware latch circuit is enabled so that the hardware latch circuit enters the fault detection state. The hardware latching circuit is used to latch hardware fault signals and output a total hardware fault signal. S3. Monitor the hardware fault signal. When the hardware fault pin triggers an edge interruption, determine whether the current motor state meets the preset conditions. If the conditions are met, set the corresponding software fault flag. S4. Obtain the software fault flag and the hardware total fault signal output by the hardware latch circuit. S5. Based on the obtained software fault flags and hardware total fault signals, and considering whether the motor is currently under high voltage, perform fault diagnosis and corresponding protection and recovery operations.

2. The hardware fault control method based on a motor controller according to claim 1, characterized in that, In step S1, the hardware fault signal configuration is executed in the control abstraction layer of the basic software layer, specifically including: Configure the PORT module, set the hardware fault pin as the input direction, and initialize the level and pull-up / pull-down mode; Configure the ICU module, assign an input capture unit to the hardware fault pin, and set the edge-triggered mode; Configure the IRQ module to allocate interrupt resources for hardware fault pins, including interrupt source, interrupt type and interrupt priority.

3. The hardware fault control method based on a motor controller according to claim 1, characterized in that, In step S2, the enabling hardware latch circuit includes: after the driver chip is successfully reset, delaying for a preset time, and then switching the hardware latch circuit from the reset state to the enabled state; the hardware latch circuit has a reset enable terminal FLTRST pin; the FLTRST pin is high level in the reset state and low level in the enabled state.

4. The hardware fault control method based on a motor controller according to claim 1, characterized in that, In step S3, the preset condition is that the motor is not in a sleep state and has not entered an active short circuit state.

5. The hardware fault control method based on a motor controller according to claim 1, characterized in that, In step S3, the software fault flags corresponding to the settings specifically include: setting independent software fault flag bits for hardware overcurrent faults, hardware overvoltage faults, and driver chip faults, and setting them in the corresponding interrupt service functions respectively.

6. The hardware fault control method based on a motor controller according to claim 1, characterized in that, In step S4, the acquisition of the software fault flag and the hardware total fault signal is achieved by transmitting the software fault flag and the hardware total fault signal from the basic software layer to the application software layer through the runtime environment interface.

7. The hardware fault control method based on a motor controller according to claim 1, characterized in that, In step S5, the specific processing of performing fault diagnosis and corresponding protection and recovery operations includes: When the motor is under high voltage, permanent shutdown protection is implemented until the system is powered off. When the motor is not under high voltage, a temporary shutdown protection is executed, and the system is reset.

8. The hardware fault control method based on a motor controller according to claim 7, characterized in that, The execution of temporary shutdown protection and triggering system reset specifically includes: if the fault disappears after the reset within a preset number of consecutive resets, the system resumes normal operation; if the fault still exists after the preset number of resets, permanent shutdown protection is executed until the system is powered down.

9. A hardware fault control system based on a motor controller, characterized in that, The hardware fault control method based on a motor controller according to any one of claims 1 to 8 includes: The hardware latch circuit has a reset enable terminal, which is used to latch hardware fault signals and output a total hardware fault signal. A microcontroller, connected to the hardware fault signal source and the hardware latch circuit, is used to execute the steps described in any one of claims 1 to 8.

Images