Scheduling optimization processor, instruction scheduling method, apparatus, medium and product

Abstract

This disclosure presents a scheduling optimization processor, instruction scheduling method, apparatus, medium, and product. The scheduling optimization processor includes multiple arithmetic pipelines and a physical register file. Each arithmetic pipeline is connected to at least two write-back caches. The number of instruction types with different execution latencies supported by the arithmetic pipeline is n. The write-back cache contains several cache partitions, with the number of cache partitions being n-1. According to the enqueue order of the cache partitions, the arithmetic pipeline writes the execution results of instructions into the idle write-back cache. In each clock cycle, the write-back cache writes the valid execution results from the last-level cache partition into the physical register file. This processor can achieve ordered buffering and parallel write-back of multiple instruction execution results by configuring multiple write-back caches for a single arithmetic pipeline and adopting a cache partition structure that matches the execution latency. This eliminates write conflicts in the physical register file at the hardware level, significantly improving processor issue efficiency and operating performance.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit design technology, and in particular to a scheduling optimization processor, instruction scheduling method, apparatus, medium and product. Background Technology

[0002] In processor architecture, after an instruction is processed by a functional unit within the arithmetic pipeline, the execution result needs to be written back to the physical register file through a write port. Due to hardware limitations, each arithmetic pipeline is usually equipped with only one physical register file write port. The results generated by different execution cycles and different functional units will compete for this write port, resulting in frequent write port resource conflicts.

[0003] Write port conflicts can directly prevent instruction results from being written back in a timely manner, which not only increases the overall execution latency of instructions, but also blocks the issuance and execution of subsequent dependent instructions, thereby reducing the throughput and overall operating efficiency of the processor pipeline. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a scheduling optimization processor, instruction scheduling method, apparatus, medium, and product that can achieve ordered buffering and parallel write-back of multiple instruction execution results by configuring multiple write-back caches for a single operation pipeline and adopting a cache partitioning structure that matches the execution latency. This eliminates write port conflicts of the physical register file at the hardware level and significantly improves processor launch efficiency and operating performance.

[0005] In a first aspect, embodiments of this disclosure provide a scheduling optimization processor, which includes multiple computation pipelines and a physical register file; Each computation pipeline is connected to at least two write-back caches. The number of different execution latency instruction types supported by the computation pipeline is n. The write-back cache contains several cache partitions, and the number of cache partitions is n-1. According to the enqueue order of the cache partitions, the operation pipeline writes the execution result of the instruction into the idle write-back cache; The write-back cache writes the valid execution results from the last-level cache partition to the physical register file in each clock cycle.

[0006] Optionally, the cache partition includes a write-valid field and a data field; When the write port of the physical register file is not occupied, the operation pipeline writes the execution result of the instruction to the physical register file and simultaneously writes it to the data field of the entry cache partition of an empty write-back cache, and the write valid field of the entry cache partition is set to invalid. When the write port of the physical register file is occupied, the operation pipeline writes the execution result of the instruction into the data field of the entry cache partition of an empty write-back cache, and sets the write valid field of the entry cache partition to valid. Each write-back cache writes the execution result with a valid write field in the last-level cache partition to the physical register file in each clock cycle. After the write is completed, the valid write field is set to invalid, and the execution result with an invalid write field in the last-level cache partition is removed.

[0007] Optionally, the scheduling optimization processor further includes a scheduling queue; The scheduling queue is used to broadcast key information of the instruction when the instruction is issued; When the physical register number of the source operand of an instruction waiting to be transmitted is detected to be the same as the destination physical register number included in the broadcast key information, the instruction waiting to be transmitted is determined to be the source instruction, and the instruction that has been transmitted is the target instruction that the source instruction depends on. The key information broadcast is then delayed and adjusted before being written into the data storage field preset by the source instruction; When the source instruction meets the issue conditions, the source instruction is issued to the corresponding computation pipeline for execution based on the data storage field of the source instruction.

[0008] Optionally, the data storage domain includes a state storage domain, a write-back cache identifier storage domain, and a computation pipeline identifier storage domain; The state storage field is used to store the execution state of each target instruction that the source instruction depends on in relation to the execution result; The write-back cache identifier storage field is used to store the write-back cache identifier to which the execution result belongs; The computation pipeline identifier storage field is used to store the computation pipeline identifier to which the execution result belongs.

[0009] Optionally, the execution state includes at least one of a waiting state and a ready state; The waiting state includes at least one of multiple waiting levels, and the number of configured waiting levels is equal to the maximum execution latency; The ready state includes at least one of the following: ready bypass state, write-back cache partition state, and physical register file state; The waiting state indicates that the execution result on which the source instruction depends has not yet been generated; The level of the ready bypass state is the minimum wait level minus 1, indicating that the execution result on which the source instruction depends is stored in the computation pipeline; The write-back cache partition status indicates the location of the cache partition on which the execution result of the source instruction depends is stored; The physical register file state indicates that the execution result on which the source instruction depends is stored in the physical register file state.

[0010] Optionally, the scheduling queue is further configured to create a data storage field in the scheduling queue for each source operand of the source instruction when the source instruction enters, wherein each source operand depends on the execution result of the corresponding target instruction; When the execution status of the key information broadcast is a waiting state, the level of the waiting state is decremented by 1 and then written into the status storage field of the source operand corresponding to the source instruction. When the execution state contained in the key information broadcast is ready, the ready state is written into the state storage field of the source operand corresponding to the source instruction; When the critical information broadcast contains a computation pipeline identifier, the computation pipeline identifier is written into the computation pipeline identifier storage field of the source operand corresponding to the source instruction; When the critical information broadcast includes a write-back cache identifier, the write-back cache identifier is written to the write-back cache identifier storage field of the source operand corresponding to the source instruction.

[0011] Optionally, the scheduling queue is further configured to determine that the source instruction meets the launch conditions when the execution status of each execution result on which the source instruction depends is in a ready state; Based on the ready state, the write-back cache identifier storage field, and the computation pipeline identifier storage field, the execution result on which the source instruction depends is read, and based on the read execution result, the source instruction is issued to the corresponding computation pipeline for execution.

[0012] Optionally, the scheduling queue is further configured to, when the ready state is a ready bypass state, read the execution result that the source instruction depends on from the computational pipeline that executes the target instruction based on the computational pipeline identifier stored in the computational pipeline identifier storage field; When the ready state is the write-back cache partition state, the execution result that the source instruction depends on is read based on the cache partition location indicated by the write-back cache partition state, the operation pipeline identifier stored in the operation pipeline identifier storage field, and the write-back cache identifier stored in the write-back cache identifier storage field. When the ready state is the physical register file state, the execution result that the source instruction depends on is read based on the physical register file number of the source operand.

[0013] Optionally, the output of the write-back buffer connected to each computation pipeline is connected to a different input port of a multiplexer; The number of input ports of the multiplexer is the same as the number of write-back buffers connected to the corresponding computation pipeline; The output of the multiplexer is connected to the write port of the physical register file.

[0014] Secondly, this disclosure also provides an instruction scheduling method, which adopts the following technical solution: Each computation pipeline is configured with at least two write-back caches, each write-back cache comprising a number of cache partitions of number n-1, where n is the number of different execution latency instruction types supported by the computation pipeline; According to the enqueue order of the cache partitions, the execution results of the instructions in the computation pipeline are written to the idle write-back cache; In each clock cycle, the valid execution results in the last-level cache partition of the write-back cache are written to the physical register file.

[0015] Optionally, the step of writing the valid execution result in the last-level cache partition of the write-back cache to the physical register file in each clock cycle includes: When the write port of the physical register file is not occupied, the execution result of the instruction on the operation pipeline is written to the physical register file, and at the same time written to the data field of the entry cache partition of an idle write-back cache, and the write valid field of the entry cache partition is set to invalid. When the write port of the physical register file is occupied, the execution result of the instruction on the arithmetic pipeline is written into the data field of the entry cache partition of an idle write-back cache, and the write valid field of the entry cache partition is set to valid. In each clock cycle, the execution results with valid write-valid fields in the last-level cache partition of each write-back cache are written to the physical register file. After the write is completed, the valid write fields are set to invalid, and the execution results with invalid write-valid fields in the last-level cache partition are removed.

[0016] Thirdly, this disclosure also provides a computer device, which adopts the following technical solution: The computer device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform any of the instruction scheduling methods described above.

[0017] Fourthly, embodiments of this disclosure also provide a computer-readable storage medium storing computer instructions for causing a computer to execute any of the instruction scheduling methods described above.

[0018] Fifthly, embodiments of this disclosure also provide a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of any of the methods described above.

[0019] The scheduling optimization processor provided in this embodiment connects at least two write-back caches to each arithmetic pipeline. When instructions with different execution latencies are executed on the same arithmetic pipeline, their execution results can be temporarily written to an idle write-back cache instead of directly competing for the physical register file write port. Each clock cycle, only the valid execution results of the last-level cache partition in the write-back cache are written back to the physical register file. By buffering and sorting the execution results through the write-back cache, the problem of instructions with different execution latencies in the same arithmetic pipeline competing for the physical register file write port due to different result generation times is avoided, thereby mitigating write port conflicts. Furthermore, once the physical register file write port is idle, only valid execution results from the last-level cache partition are allowed to be written back to the physical register file. This ensures that the execution results are kept in the write-back cache for a fixed number of clock cycles, matching the number of cache partitions. This allows instructions with different execution latencies within the same pipeline to be queued, time-aligned, and stably buffered in the write-back cache, avoiding frequent and disorderly contention for physical register file write ports due to different instruction completion times. This guarantees that write-back operations are performed in a fixed and regular timing sequence, thereby simplifying control logic, reducing the probability of write port conflicts, and improving the stability and reliability of pipeline operation. Moreover, setting the number of write-back cache partitions to n-1 ensures that the cache depth exactly covers the timing differences of all n-latency instructions, preventing write-back cache overflow.

[0020] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A schematic diagram of the structure of the scheduling optimization processor provided in the embodiments of this disclosure; Figure 2 A transition diagram of each execution state within the state storage domain provided in this embodiment of the disclosure; Figure 3A flowchart illustrating the instruction scheduling method provided in this embodiment of the disclosure; Figure 4 A flowchart illustrating the method for writing execution results provided in this embodiment of the disclosure; Figure 5 A flowchart illustrating the source command issuance method provided in this embodiment of the disclosure; Figure 6 A flowchart illustrating the method for writing key broadcast information provided in this embodiment of the disclosure; Figure 7 A schematic flowchart illustrating a source command transmission method provided in an embodiment of this disclosure when transmission conditions are met; Figure 8 A flowchart illustrating the method for reading execution results dependent on source instructions provided in this embodiment of the disclosure; Figure 9 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present disclosure. Detailed Implementation

[0023] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0024] It should be understood that the following specific examples illustrate the implementation of this disclosure, and those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0025] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0026] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. The drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0027] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0028] Explanation of core vocabulary: The arithmetic pipeline is a hardware unit that executes instruction operations, including the arithmetic logic unit (ALU), address generation unit (AGU), floating-point unit (FPU), floating-point addition (FADD), floating-point division (FDIV), floating-point shift (FSHIFT), etc., used to complete instruction operations.

[0029] Physical Register File (PRF): A hardware storage array used to temporarily store the results of instruction execution for subsequent instructions to read. It includes fixed-point physical register files and floating-point physical register files. Fixed-point physical register files are used to store the execution results of fixed-point instructions (arithmetic logic, address calculation, etc.), while floating-point physical register files are used to store the operation results of floating-point instructions (decimal arithmetic, FADD, FDIV, FPU, etc.).

[0030] Scheduler Queue: Used to cache decoded instructions that have not yet met the conditions for issuance, and to issue the instruction to the corresponding computation pipeline for execution once the source operands of the instruction are ready.

[0031] Instruction execution flow: The instruction is fetched by the instruction fetch unit, decoded, dispatched and renamed in the registers and then enters the scheduling queue. After the instruction source operands are ready, the scheduling queue issues the instruction to the corresponding arithmetic pipeline for execution. The execution result is written to the physical register file and finally the instruction is submitted by the commit unit.

[0032] Reference Figure 1This disclosure provides a scheduling optimization processor, which includes multiple arithmetic pipelines and a physical register file. Each arithmetic pipeline is connected to at least two write-back caches (FIFOs). The number of different execution latency instruction types supported by the arithmetic pipeline is n. The write-back cache contains several cache partitions (sets), and the number of cache partitions is n-1. According to the enqueue order of the cache partitions, the arithmetic pipeline writes the execution results of the instructions into the idle write-back cache. For example, if there are 4 sets, the execution results need to enter from set3 at the entry point. As new execution results enter, old execution results are moved from set3 to set2, and so on, until the last set0. In each clock cycle, the valid execution results in the last cache partition of the write-back cache are written into the physical register file.

[0033] The number of instruction types with different execution latencies refers to the number of instruction types with different execution cycles in the same computing pipeline. A computing pipeline can support the execution of multiple instructions. Instructions with different functions require different numbers of clock cycles to complete their operations. Instructions with the same execution latency are grouped into one category. The total number of such different latency categories contained in the computing pipeline is the number of instruction types with different execution latencies.

[0034] In this scheme, since each arithmetic pipeline is connected to at least two write-back buffers, when instructions with different execution latencies are executed on the same arithmetic pipeline, their execution results can be temporarily written to an idle write-back buffer instead of directly competing for the physical register file write port. The write-back buffer only writes the valid execution results of the last-level buffer partition back to the physical register file in each clock cycle. By buffering and sorting the execution results through the write-back buffer, the problem of instructions with different execution latencies in the same arithmetic pipeline competing for the physical register file write port due to different result generation times is avoided, thereby mitigating write port conflicts. Furthermore, once the physical register file write port is idle, only the valid execution results of the last-level cache partition are allowed to be written back to the physical register file. This ensures that the execution results are kept in the write-back cache for a fixed number of clock cycles, consistent with the number of cache partitions. This allows the results of instructions with different execution latencies within the same pipeline to be queued, time-aligned, and buffered stably in the write-back cache. This avoids frequent and disorderly contention for the physical register file write port due to different instruction completion times, ensuring that the write-back operation is performed in a fixed and regular timing sequence. This simplifies the control logic, reduces the probability of write port conflicts, and improves the stability and reliability of the pipeline operation.

[0035] In practice, the more write-back buffers each computation pipeline has, the more write-back conflicts to physical register bus (PBUB) are reduced, resulting in better performance. However, taking n=5 as an example, once the number of write-back buffers per pipeline exceeds four, adding more buffers becomes ineffective because the scheduling queue no longer needs to consider PBUB conflicts and can issue instructions in any order. Furthermore, it's important to note that more write-back buffers require more space and increase costs; therefore, the choice must be based on specific needs. Thus, when n=5, two write-back buffers per pipeline are sufficient.

[0036] In traditional processor architectures, the write-back cache and the physical register file are two independent modules. If the number of entries in the write-back cache (the number of ports through which functional units write to the write-back cache) is greater than the number of exits (the number of ports through which the write-back cache writes back to the physical register file), the speed at which instruction execution results are written to the cache will be faster than the speed at which they are written back to the physical register file, which can easily lead to cache overflow. Even if the number of entries and exits in the write-back cache are equal, because the same arithmetic pipeline supports multiple instructions with different execution latencies, the timing of their results is random and uneven, and cache overflow may still occur due to the concentrated arrival of execution results.

[0037] When an arithmetic pipeline supports n different instruction execution delay cycles, the maximum latency difference between instructions is n−1. Taking a pipeline supporting 5 different execution delay instructions as an example, when different delay instructions are issued consecutively, severe bus conflicts will occur when writing back to the physical register file due to the different completion times of the results. To accommodate this maximum timing difference and avoid conflicts, the write-back cache must have sufficient depth for buffering and alignment. Based on the aforementioned requirements, this solution sets the number of cache partitions in the write-back cache to n−1. This configuration ensures that the cache depth exactly covers the timing differences of all n delay instructions. When the arithmetic pipeline supports up to 5 different instruction execution delay cycles, consecutive issuance of instructions with delays of 5, 4, 3, 2, and 1 cycle will cause write-back bus conflicts, thus requiring at least 4 cache partitions for timing buffering.

[0038] Taking the configuration of 2, 3, and 4 write-back buffers per pipeline as examples, even with an additional physical register file write port, different instructions will still compete for space during write-back to the physical register file, even with only one physical register file write port. Regardless of whether 2, 3, or 4 write-back buffers are used, the instruction execution result needs to be shifted level by level in the write-back buffer and remain for a fixed period. The longest-latency instruction requires 4 shift cycles to reach the final partition and be written to the physical register file. Especially in extreme cases, consecutively issued instructions with different latency will simultaneously occupy the write-back buffer bus and be written back in a concentrated manner, further requiring sufficient buffer depth. Therefore, regardless of the write-back buffer configuration, the required number of buffer partitions is determined by the number of instruction execution latency types, requiring a minimum of 4 buffer partitions, i.e., the number of buffer partitions is the number of execution latency instruction types n−1.

[0039] Compared to traditional solutions that distribute instructions with different execution cycles across different pipelines and allocate independent physical register file write ports to each pipeline, this solution allows a single arithmetic pipeline to support multiple instructions with different execution latencies. Through write-back buffering and multi-level cache partitioning, execution results are time-aligned and buffered, ensuring that the execution results of instructions with different latencies are ultimately written back in an orderly manner through the same physical register file write port. Therefore, there is no need to allocate a separate write port for each type of instruction with different execution latencies, significantly reducing the number of physical register file write ports required by the processor, thus lowering hardware overhead and design complexity.

[0040] Optionally, the output of the write-back buffer connected to each computation pipeline is connected to a different input port of a multiplexer (MUX). The number of input ports of the multiplexer is the same as the number of write-back buffers connected to the corresponding computation pipeline. The output of the multiplexer is connected to the write port of the physical register file. By configuring the multiplexer, the ordered selection and output of multiple execution results can be achieved, avoiding bus conflicts caused by simultaneous write-back of multiple buffers and simplifying the control logic of the physical register file write port.

[0041] Optionally, each cache partition entry contains two fields: a write valid field (valid_wr) and a data field (data). The data field stores the execution result of the instruction, while the write valid field stores valid and invalid values. A valid value is true, and an invalid value is false. These two values ​​are used to indicate whether the execution result stored in the data field has been written back to the physical register file, thus avoiding duplicate write-back.

[0042] When the write port of the physical register file is not occupied, the execution pipeline writes the instruction execution result to the physical register file and simultaneously writes it to the data field of the entry cache partition of an empty write-back cache, while setting the write-valid field of the entry cache partition to invalid. This method ensures that the instruction result can be written to the physical register file in real time for subsequent instructions to access, and also backs up the result and periodically places it in the write-back cache, ensuring timing alignment of instructions with different delays and uniform cache state, avoiding data loss and timing disorder caused by temporary write port occupancy, and providing a stable data source for subsequent cache shifts.

[0043] When the write port of the physical register file is occupied, the execution result of the instruction is written to the data field of the entry cache partition of a free write-back cache, and the write-valid field of the entry cache partition is set to valid. This method can temporarily store and mark the execution result, avoid data loss due to write port conflicts, and ensure that subsequent write-backs are performed in a unified and timely manner.

[0044] Each write-back cache, in each clock cycle, writes the execution results with valid write-valid fields in the last-level cache partition to the physical register file. After the write is complete, the write-valid fields are invalidated, and the execution results with invalid write-valid fields in the last-level cache partition are removed. This operation ensures that only truly valid results that need to be written back are written to the physical register file each clock cycle, while promptly cleaning up invalid data and releasing cache resources, avoiding duplicate write-backs and cache accumulation.

[0045] When the execution result of the computation pipeline needs to be written to the write-back cache, regardless of how many write-back caches are configured for the computation pipeline, the principle of writing to the cache whose entry is empty is always maintained. If all entries are empty, the result is written to one of them. Moreover, for the same computation pipeline, the write-back caches connected to it can be set with priority or specified. When two or more write-back caches are all idle, the execution result is determined to be written to the higher priority or specified write-back cache first. For example, at time t0, an instruction with an execution cycle of 2 is issued to the arithmetic pipeline Pipe0. At this time, both write-back buffers of Pipe0, fifo0 and fifo1, are idle, so fifo0 is allocated to it. At time t1, an instruction with an execution cycle of 1 is issued to the same arithmetic pipeline Pipe0. Since fifo0 is already occupied, it is allocated to the idle fifo1. The two instructions are executed and completed at time t2, and at time t3, the results are written back to the physical register file through their respective fifo0 and fifo1. By alternately writing back through multiple fifo entries in the same pipeline, write port conflicts of the physical register file are avoided.

[0046] Optionally, when the number of write-back cache partitions decreases, in order to avoid overflow, an overflow prediction algorithm needs to be added when the scheduling queue issues instructions. This algorithm uses the number of cache partitions as the prediction period and uses the instruction history issuance information to predict whether data will be continuously written to a certain write-back cache within this period. If it is determined that the remaining space is insufficient, new data is prohibited from being written to that write-back cache and instead allocated to other idle write-back caches, thereby avoiding overflow.

[0047] Optionally, the data stored in the write-back cache remains in its original physical location. Data reading and writing are achieved only by moving the write pointer (indicating the next write position) and the read pointer (indicating the next read position). This method allows the data stored in the write-back cache to be moved without shifting. Read and write operations can be completed simply by updating the read and write pointers, thereby improving the timing performance of the processor when it is running at high frequencies.

[0048] During instruction execution, because the source operands of some instructions depend on the execution results of other instructions, subsequent instructions need to know whether to read the dependent execution results from the physical register file or the write-back cache. When there is an execution result dependency between instructions, the instruction whose execution result is depended upon is designated as the target instruction, and the instruction that depends on the execution result of the target instruction is designated as the source instruction. For example, if instruction B depends on the execution result of instruction A, then instruction B is the source instruction, and instruction A is the target instruction. The source operand refers to the input data that needs to be read during instruction execution or the register storing that input data; its value depends on the execution result of other target instructions.

[0049] In the traditional scheme that uses the Least Recently Used (LRU) algorithm to select physical register file and write-back cache entries for write-back, multiple clock cycles are required to determine whether the instruction source operand is still resident in the write-back cache in order to determine whether to read the source data from the physical register file. This significantly increases the data read latency after the instruction is scheduled to be issued and introduces a larger pipeline refresh overhead.

[0050] Optionally, to address the problem that the storage location of the execution result dependent on the source instruction is difficult to determine in a short time, the scheduling optimization processor of this scheme also includes a scheduling queue. The scheduling queue is used to create a data storage field for each source operand of the source instruction when the source instruction enters. Each source operand depends on the execution result of the corresponding target instruction. This data storage field is used to store the storage information of the execution result dependent on each source operand in the future.

[0051] The scheduling queue is also used to broadcast critical information about instructions during instruction issuance. The broadcast scope is limited to within the scheduling queue. The broadcast critical information includes the destination physical register number (the number of the physical register whose execution result needs to be written back) and the storage information of the execution result. The source operand physical register number refers to the number of the physical register whose execution result needs to be written back, depending on the source operand. Therefore, when the scheduling queue detects that the source operand physical register number of an instruction waiting to be issued is the same as the destination physical register number included in the broadcast critical information, it determines that there is a dependency between the two instructions. The instruction waiting to be issued is the source instruction, and the issued instruction is the target instruction that the source instruction depends on. When the scheduling queue detects that the source operand physical register number of an instruction waiting to be issued is different from the destination physical register number included in the broadcast critical information, it ignores the broadcast critical information.

[0052] After adjusting the delay, the key information broadcast is written into the preset data storage field of the source instruction. As time progresses, the storage information of all execution results that the source instruction depends on is written into the data storage field. When the source instruction meets the emission conditions, it can be emitted to the corresponding computation pipeline for execution based on the source instruction's data storage field. Through this broadcasting method, the data dependencies between the instruction to be emitted and the already emitted instructions can be clearly defined. Based on the storage information carried in the broadcast, the execution results that subsequent instructions depend on can be obtained to complete the source operand preparation. Then, the instruction is emitted to the corresponding computation pipeline for execution, and finally, the execution result of the instruction is obtained.

[0053] The storage information for the execution result includes at least one of the following: execution status, write-back cache identifier, and computation pipeline identifier. The execution status indicates the lifecycle stage of the execution result, including a waiting period before the result is generated, a stage where the result is in the write-back cache, and a stage where the result has been written back to the physical register file. The write-back cache identifier indicates whether the execution result is stored in the write-back cache and identifies the write-back cache to which it is stored. The computation pipeline identifier distinguishes the computation pipeline to which the execution result belongs. To accommodate the above storage information, the data storage field for each source operand is set as a union storage structure, such that the data storage field includes a status storage field, a write-back cache identifier storage field, and a computation pipeline identifier storage field. Specifically, the status storage field stores the execution status of each target instruction that the source instruction depends on for the execution result; the write-back cache identifier storage field stores the write-back cache identifier to which the execution result belongs, thus locating the write-back cache where the execution result is located; and the computation pipeline identifier storage field stores the computation pipeline identifier to which the execution result belongs, thus distinguishing the computation pipeline from which the execution result originates. Referring to the following table of new domains required for the scheduled issue queue, which illustrates which memory domains should be created each time a new source operand of an instruction is added, the table of new domains required for the scheduled issue queue is as follows: New domain tables needed for scheduling launch queues In the table, entry0…entryN represents instructions, src0, src1… represent source operands, srcFrom represents the state storage field (consisting of 4 bits), pipeldx represents the operation pipeline identifier storage field, and fifoldx (1 bit) represents the write-back cache identifier storage field.

[0054] The scheduling queue is also used to determine that the source instruction meets the emission conditions when the execution status of each execution result that the source instruction depends on is in the ready state. At this time, it can determine the location of each execution result that the source instruction depends on based on the ready state, the write-back cache identifier storage field and the operation pipeline identifier storage field. Then, according to the determined location, the execution result that the source instruction depends on is read, and based on the read execution result, the source instruction is emitted to the corresponding operation pipeline for execution.

[0055] The execution state includes at least one of a waiting state and a ready state. The waiting state includes at least one of multiple waiting levels, and the number of waiting levels is equal to the maximum execution latency. This design ensures that the waiting levels are precisely matched with the actual execution cycle of the instruction, guaranteeing that each instruction remains in a waiting state until the execution result is truly ready, avoiding data errors caused by premature issuance. Furthermore, by unifying the waiting levels, the ready time of the result can be predicted without complex detection, simplifying control logic and reducing hardware overhead. For example, if the maximum execution latency of a certain computational pipeline is 5 clock cycles, then the number of waiting levels is set to 5, corresponding to 5cycWait to 1cycWait, with each level decreasing by one for each clock cycle the instruction advances.

[0056] The ready state includes at least one of the following: ready bypass state, write-back cache partition state, and physical register file state. The ready bypass state has a level equal to the minimum wait level minus 1, and indicates that the execution result of the source instruction is stored in the computation pipeline (belonging to the bypass). When the minimum wait level is 1, this ready bypass state can be represented by 0cycbypass, which distinguishes it from the wait state while still reflecting its level of 0, indicating that the execution result has been generated and is ready. When the execution result is not stored in the computation pipeline, this ready bypass state does not exist or is displayed as invalid. The write-back cache partition state indicates that the execution result of the source instruction is stored in the write-back cache partition location. When the execution result is not stored in the write-back cache, this write-back cache partition state is not displayed or is displayed as invalid. The physical register file state indicates that the execution result of the source instruction is stored in the physical register file state. When the execution result is not stored in the physical register file, this physical register file state is not displayed or is displayed as invalid.

[0057] Reference Figure 2 The diagram shows the transitions between execution states within the state storage domain. The state machine starts from the idle state. After an instruction is issued, depending on the maximum latency of its corresponding pipeline, the idle state can transition to any of the waiting states from 1cycWait to 5cycWait (e.g., if the latency is 5, it transitions to 5cycWait). Subsequently, the waiting states decrease sequentially according to the clock cycle (5cycWait → 4cycWait → … → 1cycWait), eventually entering 0cycBypass (ready bypass state, indicating that the result has been generated and can be read from the pipeline bypass). Then, the execution result is sequentially written to the FIFO (write-back buffer) queues set0~3, and finally written back to the PRF (Physical Register File). When a new instruction is allocated to the PRF (i.e., the old result will be overwritten), the PRF state is transitioned back to idle through the issued signal, completing one lifecycle cycle. In this diagram, the self-loop connection of the PRF indicates that the execution result can be executed multiple times and the result can be read multiple times without exiting the register file state. The PRF will only jump back to the idle state when a new instruction is allocated and overwrites the physical register.

[0058] The scheduling queue is also used to decrement the waiting state level by 1 and write it into the state storage field of the source operand corresponding to the source instruction (which is the source operand consistent with the physical register number of the broadcast destination) when the execution state of the critical information broadcast contains a waiting state. This decrementing operation is to align the total delay on the transmitting side with the current remaining waiting period on the receiving side. For example, when the scheduling queue transmits an instruction in the current period and broadcasts Latency=3, this 3-period is the actual remaining waiting period calculated from the next period. The instruction listening to the broadcast has already received the information in the current period. From its perspective, the actual waiting period is reduced by 1 period. Therefore, the state storage field needs to store 2cycWait.

[0059] The scheduling queue is also used to write the ready state into the state storage field of the source operand corresponding to the source instruction when the execution state contained in the broadcast key information is ready. The ready state indicates that the execution result is available and belongs to the completion state that does not require cycle counting. Therefore, there is no need to adopt the processing method of waiting for the state level to decrement by 1. Moreover, the change of the position of the execution result in the write-back path is automatically identified by the hardware read circuit.

[0060] The scheduling queue is also used to write the computation pipeline identifier to the computation pipeline identifier storage field of the source operand corresponding to the source instruction when the critical information broadcast contains the computation pipeline identifier, and to write the write-back cache identifier to the write-back cache identifier storage field of the source operand corresponding to the source instruction when the critical information broadcast contains the write-back cache identifier.

[0061] The scheduling queue is also used to read the execution results of each dependency when the source instruction meets the issue conditions. Specifically, when the ready state is the ready bypass state, the execution results dependent on the source instruction are read from the execution pipeline of the target instruction based on the pipeline identifier stored in the pipeline identifier storage field. When the ready state is the write-back cache partition state, the write-back cache partition state, the pipeline identifier, and the write-back cache identifier jointly and uniquely determine the physical location of the execution result. Therefore, the execution results dependent on the source instruction are read based on the cache partition location indicated by the write-back cache partition state, the pipeline identifier stored in the pipeline identifier storage field, and the write-back cache identifier stored in the write-back cache identifier storage field. When the ready state is the physical register file state, only the physical register file number of the source operand is needed to determine the physical location of the execution result. Therefore, the execution results dependent on the source instruction are read based on the physical register file number of the source operand.

[0062] This solution significantly improves processor execution efficiency by employing a write-back cache design with n-1 cache partitions, combined with dispatch queue issuance control. This is because when the dispatch queue issues instructions, it only needs to determine whether there are idle write-back buses and idle write-back cache entries, without needing to handle write-back cache overflow issues. The control logic is simple, effectively reducing the hardware complexity of the dispatch queue. Compared to directly increasing the number of pipelines or binding specific cycle instructions to specific pipelines, this solution can read the execution results dependent on a subset of source operands from the write-back cache without accessing the physical register file. This reduces the requirement for the number of register file read ports, saving hardware area that can be used to increase the number of physical register file entries, further improving processor performance. Furthermore, it further reduces the probability of write port conflicts, improving the dispatch queue issuance efficiency.

[0063] Reference Figure 3 This disclosure provides an instruction scheduling method applied to a scheduling-optimized processor, which includes multiple arithmetic pipelines and a physical register file. The instruction scheduling method includes the following steps: S1: Configure at least 2 write-back caches for each computation pipeline. The write-back caches consist of n-1 cache partitions, where n is the number of different execution latency instruction types supported by the computation pipeline. S2: Write the execution results of instructions on the computation pipeline into the free write-back cache according to the enqueue order of the cache partitions; S3: In each clock cycle, write the valid execution results in the last-level cache partition in the cache back to the physical register file.

[0064] Optionally, the cache partition includes a write-valid field and a data field, under which reference... Figure 4The flowchart illustrating the execution result writing method shows that, in each clock cycle, valid execution results from the last-level cache partition in the cache are written back to the physical register file, including: S31: When the write port of the physical register file is not occupied, write the execution result of the instruction on the arithmetic pipeline to the physical register file, and at the same time write it to the data field of the entry cache partition of an empty write-back cache, and set the write valid field of the entry cache partition to invalid. S32: When the physical register file write port is occupied, write the execution result of the instruction on the arithmetic pipeline into the data field of the entry cache partition of a free write-back cache, and set the write valid field of the entry cache partition to valid. S33: In each clock cycle, write the execution results with valid write fields in the last-level cache partition of each write-back cache to the physical register file. After the write is completed, the write valid fields are set to invalid, and the execution results with invalid write valid fields in the last-level cache partition are removed.

[0065] Optionally, the scheduling optimization processor also includes a scheduling queue, under which reference is made. Figure 5 The flowchart illustrating the source command issuance method is shown. The command scheduling method also includes: S4: When the scheduling queue issues a command, it broadcasts the key information of the command. S5: When the physical register number of the source operand of an instruction waiting to be transmitted in the scheduling queue is the same as the destination physical register number included in the broadcast key information, the instruction waiting to be transmitted is determined to be the source instruction, and the transmitted instruction is determined to be the target instruction that the source instruction depends on. S6: After adjusting the delay, the key information of the broadcast is written into the data storage field preset by the source instruction; S7: When the source instruction meets the issue conditions, the source instruction is issued to the corresponding arithmetic pipeline for execution based on the data storage field of the source instruction.

[0066] Optionally, the data storage domain includes a state storage domain, a write-back cache identifier storage domain, and a computation pipeline identifier storage domain; The state storage field is used to store the execution state of each target instruction that the source instruction depends on in relation to the execution result; The write-back cache identifier storage field is used to store the write-back cache identifier to which the execution result belongs; The pipeline identifier storage field is used to store the pipeline identifier to which the execution result belongs.

[0067] Optionally, the execution state includes at least one of a waiting state and a ready state; The waiting state includes at least one of multiple waiting levels, and the number of waiting levels configured is equal to the maximum execution latency; The ready state includes at least one of the following: ready bypass state, write-back cache partition state, and physical register file state; Among them, the waiting status indicates that the execution result of the source instruction has not yet been generated; The ready bypass state level is the minimum wait level minus 1, indicating that the execution results of the source instruction are stored in the computation pipeline; The write-back cache partition status indicates the location of the cache partition where the execution results of the source instructions depend are stored; The physical register file state indicates that the execution results that the source instruction depends on are stored in the physical register file state.

[0068] Optionally, refer to Figure 6 The flowchart illustrating the method for writing critical broadcast information shows that the critical broadcast information is written to the data storage field preset by the source command after a delay adjustment, including the following steps: S61: When a source instruction enters the scheduling queue, a data storage field is created in the scheduling queue for each source operand of the source instruction, and each source operand depends on the execution result of the corresponding target instruction. S62: When the critical information broadcast contains an execution state of waiting, decrement the level of the waiting state by 1 and write it into the state storage field of the source operand corresponding to the source instruction. S63: When the execution status contained in the broadcast key information is ready, write the ready status into the status storage field of the source operand corresponding to the source instruction; S64: When the critical information broadcast contains the operation pipeline identifier, write the operation pipeline identifier to the operation pipeline identifier storage field of the source operand corresponding to the source instruction; S65: When the critical information broadcast contains a write-back cache identifier, write the write-back cache identifier to the write-back cache identifier storage field of the source operand corresponding to the source instruction.

[0069] Optionally, refer to Figure 7 The flowchart illustrates the source instruction issuance method when the issuance conditions are met. When the source instruction meets the issuance conditions, based on the source instruction's data storage field, the source instruction is issued to the corresponding computation pipeline for execution, including the following steps: S71: When the execution status of each execution result that the source instruction depends on is in the ready state, it is determined that the source instruction meets the issue condition; S72: Based on the ready state, write-back cache identifier storage field, and arithmetic pipeline identifier storage field, read the execution result that the source instruction depends on, and based on the read execution result, issue the source instruction to the corresponding arithmetic pipeline for execution.

[0070] Optionally, refer to Figure 8The flowchart illustrating the method for reading the execution result dependent on the source instruction demonstrates how, based on the ready state, the write-back cache identifier storage field, and the computation pipeline identifier storage field, the method reads the execution result dependent on the source instruction, including the following steps: S721: When the ready state is the ready bypass state, the execution result dependent on the source instruction is read from the execution pipeline of the target instruction based on the execution pipeline identifier stored in the execution pipeline identifier storage field. S722: When the ready state is write-back cache partition state, based on the cache partition location indicated by the write-back cache partition state, the operation pipeline identifier stored in the operation pipeline identifier storage field, and the write-back cache identifier stored in the write-back cache identifier storage field, read the execution result that the source instruction depends on. S723: When the ready state is the physical register file state, read the execution result that the source instruction depends on based on the physical register file number of the source operand.

[0071] Optionally, the execution results of each computation pipeline connected to the write-back buffer can be written to the physical register file using a multiplexer.

[0072] The various variations and specific examples of the scheduling optimization processor provided above are also applicable to the instruction scheduling method provided in this disclosure. Through the foregoing detailed description of the scheduling optimization processor, those skilled in the art can clearly understand the implementation method of the instruction scheduling method. For the sake of brevity, they will not be described in detail here.

[0073] A computer device according to embodiments of the present disclosure includes a memory and a processor. The memory is used to store non-transitory computer-readable instructions. Specifically, the memory may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may, for example, include random access memory (RAM) and / or cache memory. The non-volatile memory may, for example, include read-only memory (ROM), hard disk, flash memory, etc.

[0074] The processor may be a central processing unit (CPU) or other processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the computer device to perform desired functions. In one embodiment of this disclosure, the processor is used to execute computer-readable instructions stored in the memory, causing the computer device to perform all or part of the steps of the instruction scheduling methods described in the foregoing embodiments of this disclosure.

[0075] Those skilled in the art will understand that, in order to solve the technical problem of how to achieve a good user experience, this embodiment may also include well-known structures such as communication buses and interfaces, and these well-known structures should also be included within the protection scope of this disclosure.

[0076] like Figure 9 This is a schematic diagram of a computer device provided for an embodiment of the present disclosure. It illustrates a structural schematic diagram suitable for implementing the computer device in the embodiments of the present disclosure. Figure 9 The computer device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0077] like Figure 9 As shown, a computer device may include a processor (such as a central processing unit, graphics processing unit, etc.), which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) or programs loaded from storage devices into random access memory (RAM). The RAM also stores various programs and data required for the operation of the computer device. The processor, ROM, and RAM are interconnected via a bus. Input / output (I / O) interfaces are also connected to the bus.

[0078] Typically, the following devices can be connected to the I / O interface: input devices, such as sensors or visual information acquisition devices; output devices, such as displays; storage devices, such as magnetic tapes or hard drives; and communication devices. Communication devices allow the computer device to communicate wirelessly or wiredly with other devices (such as edge computing devices) to exchange data. Although Figure 9 A computer apparatus with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown. More or fewer devices may be implemented or included alternatively.

[0079] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device, or installed from a ROM. When the computer program is executed by a processor, all or part of the steps of the instruction scheduling method of embodiments of this disclosure are performed.

[0080] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0081] A computer-readable storage medium according to embodiments of the present disclosure stores non-transitory computer-readable instructions. When the non-transitory computer-readable instructions are executed by a processor, all or part of the steps of the instruction scheduling methods described in the foregoing embodiments of the present disclosure are performed.

[0082] The aforementioned computer-readable storage media include, but are not limited to: optical storage media (e.g., CD-ROM and DVD), magneto-optical storage media (e.g., MO), magnetic storage media (e.g., magnetic tape or portable hard drive), media with built-in rewritable non-volatile memory (e.g., memory card), and media with built-in ROM (e.g., ROM cartridge).

[0083] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0084] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0085] In this disclosure, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The block diagrams of devices, apparatuses, devices, and systems involved in this disclosure are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as "comprising," "including," "having," etc., are open-ended terms meaning "including but not limited to," and are used interchangeably with them. The terms "or" and "and" as used herein refer to the terms "and / or," and are used interchangeably with them unless the context clearly indicates otherwise. The term "such as" as used herein refers to the phrase "such as but not limited to," and is used interchangeably with it.

[0086] Additionally, as used herein, the "or" used in a list of items beginning with "at least one" indicates a separate list, such that a list of, for example, "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not imply that the described example is preferred or better than other examples.

[0087] It should also be noted that in the systems and methods of this disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions to this disclosure.

[0088] Various changes, substitutions, and modifications can be made to the technology described herein without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of this disclosure is not limited to the specific aspects of the processes, machines, manufactures, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufactures, events, means, methods, or actions that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein can be utilized. Therefore, the appended claims include such processes, machines, manufactures, events, means, methods, or actions within their scope.

[0089] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0090] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A scheduling optimization processor, characterized in that, The scheduling optimization processor includes multiple computation pipelines and a physical register file; Each computation pipeline is connected to at least two write-back caches. The number of different execution latency instruction types supported by the computation pipeline is n. The write-back cache contains several cache partitions, and the number of cache partitions is n-1. According to the enqueue order of the cache partitions, the operation pipeline writes the execution result of the instruction into the idle write-back cache; The write-back cache writes the valid execution results from the last-level cache partition to the physical register file in each clock cycle.

2. The scheduling optimization processor according to claim 1, characterized in that, The cache partition includes a write-valid field and a data field; When the write port of the physical register file is not occupied, the operation pipeline writes the execution result of the instruction to the physical register file and simultaneously writes it to the data field of the entry cache partition of an empty write-back cache, and the write valid field of the entry cache partition is set to invalid. When the write port of the physical register file is occupied, the operation pipeline writes the execution result of the instruction into the data field of the entry cache partition of an empty write-back cache, and sets the write valid field of the entry cache partition to valid. Each write-back cache writes the execution result with a valid write field in the last-level cache partition to the physical register file in each clock cycle. After the write is completed, the valid write field is set to invalid, and the execution result with an invalid write field in the last-level cache partition is removed.

3. The scheduling optimization processor according to claim 1, characterized in that, The scheduling optimization processor also includes a scheduling queue; The scheduling queue is used to broadcast key information of the instruction when the instruction is issued; When the physical register number of the source operand of an instruction waiting to be transmitted is detected to be the same as the destination physical register number included in the broadcast key information, the instruction waiting to be transmitted is determined to be the source instruction, and the instruction that has been transmitted is the target instruction that the source instruction depends on. The key information broadcast is then delayed and adjusted before being written into the data storage field preset by the source instruction; When the source instruction meets the issue conditions, the source instruction is issued to the corresponding computation pipeline for execution based on the data storage field of the source instruction.

4. The scheduling optimization processor according to claim 3, characterized in that, The data storage domain includes a state storage domain, a write-back cache identifier storage domain, and a computation pipeline identifier storage domain; The state storage field is used to store the execution state of each target instruction that the source instruction depends on in relation to the execution result; The write-back cache identifier storage field is used to store the write-back cache identifier to which the execution result belongs; The computation pipeline identifier storage field is used to store the computation pipeline identifier to which the execution result belongs.

5. The scheduling optimization processor according to claim 4, characterized in that, The execution state includes at least one of a waiting state and a ready state; The waiting state includes at least one of multiple waiting levels, and the number of configured waiting levels is equal to the maximum execution latency; The ready state includes at least one of the following: ready bypass state, write-back cache partition state, and physical register file state; The waiting state indicates that the execution result on which the source instruction depends has not yet been generated; The level of the ready bypass state is the minimum wait level minus 1, indicating that the execution result on which the source instruction depends is stored in the computation pipeline; The write-back cache partition status indicates the location of the cache partition on which the execution result of the source instruction depends is stored; The physical register file state indicates that the execution result on which the source instruction depends is stored in the physical register file state.

6. The scheduling optimization processor according to claim 5, characterized in that, The scheduling queue is also used to create a data storage field for each source operand of the source instruction when the source instruction enters, and each source operand depends on the execution result of the corresponding target instruction; When the execution status of the key information broadcast is a waiting state, the level of the waiting state is decremented by 1 and then written into the status storage field of the source operand corresponding to the source instruction. When the execution state contained in the key information broadcast is ready, the ready state is written into the state storage field of the source operand corresponding to the source instruction; When the critical information broadcast contains a computation pipeline identifier, the computation pipeline identifier is written into the computation pipeline identifier storage field of the source operand corresponding to the source instruction; When the critical information broadcast includes a write-back cache identifier, the write-back cache identifier is written to the write-back cache identifier storage field of the source operand corresponding to the source instruction.

7. The scheduling optimization processor according to claim 6, characterized in that, The scheduling queue is also used to determine that the source instruction meets the launch conditions when the execution status of each execution result on which the source instruction depends is in a ready state. Based on the ready state, the write-back cache identifier storage field, and the computation pipeline identifier storage field, the execution result on which the source instruction depends is read, and based on the read execution result, the source instruction is issued to the corresponding computation pipeline for execution.

8. The scheduling optimization processor according to claim 7, characterized in that, The scheduling queue is also used to read the execution result that the source instruction depends on from the computational pipeline that executes the target instruction, based on the computational pipeline identifier stored in the computational pipeline identifier storage field, when the ready state is a ready bypass state. When the ready state is the write-back cache partition state, the execution result that the source instruction depends on is read based on the cache partition location indicated by the write-back cache partition state, the operation pipeline identifier stored in the operation pipeline identifier storage field, and the write-back cache identifier stored in the write-back cache identifier storage field. When the ready state is the physical register file state, the execution result that the source instruction depends on is read based on the physical register file number of the source operand.

9. The scheduling optimization processor according to claim 1, characterized in that, The output of each operation pipeline connected to the write-back buffer is connected to a different input port of a multiplexer; The number of input ports of the multiplexer is the same as the number of write-back buffers connected to the corresponding computation pipeline; The output of the multiplexer is connected to the write port of the physical register file.

10. An instruction scheduling method, characterized in that, include: Each computation pipeline is configured with at least two write-back caches, each write-back cache comprising a number of cache partitions of number n-1, where n is the number of different execution latency instruction types supported by the computation pipeline; According to the enqueue order of the cache partitions, the execution results of the instructions in the computation pipeline are written to the idle write-back cache; In each clock cycle, the valid execution results in the last-level cache partition of the write-back cache are written to the physical register file.

11. The instruction scheduling method according to claim 10, characterized in that, The step of writing the valid execution results in the last-level cache partition of the write-back cache to the physical register file in each clock cycle includes: When the write port of the physical register file is not occupied, the execution result of the instruction on the operation pipeline is written to the physical register file, and at the same time written to the data field of the entry cache partition of an idle write-back cache, and the write valid field of the entry cache partition is set to invalid. When the write port of the physical register file is occupied, the execution result of the instruction on the arithmetic pipeline is written into the data field of the entry cache partition of an idle write-back cache, and the write valid field of the entry cache partition is set to valid. In each clock cycle, the execution results with valid write-valid fields in the last-level cache partition of each write-back cache are written to the physical register file. After the writing is completed, the valid write fields are set to invalid, and the execution results with invalid write-valid fields in the last-level cache partition are removed.

12. A computer device, characterized in that, The computer device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the instruction scheduling method according to any one of claims 10-11.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to perform the instruction scheduling method according to any one of claims 10-11.

14. A computer program product comprising computer instructions, characterized in that, When the computer instruction is executed by the processor, it implements the steps of the instruction scheduling method according to any one of claims 10-11.

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