Server failure data collection system, method, and electronic device

Abstract

This application discloses a server fault data acquisition system, method, and electronic device, relating to the field of server technology. Through the collaborative design of a target processor and a baseboard management controller group, it solves the problem of incomplete server fault data acquisition in related technologies. Specifically, the target processor, based on an interrupt request sent by the fault detection circuit, determines the target baseboard management controller from among the various baseboard management controllers, and sends a control command to the switching circuit so that the switching circuit controls the target baseboard management controller to have access to the storage unit. The target processor is also used to send fault data acquisition commands to the target baseboard management controller to control the target baseboard management controller to acquire fault data from the server motherboard and to control the target baseboard management controller to store the fault data in the storage unit.

Description

Technical Field

[0001] This application relates to the field of server technology, and in particular to a server fault data acquisition system, method and electronic device. Background Technology

[0002] As server clusters expand, sudden server failures have led to frequent server downtime. Related technologies typically involve a baseboard management controller communicating with the server motherboard to collect server event logs, enabling the collection and storage of server failure data. However, these solutions suffer from incomplete data collection of server failures. Summary of the Invention

[0003] This application provides a server fault data acquisition system, method, and electronic device to at least solve the problem of incomplete server fault data acquisition in related technologies.

[0004] This application provides a server fault data acquisition system, including a fault detection circuit, a target processor, a baseboard management controller group, and a switching circuit. The baseboard management controller group includes multiple baseboard management controllers. The fault detection circuit is communicatively connected to the server motherboard. The target processor is communicatively connected to each baseboard management controller, the fault detection circuit, and the switching circuit in the baseboard management controller group. The switching circuit is communicatively connected to each baseboard management controller and a storage unit in the baseboard management controller group. The fault detection circuit is used to acquire fault signals from the server motherboard and send an interrupt request to the target processor based on the fault signals. The target processor is used to determine the target baseboard management controller from among the baseboard management controllers in response to the interrupt request, and to send a control command to the switching circuit and a fault data acquisition command to the target baseboard management controller. The switching circuit is used to control the target baseboard management controller to have access to the storage unit according to the control command. The target baseboard management controller is used to acquire fault data from the server motherboard according to the fault data acquisition command and store the fault data in the storage unit.

[0005] This application provides a server fault data acquisition method, comprising: receiving an interrupt request sent by a fault detection circuit; wherein the interrupt request is generated by the fault detection circuit based on a fault signal acquired from the server motherboard; in response to the interrupt request, determining a target baseboard management controller from a baseboard management controller group; wherein the baseboard management controller group includes multiple baseboard management controllers; sending a control command to a switching circuit to enable the switching circuit to control the target baseboard management controller to have access to a storage unit; in response to the interrupt request, generating a fault data acquisition command; and sending the fault data acquisition command to the target baseboard management controller to control the target baseboard management controller to acquire fault data from the server motherboard and to control the target baseboard management controller to store the fault data in the storage unit.

[0006] This application provides a server fault data acquisition method, comprising: acquiring fault signals from a server motherboard; generating an interrupt request based on the fault signals; sending the interrupt request to a target processor, causing the target processor to respond to the interrupt request and determine a target baseboard management controller from a baseboard management controller group; wherein the baseboard management controller group includes multiple baseboard management controllers; causing the target processor to send a control command to a switching circuit, causing the switching circuit to control the target baseboard management controller to have access to the storage unit; causing the target processor to respond to the interrupt request and generate a fault data acquisition command; causing the target processor to send the fault data acquisition command to the target baseboard management controller, thereby controlling the target baseboard management controller to acquire fault data from the server motherboard and controlling the target baseboard management controller to store the fault data in the storage unit.

[0007] This application also provides a first server fault data acquisition device, comprising: a receiving module for receiving an interrupt request sent by a fault detection circuit; wherein the interrupt request is generated by the fault detection circuit acquiring a fault signal from the server motherboard and based on the fault signal; a first processing module for determining a target baseboard management controller from a baseboard management controller group in response to the interrupt request; wherein the baseboard management controller group includes multiple baseboard management controllers; a first sending module for sending a control command to a switching circuit to enable the switching circuit to control the target baseboard management controller to have access to the storage unit; the first processing module is further configured to generate a fault data acquisition command in response to the interrupt request; the first sending module is further configured to send the fault data acquisition command to the target baseboard management controller to control the target baseboard management controller to acquire fault data from the server motherboard and to control the target baseboard management controller to store the fault data in the storage unit.

[0008] This application also provides a second server fault data acquisition device, comprising: an acquisition module for acquiring fault signals from a server motherboard; a second processing module for generating an interrupt request based on the fault signals; a second sending module for sending the interrupt request to a target processor, so that the target processor, in response to the interrupt request, determines a target baseboard management controller from a baseboard management controller group; wherein the baseboard management controller group includes multiple baseboard management controllers; causing the target processor to send a control command to a switching circuit, so that the switching circuit controls the target baseboard management controller to have access to the storage unit; causing the target processor, in response to the interrupt request, to generate a fault data acquisition command; causing the target processor to send the fault data acquisition command to the target baseboard management controller, so as to control the target baseboard management controller to acquire fault data from the server motherboard and control the target baseboard management controller to store the fault data in the storage unit.

[0009] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above-described server fault data acquisition methods.

[0010] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described server fault data acquisition methods.

[0011] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described server fault data acquisition methods.

[0012] The server fault data acquisition system, method, and electronic device provided in this application, through the collaborative design of the target processor and the baseboard management controller group, solves the problem of incomplete server fault data acquisition caused by baseboard management controller failure when acquiring server fault data through a single baseboard management controller in related technologies. Specifically, based on the interrupt request sent by the fault detection circuit, the target processor determines the target baseboard management controller from among the baseboard management controllers in the baseboard management controller group, and sends a control command to the switching circuit so that the switching circuit controls the target baseboard management controller to have access to the storage unit, avoiding resource conflicts between the target baseboard management controller and other baseboard management controllers in the baseboard management controller group; the target processor is also used to send fault data acquisition commands to the target baseboard management controller to control the target baseboard management controller to acquire fault data of the server motherboard, and to control the target baseboard management controller to store the fault data in the storage unit. Attached Figure Description

[0013] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 System architecture of the server fault data acquisition system provided in the embodiments of this application Figure 1 ;

[0015] Figure 2 System architecture of the server fault data acquisition system provided in the embodiments of this application Figure 2 ;

[0016] Figure 3 System architecture of the server fault data acquisition system provided in the embodiments of this application Figure 3 ;

[0017] Figure 4 System architecture of the server fault data acquisition system provided in the embodiments of this application Figure 4 ;

[0018] Figure 5 System architecture of the server fault data acquisition system provided in the embodiments of this application Figure 5 ;

[0019] Figure 6 A flowchart illustrating the server fault data acquisition method provided in this application embodiment. Figure 1 ;

[0020] Figure 7 A flowchart illustrating the server fault data acquisition method provided in this application embodiment. Figure 2 ;

[0021] Figure 8 A schematic diagram of the structure of the first server fault data acquisition device provided in the embodiments of this application;

[0022] Figure 9 This is a schematic diagram of the structure of the second server fault data acquisition device provided in the embodiments of this application;

[0023] Figure 10 A schematic diagram of the structure of the electronic device provided in this application.

[0024] Figure label:

[0025] 100 - Fault detection circuit; 101 - First input terminal; 102 - First output terminal; 103 - Analog-to-digital converter; 1031 - First terminal; 1032 - Second terminal; 104 - First processor; 1041 - Third terminal; 1042 - Fourth terminal; 105 - Second processor; 1051 - Fifth terminal; 1052 - Sixth terminal; 106 - Logic gate circuit combination; 200 - Target processor; 201 - First input / output terminal; 202 - Second input terminal; 203 - Second output terminal; 204 - Fourth input / output interface; 300 - Baseboard management controller group; 301 - Baseboard management controller; 3011 - Target baseboard management controller; 302 - Second input / output terminal; 303 - Third input / output terminal; 400 - Switching circuit; 401 - Control terminal; 402 - Channel terminal; 403 - Common terminal; 500 - Server motherboard; 501 - Motherboard internal signal interface; 600 - Storage unit. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0027] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0028] As server clusters expand, sudden server failures have led to frequent server downtime. Related technologies typically involve a baseboard management controller communicating with the server motherboard to collect server event logs, enabling the collection and storage of server failure data. However, these solutions suffer from incomplete data collection of server failures.

[0029] To address the aforementioned technical problems, this application proposes the following technical concept: constructing a server fault data acquisition system and method based on multiple baseboard management controllers and a target processor. Specifically, by introducing a low-power, highly reliable target processor, when a server fault occurs, an interrupt request is sent via a fault detection circuit to wake up the target processor. The target processor then quickly responds to the interrupt request, determines the target baseboard management controller from among the baseboard management controllers, and sends control commands to a switching circuit, as well as fault data acquisition commands to the target baseboard management controller. The switching circuit, according to the control commands, controls the target baseboard management controller to have access to the storage unit. The target baseboard management controller, according to the fault data acquisition commands, acquires fault data from the server motherboard and stores the fault data in the storage unit, thereby ensuring the reliability and integrity of the server fault data.

[0030] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0031] refer to Figure 1 , Figure 1 System architecture of the server fault data acquisition system provided in the embodiments of this application Figure 1 .

[0032] like Figure 1 As shown, the server fault data acquisition system includes a fault detection circuit 100, a target processor 200, a baseboard management controller group 300, and a switching circuit 400; the baseboard management controller group 300 includes multiple baseboard management controllers 301.

[0033] The fault detection circuit 100 is communicatively connected to the server motherboard 500; the target processor 200 is communicatively connected to each baseboard management controller 301, the fault detection circuit 100, and the switching circuit 400 in the baseboard management controller group 300; the switching circuit 400 is communicatively connected to each baseboard management controller 301 and the storage unit 600 in the baseboard management controller group 300.

[0034] The fault detection circuit 100 is used to collect fault signals from the server motherboard 500 and send an interrupt request to the target processor 200 based on the fault signals. The target processor 200, in response to the interrupt request, determines the target baseboard management controller 3011 from each baseboard management controller 301, and sends a control command to the switching circuit 400, sending a fault data acquisition command to the target baseboard management controller 3011. The switching circuit 400, according to the control command, controls the target baseboard management controller 3011 to have access to the storage unit 600. The target baseboard management controller 3011, according to the fault data acquisition command, collects fault data from the server motherboard 500 and stores the fault data in the storage unit 600.

[0035] In one possible implementation, the fault detection circuit 100 is composed of one or more logic gates. The target processor 200 is a microcontroller unit (MCU). The switching circuit 400 is a multi-channel analog switch (e.g., a MOSFET array analog switch), wherein the number of channels of the multi-channel analog switch is greater than or equal to the number of substrate management controllers 301 in the substrate management controller group 300; wherein the MOSFET is a Metal-Oxide-Semiconductor Field-Effect Transistor.

[0036] In this embodiment, the collaborative design of the target processor 200 and the baseboard management controller group 300 solves the problem of incomplete server fault data collection caused by a fault in the baseboard management controller 301 when collecting server fault data through a single baseboard management controller in related technologies. Specifically, based on the interrupt request sent by the fault detection circuit 100, the target processor 200 determines the target baseboard management controller 3011 from among the baseboard management controllers 301 in the baseboard management controller group 300, and sends a control command to the switching circuit 400 so that the switching circuit 400 controls the target baseboard management controller 3011 to have access to the storage unit 600, avoiding resource conflicts between the target baseboard management controller 301 and other baseboard management controllers 301 in the baseboard management controller group 300; the target processor 200 is also used to send a fault data collection command to the target baseboard management controller 3011 to control the target baseboard management controller 3011 to collect fault data of the server motherboard 500, and to control the target baseboard management controller 3011 to store the fault data in the storage unit 600.

[0037] exist Figure 1 Based on the server fault data acquisition system shown, Figure 2System architecture of the server fault data acquisition system provided in the embodiments of this application Figure 2 .

[0038] like Figure 2 As shown, the first input terminal 101 of the fault detection circuit 100 is communicatively connected to the internal signal interface 501 of the server motherboard 500; the first input / output terminal 201 of the target processor 200 is communicatively connected to the second input / output terminal 302 of each substrate management controller 301 in the substrate management controller group 300; the second input terminal 202 of the target processor 200 is communicatively connected to the first output terminal 102 of the fault detection circuit 100; the second output terminal 203 of the target processor 200 is communicatively connected to the control terminal 401 of the switching circuit 400, and the second output terminal 203 is used to send control commands from the target processor 200 to the switching circuit 400; the channel terminal 402 of the switching circuit 400 is communicatively connected to the third input / output terminal 303 of each substrate management controller 301 in the substrate management controller group 300; and the common terminal 403 of the switching circuit 400 is communicatively connected to the storage unit 600.

[0039] Taking the substrate management controller group 300 as an example where there are two substrate management controllers 301 (including target substrate management controller 3011), the number of the first input / output terminal 201, the second input / output terminal 302, the channel terminal 402, and the third input / output terminal 303 are also two.

[0040] In one possible implementation, the interface type of the first input / output terminal 201 includes a Universal Asynchronous Receiver / Transmitter (UART interface); the interface type of the second input terminal 202 includes an external interrupt pin; the interface type of the second output terminal 203 includes a General Purpose Input / Output (GPIO pin); and the interface type of the third input / output terminal 303 includes a Serial Peripheral Interface (SPI interface).

[0041] exist Figure 2 Based on the server fault data acquisition system shown, Figure 3 System architecture of the server fault data acquisition system provided in the embodiments of this application Figure 3 .

[0042] like Figure 3As shown, the fault detection circuit 100 includes an analog-to-digital converter 103 and a first processor 104; the first terminal 1031 of the analog-to-digital converter 103 is communicatively connected to the internal signal interface 501 of the server motherboard 500; the second terminal 1032 of the analog-to-digital converter 103 is communicatively connected to the third terminal 1041 of the first processor 104; and the fourth terminal 1042 of the first processor 104 is communicatively connected to the second input terminal 202 of the target processor 200.

[0043] The analog-to-digital converter 103 is used to collect fault signals from the server motherboard 500 and convert the fault signals into fault digital signals. The first processor 104 is used to adjust the fault trigger threshold according to the server load, and generate an interrupt request to send the interrupt request to the target processor 200 when the amplitude of the fault digital signal is greater than or equal to the fault trigger threshold.

[0044] The first terminal 1031 of the analog-to-digital converter 103 is the first input terminal 101 of the fault detection circuit 100; the fourth terminal 1042 of the first processor 104 is the first output terminal 102 of the fault detection circuit 100.

[0045] In this embodiment, the collected fault signal is converted into a fault digital signal by the analog-to-digital converter 103, and then the first processor 104 adjusts the fault trigger threshold according to the server load. When the amplitude of the fault digital signal is greater than or equal to the fault trigger threshold, an interrupt request is generated so that the target processor 200 responds to the interrupt request and executes subsequent steps. This reduces the false trigger rate of server fault data collection and improves the targeting of server fault data collection.

[0046] exist Figure 2 Based on the server fault data acquisition system shown, Figure 4 System architecture of the server fault data acquisition system provided in the embodiments of this application Figure 4 .

[0047] like Figure 4 As shown, the fault detection circuit 100 also includes a second processor 105; the fifth terminal 1051 of the second processor 105 is communicatively connected to the internal signal interface 501 of the server motherboard 500; the sixth terminal 1052 of the second processor 105 is communicatively connected to the fourth input / output interface 204 of the target processor 200.

[0048] The second processor 105 is used to generate fault category features based on the fault signal and send the fault category features to the target processor 200. The target processor 200 is also used to read or receive the fault category features through the fourth input / output interface 204 in response to an interrupt request, and generate a fault data acquisition instruction based on the fault category features.

[0049] In one possible implementation, the fault detection circuit 100, based on a logic gate combination 106, is communicatively connected to the internal signal interface 501 of the server motherboard 500 via a first input terminal 101, and communicatively connected to the second input terminal 202 of the target processor 200 via a first output terminal 102. This allows it to collect fault signals from the server motherboard 500 and send an interrupt request to the target processor 200 based on the fault signals. Furthermore, the fault detection circuit 100, based on a second processor 105, generates fault category features according to the fault signals and sends these features to the target processor 200. The logic gate combination 106 includes one or more logic gates.

[0050] Furthermore, in one possible implementation, both the sixth terminal 1052 and the fourth input / output interface 204 are multiple GPIO pins; then the second processor 105 changes the level of the GPIO pin corresponding to the sixth terminal 1052 according to the generated fault category characteristics to obtain different level combinations, and different level combinations represent different fault category characteristics; then the target processor 200, in response to an interrupt request, reads the level combination through the fourth input / output interface 204 to determine the corresponding fault category characteristics, and then realizes the generation of fault data acquisition instructions based on the fault category characteristics.

[0051] Furthermore, in another possible implementation, both the sixth terminal 1052 and the fourth input / output interface 204 are synchronous or asynchronous serial communication interfaces. The second processor 105 then generates a corresponding fault code based on the generated fault category characteristics. This fault code is then sent to the target processor 200 via the synchronous or asynchronous serial communication interface. That is, in response to an interrupt request, the target processor 200 receives the fault code corresponding to the fault category characteristics via the synchronous or asynchronous serial communication interface and generates a fault data acquisition command based on the fault code. The synchronous serial communication interface includes an Inter-Integrated Circuit (I2C) interface and an SPI interface; the asynchronous serial communication interface includes a UART interface.

[0052] Specifically, the second processor 105 compares the fault signal with fault category features in a predefined fault mode library to determine the fault category feature corresponding to the fault signal. Then, the second processor 105 sends the fault category feature corresponding to the fault signal to the target processor 200, so that the target processor 200 can read or receive the fault category feature sent by the second processor 105 in response to an interrupt request. The predefined fault mode library stores predefined fault category features (e.g., "server processor overheating leading to system crash" or "accumulation of errors in memory error verification and correction").

[0053] In this embodiment, the second processor 105 generates differentiated fault category features based on the fault signal and outputs them to the target processor 200, so that the target processor 200 can initiate the server fault data collection process in a targeted manner. For example, for memory errors, the collection of error verification and correction logs (Error Correcting Code Log, or ECC error log) is initiated first, which improves the server fault data collection system's ability to identify complex fault scenarios and the targeting of server fault data collection.

[0054] exist Figure 3 Based on the server fault data acquisition system shown, Figure 5 System architecture of the server fault data acquisition system provided in the embodiments of this application Figure 5 .

[0055] like Figure 5 As shown, the fault detection circuit 100 also includes a second processor 105; the fifth terminal 1051 of the second processor 105 is communicatively connected to the internal signal interface 501 of the server motherboard 500; the sixth terminal 1052 of the second processor 105 is communicatively connected to the fourth input / output interface 204 of the target processor 200.

[0056] The second processor 105 is used to generate fault category features based on the fault signal and send the fault category features to the target processor 200. The target processor 200 is also used to read or receive the fault category features through the fourth input / output interface 204 in response to an interrupt request, and generate a fault data acquisition instruction based on the fault category features.

[0057] That is, the first terminal 1031 of the analog-to-digital converter 103 and the fifth terminal 1051 of the second processor 105 are both connected to the internal signal interface 501 of the server motherboard 500.

[0058] Figure 6 A flowchart illustrating the server fault data acquisition method provided in this application embodiment. Figure 1 ,like Figure 6As shown, an embodiment of this application provides a server fault data acquisition method, with the target processor as the execution subject. The method is described in detail below:

[0059] S601: Receives an interrupt request sent by the fault detection circuit; wherein, the interrupt request is generated by the fault detection circuit based on the fault signal collected by the server motherboard.

[0060] For example, the target processor is a microcontroller unit (MCU). During normal server operation, the target processor is in a low-power monitoring mode to listen for interrupt requests from the fault detection circuit; then, upon receiving an interrupt request from the fault detection circuit, the target processor is woken up to enter the working mode.

[0061] S602: In response to an interrupt request, determine a target substrate management controller from the substrate management controller group; wherein the substrate management controller group includes multiple substrate management controllers.

[0062] Specifically, the specific implementation steps of step S602 include:

[0063] Step S6021: In response to the interrupt request, obtain the operating status data of each baseboard management controller in the baseboard management controller group.

[0064] For example, in response to an interrupt request, the target processor sends a status query command, such as AT#GETSTATUS in the AT command, to each baseboard management controller in the baseboard management controller group to obtain the operating status data of each baseboard management controller.

[0065] The operating status data of the baseboard management controller includes the server's processor utilization, memory usage, and heartbeat signal status.

[0066] Step S6022: Determine the target operating status data from the operating status data of each board management controller according to the preset calling strategy.

[0067] Step S6023: Determine the baseboard management controller corresponding to the target operating status data as the target baseboard management controller.

[0068] For example, based on a preset invocation strategy, the operating status data corresponding to the preset invocation strategy is determined from the operating status data of each baseboard management controller, and then the operating status data corresponding to the preset invocation strategy of each baseboard management controller is compared to determine the target operating status data.

[0069] Specifically, for example, if the preset invocation strategy is a load balancing strategy, then the processor utilization rate of the servers handled by each baseboard management controller is determined from the operating status data of each baseboard management controller according to the load balancing strategy. The processor utilization rates of the servers handled by each baseboard management controller are then compared, and the lowest processor utilization rate is determined as the target operating status data. Furthermore, the baseboard management controller corresponding to the target operating status data is determined as the target baseboard management controller, that is, the baseboard management controller corresponding to the lowest processor utilization rate is determined as the target baseboard management controller.

[0070] For example, if the preset invocation strategy is a health status priority strategy, then the memory usage and / or heartbeat signal status are determined from the operating status data of each baseboard management controller according to the health status priority strategy. The memory usage and / or heartbeat signal status of each baseboard management controller are then compared to determine the memory usage and / or heartbeat signal status with the best health status, thus obtaining the target operating status data. Furthermore, the baseboard management controller corresponding to the target operating status data is determined as the target baseboard management controller, that is, the baseboard management controller corresponding to the best memory usage and / or heartbeat signal status is determined as the target baseboard management controller.

[0071] In this embodiment, by dynamically selecting the load balancing strategy and the health status priority strategy, the target processor can determine the target baseboard management controller for collecting server fault data from the baseboard management controller group according to the actual operating status of each baseboard management controller. This improves the efficiency and reliability of server fault data collection and avoids server fault data collection failure due to insufficient available resources of the target baseboard management controller.

[0072] Furthermore, in another possible implementation, the preset invocation strategy is a comprehensive invocation strategy; then the specific implementation steps of step S6022 include:

[0073] Step S60221: Based on the comprehensive call strategy, obtain the weighting coefficients of server load and various operating status data.

[0074] Step S60222: Update the weighting coefficients of various operating status data according to the server load to obtain the updated weighting coefficients of various operating status data.

[0075] For example, the weighting coefficients of various operating status data determined by the comprehensive call strategy are, for example, 60% for load weight and 40% for health status weight; based on the server load, the 60% for load weight and 40% for health status weight are updated to obtain the updated weighting coefficients of various operating status data, for example, 75% for load weight and 25% for health status weight.

[0076] Step S60223: Based on the updated weighting coefficients of various operating status data, the operating status data of each baseboard management controller is weighted and calculated to obtain the comprehensive operating status score of each baseboard management controller.

[0077] For example, the overall operating status score consists of a load score and a health status score. Based on step S60222, the load weight corresponding to the load score is 75%, and the health status weight corresponding to the health status score is 25%. The load score is calculated as (100% - server processor utilization) × 70%. The lower the server's processor utilization, the higher the load score. When the health status is normal, the health status weight of 25% is determined as the health status score, so the health status score is 25%. When the health status is abnormal, a corresponding deduction is made. Then, the load score and the health status score are summed to obtain the overall operating status score.

[0078] Step S60224: Compare the overall operating status scores of each baseboard management controller to determine the maximum overall operating status score.

[0079] Step S60225: Determine the operating status data corresponding to the maximum operating status comprehensive score as the target operating status data.

[0080] In this embodiment, by weighted calculation of the comprehensive score of the operating status of each baseboard management controller, the adaptability based on the determined target operating status data is realized, which improves the robustness and stability when collecting server fault data in complex fault scenarios.

[0081] S603: Send a control command to the switching circuit so that the switching circuit controls the target board management controller to have access to the memory unit.

[0082] For example, based on the target substrate management controller identifier of the determined target substrate management controller, a control command is sent to the switching circuit so that the switching circuit controls the target substrate management controller to have access to the storage unit; and prevents other substrate management controllers in the substrate management controller group from having access to the storage unit, thereby avoiding resource conflicts between other substrate management controllers in the substrate management controller group and the target substrate management controller.

[0083] S604: In response to an interrupt request, generate a fault data acquisition command.

[0084] For example, the fault data acquisition command is used to control the target board management controller to acquire fault data from the server motherboard and to control the target board management controller to store the fault data in the storage unit. Specifically, for example, the fault data acquisition command includes freezing the current System Event Log (SEL record), acquiring instantaneous sensor data (voltage, temperature, power consumption), reading the PCIe Advanced Error Reporting (AER log), triggering or obtaining the server operating system crash dump file out of band, and obtaining the Common Platform Error Record (CPER record).

[0085] Then, in response to the interrupt request, the target processor can generate a fault data acquisition instruction.

[0086] Furthermore, in one possible implementation, step S604 includes the following specific steps:

[0087] Step S6041: In response to an interrupt request, read or receive the fault category characteristics sent by the fault detection circuit; wherein, the fault category characteristics are determined by the fault detection circuit based on the fault signal.

[0088] For example, the fault detection circuit compares the fault signal with fault category features in a predefined fault mode library to determine the fault category feature corresponding to the fault signal. Then, the fault detection circuit sends the fault category feature corresponding to the fault signal to the target processor, so that the target processor can read or receive the fault category feature sent by the fault detection circuit in response to an interrupt request. The predefined fault mode library stores predefined fault category features (e.g., "server processor overheating leading to crash" or "accumulation of errors in memory error verification and correction").

[0089] Step S6042: Generate a fault data acquisition command based on the fault category characteristics.

[0090] For example, the target processor generates a fault data acquisition instruction corresponding to the fault category characteristics. Specifically, for example, if the fault category characteristic is the accumulation of errors in memory error verification and correction, the fault data acquisition instruction is to prioritize the acquisition of the Error Correcting Code Log (ECC error log), and then execute step S605 to control the target baseboard management controller to prioritize the acquisition of the error verification and correction log.

[0091] In this embodiment, the fault detection circuit generates differentiated fault category features based on the fault signal and outputs them to the target processor. This enables the target processor to initiate the server fault data collection process in a targeted manner. For example, for memory errors, the collection of Error Correcting Code Log (ECC error log) is initiated first, which improves the ability to identify complex fault scenarios and the targeting of server fault data collection.

[0092] S605: Sends a fault data acquisition command to the target board management controller to control the target board management controller to acquire fault data from the server motherboard and to control the target board management controller to store the fault data in the storage unit.

[0093] For example, the storage unit is a non-volatile memory, a storage medium that retains data even after power failure, such as SPI Flash or EEPROM. Furthermore, fault data can be output through an out-of-band management interface; wherein, the out-of-band management interface is, for example, an SOL (Serial Over LAN) interface or a USB interface.

[0094] In the process of the target baseboard management controller collecting fault data from the server motherboard and storing the fault data in the storage unit, the target baseboard management controller can be powered by a backup power supply to ensure that the target baseboard management controller can operate stably when the server loses power.

[0095] In this embodiment, the collaborative design of the target processor and the baseboard management controller group solves the problem of incomplete server fault data acquisition caused by baseboard management controller failure when collecting server fault data through a single baseboard management controller in related technologies. Specifically, based on the interrupt request sent by the fault detection circuit, the target processor determines the target baseboard management controller from among the baseboard management controllers in the baseboard management controller group, and sends a control command to the switching circuit so that the switching circuit controls the target baseboard management controller to have access to the storage unit, avoiding resource conflicts between the target baseboard management controller and other baseboard management controllers in the baseboard management controller group; then, the target processor sends a fault data acquisition command to the target baseboard management controller to control the target baseboard management controller to collect the fault data of the server motherboard and control the target baseboard management controller to store the fault data in the storage unit.

[0096] Furthermore, in the process of controlling the target substrate management controller to collect fault data from the server motherboard and controlling the target substrate management controller to store the fault data in the storage unit, the method provided in this application embodiment further includes:

[0097] S606: Receives fault data acquisition response signals sent by the target substrate management controller.

[0098] S607: Determine the relationship between the transmission time interval of the fault data acquisition response signal sent by the target substrate management controller and the time interval threshold.

[0099] S608: If the transmission time interval is less than or equal to the time interval threshold, continue to control the target baseboard management controller to collect fault data from the server motherboard and control the target baseboard management controller to store the fault data in the storage unit.

[0100] The time interval threshold can be a preset fixed value or a dynamic value based on changes in server load.

[0101] S609: If the transmission time interval is greater than the time interval threshold, then determine the backup baseboard management controller and the backup baseboard management controller identifier from the other baseboard management controllers in the baseboard management controller group 300.

[0102] S610: Based on the identifier of the backup board management controller, send a switching command to the switching circuit so that the switching circuit controls the backup board management controller to have access to the storage unit and controls the target board management controller to not have access to the storage unit.

[0103] S611: Sends the fault data acquisition command to the backup board management controller to control the backup board management controller to reacquire the fault data of the server motherboard and to control the backup board management controller to store the fault data in the storage unit.

[0104] Specifically, during the process of controlling the backup baseboard management controller to re-collect the server motherboard's fault data and controlling the backup baseboard management controller to store the fault data in the storage unit, the backup baseboard management controller is re-identified as the target baseboard management controller to re-execute step S606 and subsequent steps. This achieves full monitoring of the target baseboard management controller's collection of server motherboard fault data and its storage of fault data in the storage unit, ensuring the integrity of the server fault data collection. This solves the problem in related technologies where incomplete server fault data collection is caused by baseboard management controller failure when collecting server fault data through a single baseboard management controller.

[0105] Figure 7 A flowchart illustrating the server fault data acquisition method provided in this application embodiment. Figure 2 In this embodiment, the execution entity is a fault detection circuit; such as... Figure 7 As shown, the method includes:

[0106] S701: Collects fault signals from the server motherboard.

[0107] S702: Generates an interrupt request based on the fault signal.

[0108] S703: Send an interrupt request to the target processor, so that the target processor responds to the interrupt request and determines the target baseboard management controller from the baseboard management controller group; wherein the baseboard management controller group includes multiple baseboard management controllers; cause the target processor to send a control command to the switching circuit, so that the switching circuit controls the target baseboard management controller to have access to the storage unit; cause the target processor to generate a fault data acquisition command in response to the interrupt request; cause the target processor to send the fault data acquisition command to the target baseboard management controller, so as to control the target baseboard management controller to acquire fault data of the server motherboard, and control the target baseboard management controller to store the fault data in the storage unit.

[0109] Figure 7 The description of the features in the embodiment corresponding to the server fault data acquisition method shown can be found in the relevant description of the embodiment corresponding to the fault detection circuit in the server fault data acquisition system, and will not be repeated here.

[0110] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0111] Figure 8 This is a schematic diagram of the structure of the first server fault data acquisition device provided in an embodiment of this application. Figure 8 As shown, embodiments of this application also provide a first server fault data acquisition device 80, including: a receiving module 801, a first processing module 802, and a first sending module 803.

[0112] The receiving module 801 is used to receive the interrupt request sent by the fault detection circuit; wherein, the interrupt request is generated by the fault detection circuit based on the fault signal collected by the server motherboard.

[0113] The first processing module 802 is configured to determine a target substrate management controller from the substrate management controller group in response to an interrupt request; wherein the substrate management controller group includes multiple substrate management controllers.

[0114] The first transmitting module 803 is used to send control commands to the switching circuit so that the switching circuit controls the target board management controller to have access to the storage unit.

[0115] The first processing module 802 is also used to generate fault data acquisition instructions in response to interrupt requests.

[0116] The first sending module 803 is also used to send a fault data acquisition instruction to the target baseboard management controller to control the target baseboard management controller to acquire fault data of the server motherboard and to control the target baseboard management controller to store the fault data in the storage unit.

[0117] In one possible implementation, when the first processing module 802 determines the target baseboard management controller from the baseboard management controller group in response to an interrupt request, it is specifically configured to: obtain the operating status data of each baseboard management controller in the baseboard management controller group in response to the interrupt request; determine the target operating status data from the operating status data of each baseboard management controller according to a preset calling strategy; and determine the baseboard management controller corresponding to the target operating status data as the target baseboard management controller.

[0118] In one possible implementation, when the first processing module 802 generates a fault data acquisition instruction in response to an interrupt request, it is specifically used to: read or receive fault category characteristics sent by the fault detection circuit in response to the interrupt request; wherein the fault category characteristics are determined by the fault detection circuit based on the fault signal; and generate a fault data acquisition instruction based on the fault category characteristics.

[0119] In one possible implementation, during the process of controlling the target baseboard management controller to collect fault data from the server motherboard and to store the fault data in the storage unit, the first server fault data acquisition device 80 is further configured to: receive a fault data acquisition response signal sent by the target baseboard management controller; determine the relationship between the transmission time interval of the fault data acquisition response signal sent by the target baseboard management controller and a time interval threshold; if the transmission time interval is less than or equal to the time interval threshold, continue to control the target baseboard management controller to collect fault data from the server motherboard and store the fault data in the storage unit; if the transmission time interval is greater than the time interval threshold, determine a backup baseboard management controller and its backup baseboard management controller identifier from other baseboard management controllers in the baseboard management controller group; send a switching command to the switching circuit according to the backup baseboard management controller identifier, so that the switching circuit controls the backup baseboard management controller to have access to the storage unit and controls the target baseboard management controller to not have access to the storage unit; send a fault data acquisition command to the backup baseboard management controller to control the backup baseboard management controller to re-collect the fault data from the server motherboard and store the fault data in the storage unit.

[0120] A description of the features corresponding to the embodiment of the first server fault data acquisition device 80 can be found in [reference needed]. Figure 6 The relevant descriptions of the embodiments corresponding to the server fault data collection method shown are not repeated here.

[0121] Figure 9 This is a schematic diagram of the structure of the second server fault data acquisition device provided in an embodiment of this application. Figure 9 As shown, embodiments of this application also provide a second server fault data acquisition device 90, including: an acquisition module 901, a second processing module 902, and a second sending module 903.

[0122] The acquisition module 901 is used to acquire fault signals from the server motherboard.

[0123] The second processing module 902 is used to generate an interrupt request based on the fault signal.

[0124] The second sending module 903 is used to send an interrupt request to the target processor, so that the target processor, in response to the interrupt request, determines the target baseboard management controller from the baseboard management controller group; wherein the baseboard management controller group includes multiple baseboard management controllers; to cause the target processor to send a control command to the switching circuit, so that the switching circuit controls the target baseboard management controller to have access to the storage unit; to cause the target processor, in response to the interrupt request, generate a fault data acquisition command; and to cause the target processor to send the fault data acquisition command to the target baseboard management controller, so as to control the target baseboard management controller to acquire fault data of the server motherboard and control the target baseboard management controller to store the fault data in the storage unit.

[0125] The description of the features corresponding to the embodiment of the second server fault data acquisition device 90 can be found in [reference needed]. Figure 7 The relevant descriptions of the embodiments corresponding to the server fault data collection method shown are not repeated here.

[0126] Figure 10 A schematic diagram of the structure of the electronic device provided in this application. Figure 10 As shown, the electronic device 700 provided in this embodiment includes at least one processor 7001 and a memory 7002. Optionally, the electronic device 700 further includes a communication component 7003. The processor 7001, memory 7002, and communication component 7003 are connected via a bus.

[0127] In the specific implementation process, at least one processor 7001 executes computer execution instructions stored in memory 7002, causing at least one processor 7001 to execute the above-described server fault data acquisition method embodiment.

[0128] The specific implementation process of processor 7001 can be found in the above method embodiments, and its implementation principle and technical effect are similar. It will not be repeated here.

[0129] Specifically, processor 7001 executes Figure 6 In the server fault data acquisition method embodiment shown, processor 7001 is the target processor 200; processor 7001 executes... Figure 7 In the server fault data acquisition method embodiment shown, the processor 7001 is the fault detection circuit 100.

[0130] In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0131] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0132] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0133] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described embodiments of the server fault data acquisition method when running.

[0134] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0135] The embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above embodiments of the server fault data acquisition method.

[0136] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described server fault data acquisition method embodiments.

[0137] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be executed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip (SoC), a complex programmable logic device (CPLD), a microprocessor (MCU), etc. The terms "system," "computing device," or "apparatus" as used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or one or more combinations thereof. The aforementioned computer program (also known as a program, software, software application, app, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0138] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0139] The foregoing has provided a detailed description of a server fault data acquisition system, method, and electronic device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A server fault data acquisition system, characterized in that, It includes a fault detection circuit (100), a target processor (200), a baseboard management controller group (300), and a switching circuit (400); the baseboard management controller group (300) includes a plurality of baseboard management controllers (301); The fault detection circuit (100) is communicatively connected to the server motherboard (500); the target processor (200) is communicatively connected to each baseboard management controller (301) in the baseboard management controller group (300), the fault detection circuit (100), and the switching circuit (400); the switching circuit (400) is communicatively connected to each baseboard management controller (301) in the baseboard management controller group (300) and the storage unit (600). The fault detection circuit (100) is used to collect fault signals from the server motherboard (500) and send an interrupt request to the target processor (200) based on the fault signals. The target processor (200) is configured to, in response to the interrupt request, determine the target substrate management controller (3011) from each substrate management controller (301) to send control instructions to the switching circuit (400) and send fault data acquisition instructions to the target substrate management controller (3011); The switching circuit (400) is used to control the target substrate management controller (3011) to have access to the storage unit (600) according to the control command; The target baseboard management controller (3011) is used to collect fault data of the server motherboard (500) according to the fault data collection instruction, and store the fault data in the storage unit (600).

2. The server fault data acquisition system according to claim 1, characterized in that, The first input terminal (101) of the fault detection circuit (100) is communicatively connected to the internal signal interface (501) of the server motherboard (500); The first input / output terminal (201) of the target processor (200) is communicatively connected to the second input / output terminal (302) of each substrate management controller (301) in the substrate management controller group (300); The second input terminal (202) of the target processor (200) is communicatively connected to the first output terminal (102) of the fault detection circuit (100); The second output terminal (203) of the target processor (200) is communicatively connected to the control terminal (401) of the switching circuit (400); The channel terminal (402) of the switching circuit (400) is communicatively connected to the third input / output terminal (303) of each substrate management controller (301) in the substrate management controller group (300); The common terminal (403) of the switching circuit (400) is communicatively connected to the storage unit (600).

3. The server fault data acquisition system according to claim 2, characterized in that, The fault detection circuit (100) includes an analog-to-digital converter (103) and a first processor (104). The first end (1031) of the analog-to-digital converter (103) is communicatively connected to the internal signal interface (501) of the server motherboard (500); the second end (1032) of the analog-to-digital converter (103) is communicatively connected to the third end (1041) of the first processor (104); the fourth end (1042) of the first processor (104) is communicatively connected to the second input end (202) of the target processor (200). The analog-to-digital converter (103) is used to collect fault signals from the server motherboard (500) and convert the fault signals into fault digital signals. The first processor (104) is configured to adjust the fault trigger threshold according to the server load, and generate the interrupt request to send the interrupt request to the target processor (200) when the amplitude of the fault digital signal is greater than or equal to the fault trigger threshold.

4. The server fault data acquisition system according to claim 2, characterized in that, The fault detection circuit (100) also includes a second processor (105); The fifth terminal (1051) of the second processor (105) is communicatively connected to the internal signal interface (501) of the server motherboard (500); the sixth terminal (1052) of the second processor (105) is communicatively connected to the fourth input / output interface (204) of the target processor (200); The second processor (105) is used to generate fault category features based on the fault signal and send the fault category features to the target processor (200). The target processor (200) is also configured to, in response to the interrupt request, read or receive the fault category characteristics through the fourth input / output interface (204), and generate the fault data acquisition instruction based on the fault category characteristics.

5. A method for collecting server fault data, characterized in that, include: Receive an interrupt request sent by the fault detection circuit; wherein the interrupt request is generated by the fault detection circuit based on the fault signal collected from the server motherboard; In response to the interrupt request, a target substrate management controller is determined from the substrate management controller group; wherein the substrate management controller group includes multiple substrate management controllers; Send a control command to the switching circuit so that the switching circuit controls the target substrate management controller to have access to the storage unit; In response to the interruption request, a fault data acquisition instruction is generated; The fault data acquisition command is sent to the target baseboard management controller to control the target baseboard management controller to acquire the fault data of the server motherboard and to control the target baseboard management controller to store the fault data in the storage unit.

6. The server fault data acquisition method according to claim 5, characterized in that, The step of determining the target substrate management controller from the substrate management controller group in response to the interrupt request includes: In response to the interrupt request, the operating status data of each baseboard management controller in the baseboard management controller group is obtained; According to the preset calling strategy, the target operating status data is determined from the operating status data of each baseboard management controller; The baseboard management controller corresponding to the target operating status data is identified as the target baseboard management controller.

7. The server fault data acquisition method according to claim 5, characterized in that, The step of generating a fault data acquisition instruction in response to the interruption request includes: In response to the interrupt request, the fault detection circuit reads or receives fault category features sent by the fault detection circuit; wherein the fault category features are determined by the fault detection circuit based on the fault signal. Based on the fault category characteristics, the fault data acquisition instruction is generated.

8. The server fault data acquisition method according to any one of claims 5-7, characterized in that, In the process of controlling the target baseboard management controller to collect fault data of the server motherboard and controlling the target baseboard management controller to store the fault data in the storage unit, the method further includes: Receive the fault data acquisition response signal sent by the target substrate management controller; Determine the relationship between the transmission time interval of the fault data acquisition response signal sent by the target baseboard management controller and the time interval threshold; If the transmission time interval is less than or equal to the time interval threshold, then the target baseboard management controller continues to collect the fault data of the server motherboard and controls the target baseboard management controller to store the fault data in the storage unit; If the transmission time interval is greater than the time interval threshold, a backup baseboard management controller is determined from the other baseboard management controllers in the baseboard management controller group, and the backup baseboard management controller identifier of the backup baseboard management controller is determined. Based on the identifier of the backup board management controller, a switching command is sent to the switching circuit so that the switching circuit controls the backup board management controller to have access to the storage unit and controls the target board management controller not to have access to the storage unit. The fault data acquisition command is sent to the backup board management controller to control the backup board management controller to reacquire the fault data of the server motherboard and to control the backup board management controller to store the fault data in the storage unit.

9. A method for collecting server fault data, characterized in that, include: Collect fault signals from the server motherboard; Based on the fault signal, an interrupt request is generated; The interrupt request is sent to the target processor, so that the target processor, in response to the interrupt request, determines a target baseboard management controller from the baseboard management controller group; wherein the baseboard management controller group includes multiple baseboard management controllers; so that the target processor sends a control command to the switching circuit, so that the switching circuit controls the target baseboard management controller to have access to the memory unit; so that the target processor, in response to the interrupt request, generates a fault data acquisition command; The target processor sends the fault data acquisition instruction to the target baseboard management controller to control the target baseboard management controller to acquire the fault data of the server motherboard and to control the target baseboard management controller to store the fault data in the storage unit.

10. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the steps of the server fault data acquisition method as described in any one of claims 5 to 8, or the steps of the server fault data acquisition method as described in claim 9.

Images