PCB defect recognition method and system fusing attention mechanism and graph neural network

Abstract

This invention provides a method and system for PCB defect identification that integrates an attention mechanism and a graph neural network. The method includes multi-scale feature extraction from PCB images, followed by spatial and channel-selective attention enhancement of the multi-scale defect features. The spatially enhanced features and channel-selective enhanced features are then fused to obtain the final enhanced features. A graph neural network is used to learn features from the PCB structure diagram, resulting in a node graph. The final enhanced features and the node graph are then fused to obtain the fused features. The fused features are then optimized through comparative learning to obtain the optimized features. Based on the optimized features, the defect location and defect category are predicted, and the defect severity is predicted by combining the defect location and circuit function. This invention designs a multi-level attention mechanism that adaptively focuses on regions in the image that may contain defects, suppressing interference from irrelevant backgrounds. The method provided by this invention can effectively identify minute PCB defects, fully utilize prior knowledge of the PCB structure, and possesses strong generalization capabilities.

Description

Technical Field

[0001] This invention relates to the fields of PCB defect detection and image processing technology, and in particular to a PCB defect identification method and system that integrates attention mechanisms and graph neural networks. Background Technology

[0002] Printed Circuit Boards (PCBs), as the core carriers of modern electronic devices, directly affect the reliability and lifespan of the entire electronic product through their manufacturing quality. As electronic products evolve towards miniaturization, high integration, and high reliability, PCB manufacturing processes are becoming increasingly sophisticated, component density is constantly increasing, and line spacing is continuously shrinking. This makes the detection of minute defects on PCBs particularly critical and challenging. Minute defects typically refer to defects smaller than 50 micrometers in size, including micro-open circuits, micro-short circuits, micro-pinholes, micro-copper foil residue, and micro-scratches. Although these defects are tiny, they can lead to serious electrical failures or potential reliability issues.

[0003] Current PCB micro-defect detection technologies mainly include manual visual inspection, automated optical inspection (AOI), and automated X-ray inspection (AXI). Manual visual inspection relies on the operator's experience and judgment, resulting in high subjectivity, low efficiency, and fatigue, making it difficult to meet the high efficiency and high precision requirements of modern PCB manufacturing. While traditional AOI systems achieve automated inspection, they face several challenges when handling micro-defects: First, image resolution limitations lead to indistinct micro-defect features, low signal-to-noise ratio, and difficulty in distinguishing them from the normal background; second, the complex textures, reflections, and color variations on the PCB surface interfere with defect identification; third, micro-defects exhibit diverse shapes and blurred boundaries, making them difficult to describe using simple morphological features; finally, differences in manufacturing processes between different batches of PCBs result in inconsistent defect appearances, increasing the difficulty of inspection.

[0004] Existing PCB defect detection algorithms are mainly divided into template matching-based methods and machine learning-based methods. Template matching-based methods identify potential defects by comparing the PCB image to be detected with a standard template at the pixel level. These methods require extremely high image registration accuracy and are difficult to adapt to normal process fluctuations in PCB manufacturing, easily generating a large number of false alarms. Machine learning-based methods, especially deep learning methods, have made some progress in the field of PCB defect detection, but still have significant shortcomings in the identification of minute defects: First, existing convolutional neural networks are difficult to effectively extract discriminative features of minute defects; second, they lack effective utilization of prior knowledge of PCB structure; third, they are highly dependent on minute defect samples, which are extremely scarce in actual production; and fourth, the model's generalization ability is limited, making it difficult to adapt to the detection needs of different batches and types of PCBs.

[0005] Furthermore, existing methods generally neglect the structural characteristics of PCB circuits and the correlation between defects. A PCB is essentially a complex network structure composed of elements such as conductors, pads, and vias, with clearly defined electrical connections and spatial topological relationships between these elements. The occurrence and impact of minute defects are often closely related to their surrounding circuit structure environment. For example, a tiny scratch of the same shape can have drastically different effects depending on whether it appears on a critical signal line or in a non-functional area. Most existing methods treat PCB images as ordinary two-dimensional images, failing to fully utilize the structural characteristics of PCBs to enhance the detection capability of minute defects.

[0006] Therefore, there is an urgent need to develop a detection method that can effectively identify minute defects in PCBs, make full use of prior knowledge of PCB structure, and has strong generalization ability, so as to meet the urgent needs of modern PCB manufacturing industry for high-precision and high-reliability quality control. Summary of the Invention

[0007] To overcome the problems existing in related technologies, the purpose of this invention is to provide a PCB defect identification method and system that integrates attention mechanism and graph neural network, wherein the method can effectively identify PCB micro-defects, make full use of prior knowledge of PCB structure, and has strong generalization ability.

[0008] A PCB defect identification method integrating attention mechanisms and graph neural networks includes: Acquire PCB images and PCB structure diagrams, and perform multi-scale feature extraction on the PCB images to obtain multi-scale defect features; Spatial attention enhancement is applied to the multi-scale defect features to obtain spatially enhanced features; channel attention enhancement is applied to the multi-scale defect features to obtain channel-selective enhanced features. The spatial enhancement feature and the channel-selective enhancement feature are fused to obtain the final enhancement feature; A graph neural network is used to learn features from the PCB structure diagram to obtain a node diagram; The final enhanced feature and the node graph are fused to obtain the fused feature; The fused features are compared and optimized to obtain optimized features; Based on the optimized features, the defect location and defect category are predicted, and the defect severity is predicted by combining the defect location and circuit function.

[0009] In a preferred embodiment of the present invention, the step of performing spatial attention enhancement on the multi-scale defect features to obtain spatially enhanced features includes: The similarity score between position i and position j on the PCB is calculated using the following formula: ; Among them, s ij W represents the similarity score between positions i and j on the PCB. Q For querying the matrix, W K F is the bond matrix; i F represents the feature vector at position i on the PCB. j The feature vector representing position j on the PCB, where d is the feature dimension; Normalize the similarity scores of positions i and j on the PCB to obtain the attention weight of position i to position j; Based on the attention weights of position i to position j, the spatial augmentation features are calculated using the following formula: ; in, The enhanced feature at position i on the PCB is represented by N, where N represents the total number of positions to be detected on the PCB, and j represents the position number. W represents the attention weight of position i to position j. V Let F represent a value matrix. j The feature vector representing position j on the PCB.

[0010] In a preferred embodiment of the present invention, the step of performing channel attention enhancement on the multi-scale defect features to obtain channel-selective enhanced features includes: Perform global average pooling on the c-th channel feature to obtain the global average pooling result for channel c; The following formula is used to perform nonlinear activation on the global average pooling result of channel c: ; Among them, s cThis represents the attention weight of channel c. W1 represents the sigmoid activation function, W2 represents the first weight matrix of the fully connected layer, and W3 represents the second weight matrix of the fully connected layer. z represents the ReLU activation function. c The result of global average pooling represents the enhanced features of channel c; Multiplying the attention weight of channel c by the enhanced feature of channel c yields the selectively enhanced feature of channel c.

[0011] In a preferred embodiment of the present invention, before performing feature learning on the PCB structure diagram using a graph neural network, the method further includes: Count the component nodes, connection nodes, and wire nodes of the PCB, and form a node set from the component nodes, connection nodes, and wire nodes; Count the spatial proximity edges and electrical connection edges of the PCB, and form an edge set from the spatial proximity edges and electrical connection edges. Set the edge weight according to the edge type of each edge in the edge set, and form an adjacency matrix from all the edge weights; Statistical analysis of the node feature matrix of the PCB; the node feature matrix includes the visual features of the nodes, the spatial location of the nodes, the electrical characteristics of the nodes, and the functional attributes of the nodes; The PCB structure diagram is composed of the node set, edge set, adjacency matrix, and node feature matrix.

[0012] In a preferred embodiment of the present invention, the step of using a graph neural network to perform feature learning on the PCB structure diagram to obtain a node diagram includes: The attention weights between nodes are learned using a graph attention mechanism. Design a graph convolutional network based on the attention weights between nodes; The graph convolutional network is used to perform message passing and aggregation between nodes to update the feature vectors of the nodes in the node set, resulting in an updated node set; the updated node set and the edge set together form a node graph.

[0013] In a preferred embodiment of the present invention, the graph convolutional network designed based on the attention weights between nodes includes: The node feature matrix is ​​updated according to the following formula: ; in, This represents the node feature matrix of node i at the (l+1)th layer. This represents the node feature matrix of the l-th layer of node j. Let r represent the non-linear activation function, r represent the edge type, R represent the set of edge types, and j represent the neighbor node index of node i. This represents the set of neighboring nodes connected to node i via an edge of type r; This represents the normalization constant for node i when the edge type is r. It is a weight matrix associated with edge type r, used to characterize the attention weights between nodes.

[0014] In a preferred embodiment of the present invention, the step of performing comparative learning optimization on the fused features to obtain optimized features includes: The contrastive learning loss function for each fused feature is calculated using the following formula: ; in, Let represent the contrastive learning loss function for the i-th fused feature, where log represents the logarithmic function with base 1, exp represents the exponential function, sim represents the similarity function, and v i Let v represent the positive embedding vector of the i-th fused feature. j This represents the positive embedding vector of the j-th fused feature. This represents the negative embedding vector of the k-th fused feature. The temperature parameter is represented by k, the index of the negative embedding vector is represented by k, and 2N represents the total number of positive and negative embedding vectors. The contrastive learning weights of fused feature i are calculated using the following formula: ; in, This represents the contrastive learning weight of the i-th fused feature. Let i represent the contrastive learning loss function for the i-th fused feature. Let represent the contrastive learning loss function for the j-th fused feature. This represents the contrastive learning weight distribution parameters, and total represents the total number of fused features; The contrastive learning loss function is weighted and summed using the contrastive learning weights to obtain the final contrastive learning loss function. The final contrastive learning loss function is used to optimize the fused features, resulting in optimized features.

[0015] In a preferred embodiment of the present invention, the step of predicting the defect location and defect category based on the optimized features, and predicting the defect severity in conjunction with the defect location and circuit function, includes: The optimized features are input into the region proposal network and the detection head to predict the defect location and defect type: ; Among them, b i Let s represent the coordinates of the i-th detection box. i c represents the confidence score of the i-th detection box.i This represents the defect category of the i-th detection box; M represents the total number of detection boxes; DetectionHead represents the detection head; and RPN represents the Region Proposal Network. Indicates the optimized features; The severity of the defect is calculated using the following formula: ; ; ; Among them, S defect Indicates the severity of the defect. This represents the severity coefficient of the first defect. This represents the severity coefficient of the second defect. S represents the severity coefficient of the third defect; visual S represents the severity score based on the visual features of the defect. location S represents a severity score based on the location of the defect. functional Indicates the severity score based on circuit function; V key I represents the set of key circuit elements. j d represents the importance score of element j. ij This represents the distance between defect i and element j. This represents the distance adjustment coefficient; MLP represents a multilayer perceptron. This represents the characteristic representation of node i after T rounds of message passing.

[0016] In a preferred embodiment of the present invention, the step of performing multi-scale feature extraction on the PCB image to obtain multi-scale defect features includes: Design a multi-scale feature extraction network, which adopts a feature pyramid structure and uses the ResNet-50 architecture for the network backbone; The feature map of the PCB image is updated using the following formula: ; Among them, F l H represents the l-th layer feature map of the PCB image. l Let F represent the nonlinear transformation function of the l-th layer. l-1 This represents the (l-1)th layer feature map of the PCB image; By combining the feature maps of all layers of the PCB image, multi-scale defect features are obtained.

[0017] This invention also provides a PCB defect identification system that integrates attention mechanisms and graph neural networks, including: A multi-scale feature extraction module is used to acquire PCB images and PCB structure diagrams, and to perform multi-scale feature extraction on the PCB images to obtain multi-scale defect features; An attention enhancement module is used to perform spatial attention enhancement on the multi-scale defect features to obtain spatially enhanced features; and to perform channel attention enhancement on the multi-scale defect features to obtain channel-selective enhanced features. An enhanced feature fusion module is used to fuse the spatial enhanced features and the channel-selective enhanced features to obtain the final enhanced features; The feature learning module is used to perform feature learning on the PCB structure diagram using a graph neural network to obtain a node diagram; The feature map and node map fusion module is used to fuse the final enhanced feature and the node map to obtain the fused feature; The contrastive learning optimization module is used to perform contrastive learning optimization on the fused features to obtain optimized features; The defect prediction module is used to predict the defect location and defect category based on the optimized features, and to predict the defect severity by combining the defect location and circuit function.

[0018] The beneficial effects of this invention are as follows: The PCB defect recognition method fused with attention mechanism and graph neural network provided by this invention includes acquiring PCB images and PCB structure diagrams, extracting multi-scale features from the PCB images to obtain multi-scale defect features, which can reflect the deep features of the PCB images. Spatial attention enhancement is applied to the multi-scale defect features to obtain spatially enhanced features; channel attention enhancement is also applied to the multi-scale defect features to obtain channel-selective enhanced features. To enhance the visual representation of minute defects, this invention designs a multi-level attention mechanism that adaptively focuses on regions in the image that may contain defects, suppressing interference from irrelevant backgrounds. The spatially enhanced features and the channel-selective enhanced features are fused to obtain the final enhanced features. A graph neural network is used to learn features from the PCB structure diagram to capture the complex relationships between nodes, resulting in a node graph. The graph neural network can perform feature propagation and aggregation on the PCB structure diagram, thereby perceiving the role and importance of each node in the circuit. The final enhanced features and the node graph are fused to obtain fused features, which contain both image information and node graph context information. The fused features are then optimized through contrastive learning to improve the feature representation, resulting in optimized features. This invention employs contrastive learning to automatically identify and focus on indistinguishable samples, improving the model's sensitivity to minute defects. Based on optimized features, the defect location and category are predicted, and the defect severity is predicted by combining the defect location with circuit function. The method provided by this invention can effectively identify minute defects in PCBs, fully utilize prior knowledge of PCB structure, and possesses strong generalization capabilities. Attached Figure Description

[0019] Figure 1 This is a flowchart of the PCB defect identification method that integrates attention mechanism and graph neural network of the present invention; Figure 2 This is a flowchart of the present invention on using graph neural networks to learn features from PCB structure diagrams; Figure 3 This is a result image showing the detection of open-circuit defects on a PCB using the method provided by this invention; Figure 4 This is a diagram showing the results of detecting via defects on a PCB using the method provided by this invention. Figure 5 This is a result image showing the detection of burr defects on a PCB using the method provided by this invention. Detailed Implementation

[0020] Preferred embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0021] Example 1 like Figure 1 As shown, this embodiment provides a PCB defect identification method that integrates attention mechanisms and graph neural networks, including: S1: Obtain PCB image and PCB structure diagram, and perform multi-scale feature extraction on the PCB image to obtain multi-scale defect features; S2: Perform spatial attention enhancement on the multi-scale defect features to obtain spatially enhanced features; perform channel attention enhancement on the multi-scale defect features to obtain channel-selective enhanced features; S3: The spatial enhancement feature and the channel-selective enhancement feature are fused to obtain the final enhancement feature; S4: Use a graph neural network to learn features from the PCB structure diagram to obtain a node diagram; S5: Merge the final enhanced feature and the node graph to obtain the fused feature; S6: Perform comparative learning optimization on the fused features to obtain optimized features; S7: Predict the defect location and defect category based on the optimized features, and predict the defect severity by combining the defect location and circuit function.

[0022] A PCB image is a visual representation of the surface or interior of a PCB, consistent with its appearance in a real-world scenario. PCB images are RGB images. A PCB structure diagram treats different areas on the PCB as nodes, with spatial or functional connections between related nodes.

[0023] The spatial attention enhancement of the multi-scale defect features to obtain spatially enhanced features includes: The similarity score between position i and position j on the PCB is calculated using the following formula: (1) Among them, s ij W represents the similarity score between positions i and j on the PCB. Q For querying the matrix, W K F is the bond matrix; i F represents the feature vector at position i on the PCB. j The feature vector representing position j on the PCB, where d is the feature dimension; Normalize the similarity scores of positions i and j on the PCB to obtain the attention weight of position i to position j, (W Q F i ) T This represents the transpose of the product of the query matrix and the eigenvector at position i on the PCB.

[0024] Based on the attention weights of position i to position j, the spatial augmentation features are calculated using the following formula: (2) in, The enhanced feature at position i on the PCB is represented by N, where N represents the total number of positions to be detected on the PCB, and j represents the position number. W represents the attention weight of position i to position j. V Represents a value matrix, The feature vector representing position j on the PCB.

[0025] To enhance the visual representation of minute defects, this invention designs a multi-layered spatial attention mechanism. This mechanism adaptively focuses on regions in an image that may contain defects, suppressing interference from irrelevant backgrounds. The spatial attention module employs a self-attention mechanism to calculate the correlation between each location in the feature map and other locations: (3) Where exp represents the exponential function, N represents the total number of spatial locations of the multi-scale defect features, N=H×W, H represents the height of the multi-scale defect features, and W represents the width of the multi-scale defect features; s ijThis represents the similarity score between position i and position j in the PCB image. In this embodiment, cosine similarity is used to calculate s. ij For example, substituting formula (1) into formula (3), we can calculate the attention weight of position i to position j. Then Substituting into formula (2), we obtain the enhanced feature at position i on the PCB. .

[0026] The process of performing channel attention enhancement on the multi-scale defect features to obtain channel-selective enhanced features includes: Perform global average pooling on the c-th channel feature to obtain the global average pooling result for channel c; The following formula is used to perform nonlinear activation on the global average pooling result of channel c: (4) Among them, s c This represents the attention weight of channel c. W1 represents the sigmoid activation function, W2 represents the first weight matrix of the fully connected layer, and W3 represents the second weight matrix of the fully connected layer. z represents the ReLU activation function. c The result represents the global average pooling of the enhanced features of channel c; the first weight matrix is ​​used to complete the linear mapping of the input space, and the second weight matrix is ​​used to enhance the feature expressiveness through multi-layer transformation.

[0027] Multiplying the attention weight of channel c by the enhanced feature of channel c yields the selectively enhanced feature of channel c.

[0028] Based on the spatial dimension attention mechanism, this invention also designs a channel attention mechanism, which is used to enhance feature channels related to defects and suppress irrelevant channels. The Squeeze-and-Excitation (SE) channel attention mechanism includes the following operations: (1) Squeeze: The input features are compressed into channel descriptors with a dimension of C×1×1 (C is the number of channels) through global average pooling, which is used to capture global spatial information. (2) Excitation: Channel weights are generated through two fully connected layers and an activation function (ReLU+Sigmoid) with a dimension of C. (3) Recalibration: The weights obtained by excitation are multiplied with the original features channel by channel to adjust the channel weights. The channel attention module of this invention is based on the SE structure, but improvements have been made for the detection of small defects: (5) (6) in, This indicates the enhancement feature of channel c. This represents the element in the row-th row and column-th column of the enhanced feature of channel c, where . represents a multiplication operation. This represents the selective enhancement feature of channel c. c = 1, 2, 3. When c = 1, it represents the R channel (red channel); when c = 2, it represents the G channel (green channel); when c = 3, it represents the B channel (blue channel). For each channel, use formulas (1)-(3) to update the features of all PCB locations in each channel. For example, for the R channel of the PCB image, use formulas (1)-(3) to calculate the enhancement features of each location on the PCB in the R channel. Then use formula (5) to calculate the global average pooling result of the enhancement features in the R channel to obtain z1. Substitute z1 into formula (4) to calculate s1. Finally, multiply s1 by... ,get This refers to the selective enhancement feature of the R channel. and These are two different representations. The former emphasizes the channel number, using row and column numbers to characterize the center coordinates of the local location of the enhanced feature of channel c. The latter directly refers to the enhanced feature at position i on the PCB, with position i corresponding to the center coordinates (row, col).

[0029] To fully leverage the complementary advantages of spatial attention and channel attention, this invention designs an adaptive attention fusion strategy. The weights α of the two attention mechanisms are determined through learning, and spatial enhancement features and channel-selective enhancement features are fused using the following formula: (7) Among them, F enhanced F represents the final enhanced feature. spatial F represents spatial augmentation features. channel F represents the channel-selective enhancement feature. channel for , or , This indicates the selective enhancement feature of the red channel. This indicates the selective enhancement feature of the green channel. This represents the selective enhancement feature of the blue channel. α represents the enhancement feature fusion coefficient, which is normalized to the [0,1] interval using the Sigmoid function. Finally, the enhancement feature, spatial enhancement feature, and channel-selective enhancement feature are all represented by a single feature map.

[0030] Extensive comparative experiments conducted on standard PCB defect datasets and self-built micro-defect datasets demonstrate that the method of this invention has significant advantages in micro-defect detection. The detection results for micro-defects are shown in Table 1; the method of this invention achieves excellent detection performance for different types of micro-defects.

[0031] Table 1. Comparison of detection rates for different types of minor defects. ; Especially for extremely small defects smaller than 30 micrometers, the detection rate of the method of this invention reaches 85.3%, which is 32.6% higher than the traditional method and 18.9% higher than the general deep learning method. As shown in Table 1, for small open-circuit defects, the detection rate of the method provided by this invention is 92.7%, significantly higher than the 68.5% of the traditional method and 79.2% of the deep learning method. In the detection of small defects in complex backgrounds, the F1 score of the method of this invention reaches 0.912, significantly better than the comparison methods. The F1 score is a core metric used in statistics and machine learning to evaluate the performance of binary classification models, calculated as the harmonic mean of precision and recall. Figure 3 As shown, the method provided by this invention detected five open-circuit defects on the first PCB. Figure 3 The red boxes in the diagram indicate the location of open-circuit defects, `open_circuit` represents the open-circuit defect, and the decimal indicates the confidence level of the open-circuit defect detected in the corresponding red box. Open-circuit defects can cause circuit signal interruption or circuit malfunction, and may be caused by manufacturing process defects such as over-etching or drilling misalignment. Figure 4 As shown, the method provided by this invention detected five via defects on the second PCB. Figure 4 The blue boxes in the diagram indicate the location of via defects, "missing_hole" represents the defect, and the decimal indicates the confidence level of the via defect detected by the corresponding blue box. Visible defects can cause electrical connection failures or prevent component installation. These defects may be caused by PCB design errors, such as slots not being placed on the drill layer, or manufacturing process issues, such as drill wear or excessive drill drop speed. Figure 5 As shown, the method provided by this invention detected five burr defects on the third PCB. Figure 5 The purple boxes in the diagram indicate the location of burr defects, spur indicates the burr defect itself, and the decimal indicates the confidence level of the burr defect detected in the corresponding purple box. Burr defects can cause short circuits or poor contact in circuits, and may be caused by processing equipment malfunctions or incomplete removal of residues from the copper foil surface.

[0032] Multi-scale attention mechanisms significantly improved the visual representation of minute defects, validating the effectiveness of attention enhancement strategies. Detection results for different attention strategies are shown in Table 2. Multi-scale attention enhancement adaptively enhances the visual feature representation of minute defects by designing multi-level spatial and channel attention mechanisms, improving the contrast between defects and the background, and solving the key problems of indistinct features and susceptibility to background interference in minute defects. Employing multi-scale attention enhancement can capture defect features at different scales and levels of abstraction, significantly improving the detectability of minute defects.

[0033] Table 2. Detection results for different attention strategies ; As shown in Table 2, the accuracy, recall, and F1 score of the multi-scale attention method of this invention are superior to other attention strategies. Visualization analysis shows that the multi-scale attention mechanism can effectively highlight tiny defect regions, suppress background interference, and make defect features more obvious. Attention heatmaps show that the method of this invention can accurately locate tiny defects with a size of only 20 micrometers, while traditional methods are almost unable to detect them in this case.

[0034] This invention not only enables high-precision detection of minute defects on PCBs, but also automatically assesses their severity based on the circuit environment in which they occur, providing comprehensive and intelligent technical support for PCB quality control. The method has strong generalization and adaptability, capable of meeting the inspection needs of different batches and types of PCBs, thus providing a powerful guarantee for quality improvement in the electronics manufacturing industry.

[0035] The PCB defect recognition method fused with attention mechanism and graph neural network provided in this embodiment includes acquiring PCB images and PCB structure diagrams, extracting multi-scale features from the PCB images to obtain multi-scale defect features, which can reflect the deep features of the PCB images. Spatial attention enhancement is applied to the multi-scale defect features to obtain spatially enhanced features; channel attention enhancement is also applied to the multi-scale defect features to obtain channel-selective enhanced features. To enhance the visual representation of minute defects, this invention designs a multi-level attention mechanism that can adaptively focus on regions in the image that may contain defects, suppressing interference from irrelevant backgrounds. The spatially enhanced features and the channel-selective enhanced features are fused to obtain the final enhanced features. A graph neural network is used to learn features from the PCB structure diagram to capture the complex relationships between nodes, resulting in a node graph. The graph neural network can perform feature propagation and aggregation on the PCB structure diagram, thereby perceiving the role and importance of each node in the circuit. The final enhanced features and the node graph are fused to obtain fused features, which contain both image information and node graph context information. The fused features are then optimized through contrastive learning to improve the feature representation, resulting in optimized features. This invention employs contrastive learning to automatically identify and focus on indistinguishable samples, improving the model's sensitivity to minute defects. Based on optimized features, the defect location and category are predicted, and the defect severity is predicted by combining the defect location with circuit function. The method provided by this invention can effectively identify minute defects in PCBs, fully utilize prior knowledge of PCB structure, and possesses strong generalization capabilities.

[0036] Example 2 like Figure 1 As shown, this embodiment provides a PCB defect identification method that integrates attention mechanisms and graph neural networks. This embodiment describes the differences from Embodiment 1, based on Embodiment 1. The method includes: S1: Obtain PCB image and PCB structure diagram, and perform multi-scale feature extraction on the PCB image to obtain multi-scale defect features; S2: Perform spatial attention enhancement on the multi-scale defect features to obtain spatially enhanced features; perform channel attention enhancement on the multi-scale defect features to obtain channel-selective enhanced features; S3: The spatial enhancement feature and the channel-selective enhancement feature are fused to obtain the final enhancement feature; S4: Use a graph neural network to learn features from the PCB structure diagram to obtain a node diagram; S5: Merge the final enhanced feature and the node graph to obtain the fused feature; S6: Perform comparative learning optimization on the fused features to obtain optimized features; S7: Predict the defect location and defect category based on the optimized features, and predict the defect severity by combining the defect location and circuit function.

[0037] Before employing a graph neural network to perform feature learning on the PCB structure diagram, the method further includes: S31': Count the component nodes, connection nodes, and wire nodes of the PCB, and form a node set from the component nodes, connection nodes, and wire nodes; S32': Count the spatial proximity edges and electrical connection edges of the PCB, and form an edge set from the spatial proximity edges and electrical connection edges; S33': Set the edge weight according to the edge type of each edge in the edge set, and form an adjacency matrix from all the edge weights; S34': Statistical analysis of the node feature matrix of the PCB; the node feature matrix includes the visual features of the nodes, the spatial location of the nodes, the electrical characteristics of the nodes, and the functional attributes of the nodes; S35': Combine the node set, edge set, adjacency matrix, and node feature matrix to form a PCB structure diagram.

[0038] This invention models the PCB as a heterogeneous graph G, which refers to a graph structure containing multiple node types and / or edge types. G=(V,E,A,X), where V represents the set of nodes, E represents the set of edges, A represents the adjacency matrix, and X represents the node feature matrix. The node set V contains three types of nodes: component nodes such as ICs, resistors, and capacitors; connection nodes such as pads and vias; and wire nodes. The edge set E contains two types of edges: electrical connection edges and spatial proximity edges. Steps S31'-S35' are performed before step S1, that is, after constructing the PCB structure diagram using steps S31'-S35', the PCB image and the PCB structure diagram are obtained. The PCB image reflects the visual characteristics of the PCB, and the PCB structure diagram reflects the relationships between different structures on the PCB.

[0039] Node feature X contains the following information: (8) Among them, X visual Representing the visual features of nodes, extracting X from the PCB image. visual X position X represents the spatial location of a node. electrical X represents the electrical characteristics of a node, such as impedance and capacitance. functional The functional attributes of a node are represented, such as signal type and node importance, and all node features are combined into a node feature matrix.

[0040] Regarding project feasibility, X electricalThis data originates from design files and / or simulation libraries, including netlists and parameter libraries. If online detection fails to obtain this data, it can be regressed to using only X. visual X position With topologically derived X functional For example, the system can still function with usernames and key area labels, but its sensitivity to electrical properties will be reduced when assessing the severity of defects.

[0041] The weight of an edge is calculated using different methods depending on the edge type: (9) Among them, A ij This represents the element in the i-th row and j-th column of the adjacency matrix, i.e., the weight of the edge connecting node i and node j. Indicates the basic weight of the electrical connection edge. Represents the basic weight of spatially adjacent edges. (i,j) represents the edge connecting node i and node j, E electrical E represents the electrical connection side. spatial Denotes the spatially adjacent edge, d ij This represents the distance between node i and node j. This represents the distance attenuation parameter. This indicates a belonging relationship.

[0042] like Figure 2 As shown, the step of using a graph neural network to perform feature learning on the PCB structure diagram to obtain a node graph includes: S41: Employ graph attention mechanism to learn attention weights between nodes; S42: Design of graph convolutional networks based on attention weights between nodes; S43: The graph convolutional network is used to perform message passing and aggregation between nodes to update the feature vectors of the nodes in the node set, resulting in an updated node set; the updated node set and the edge set together form a node graph.

[0043] To accurately align PCB design data, such as Gerber files and CAD data, with actual PCB images, this embodiment designs a precise registration algorithm based on feature point matching. The algorithm first extracts stable feature points, such as via centers and IC corner points, from the design data and PCB images. Then, it estimates the transformation matrix using the RANSAC algorithm to achieve precise alignment between the design data and the image. This paper employs affine registration or homography registration to improve alignment accuracy. (10) Among them, a 11 This represents the parameter that controls scaling and rotation in the x-direction, a. 12 The parameter a represents the control of shear in the y-direction.21 This represents the parameter controlling shearing in the x-direction, a 22 This represents the parameter that controls scaling and rotation in the y-direction, a 13 a represents the translation parameter in the x-direction. 23 This represents the translation parameter in the y-direction. x represents the x-coordinate of a point in the PCB design data, y represents the y-coordinate of a point in the PCB design data, x' represents the x-coordinate of a point in the PCB structure diagram, and y' represents the y-coordinate of a point in the PCB structure diagram. Registration parameters are estimated using RANSAC to suppress erroneous matches, and the transformation matrix is ​​solved by minimizing the distance error between corresponding point pairs.

[0044] Circuit Functional Area Division: This invention divides the PCB into different functional areas based on its circuit functions, such as power supply areas, signal areas, and ground areas, and assigns different importance weights to each area. This functional area division provides an important basis for subsequent defect severity assessment. (11) Among them, I region The score indicates the importance of the region. f represents the weight of the num1-th functional factor. num1 This represents the score of the num1th functional factor, where K is the total number of functional factors.

[0045] This invention designs a Graph Convolutional Network (GCN) suitable for heterogeneous PCB diagrams. This network can perform feature propagation and aggregation on the graph structure, enabling each node to perceive its role and importance in the circuit. Graph Neural Network inference is based on Graph Convolutional Network and Graph Attention mechanism to achieve deep learning of PCB structure diagrams. This module can not only detect single defects, but more importantly, it can understand the location and impact of defects in the entire circuit, realizing intelligent defect assessment based on circuit function.

[0046] To handle different types of nodes and edges in heterogeneous PCB graphs, this invention improves upon standard GCN by introducing type-aware graph convolution operations: (12) in, This represents the node feature matrix of node i at the (l+1)th layer. This represents the node feature matrix of the l-th layer of node j. This invention represents a nonlinear activation function, specifically the nonlinear activation function described in this invention. ReLU or Sigmoid functions are non-linear activation functions used to enhance the non-linear expressiveness of the model. r represents the edge type, and R represents the set of edge types. This indicates a membership relationship; j represents the index of a neighboring node of node i. This represents the set of neighboring nodes connected to node i via an edge of type r; This represents the normalization constant for node i when the edge type is r. It is a weight matrix related to the edge type r. The graph convolutional network is based on the type-aware graph convolution operation described above, which is used to characterize the attention weights between nodes. ,or .

[0047] To better capture the important relationships between nodes, this invention introduces a graph attention mechanism (GAT), which can adaptively learn the attention weights between nodes: (13) in, Let represent the attention weight of node j towards node i, 'a' represent the attention vector, 'W' represent the weight matrix, 'hi' represent the feature vector of node i, and 'hj' represent the feature vector of node j. || represents the feature concatenation operation, and 'Ni' represent the set of neighbors of node i. It is a component element of the weight matrix, located in the i-th row and j-th column of the weight matrix, a T The matrix represents the transpose of the attention vector. Formula 13 uses the matrix transpose of the attention vector before it is used in the calculation.

[0048] To enhance the expressive power of the model, this invention employs a multi-head attention mechanism: (14) Where Concat represents the attention head concatenation operation, and num2 represents the total number of attention heads. W represents the attention weight of the k-th attention head. k This represents the weight matrix of the k-th attention head. This represents the feature vector of node i after the attention heads are concatenated.

[0049] This invention implements information exchange and feature aggregation between nodes based on the Message Passing Neural Network (MPNN) framework. The message passing process includes message functions and update functions: (15) (16) in, M represents the message received by node i at step t+1. t This represents a message passing function. This represents the feature vector of node i at step t. Let e ​​represent the eigenvector of node j at step t. ijU represents the edge characteristics between node i and node j. t Indicates the update function, Let i represent the feature vector of node i at step t+1. The message passing function and update function are based on type-aware graph convolution operations.

[0050] The formulas for the message function and the update function are as follows: (17) (18) Among them, A ij This represents the element in the i-th row and j-th column of the adjacency matrix. MLP stands for Multilayer Perceptron, and GRU stands for Gated Recurrent Unit. The Gated Recurrent Unit is used to update the node state.

[0051] Graph attention is an operation in the graph convolution process. A graph convolutional network performs one or more graph convolutions. The role of graph convolution is to aggregate and pass features between nodes connected by edges. It can be seen as each node having a feature vector, which is passed to neighboring nodes through edges to update the feature vector of each node. That is, the feature vector of the node is updated by means of message passing and aggregation.

[0052] Graph neural networks (GNNs) are used for deep feature learning and inference. PCB structure diagram modeling and GNN inference significantly improve the contextual understanding of defect detection, especially for minor defects in critical circuit areas, where the improvement in detection accuracy is more pronounced. As shown in Table 3, graph structure modeling has a significant effect on understanding the circuit environment of defects and assessing the severity of defects.

[0053] Table 3 Performance Improvement Table for Defect Detection in Different Circuit Regions ; This embodiment combines PCB design data, such as Gerber files or CAD data, to construct a heterogeneous graph, or PCB structure diagram, reflecting the PCB circuit topology. A graph neural network is then used to learn features from this PCB structure diagram, capturing the complex relationships between nodes. By mapping the input sequence to multiple subspaces, each attention head can independently learn different feature associations, thus comprehensively modeling the complex relationships between nodes. A message passing mechanism, through message transmission between nodes, allows the target node to aggregate multiple messages received from adjacent nodes using an aggregation function. This dynamically integrates local topology information, effectively capturing the complex dependencies between nodes. Example 3 like Figure 1 As shown, this embodiment provides a PCB defect identification method that integrates attention mechanisms and graph neural networks. This embodiment describes the differences from Embodiment 1, based on Embodiment 1. The method includes: S1: Obtain PCB image and PCB structure diagram, and perform multi-scale feature extraction on the PCB image to obtain multi-scale defect features; S2: Perform spatial attention enhancement on the multi-scale defect features to obtain spatially enhanced features; perform channel attention enhancement on the multi-scale defect features to obtain channel-selective enhanced features; S3: The spatial enhancement feature and the channel-selective enhancement feature are fused to obtain the final enhancement feature; S4: Use a graph neural network to learn features from the PCB structure diagram to obtain a node diagram; S5: Merge the final enhanced feature and the node graph to obtain the fused feature; S6: Perform comparative learning optimization on the fused features to obtain optimized features; S7: Predict the defect location and defect category based on the optimized features, and predict the defect severity by combining the defect location and circuit function.

[0054] The step of performing comparative learning optimization on the fused features to obtain optimized features includes: The contrastive learning loss function for each fused feature is calculated using the following formula: (19) in, Let represent the contrastive learning loss function for the i-th fused feature, where log represents the logarithmic function with the natural constant as the base, exp represents the exponential function, and sim represents the similarity function. In this embodiment, sim is taken as the cosine similarity function. i Let v represent the positive embedding vector of the i-th fused feature. j This represents the positive embedding vector of the j-th fused feature. This represents the negative embedding vector of the k-th fused feature. The parameter represents the temperature parameter, k represents the index of the negative embedding vector, and 2N represents the total number of positive and negative embedding vectors. Positive embedding vectors correspond to positive sample pairs, and negative embedding vectors correspond to negative sample pairs. Positive sample pairs are different augmented views of the same instance, such as the same image after rotation and cropping. Negative sample pairs are samples from different instances, such as different images or text. The contrastive learning weights of fused feature i are calculated using the following formula: (20) in, This represents the contrastive learning weight of the i-th fused feature. Let i represent the contrastive learning loss function for the i-th fused feature. Let represent the contrastive learning loss function for the j-th fused feature. This represents the contrastive learning weight distribution parameters. Used to control the smoothness of the weight distribution, total represents the total number of fused features; The contrastive learning loss function is weighted and summed using the contrastive learning weights to obtain the final contrastive learning loss function. The final contrastive learning loss function is used to optimize the fused features, resulting in optimized features.

[0055] To learn more discriminative defect feature representations, this embodiment designs a feature optimization framework based on contrastive learning. This framework constructs positive and negative sample pairs, making the feature representations of similar samples more similar and the feature representations of different samples more different.

[0056] This embodiment takes the cosine similarity function as the example of the similarity function sim, with the denominator being... This approach avoids self-comparison and eliminates the need for an additional indicator function. To address the scarcity of minute defect samples, this invention designs a hard sample mining strategy. This strategy automatically identifies and focuses on samples that are difficult to distinguish, effectively solving the problem of scarce minute defect samples and improving the model's sensitivity and recognition ability for minute defects.

[0057] Multiple contrastive learning loss functions are fused using contrastive learning weights: ;(twenty one) Among them, L weighted num3 represents the final contrastive learning loss function, and num3 represents the total number of contrastive learning loss functions. To address the scarcity of samples with minor defects, this invention designs a hard sample mining strategy. This strategy can automatically identify and focus on samples that are difficult to distinguish, improving the model's sensitivity to minor defects.

[0058] To further improve the detection capability of minute defects, this invention designs a feature enhancement strategy, which generates more diverse training samples through feature mixing and feature perturbation: ;(twenty two) in, This represents the i-th enhanced feature vector. Let represent the eigenvector after adding perturbation to the i-th feature vector. This represents the j-th feature vector after adding perturbation. Represents the mixing coefficient. .

[0059] ;(twenty three) in, This represents the i-th eigenvector. Indicates the intensity of the disturbance. This represents a noise vector sampled from a standard normal distribution.

[0060] The step of predicting the defect location and defect category based on the optimized features, and predicting the defect severity by combining the defect location and circuit function, includes: The optimized features are input into the region proposal network and the detection head to predict the defect location and defect type: ;(twenty four) Among them, b i Let s represent the coordinates of the i-th detection box. i c represents the confidence score of the i-th detection box. i This represents the defect category of the i-th detection box; M represents the total number of detection boxes; DetectionHead represents the detection head; and RPN represents the Region Proposal Network. This represents the optimized features; RPN is used to generate candidate regions on the feature map. Each candidate region is input into the corresponding detection head, which classifies the input candidate regions and performs bounding box regression. The detection head outputs the target category and bounding box.

[0061] To improve the detection accuracy of minute defects, this invention introduces a Feature Pyramid Network (FPN) to enhance multi-scale feature representation and designs a weighted loss for small targets: (25) (26) in, Based on the defect area A i Sample weights, It is a coefficient that controls the decay rate, y i,c For the one-hot label of category c, p i,c For y i,c The corresponding predicted probability, in this invention, exp represents the exponential function, log is the logarithmic function with the natural constant as the base, N pos Indicates the total number of tags. L cls L represents the category prediction loss function. box Represents the bounding box loss function. L represents the coefficients of the bounding box loss function. detection The small target weighted loss function is used to train the defect detection network, which includes a region proposal network and a detection head.

[0062] The severity of the defect is calculated using the following formula: (27) (28) (29) Among them, S defect Indicates the severity of the defect. This represents the severity coefficient of the first defect. This represents the severity coefficient of the second defect. S represents the severity coefficient of the third defect; visual S represents the severity score based on the visual features of the defect. location S represents a severity score based on the location of the defect. functional Indicates the severity score based on circuit function; V key I represents the set of key circuit elements. j I represents the importance score of element j. j Derived from functional area weights, username priorities, or learned information. ij This represents the distance between defect i and element j. This represents the distance adjustment coefficient; MLP represents a multilayer perceptron. This represents the characteristic representation of node i after T rounds of message passing. This invention combines the visual characteristics, location, and circuit function of defects to comprehensively evaluate the severity of PCB defects.

[0063] The contrastive learning optimization strategy significantly improved the model's sensitivity and recognition ability for minor defects, especially when the sample size was scarce. By adjusting the number of training samples, the detection accuracy of minor defects by the standard training method and the contrastive learning method was compared. The results are shown in Table 4.

[0064] Table 4. Results of Minor Defect Detection with Different Numbers of Training Samples ; The hard sample mining strategy further improved model performance, especially for minute defects that are difficult to distinguish. Experiments show that after adopting hard sample mining, the model's detection accuracy for the most challenging top 20% of samples improved by 15.3%.

[0065] The step of performing multi-scale feature extraction on the PCB image to obtain multi-scale defect features includes: Design a multi-scale feature extraction network, which adopts a feature pyramid structure and uses the ResNet-50 architecture for the network backbone; The feature map of the PCB image is updated using the following formula: (30) Among them, F l H represents the l-th layer feature map of the PCB image. l H represents the nonlinear transformation function of the l-th layer.l Including convolution, batch normalization, and activation operations, F l-1 This represents the (l-1)th layer feature map of the PCB image; By combining the feature maps of all layers of the PCB image, multi-scale defect features are obtained.

[0066] To more effectively capture defect features at different scales, the network in this embodiment is designed with a Feature Pyramid Module (FPM), which fuses features from different levels through top-down paths and lateral connections. (31) Among them, P l P represents the feature map of the l-th layer in the feature pyramid. l+1 This represents the feature map of the (l+1)th layer in the feature pyramid, Conv 1×1 represents a 1×1 convolution operation, and Upsample represents an upsampling operation.

[0067] The method provided by this invention achieves a detection speed of 12 square centimeters per second, measured in PCB area, meeting the requirements for online inspection. The detection rate of minute defects has increased from 68.5% to 91.2% compared to the original system, while the false alarm rate has decreased from 7.8% to 2.3%. Adaptability tests of this method on different types of PCBs and under different production environments demonstrate its good generalization ability and robustness. For new product types, only 50 samples are needed to achieve a detection accuracy of over 88%. Under different lighting conditions, the fluctuation in detection performance does not exceed 3%. Long-term stability testing over three months of continuous operation shows that the system performance remains stable, with detection accuracy attenuation not exceeding 1.5%.

[0068] The final enhanced features and node graph are fused using a gated fusion method: (32) Among them, f fuse As a feature of fusion, The fusion coefficient is... Data-driven learning is used to control the ratio of images to graph context. For the final enhanced features, f graph Graph context features are high-dimensional dynamic representations generated by graph neural networks by combining semantic context and relational environment.

[0069] To address the issue of indistinct features of minute defects in PCBs and their susceptibility to background interference, this invention designs a multi-scale feature extraction network (MS-FEN). This network employs an improved feature pyramid structure, enabling it to capture defect features at different scales and levels of abstraction. The network backbone uses the ResNet-50 architecture, but two key improvements have been made to the standard structure: first, depthwise separable convolutional layers have been added to reduce the number of parameters while maintaining feature extraction capabilities; second, a dense connection mechanism has been introduced to enhance feature propagation and gradient flow.

[0070] Example 4 This embodiment provides a PCB defect identification system that integrates attention mechanisms and graph neural networks, including: A multi-scale feature extraction module is used to acquire PCB images and PCB structure diagrams, and to perform multi-scale feature extraction on the PCB images to obtain multi-scale defect features; An attention enhancement module is used to perform spatial attention enhancement on the multi-scale defect features to obtain spatially enhanced features; and to perform channel attention enhancement on the multi-scale defect features to obtain channel-selective enhanced features. An enhanced feature fusion module is used to fuse the spatial enhanced features and the channel-selective enhanced features to obtain the final enhanced features; The feature learning module is used to perform feature learning on the PCB structure diagram using a graph neural network to obtain a node diagram; The feature map and node map fusion module is used to fuse the final enhanced feature and the node map to obtain the fused feature; The contrastive learning optimization module is used to perform contrastive learning optimization on the fused features to obtain optimized features; The defect prediction module is used to predict the defect location and defect category based on the optimized features, and to predict the defect severity by combining the defect location and circuit function.

[0071] The PCB defect identification system that combines attention mechanism and graph neural network in this embodiment is used to implement the PCB defect identification method that combines attention mechanism and graph neural network in any one of the embodiments 1-3.

[0072] This embodiment also provides a computer device, which may be a server. The computer device includes a processor, memory, a network interface, and a database connected via a system bus. The processor in this computer design provides computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface of the computer device is used for communication with external terminals via a network connection.

[0073] This embodiment also provides a computer-readable storage medium storing a computer program thereon. When the computer program is executed by a processor, it implements a PCB defect identification method that integrates an attention mechanism and a graph neural network. It is understood that the computer-readable storage medium in this embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0074] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, apparatus, article, or method. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, apparatus, article, or method that includes that element.

[0075] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made based on the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A PCB defect identification method integrating attention mechanism and graph neural network, characterized in that, include: Acquire PCB images and PCB structure diagrams, and perform multi-scale feature extraction on the PCB images to obtain multi-scale defect features; Spatial attention enhancement is applied to the multi-scale defect features to obtain spatially enhanced features; Channel attention enhancement is applied to the multi-scale defect features to obtain channel selective enhancement features; The spatial enhancement feature and the channel-selective enhancement feature are fused to obtain the final enhancement feature; A graph neural network is used to learn features from the PCB structure diagram to obtain a node diagram; The final enhanced feature and the node graph are fused to obtain the fused feature; The fused features are compared and optimized to obtain optimized features; Based on the optimized features, the defect location and defect category are predicted, and the defect severity is predicted by combining the defect location and circuit function.

2. The PCB defect identification method integrating attention mechanism and graph neural network according to claim 1, characterized in that, The spatial attention enhancement of the multi-scale defect features to obtain spatially enhanced features includes: The similarity score between position i and position j on the PCB is calculated using the following formula: ； Among them, s ij W represents the similarity score between positions i and j on the PCB. Q For querying the matrix, W K F is the bond matrix; i F represents the feature vector at position i on the PCB. j The feature vector representing position j on the PCB, where d is the feature dimension; Normalize the similarity scores of positions i and j on the PCB to obtain the attention weight of position i to position j; Based on the attention weights of position i to position j, the spatial augmentation features are calculated using the following formula: ； in, The enhanced feature at position i on the PCB is represented by N, where N represents the total number of positions to be detected on the PCB, and j represents the position number. W represents the attention weight of position i to position j. V Let F represent a value matrix. j The feature vector representing position j on the PCB.

3. The PCB defect identification method integrating attention mechanism and graph neural network according to claim 1, characterized in that, The process of performing channel attention enhancement on the multi-scale defect features to obtain channel-selective enhanced features includes: Perform global average pooling on the c-th channel feature to obtain the global average pooling result for channel c; The following formula is used to perform nonlinear activation on the global average pooling result of channel c: ； Among them, s c This represents the attention weight of channel c. W1 represents the sigmoid activation function, W2 represents the first weight matrix of the fully connected layer, and W3 represents the second weight matrix of the fully connected layer. z represents the ReLU activation function. c The result of global average pooling represents the enhanced features of channel c; Multiplying the attention weight of channel c by the enhanced feature of channel c yields the selectively enhanced feature of channel c.

4. The PCB defect identification method integrating attention mechanism and graph neural network according to claim 1, characterized in that, Before employing a graph neural network to perform feature learning on the PCB structure diagram, the method further includes: Count the component nodes, connection nodes, and wire nodes of the PCB, and form a node set from the component nodes, connection nodes, and wire nodes; Count the spatial proximity edges and electrical connection edges of the PCB, and form an edge set from the spatial proximity edges and electrical connection edges. Set the edge weight according to the edge type of each edge in the edge set, and form an adjacency matrix from all the edge weights; Statistical analysis of the node feature matrix of the PCB; the node feature matrix includes the visual features of the nodes, the spatial location of the nodes, the electrical characteristics of the nodes, and the functional attributes of the nodes; The PCB structure diagram is composed of the node set, edge set, adjacency matrix, and node feature matrix.

5. The PCB defect identification method integrating attention mechanism and graph neural network according to claim 4, characterized in that, The step of using a graph neural network to learn features from the PCB structure diagram to obtain a node graph includes: The attention weights between nodes are learned using a graph attention mechanism. Design a graph convolutional network based on the attention weights between nodes; The graph convolutional network is used to perform message passing and aggregation between nodes to update the feature vectors of the nodes in the node set, resulting in an updated node set; the updated node set and the edge set together form a node graph.

6. The PCB defect identification method integrating attention mechanism and graph neural network according to claim 5, characterized in that, The graph convolutional network designed based on the attention weights between nodes includes: The node feature matrix is ​​updated according to the following formula: ； in, This represents the node feature matrix of node i at the (l+1)th layer. This represents the node feature matrix of the l-th layer of node j. Let r represent the non-linear activation function, r represent the edge type, R represent the set of edge types, and j represent the neighbor node index of node i. This represents the set of neighboring nodes connected to node i via an edge of type r; This represents the normalization constant for node i when the edge type is r. It is a weight matrix associated with edge type r, used to characterize the attention weights between nodes.

7. The PCB defect identification method integrating attention mechanism and graph neural network according to claim 1, characterized in that, The step of performing comparative learning optimization on the fused features to obtain optimized features includes: The contrastive learning loss function for each fused feature is calculated using the following formula: ； in, Let represent the contrastive learning loss function for the i-th fused feature, where log represents the logarithmic function with base 1, exp represents the exponential function, sim represents the similarity function, and v i Let v represent the positive embedding vector of the i-th fused feature. j This represents the positive embedding vector of the j-th fused feature. This represents the negative embedding vector of the k-th fused feature. The temperature parameter is represented by k, the index of the negative embedding vector is represented by k, and 2N represents the total number of positive and negative embedding vectors. The contrastive learning weights of fused feature i are calculated using the following formula: ； in, This represents the contrastive learning weight of the i-th fused feature. Let i represent the contrastive learning loss function for the i-th fused feature. Let represent the contrastive learning loss function for the j-th fused feature. This represents the contrastive learning weight distribution parameters, and total represents the total number of fused features; The contrastive learning loss function is weighted and summed using the contrastive learning weights to obtain the final contrastive learning loss function. The final contrastive learning loss function is used to optimize the fused features, resulting in optimized features.

8. The PCB defect identification method integrating attention mechanism and graph neural network according to claim 1, characterized in that, The step of predicting the defect location and defect category based on the optimized features, and predicting the defect severity by combining the defect location and circuit function, includes: The optimized features are input into the region proposal network and the detection head to predict the defect location and defect type: ； Among them, b i Let s represent the coordinates of the i-th detection box. i c represents the confidence score of the i-th detection box. i This represents the defect category of the i-th detection box; M represents the total number of detection boxes; DetectionHead represents the detection head; and RPN represents the Region Proposal Network. Indicates the optimized features; The severity of the defect is calculated using the following formula: ； ； ； Among them, S defect Indicates the severity of the defect. This represents the severity coefficient of the first defect. This represents the severity coefficient of the second defect. S represents the severity coefficient of the third defect; visual S represents the severity score based on the visual features of the defect. location S represents a severity score based on the location of the defect. functional Indicates the severity score based on circuit function; V key I represents the set of key circuit elements. j d represents the importance score of element j. ij This represents the distance between defect i and element j. This represents the distance adjustment coefficient; MLP represents a multilayer perceptron. This represents the characteristic representation of node i after T rounds of message passing.

9. The PCB defect identification method integrating attention mechanism and graph neural network according to claim 1, characterized in that, The step of performing multi-scale feature extraction on the PCB image to obtain multi-scale defect features includes: Design a multi-scale feature extraction network, which adopts a feature pyramid structure and uses the ResNet-50 architecture for the network backbone; The feature map of the PCB image is updated using the following formula: ； Among them, F l H represents the l-th layer feature map of the PCB image. l Let F represent the nonlinear transformation function of the l-th layer. l-1 This represents the (l-1)th layer feature map of the PCB image; By combining the feature maps of all layers of the PCB image, multi-scale defect features are obtained.

10. A PCB defect identification system integrating attention mechanism and graph neural network, characterized in that, include: A multi-scale feature extraction module is used to acquire PCB images and PCB structure diagrams, and to perform multi-scale feature extraction on the PCB images to obtain multi-scale defect features; An attention enhancement module is used to perform spatial attention enhancement on the multi-scale defect features to obtain spatially enhanced features; Channel attention enhancement is applied to the multi-scale defect features to obtain channel selective enhancement features; An enhanced feature fusion module is used to fuse the spatial enhanced features and the channel-selective enhanced features to obtain the final enhanced features; The feature learning module is used to perform feature learning on the PCB structure diagram using a graph neural network to obtain a node diagram; The feature map and node map fusion module is used to fuse the final enhanced feature and the node map to obtain the fused feature; The contrastive learning optimization module is used to perform contrastive learning optimization on the fused features to obtain optimized features; The defect prediction module is used to predict the defect location and defect category based on the optimized features, and to predict the defect severity by combining the defect location and circuit function.

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