Wafer nanotopography extraction method, system, computing device, and storage medium

Abstract

This disclosure provides a method, system, computing device, and storage medium for extracting wafer nanomorphology. The method involves acquiring a height image of the wafer surface; obtaining the gradient distribution of the wafer surface based on the height image and generating a corresponding initial gradient image; smoothing the initial gradient image using a preset filter to obtain a filtered gradient image; wherein the filter is configured to reduce its filtering window size from a first size to a second size as it moves from the center of a preset effective region of the wafer in the initial gradient image towards the edge; and finally, reconstructing a nanomorphology map of the wafer surface based on the filtered gradient image. The filter of this disclosure effectively suppresses edge truncation effects, ensuring the realism and accuracy of the edge morphology, thereby improving the accuracy of the final reconstructed nanomorphology map.

Description

Technical Field

[0001] This disclosure relates to the field of silicon wafer inspection technology, and in particular to a method, system, computing device and storage medium for extracting wafer nanomorphology. Background Technology

[0002] In semiconductor manufacturing processes, the nanoscale morphology of the wafer surface is a key factor affecting the uniformity of chemical mechanical polishing (CMP) planarity and the control of photolithography depth of focus. Nanoscale morphology typically refers to surface features with spatial wavelengths ranging from 0.2 mm to 20 mm and height variations on the nanometer scale.

[0003] Current technologies primarily rely on phase-shifting interferometry to perform high-resolution scanning of the wafer surface, acquiring morphological height data, and then using single or double Gaussian filters to separate the nano-morphology from this data. However, traditional Gaussian filters suffer from severe boundary truncation at wafer edges, causing distortion in the filtered data at these edges and failing to accurately reflect the risk of yield loss at the edges. Summary of the Invention

[0004] This disclosure provides a method, system, computing device, and storage medium for extracting wafer nanomorphology; it can solve the edge effect of traditional Gaussian filters and ensure the authenticity and accuracy of edge morphology.

[0005] The technical solution disclosed herein is implemented as follows: In a first aspect, this disclosure provides a method for extracting wafer nanostructures, including: Obtain the height image of the wafer surface; The gradient distribution on the wafer surface is obtained from the height image, and the corresponding initial gradient image is generated. The initial gradient image is smoothed using a preset filter to obtain the filtered gradient image. Nanoscale topography of the wafer surface is obtained by reconstructing the filtered gradient image; The filter is configured such that, as the filter moves from the center of the preset effective region of the wafer in the initial gradient image to the edge, the size of the filter window is reduced from a first size to a second size; the first size is larger than the second size.

[0006] Secondly, this disclosure provides a wafer nanostructure extraction system, comprising: The image acquisition module is used to acquire height images of the wafer surface; The gradient acquisition module is used to obtain the gradient distribution on the wafer surface based on the height image and generate the corresponding initial gradient image; The gradient filtering module is used to smooth the initial gradient image using a preset filter to obtain the filtered gradient image. The topography reconstruction module is used to reconstruct nanoscale topography maps of the wafer surface based on the filtered gradient image; The filter is configured to reduce the size of its filtering window from a first size to a second size as it moves from the center of the preset effective region of the wafer in the initial gradient image to the edge; the first size is larger than the second size.

[0007] Thirdly, this disclosure provides a computing device, including a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the wafer nanomorphology extraction method described in the first aspect.

[0008] Fourthly, this disclosure provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the wafer nanomorphology extraction method described in the first aspect.

[0009] This disclosure provides a method, system, computing device, and storage medium for extracting wafer nanomorphology. First, a height image of the wafer surface is acquired. Based on the height image, the gradient distribution of the wafer surface is obtained, and a corresponding initial gradient image is generated to facilitate the identification of sudden measurement anomalies. Then, a preset filter is used to smooth the initial gradient image. The filter is configured to reduce its filtering window size from a first size to a second size as it moves from the center of a preset effective wafer region in the initial gradient image towards the edge. The first size is larger than the second size, which effectively suppresses edge truncation effects, ensuring that the filtered gradient image maintains smoothness in the central region while ensuring the realism and accuracy of the edge morphology. Finally, reconstruction is performed based on the filtered gradient image to obtain a wafer surface nanomorphology map with realistic and consistent edges. Attached Figure Description

[0010] Figure 1 This is a flowchart of the wafer nanomorphology extraction method provided in this disclosure.

[0011] Figure 2 This is a flowchart for obtaining the initial gradient image provided in this disclosure.

[0012] Figure 3 This is a flowchart for obtaining the parameters of the best-fit plane provided in this disclosure.

[0013] Figure 4 A comparison of the initial gradient images obtained using the traditional finite difference method and the plane fitting algorithm provided in this disclosure.

[0014] Figure 5 This is a flowchart for obtaining a filtered gradient image using a filter, as provided in this disclosure.

[0015] Figure 6 This is a comparison diagram of the filtered gradient images obtained using a conventional Gaussian filter and an improved filter, as provided in this disclosure.

[0016] Figure 7 A comparison chart showing the edge gradient values ​​obtained using a conventional Gaussian filter and an improved filter, as provided in this disclosure.

[0017] Figure 8 This is a flowchart illustrating the process of reconstructing nanoscale topography using the Poisson integral algorithm provided in this disclosure.

[0018] Figure 9 This is a three-dimensional image of a nano-morphology generated using the Poisson integral algorithm, as provided in this disclosure.

[0019] Figure 10 The three-dimensional image of the nano-morphology generated using the path integral method is provided in this disclosure.

[0020] Figure 11 This is a schematic diagram of the wafer nanomorphology extraction system provided in this disclosure.

[0021] Figure 12 This is a schematic diagram of the structure of the computing device provided in this disclosure. Detailed Implementation

[0022] The technical solutions in this disclosure will now be clearly and completely described with reference to the accompanying drawings.

[0023] In high-volume semiconductor manufacturing environments, monitoring of wafer surface morphology is typically integrated after certain process nodes, such as after chemical mechanical polishing, after epitaxial layer growth, or before photolithography. This disclosure aims to characterize the surface morphology of wafers with sub-nanometer precision.

[0024] Figure 1 This is a flowchart of the wafer nanostructure extraction method provided in this disclosure. Figure 1 As shown, the method includes: Step S110: Obtain the height image of the wafer surface.

[0025] This disclosure uses an interferometer to scan the wafer surface to obtain a height image of the wafer surface. Specifically, the interferometer splits a coherent light source into a reference beam and a test beam using a beam splitter. The reference beam is reflected by a highly flat reference mirror, while the test beam illuminates the wafer surface. The test beam reflected back from the wafer surface merges with the reference beam at the beam splitter. Due to nanometer-scale height undulations at various points on the wafer surface, different optical path differences are generated between the reflected test beam and the reference beam. These optical path differences cause the two beams to coherently reinforce or cancel each other out, forming an interference fringe pattern with varying brightness.

[0026] By fine-tuning the position of the reference mirror and repeatedly changing the phase of the reference light, a series of interference fringe patterns with phase shifts can be obtained. Then, a phase-shifting algorithm is used to calculate the original phase value of each pixel in the acquired interferograms, resulting in a phase image. At this point, the phase values ​​in the phase image are at... The phase images exhibit periodic jumps between adjacent pixels. Algorithms are used to identify the transitions between these pixels. The phase compensation map, obtained by hopping and accumulating compensation in space, represents a continuous optical path difference distribution, reflecting the macroscopic contour and microscopic undulations of the wafer surface. Finally, the phase values ​​in the phase compensation map are mapped to the actual physical height to obtain the height image of the wafer surface. During scanning, the horizontal principal axis (X-axis) of the scanning probe movement is typically defined as the horizontal direction (i.e., the X-direction), and the secondary axis (Y-axis) perpendicular to the X-axis is defined as the vertical direction (i.e., the Y-direction), used to cover the entire wafer plane. The height image obtained by scanning is in matrix form, denoted as H( x , y This matrix completely covers the circular wafer region and its surrounding background region. The wafer region has continuous height values, while the background region contains background noise or is marked as invalid. Within the wafer region, each element represents a corresponding coordinate point on the wafer surface (…). x , y Height value relative to the reference plane z .

[0027] The height images obtained by scanning typically contain macroscopic shapes (e.g., wavelength > 20 mm) and nanoscale morphologies (e.g., wavelength 0.2 mm - 20 mm). The range of macroscopic shapes can be as high as tens of micrometers (μm), while the range of nanoscale morphologies is only tens of nanometers (nm). The difference between the two is more than three orders of magnitude, making direct analysis extremely difficult.

[0028] Step S120: Obtain the gradient distribution on the wafer surface based on the height image, and generate the corresponding initial gradient image.

[0029] In this disclosure, for each pixel in the height image, its gradient value is calculated, which includes gradient values ​​in the X and Y directions. The gradient value characterizes the degree of drastic change in surface height; the larger the gradient value, the more drastic the height change. On sub-nanometer wafer surfaces, macroscopic morphology smoothness is very high, but nanoscale morphology (such as fine scratches or depressions) typically exhibits localized high-frequency fluctuations, whose signal characteristics are more significant in the gradient domain than in the height domain. When acquiring the initial gradient image based on the height image, the region generated by calculating the gradient values ​​of the pixels corresponding to the wafer region in the height image is marked as the valid wafer region, and other regions are marked as invalid regions.

[0030] Step S130: Smooth the initial gradient image using a preset filter to obtain the filtered gradient image.

[0031] The filter is configured to reduce its filter window size from a first size to a second size as it moves from the center of a preset wafer effective region in the initial gradient image towards the edge; the first size is larger than the second size. The first size is a preset maximum size, such as 10mm; the second size is a preset minimum size, such as 1mm. Furthermore, the filter is configured to, when the filter window size is the second size, set the weights of invalid pixels falling outside the wafer effective region within the filter window to zero, and re-normalize the weights of valid pixels falling within the wafer effective region.

[0032] In existing technologies, single-Gaussian filters or double-Gaussian filters are typically used to extract the nanostructures of wafer surfaces. The standard Gaussian kernel weighting function is... .in, u - v This represents the pixel to be processed in the initial gradient image. u At that point, the pixel within the filtering window corresponding to the Gaussian kernel. v With the pixel to be processed u Distance between; standard deviation From the cutoff wavelength Decision, usually related to For example, for a cutoff wavelength of 20mm, the size of the filtering window may cover hundreds of pixels. When the center of the filtering window moves to the edge of the initial gradient image, part of the window will fall within the effective area of ​​the wafer, and another part will fall within the invalid area. A conventional Gaussian kernel will "pad zeros" for the missing data in the invalid area, but this method also includes "0"s or invalid information outside the edge in the calculation. This causes the sub-nanometer features near the edge to be forcibly lowered or smoothed by the surrounding invalid background, resulting in the filtered data deviating significantly from the true value.

[0033] The filter in this disclosure is an improved Gaussian filter configured to adaptively adjust the size and weights of the filter window, specifically by calculating: ; Regarding the size of the filtering window, it should be close to the effective area of ​​the wafer. The filter window gradually shrinks at the edges to ensure that all pixels within the filter range are valid. However, the minimum size of the filter window is not zero. If the filter is located at the edge of the wafer's effective region (i.e., the distance from the center of the filter window to the boundary of the wafer's effective region is less than a preset limit distance, such as less than 1mm), the filter window will not be able to effectively filter pixels within the wafer's effective region. Each valid pixelv Its normalized weights are adjusted to This means that when half of the filter window is in the invalid region, the sum of the weights within the effective region of the wafer is forced to be renormalized to 1. In other words, the energy of the filter is contracted and concentrated within the effective region of the wafer, thereby ensuring that the signal strength at the edges does not attenuate, and thus improving the consistency and accuracy of the subsequent reconstruction results across the entire domain.

[0034] Therefore, the filter in this disclosure can shrink and correct the filter kernel weights in the edge region while maintaining the smoothing effect of Gaussian filtering, thereby reducing the distortion problem caused by the boundary truncation effect and maintaining the moment invariance of the overall filtering process.

[0035] Step S140: Obtain the nano-morphological map of the wafer surface based on the filtered gradient image reconstruction.

[0036] The filtered gradient image contains filtered gradient values ​​in the X direction (representing the slope in the X direction) and filtered gradient values ​​in the Y direction (representing the slope in the Y direction), which can reflect the orientation and tilt of the wafer surface at each pixel. In this disclosure, the surface region corresponding to each pixel is "stitched" with the surface regions of surrounding pixels according to its gradient value to finally generate a complete nanomorphic map of the wafer surface.

[0037] In this disclosure, a height image of the wafer surface is first acquired. Based on this height image, the gradient distribution of the wafer surface is obtained, and a corresponding initial gradient image is generated to facilitate the identification of sudden measurement anomalies. Then, a preset filter is used to smooth the initial gradient image. The filter is configured to reduce its filtering window size from a first size to a second size as it moves from the center of the preset effective wafer region in the initial gradient image towards the edge. This effectively suppresses edge truncation effects, ensuring that the filtered gradient image maintains smoothness in the central region while ensuring the realism and accuracy of the edge morphology. Finally, reconstruction is performed based on the filtered gradient image to obtain a nano-morphology map of the wafer surface with realistic and consistent edges.

[0038] Figure 2 This is a flowchart for obtaining the initial gradient image provided in this disclosure. Figure 2 As shown, the gradient distribution of the wafer surface is obtained based on the height image, and a corresponding initial gradient image is generated, including: Step S210: For each pixel in the height image, select a neighborhood window of a preset size centered on it.

[0039] In this disclosure, it is assumed that the height image is an M×N two-dimensional matrix H( x , yThe coordinates of the pixel to be processed are ( ). x , y ). A preset size is k × k Neighborhood window (usually) k If the value is an odd number (e.g., 3, 5, 7, etc.), then the neighborhood window radius r = ( k -1) / 2. With ( x , y Centered on ), the range covered by this neighborhood window in the image matrix is: row coordinate range [ x - r , x + r ], column coordinate range[ y - r , y + r ].

[0040] If the neighborhood window is too small (e.g., 2×2), it cannot provide enough sample points for statistical fitting; if the neighborhood window is too large (e.g., 11×11), it will cause excessive smoothing of local details and reduce spatial resolution. Preferably, for a 300mm wafer with a resolution of 50μm pixels, a 5×5 neighborhood window (25 pixels in total) is selected to achieve the best balance between computational efficiency and noise reduction capability.

[0041] Step S220: Use a plane fitting algorithm to perform regression analysis on the height data of each pixel in the neighborhood window to obtain the parameters of the best fitting plane.

[0042] In semiconductor metrology, height images are often affected by noise, which may originate from dead pixels in CCD / CMOS sensors, airborne dust particles, or tiny scratches on the wafer surface. Traditional finite difference methods calculate gradients using adjacent pixels, making them highly susceptible to single-point noise that can produce erroneous gradient "peaks," leading to false pits or protrusions in the subsequently reconstructed topography. Therefore, this disclosure employs a plane fitting algorithm to estimate local gradients, effectively reducing errors introduced by measurement noise or local anomalies, resulting in a smoother and more robust initial gradient image.

[0043] Specifically, for each pixel in the height image, first extract the set of three-dimensional coordinates S = { ( x i , y i , z i ) | i =1, 2, …, n}, where n is the total number of pixels in the window. z iFor the first i Height data corresponding to each pixel.

[0044] Then, based on the height data of each pixel within its neighborhood window, a plane fitting algorithm is used to fit an optimal plane A. x +B y +C z By setting +D=0, we can obtain the parameters A, B, C, and D of the best-fit plane. Here, (A,B,C) is the normal vector of the best-fit plane, and C is not 0.

[0045] Step S230: Determine the gradient values ​​of the corresponding pixel points in the X and Y directions based on the parameters of the best-fit plane; where the X and Y directions are the horizontal and vertical directions on the predefined wafer surface, respectively.

[0046] For the best-fit plane, z Represented as x and y Functions: z = (-A / C) x + (-B / C) y -D / C. Then the gradient value in the X direction (i.e., z right x The partial derivative is -A / C, in y gradient value in the direction (i.e.) z right y The partial derivative of ( ) is -B / C.

[0047] Step S240: Generate an initial gradient image based on the gradient values ​​of each pixel in the height image in the X and Y directions.

[0048] The calculated (-A / C, -B / C) values ​​are assigned to the initial gradient image at coordinates ( x , y The pixel value at position () is used. After traversing all pixels, an initial gradient image is generated.

[0049] Figure 3 This is a flowchart for obtaining the parameters of the best-fit plane provided in this disclosure. Figure 3 As shown, a plane fitting algorithm is used to perform regression analysis on the height data of each pixel within the neighborhood window to obtain the parameters of the best-fit plane, including: Step S310: Use the random sampling consensus algorithm to sample and iterate the height data within the neighborhood window to obtain non-noise pixels.

[0050] To further eliminate the influence of noise points, the present disclosure uses the RANdom SAmple Consensus (RANSAC) algorithm for plane fitting. Among them, the RANSAC algorithm is an iterative algorithm. In each iteration, first randomly select 3 non-collinear pixel points (the minimum number of points required to determine a plane) from the three-dimensional coordinate set S of each pixel point within the neighborhood window, and calculate a temporary plane A based on these 3 non-collinear pixel points x +B y +C z +D = 0. Then, traverse all the remaining pixel points within the neighborhood window and calculate the perpendicular distance from each pixel point to this temporary plane d i . Count the number of pixel points that satisfy d i <T, and mark these pixel points as non-noise pixel points. Among them, T is the set distance threshold, and this threshold is usually 2-3 times the vertical noise level of the system. For example, T = 0.5nm. In this way, pixel points within the neighborhood window that deviate far from the mainstream plane will be determined as noise points by the RANSAC algorithm and excluded

[0051] In the present disclosure, the number of iterations is usually set to 10 to 50 times. In each iteration, a temporary plane will be generated, and the number of non-noise pixel points will be counted. Select the temporary plane with the largest number of non-noise pixel points as the target fitting plane

[0052] Step S320: Obtain the parameters of the best fitting plane based on non-noise pixel points

[0053] To further improve the accuracy, the present disclosure uses all non-noise pixel points corresponding to the target fitting plane to perform linear regression again to obtain the parameters A, B, C, and D of the best fitting plane

[0054] For each pixel point in the height image, its gradient value in the X direction -A / C and the gradient value in the Y direction -B / C can be calculated according to the parameters of its best fitting plane, and then the initial gradient image corresponding to the height image can be obtained

[0055] Among them, Figure 4 is the comparison diagram of the initial gradient images obtained by using the traditional finite difference method and the plane fitting algorithm provided by the present disclosure. Among them, Figure 4 .. (a) is the initial gradient image obtained by using the traditional finite difference method Figure 4 (b) is the initial gradient image obtained by using the plane fitting algorithm. By comparison, Figure 4 the stripes in (a) are more obvious, indicating that the original noise points have a greater impact on the calculation results Figure 4(b) shows a significant improvement in the stripes and a smoother overall result, indicating that the original noise has a smaller impact on the calculation results. Especially when there are local steps or protrusions on the wafer surface, it can still maintain high gradient estimation accuracy, thereby improving the overall quality of topography reconstruction. Therefore, the plane fitting algorithm is more robust than the traditional difference method under complex surface structures.

[0056] In this disclosure, a preset filter is used to smooth the initial gradient image to obtain a filtered gradient image, including: In the filter, the weighted square root algorithm is used to perform nonlinear convolution on the initial gradient image to obtain the filtered gradient image.

[0057] When performing convolution operations, conventional Gaussian kernels use a weighted averaging algorithm for linear weighting. This involves directly accumulating all gradient values ​​within the filtering window according to their corresponding weights. This method averages regions with larger gradient values ​​(such as minor scratches or dents) with surrounding flat regions with smaller gradient values. This smooths out the sharp edges of minor scratches or dents, resulting in blurred edges in local areas of the filtered gradient image. Furthermore, if the radial artifacts (periodic ring-shaped ripples or stripe-like deviations spreading outward from a center point) in the initial gradient image have a large period, the weighted averaging algorithm cannot completely cancel them out within the filtering window. The radial artifacts will remain in the filtered gradient image as "low-frequency fluctuations."

[0058] This disclosure employs a weighted square root algorithm to perform nonlinear convolution operations on the initial gradient image, which involves squaring the gradient values ​​of all pixels within the filtering window, then taking a weighted average and finally rooting the square root. The squaring operation causes a surge in the squared value of regions with large gradient values ​​(such as minute scratches or depressions, or other nano-morphological features), while radial artifacts typically have smaller gradient values, resulting in a relatively lower squared value. This significantly widens the gap between nano-morphological features and artifacts, enhancing nano-morphological features while effectively reducing radial artifacts.

[0059] Figure 5 This is a flowchart illustrating the process of obtaining a filtered gradient image using a filter, as provided in this disclosure. Figure 5 As shown, in the filter, a weighted square root algorithm is used to perform a nonlinear convolution operation on the initial gradient image to obtain the filtered gradient image, including: Step S510: In the initial gradient image, determine the filtering window for the pixels to be processed, and obtain the spatial distribution weight of each pixel within the filtering window relative to the pixels to be processed.

[0060] In this disclosure, the filtering window is defined by the pixels to be processed in the initial gradient image. u The rectangular region centered on the filter window is sized by the standard deviation of the Gaussian filter. To cover the main energy region of the Gaussian distribution, the horizontal and vertical distances from the center to the edge of the filter window are typically set to 3. The filtering window is typically a window of size 10 ... A square matrix. For example, when In this case, the filter window is usually selected as 7×7 pixels, that is, the filter window contains a total of 49 pixels.

[0061] For each pixel within the filtering window v Calculate its relative to the pixel to be processed. u Spatial distribution weights are It defines the distance from the pixel to be processed. u The contribution weight of pixels at different distances to the final result is as follows: the closer the distance, the greater the weight.

[0062] Step S520: Use the squared value of the gradient of the pixel within the filtering window as the gradient energy of the pixel.

[0063] Specifically, pixels v The gradient value is denoted as Then, squaring it yields the gradient energy. .

[0064] Step S530: Use spatial distribution weights to perform weighted aggregation of the gradient energy of each pixel in the filtering window to obtain the total window energy feature of the pixel to be processed.

[0065] Specifically, for each pixel within the filtering window, its gradient energy is multiplied by the corresponding spatial distribution weight to obtain the gradient energy feature of each pixel. Then, the gradient energy features of all pixels are summed to obtain the total window energy feature corresponding to the pixel to be processed.

[0066] Step S540: Perform a square root operation on the total energy feature of the window to obtain the filtered gradient value of the pixel to be processed.

[0067] Based on steps S510 to S540 above, the formula for performing nonlinear convolution operations on the initial gradient image at the pixels to be processed using the weighted square root algorithm in this disclosure is as follows: ; in, Indicates the pixel to be processed u The filtered gradient value.

[0068] In this disclosure, the gradient is first squared to enhance signal features and eliminate phase interference, then spatial domain smoothing is performed using a weighting function, and finally, square root restoration is performed. This approach makes the filter more sensitive to large gradient changes (i.e., significant nanoscale topographic features), better preserves signal energy, and significantly reduces radial artifacts.

[0069] Step S550: Generate a filtered gradient image based on the filtered gradient value of each pixel to be processed in the initial gradient image.

[0070] In this disclosure, the filter slides row by row and column by column on the initial gradient image with a specified step size (e.g., step size of 1). Each time it moves to a new position, a new pixel to be processed is determined. Through the above steps S510 to S540, the filtered gradient value of the new pixel to be processed can be obtained. After the filter has traversed all the pixels to be processed in the initial gradient image, the filtered gradient image can be obtained.

[0071] Figure 6 This is a comparison image of the filtered gradient images obtained using a conventional Gaussian filter and an improved filter, as provided in this disclosure. Figure 6 (a) is the gradient image obtained by using a conventional Gaussian filter. Figure 6 (b) is the filtered gradient image obtained using the improved filter. The comparison shows that in edge regions, the improved filter in this disclosure handles edge effects better than the conventional Gaussian filter, ensuring that the edge values ​​of the gradient image are neither too large nor too small. Figure 7 This is a comparison chart of the edge gradient values ​​obtained using a conventional Gaussian filter and an improved filter, as provided in this disclosure. Figure 7 (a) is for Figure 6 (a) shows the edge gradient value curve obtained by cross-sectioning the filtered gradient image and obtaining the edge gradient value curve under the conventional Gaussian filter. Figure 7 (b) is for Figure 6 (b) shows the edge gradient curve obtained by cross-sectioning the filtered gradient image and obtaining the edge gradient value curve under the improved Gaussian filter. Figure 7 (a) and Figure 7 In (b), the horizontal axis represents the distance between the filter window and the center of the effective region of the wafer (referred to as distance in the figure, in pixels), and the vertical axis represents the gradient value. Figure 7 As shown in (a), the difference between the maximum and minimum values ​​in the curve data is close to 180, and the edge gradient values ​​will jump significantly. This is because the edge gradient values ​​lack valid points within the filtering window; Figure 7As shown in (b), the difference between the maximum and minimum values ​​in the curve data is approximately 50, and there is no obvious jump in the edge gradient. Therefore, the improved filter of this disclosure has a significant improvement effect compared with the conventional filter, reduces the edge effect, and can improve the overall measurement accuracy.

[0072] In this disclosure, a nano-morphological map of the wafer surface is obtained based on the reconstruction of the filtered gradient image, including: First, calculate the partial derivatives of the filtered gradient image in the X and Y directions, and sum them to obtain the divergence image; The initial gradient image contains gradients in the X and Y directions, which are vectors and cannot be directly recovered as a scalar (height). Therefore, this disclosure fuses the gradients in the X and Y directions into a single-channel scalar field. Specifically, for the gradient in the X direction... p Differential processing yields gradient in the Y direction q Differential processing yields After fusion, a divergence image is generated. .

[0073] Subsequently, the divergence image was reconstructed using the Poisson integral algorithm to obtain the nanoscale topography of the wafer surface.

[0074] In this disclosure, the Poisson equation is used for global integration calculation, and the Poisson equation is: ; This equation describes the equivalence between the Laplacian operator and the divergence image of the nanostructure map. Wherein, z ( x , y () is the height function to be determined; x , y () represents the pixel coordinates; The Laplace operator represents the second derivative of the height function in the X direction. and the second derivative in the Y direction sum.

[0075] In existing technologies, an integral-based height reconstruction method is typically used. To calculate the height of a pixel, this algorithm accumulates the height step by step along a path. This approach allows small random noises present in the measurement to accumulate along the path. If there is an error in the gradient value of a pixel, this error will be propagated to all subsequent pixels, causing the final shape to tilt or drift.

[0076] In this disclosure, the core objective of using the Poisson integral algorithm to reconstruct nanoscale topography images from divergence images is to find a height function whose gradient approximates the filtered gradient image to the greatest extent possible. Therefore, the Poisson equation is used as the objective function, and the filtered gradient image is used as the boundary condition for the Poisson equation. This transforms the nanoscale topography reconstruction problem into solving the Poisson equation. By solving the Poisson equation, the height distribution of the wafer surface can be recovered, yielding the nanoscale topography image. Solving the Poisson equation distributes measurement errors evenly across the entire surface, thereby suppressing drift.

[0077] Figure 8 This is a flowchart illustrating the process of reconstructing nanoscale topography using the Poisson integral algorithm provided in this disclosure. Figure 8 As shown, the divergence image is reconstructed using the Poisson integral algorithm to obtain a nanoscale topography map of the wafer surface, including: Step S810: Convert the divergence image to the frequency domain using Fourier transform and obtain the frequency domain representation of the divergence image.

[0078] In the spatial domain, solving the Poisson equation involves solving a huge system of linear equations, including second-order partial derivative operations, resulting in extremely high computational complexity and convergence speed limited by the grid size. Therefore, this disclosure maps the divergence image to the frequency domain using a Fourier transform to obtain the frequency domain representation F(…). f ).

[0079] During mapping, the number of columns M and rows N of the divergence image are first obtained. An integer sequence from 0 to M-1 is created as the horizontal index m, and an integer sequence from 0 to N-1 is created as the vertical index n. Then, a gridding operation is performed: the sequence [0, 1, …, M-1] is copied N times along the row direction to obtain an N×M matrix as matrix m; the sequence [0, 1, …, N-1] is copied M times along the row direction to obtain an N×M matrix as matrix n; for each pixel position (x, y) in the divergence image, there is a corresponding frequency index (m, n) in the frequency domain.

[0080] Step S820: Construct the eigenvalue matrix of the Laplacian operator.

[0081] Specifically, based on the dimensions M and N of the divergence image, eigenvalue vectors in the horizontal direction are constructed respectively. and the eigenvalue vector in the vertical direction : ; ; Using the concepts of matrix broadcasting or Kronecker product, the two vectors mentioned above are expanded into an eigenvalue matrix of size M × N, consistent with the size of the divergence image. : ; Step S830: Solve the frequency domain representation of the divergence image using the eigenvalue matrix in the frequency domain, and transform the solution to the spatial domain through inverse Fourier transform to obtain the nano-topography height map.

[0082] Specifically, by performing point-by-point division between the frequency domain representation of the divergence image and the Laplacian eigenvalue matrix, and then performing an inverse Fourier transform on the result, the nanostructure height map is obtained: ; In the formula, This is a height map of the nano-morphology; This represents the inverse Fourier transform. By performing point-by-point division between the frequency domain representation of the divergence image and the Laplace eigenvalue matrix, the gradient across the entire field can be automatically balanced, thereby evenly distributing measurement errors and suppressing drift.

[0083] Figure 9 The three-dimensional image of nano-topography generated using the Poisson integral algorithm provided in this disclosure is obtained by adding X and Y pixel coordinates to a height map. Figure 10 This is a three-dimensional image of nanostructures generated using the path integral method as provided in this disclosure. (Comparison is also possible.) Figure 9 and Figure 10 It is evident that, compared to the Poisson integral algorithm, the path integral method produces fringe errors in the 3D images of nano-topography, resulting in wavy fringes on the surface. The Poisson integral algorithm, however, produces smoother 3D images of nano-topography, effectively suppressing noise in the original data and improving measurement accuracy. Comparative results show that the Poisson integral algorithm achieves a better balance between global stability and local precision, exhibiting robustness against noise and non-integrable errors, making it suitable for recovering topography from interferometry, laser scanning, or phase gradients. Therefore, under optimal conditions, this disclosure utilizes the Fourier integral algorithm to achieve superior reconstruction results.

[0084] Figure 11 This is a schematic diagram of the wafer nanostructure extraction system provided in this disclosure, as shown below. Figure 11 As shown, the wafer nanostructure extraction system 1100 includes: Image acquisition module 1110 is used to acquire height images of the wafer surface; The gradient acquisition module 1120 is used to acquire the gradient distribution on the wafer surface based on the height image and generate the corresponding initial gradient image; The gradient filtering module 1130 is used to smooth the initial gradient image using a preset filter to obtain a filtered gradient image. The topography reconstruction module 1140 is used to reconstruct the nano-topography of the wafer surface based on the filtered gradient image. The filter is configured such that, as the filter moves from the center of the preset effective region of the wafer in the initial gradient image to the edge, the size of the filter window is reduced from a first size to a second size; the first size is larger than the second size.

[0085] The wafer nanomorphology extraction system disclosed herein can realize the wafer nanomorphology extraction method provided herein, and their implementation principles are similar. The actions performed by each module and unit in the wafer nanomorphology extraction system disclosed herein correspond to the steps of the wafer nanomorphology extraction method disclosed herein. For a detailed description of each module and unit in the wafer nanomorphology extraction system disclosed herein, please refer to the description of the corresponding wafer nanomorphology extraction method shown above, which will not be repeated here.

[0086] Figure 12 This is a schematic diagram of the structure of the computing device provided in this disclosure. Figure 12 As shown, the computing device 1200 includes a processor 1210, a memory 1220, and a computer program stored in the memory and executable on the processor. When the processor 1210 executes the computer program, it implements the wafer nanomorphology extraction method described in this disclosure.

[0087] In some examples, the computing device 1200 can be at least one of the following: a smartphone, a smartwatch, a desktop computer, a laptop, a virtual reality terminal, an augmented reality terminal, a wireless terminal, and a laptop computer. The computing device 1200 has communication capabilities and can access wired or wireless networks. The computing device 1200 can refer to one of multiple terminals; those skilled in the art will understand that the number of such terminals can be more or less. In some examples, the computing device 1200 can receive the raw electromagnetic flaw detection signals from the downhole tubing under test based on the accessed wired or wireless network. It is understood that the computing device 1200 undertakes the calculation and processing work of the technical solution of this disclosure, and this disclosure does not limit it in this regard.

[0088] Optionally, the processor 1210 connects various parts within the computing device using various interfaces and lines, and performs various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 1220, and by calling data stored in the memory 1220. Optionally, the processor 1210 can be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 1210 can integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), Neural-network Processing Unit (NPU), and baseband chip. Specifically, the CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required to be displayed on the touch screen; the NPU is used to implement Artificial Intelligence (AI) functions; and the baseband chip is used to handle wireless communication. It is understandable that the aforementioned baseband chip may not be integrated into the processor 1210, but may be implemented using a separate chip.

[0089] The memory 1220 may include random access memory (RAM) or read-only memory (ROM). Optionally, the memory 1220 may include a non-transitory computer-readable storage medium. The memory 1220 may be used to store instructions, programs, code, code sets, or instruction sets. The memory 1220 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the various method embodiments described above, etc.; the data storage area may store data created according to the use of the computing device, etc.

[0090] In addition, those skilled in the art will understand that the structure of the computing device shown in the above figures does not constitute a limitation on the computing device. The computing device may include more or fewer components than shown, or combine certain components, or have different component arrangements. For example, the computing device may also include a display screen, camera assembly, microphone, speaker, radio frequency circuit, input unit, sensors (such as accelerometer, angular velocity sensor, light sensor, etc.), audio circuit, WiFi module, power supply, Bluetooth module, etc., which will not be described in detail here.

[0091] This disclosure also provides a computer-readable storage medium storing at least one instruction that is executed by a processor to implement the wafer nanostructure extraction method as described in the above embodiments.

[0092] This disclosure also provides a computer program product including computer instructions stored in a computer-readable storage medium; a processor of a computing device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computing device to perform the wafer nanostructure extraction method described in the above embodiments.

[0093] Those skilled in the art will recognize that the functions described in this disclosure in one or more of the examples above can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer.

[0094] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily as long as they do not conflict.

[0095] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for extracting nanostructures from wafers, characterized in that, include: Obtain the height image of the wafer surface; The gradient distribution of the wafer surface is obtained based on the height image, and a corresponding initial gradient image is generated; The initial gradient image is smoothed using a preset filter to obtain a filtered gradient image. The nano-morphology map of the wafer surface is obtained by reconstructing the filtered gradient image. The filter is configured to reduce the size of its filtering window from a first size to a second size as the filter moves from the center of the preset effective region of the wafer in the initial gradient image to the edge. The first dimension is larger than the second dimension.

2. The wafer nanostructure extraction method according to claim 1, characterized in that, The step of obtaining the gradient distribution of the wafer surface based on the height image and generating a corresponding initial gradient image includes: For each pixel in the height image, a neighborhood window of a preset size is selected centered on it; A plane fitting algorithm is used to perform regression analysis on the height data of each pixel within the neighborhood window to obtain the parameters of the best fitting plane. Based on the parameters of the best-fit plane, determine the gradient values ​​of the corresponding pixel in the X and Y directions; The initial gradient image is generated based on the gradient values ​​of each pixel in the height image in the X and Y directions; Wherein, the X direction and the Y direction are the horizontal and vertical directions on the predefined wafer surface, respectively.

3. The wafer nanostructure extraction method according to claim 2, characterized in that, The step involves using a plane fitting algorithm to perform regression analysis on the height data of each pixel within the neighborhood window to obtain the parameters of the best-fit plane, including: The height data within the neighborhood window is sampled and iterated using a random sampling consensus algorithm to obtain non-noise pixels; The parameters of the best-fit plane are obtained based on the non-noise pixels.

4. The wafer nanostructure extraction method according to claim 1, characterized in that, The step of smoothing the initial gradient image using a preset filter to obtain a filtered gradient image includes: In the filter, the initial gradient image is subjected to nonlinear convolution operation using the weighted square root algorithm to obtain the filtered gradient image.

5. The wafer nanostructure extraction method according to claim 4, characterized in that, In the filter, a weighted square root algorithm is used to perform a nonlinear convolution operation on the initial gradient image to obtain the filtered gradient image, including: In the initial gradient image, a filtering window for the pixels to be processed is determined, and the spatial distribution weights of each pixel within the filtering window relative to the pixels to be processed are obtained. The squared value of the gradient of each pixel within the filtering window is taken as the gradient energy of the pixel. The gradient energy of each pixel within the filtering window is weighted and aggregated using the spatial distribution weights to obtain the total window energy feature of the pixel to be processed. Perform a square root operation on the total energy feature of the window to obtain the filtered gradient value of the pixel to be processed; The filtered gradient image is generated based on the filtered gradient value of each pixel to be processed in the initial gradient image.

6. The wafer nanostructure extraction method according to claim 2, characterized in that, The process of reconstructing the nanostructure map of the wafer surface based on the filtered gradient image includes: Calculate the partial derivatives of the filtered gradient image in the X and Y directions, and sum them to obtain the divergence image; The divergence image is reconstructed using the Poisson integral algorithm to obtain a nanoscale topography map of the wafer surface.

7. The wafer nanostructure extraction method according to claim 6, characterized in that, The step of using the Poisson integral algorithm to perform integral reconstruction on the divergence image to obtain the nanoscale topography map of the wafer surface includes: The divergence image is converted to the frequency domain by Fourier transform, and the frequency domain representation of the divergence image is obtained. Construct the eigenvalue matrix of the Laplacian operator; The frequency domain representation of the divergence image is solved using the eigenvalue matrix in the frequency domain, and the solution is transformed to the spatial domain by inverse Fourier transform to obtain the nano-topography height map.

8. A wafer nanostructure extraction system, characterized in that, include: The image acquisition module is used to acquire height images of the wafer surface; The gradient acquisition module is used to acquire the gradient distribution of the wafer surface based on the height image and generate a corresponding initial gradient image; The gradient filtering module is used to smooth the initial gradient image using a preset filter to obtain a filtered gradient image. The topography reconstruction module is used to reconstruct a nano-topography map of the wafer surface based on the filtered gradient image; The filter is configured such that, during the process of the filter moving from the center of the preset effective region of the wafer in the initial gradient image to the edge, the size of the filter window is reduced from a first size to a second size; the first size is larger than the second size.

9. A computing device, characterized in that, The method includes a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the wafer nanomorphology extraction method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the wafer nanomorphology extraction method as described in any one of claims 1 to 7.

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