Display device

Abstract

The embodiment relates to a display device, comprising: a pixel disposed in a display area; and at least one driving unit disposed in a non-display area surrounding the display area, each pixel comprising: a light-emitting element including a plurality of light-emitting units connected in series via a common node; a driving transistor having a first electrode connected to a high-potential driving voltage line via a first node, a gate connected to a second node, and a second electrode connected to the light-emitting element via a third node; a compensation transistor connected between the second node and the third node, having a gate configured to receive a first scan signal; a switching transistor connected between a data line and the first node, having a gate configured to receive a second scan signal; an anode reset transistor connected between the light-emitting element and the anode reset voltage line, having a gate configured to receive a third scan signal; and a common node reset voltage line connected to the common node.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0196003, filed on December 24, 2024, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This invention relates to a display device. Background Technology

[0004] With the advancement of the information society, the demand for display devices that can display images is increasing, and various types of display devices are being used, such as liquid crystal display (LCD) devices and organic light-emitting diode (OLED) displays.

[0005] These display devices include multiple components, including a display panel, a data driver, a gate driver, a timing controller, and a power management unit. The power management unit uses the input power supply to generate and provide the various drive voltages required for the operation of these components. Summary of the Invention

[0006] One objective of the embodiments is to provide a display device comprising a light-emitting element having a series structure having a plurality of light-emitting units, wherein, during an anode reset period within a frame, the voltage of a common node connected to the light-emitting units is reset.

[0007] Another objective of the implementation is to provide a display device that applies an anode reset voltage to a common node during an on-bias period.

[0008] Another objective of the embodiments is to provide a display device that includes a connection transistor in a non-display area, the connection transistor being electrically connected to an anode reset voltage line and a common node reset voltage line.

[0009] Another objective of the embodiments is to provide a display device in which, in the non-display area, a common node reset electrode and the anode of the light-emitting element are formed on the same layer, and the common node reset electrode is in contact with the anode reset voltage line.

[0010] Another object of the embodiments is to provide a hybrid pixel, a method for driving the hybrid pixel, and a display device including the hybrid pixel, wherein the hybrid pixel can minimize current leakage using oxide semiconductor transistors.

[0011] The display device according to the embodiments may include a plurality of pixels arranged in a display area and at least one driving unit arranged in a non-display area surrounding the display area.

[0012] Each pixel may include: a light-emitting element comprising a plurality of light-emitting units connected in series via a common node; a driving transistor comprising a first electrode connected to a high-potential driving voltage line via a first node, a gate connected to a second node, and a second electrode connected to the anode of the light-emitting element via a third node; a compensation transistor connected between the second node and the third node and having a gate configured to receive a first scan signal; a switching transistor connected between a data line and the first node and having a gate configured to receive a second scan signal; an anode reset transistor connected between the light-emitting element and the anode reset voltage line and having a gate configured to receive a third scan signal; and a common node reset voltage line connected to the common node.

[0013] The common node reset voltage line can be electrically connected to the anode reset voltage line via a connecting transistor.

[0014] The connection transistor can be connected between the anode reset voltage line and the common node reset voltage line, and has a gate configured to receive the third scan signal.

[0015] When the third scan signal is applied at an on level during the anode reset period within a frame, the anode reset transistor is turned on and applies the anode reset voltage to the anode, the connection transistor is turned on and electrically connects the anode reset voltage line and the common node reset voltage line, the common node reset voltage line can apply the anode reset voltage to the common node.

[0016] The connection transistor can be located in the non-display area.

[0017] The anode reset voltage line and the common node reset voltage line may be disposed between the at least one driving unit and the display area, and the connection transistor may be disposed in the connection area located between the anode reset voltage line and the common node reset voltage line.

[0018] The common node reset voltage line can be formed in a closed loop shape around the display area, and the anode reset voltage line can be formed around at least three sides of the display area.

[0019] The light-emitting element may include: a first electrode; a second electrode arranged opposite to the first electrode; a first light-emitting unit and a second light-emitting unit disposed between the first electrode and the second electrode; and a charge-generating layer inserted between the first light-emitting unit and the second light-emitting unit to form the common node.

[0020] Each pixel may further include: an initialization transistor connected between an initialization voltage line and the second node, and having a gate configured to receive a fourth scan signal; a first light-emitting transistor connected between the high-potential drive voltage line and the first node, and having a gate configured to receive a light-emitting signal; a second light-emitting transistor connected between the third node and the light-emitting element, and having a gate configured to receive the light-emitting signal; a conduction bias transistor connected between the first node and the conduction bias voltage line, and having a gate configured to receive the third scan signal; and a storage capacitor connected between the high-potential drive voltage line and the second node.

[0021] The at least one driving unit may include a gate driver, which is configured to output the first scan signal, the second scan signal, the third scan signal, the fourth scan signal, and the light emission signal respectively through corresponding scan lines and light emission lines.

[0022] The gate driver may include: a first shift register configured to output the first scan signal; a second shift register configured to output the second scan signal; a third shift register configured to output the third scan signal; a fourth shift register configured to output the fourth scan signal; and a fifth shift register configured to output the light emission signal.

[0023] The second shift register may be disposed adjacent to the display area, and the first shift register, the third shift register, the fourth shift register, and the fifth shift register may be disposed sequentially away from the display area.

[0024] At least some of the driving transistor, the compensation transistor, and the anode reset transistor may be low-temperature polycrystalline silicon (LTPS) transistors, and the remaining transistors may be oxide transistors.

[0025] The display device may further include: a substrate; a first buffer layer disposed on the substrate; a first semiconductor layer of a first transistor disposed on the first buffer layer; a first insulating layer disposed on the first semiconductor layer; a first gate of the first transistor disposed on the first insulating layer; a second insulating layer disposed on the first gate of the first transistor; a second buffer layer disposed on the second insulating layer; a second semiconductor layer of a second transistor disposed on the second buffer layer; a third insulating layer disposed on the second semiconductor layer; a second gate of the second transistor disposed on the third insulating layer; a fourth insulating layer disposed on the second gate of the second transistor; a source and a drain of the first transistor and the second transistor disposed on the fourth insulating layer; a protective film disposed on the source and the drain; a planarization layer disposed on the protective film; an anode of the light-emitting element disposed on the planarization layer; a first light-emitting unit of the light-emitting element disposed on the anode; a charge-generating layer of the light-emitting element disposed on the first light-emitting unit, the charge-generating layer constituting the common node; a second light-emitting unit of the light-emitting element disposed on the charge-generating layer; and a cathode of the light-emitting element disposed on the second light-emitting unit.

[0026] The first transistor may be one of the driving transistor, the compensation transistor, and the anode reset transistor, and the second transistor may be another of the driving transistor, the compensation transistor, and the anode reset transistor.

[0027] The display device may further include a connection transistor, the connection transistor comprising: a third semiconductor layer disposed on the first buffer layer; a gate disposed on the first insulating layer; and a third source and a third drain disposed on the fourth insulating layer.

[0028] The third source can be connected to the anode reset voltage line, and the third drain can be connected to the common node reset voltage line.

[0029] The display device may further include a common node reset electrode disposed on a planarization layer in the non-display area, wherein the common node reset electrode is connected to the charge generation layer and the common node reset voltage line through a contact hole.

[0030] The common node reset electrode may also be disposed in the display area and can be connected to the charge generation layer and the common node reset voltage line through at least one contact hole in the display area.

[0031] A display device according to an embodiment may include: a substrate, the substrate including a display area and a non-display area; a first buffer layer disposed on the substrate; a first semiconductor layer of a first transistor disposed on the first buffer layer in the display area; a first insulating layer disposed on the first semiconductor layer; a first gate of the first transistor disposed on the first insulating layer in the display area; a second insulating layer disposed on the first gate of the first transistor; a second buffer layer disposed on the second insulating layer; a second semiconductor layer of a second transistor disposed on the second buffer layer in the display area; a third insulating layer disposed on the second semiconductor layer; a second gate of the second transistor disposed on the third insulating layer in the display area; a fourth insulating layer disposed on the second gate of the second transistor; a source and a drain of the first transistor and the second transistor disposed on the fourth insulating layer in the display area; a protective film disposed on the source and the drain; a planarization layer disposed on the protective film; an anode of a light-emitting element disposed on the planarization layer in the display area; a first light-emitting unit of the light-emitting element disposed on the anode; a charge-generating layer of the light-emitting element disposed on the first light-emitting unit, the charge-generating layer constituting a common node; a second light-emitting unit of the light-emitting element disposed on the charge-generating layer; and a cathode of the light-emitting element disposed on the second light-emitting unit.

[0032] The display device may further include: a connection transistor located in the non-display area, the connection transistor including a third semiconductor layer disposed on the first buffer layer, a gate disposed on the first insulating layer, and a third source and a third drain disposed on the fourth insulating layer.

[0033] The third source can be connected to the anode reset voltage line, and the third drain can be connected to the common node reset voltage line.

[0034] The display device may further include a common node reset electrode disposed on a planarization layer in the non-display area, the common node reset electrode being connected to the common node reset voltage line through a contact hole.

[0035] The charge generation layer can extend from the display area to the non-display area and can be connected to the common node reset electrode through a contact hole in the non-display area.

[0036] The common node reset electrode may also be disposed in the display area and can be connected to the charge generation layer and the common node reset voltage line through at least one contact hole in the display area.

[0037] The planarization layer may include a first planarization layer and a second planarization layer disposed on the first planarization layer, and the common node reset voltage line and the anode reset voltage line may include a first conductive layer disposed on the first planarization layer and a second conductive layer disposed on the fourth insulating layer and connected to the first conductive layer through a contact hole. Attached Figure Description

[0038] Figure 1 This is a block diagram illustrating the configuration of a display device according to an embodiment;

[0039] Figure 2 It is a circuit diagram of the pixels according to the implementation method;

[0040] Figure 3 This is a circuit diagram of a pixel according to another embodiment;

[0041] Figure 4 It shows the basis Figure 2 A timing diagram of the driving method for the implementation of the pixels shown;

[0042] Figure 5 This is a diagram showing the structure of a light-emitting element according to an embodiment;

[0043] Figure 6 This is a plan view showing the configuration of the display panel according to an embodiment;

[0044] Figure 7 yes Figure 6 An enlarged plan view of region A in the image;

[0045] Figure 8 It is shown Figure 6 A block diagram of the configuration of the gate drivers in the diagram;

[0046] Figure 9 This is a cross-sectional view showing the stacked structure of the display device according to an embodiment;

[0047] Figure 10 This is a cross-sectional view showing the stacked structure of a display device according to another embodiment; and

[0048] Figures 11 to 13 It shows the formation Figure 10 A diagram showing the contact area method. Detailed Implementation

[0049] In the following description, embodiments will be described with reference to the accompanying drawings. In the specification, when a component (or region, layer, portion, etc.) is referred to as "on another component," "connected to" another component, or "joined to" another component, it means that it can be directly connected / joined to the other component, or a third component can be disposed therein.

[0050] The same reference numerals denote the same components. Furthermore, in the accompanying drawings, the thickness, scale, and dimensions of the components are exaggerated for the purpose of effectively describing the technical content. The term "and / or" is considered to include one or more combinations that can be defined by the associated components.

[0051] The terms "first," "second," etc., are used to describe various components, but the components are not limited by these terms. These terms are only used to distinguish one component from another. For example, without departing from the scope of the invention, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

[0052] Terms such as “below,” “on the lower side,” “above,” and “on the upper side” are used to describe the relationships between the components shown in the accompanying drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0053] It will be further understood that the terms “comprising”, “having”, etc., are intended to indicate the presence of the described features, numbers, steps, operations, components, parts or combinations thereof, but are not intended to exclude the presence or possibility of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0054] Figure 1 This is a block diagram illustrating the configuration of a display device according to an embodiment.

[0055] Reference Figure 1 The display device 1 includes a timing controller 10, a gate driver 20, a data driver 30, a power supply unit 40, and a display panel 50.

[0056] The timing controller 10 can receive video signals RGB and control signals CS from an external host system, etc. The video signals may include multiple grayscale levels of data. The control signals CS may include a horizontal synchronization signal, a vertical synchronization signal, and a master clock signal.

[0057] The timing controller 10 can process the video signal RGB and the control signal CS into operating conditions suitable for the display panel 60, and can generate and output image data DATA, gate drive control signal CONT1, light emission drive control signal CONT2, data drive control signal CONT3 and power control signal CONT4.

[0058] The gate driver 20 may include a scan drive circuit 20A, which generates a scan signal based on a gate drive control signal CONT1 received from the timing controller 10. The scan drive circuit 20A can provide the generated scan signal to the pixel PX via multiple scan lines GL. In one embodiment, a single pixel PX may be configured to receive multiple scan signals with different waveforms. In this case, the scan drive circuit 20A can provide multiple scan signals to the pixel PX via corresponding scan lines GL.

[0059] The gate driver 20 may further include a light-emitting driving circuit 20B, which generates a light-emitting control signal based on the light-emitting driving control signal CONT2 received from the timing controller 10. The light-emitting driving circuit 20B provides the generated light-emitting control signal to the pixel PX via the light-emitting line EL.

[0060] The gate driver 20 can be configured as a gate-in-panel (GIP) implemented on the display panel 50. The gate driver 20 can be disposed on one side of the display panel 50, or, as shown, on both sides (e.g., left and right sides) of the display panel 50. Depending on the driving method, panel design method, etc., the gate driver 20 can be disposed on both sides (e.g., left and right sides) of the display panel 50, as shown; or it can be connected to two or more of the four sides of the display panel 50.

[0061] The data driver 30 can generate a data signal based on the image data DATA output from the timing controller 10 and the data drive control signal CONT3. The data driver 30 can provide the generated data signal to the pixel PX through multiple data lines DL.

[0062] The power supply unit 40 can generate a high-potential driving voltage ELVDD and a low-potential driving voltage ELVSS to be supplied to the display panel 50 based on the power control signal CONT4. The power supply unit 40 can provide the generated driving voltages ELVDD and ELVSS to the pixel PX through the corresponding voltage lines PL1 and PL2. In addition, the power supply unit 40 can also generate the initialization voltage Vini and the on-vias voltage Vobs required to drive the pixel PX (see...). Figure 2 ) and / or the anode reset voltage VAR, and provide it to the pixel PX through the corresponding voltage lines ViniL, VobsL and VARL.

[0063] Display panel 50 includes a plurality of pixels PX (or subpixels) arranged thereon. For example, the pixels PX may be arranged in a matrix on display panel 50. Pixels PX arranged in a single pixel row are connected to the same scan line GL and light emission line EL, and pixels PX arranged in a single pixel column are connected to the same data line DL. In response to a light emission control signal applied through the light emission line EL, the pixels PX may emit light with a brightness corresponding to the scan signal and data signal provided through the scan line GL and the data line DL.

[0064] In one implementation, each pixel PX can display one of a variety of colors, such as red, green, or blue. In another implementation, each pixel PX can display one of a variety of colors, such as cyan, magenta, or yellow. In various implementations, each pixel PX can display one of a variety of colors, such as red, green, blue, or white.

[0065] In one embodiment, one or more optical zones OA1 and OA2 may be arranged on the display panel 50. The one or more optical zones OA1 and OA2 may be arranged overlapping with one or more optoelectronic devices such as imaging devices (e.g., cameras or image sensors), proximity sensors, or illuminance sensors.

[0066] To operate the optoelectronic device, one or more optical regions OA1 and OA2 may include a light-transmitting structure having a transmittance above a certain level. The light-transmitting structure can be formed by patterning a cathode in an area where no pixels PX are disposed. The cathode can be patterned by laser removal or by selective formation using a cathode deposition anti-cathode layer.

[0067] Optionally, the light transmission structure can be formed by separating the light-emitting elements within the pixel PX. In this embodiment, the light-emitting elements of the pixel PX are located in the optical regions OA1 and OA2, and a plurality of transistors constituting the pixel PX are arranged around the optical regions OA1 and OA2. The light-emitting elements and the pixel can be electrically connected through a transparent metal layer.

[0068] The number of pixels per unit area in one or more optical regions OA1 and OA2 may be less than the number of pixels per unit area in the remaining regions other than optical regions OA1 and OA2. In other words, the resolution of one or more optical regions OA1 and OA2 may be lower than the resolution of the remaining regions.

[0069] Figure 2 This is a circuit diagram of the pixel according to the implementation method. Figure 3 This is a circuit diagram of a pixel according to another embodiment.

[0070] Reference Figure 2According to the embodiments, the pixel PX may include a control circuit for controlling the amount of drive current applied to the light-emitting element LD through the drive transistor DT. The control circuit is connected to the drive transistor DT and the light-emitting element LD. For example, the control circuit may include transistors T1 to T7 and a storage capacitor Cst.

[0071] The first electrode (e.g., the source) of the driving transistor DT is connected to the data line DL via a first node N1, and the second electrode (e.g., the drain) is connected to the light-emitting element LD via a third node N3. The gate of the driving transistor DT is configured to be supplied with a high-potential driving voltage ELVDD via a second node N2 (connected to the high-potential driving voltage line PL1). The driving transistor DT can be turned on based on the voltage difference between the second node N2 and the first node N1 (i.e., the gate-source voltage) to control the amount of driving current flowing through the light-emitting element LD.

[0072] The first electrode of the first transistor T1 is connected to the data line DL, and the second electrode is connected to the source of the driving transistor DT through the first node N1. The gate of the first transistor T1 is connected to the second scan line GL2 and can receive the second scan signal SC2. The first transistor T1 can be turned on according to the second scan signal SC2 applied to the second scan line GL2, and can transmit the data voltage Vdata applied to the data line DL to the first node N1. The first transistor T1 can be referred to as a switching transistor.

[0073] The second transistor T2 is connected between the second node N2 and the third node N3. The gate of the second transistor T2 is connected to the first scan line GL1 and can receive the first scan signal SC1. The second transistor T2 can be turned on according to the first scan signal SC1 applied to the first scan line GL1 and electrically connect the gate and drain of the driving transistor DT. The second transistor T2 can be referred to as a compensation transistor.

[0074] The first electrode of the third transistor T3 is connected to the second node N2, and the second electrode is configured to receive the initialization voltage Vini (connected to the initialization voltage line ViniL). The gate of the third transistor T3 is connected to the fourth scan line GL4 and can receive the fourth scan signal SC4. The third transistor T3 can be turned on according to the fourth scan signal SC4 applied to the fourth scan line GL4, and the initialization voltage Vini is applied to the gate of the driving transistor DT. The third transistor T3 can be referred to as the initialization transistor.

[0075] The first electrode of the fourth transistor T4 is configured to receive a high-potential drive voltage ELVDD (connected to the high-potential drive voltage line PL1), and the second electrode is connected to the drive transistor DT via the first node N1. The gate of the fourth transistor T4 is connected to the light-emitting line EL to receive the light-emitting signal EM. In response to the light-emitting signal EM applied to the light-emitting line EL, the fourth transistor T4 can connect the high-potential drive voltage line PL1 and the drive transistor DT.

[0076] The first electrode of the fifth transistor T5 is connected to the driving transistor DT via the third node N3, and the second electrode is connected to the light-emitting element LD via the fourth node N4. The gate of the fifth transistor T5 is connected to the light-emitting line EL to receive the light-emitting signal EM. In response to the light-emitting signal EM applied to the light-emitting line EL, the fifth transistor T5 can connect the driving transistor DT and the light-emitting element LD.

[0077] When the fourth transistor T4 and the fifth transistor T5 are turned on, a current path is formed between the high-potential drive voltage ELVDD and the low-potential drive voltage ELVSS, and the drive current flows through the light-emitting element LD, causing the light-emitting element LD to emit light. The fourth transistor T4 and the fifth transistor T5 can be referred to as light-emitting transistors.

[0078] The first electrode of the sixth transistor T6 is configured to receive the anode reset voltage VAR (connected to the anode reset voltage line VARL), and the second electrode is connected to the fourth node N4. The gate of the sixth transistor T6 is connected to the third scan line GL3 to receive the third scan signal SC3. In response to the third scan signal SC3 applied to the third scan line GL3, the sixth transistor T6 can be turned on and apply the anode reset voltage VAR to the anode of the light-emitting element LD. The sixth transistor T6 may be referred to as the anode reset transistor.

[0079] The first electrode of the seventh transistor T7 is connected to the first node N1, and the second electrode is configured to receive the on-bias voltage Vobs (connected to the on-bias voltage line VobsL). The gate of the seventh transistor T7 is connected to the third scan line GL3 to receive the third scan signal SC3. In response to the third scan signal SC3 applied to the third scan line GL3, the seventh transistor T7 can be turned on and apply the on-bias voltage Vobs to the source of the driving transistor DT. The seventh transistor T7 may be referred to as the on-bias transistor.

[0080] The storage capacitor Cst is connected between the high-potential drive voltage line PL1 and the second node N2. The storage capacitor Cst stores the voltage corresponding to the voltage difference between the high-potential drive voltage ELVDD and the voltage of the second node N2, and maintains the stored voltage during a frame period to stabilize the voltage of the gate of the drive transistor DT (i.e., the second node N2).

[0081] The light-emitting element (LD) connects its anode to the fourth node N4 and its cathode to the low-potential drive voltage ELVSS (connected to the low-potential drive voltage line PL2). When the drive transistor DT, the fourth transistor T4, and the fifth transistor T5 are turned on, a current path is formed between the high-potential drive voltage ELVDD and the low-potential drive voltage ELVSS to allow drive current to flow through the LD. The LD emits light with a brightness corresponding to the amount of drive current applied.

[0082] In one embodiment, the light-emitting element (LD) may have a series structure, wherein multiple light-emitting units LD1 and LD2 are connected in series. By having multiple stacked light-emitting units LD1 and LD2, the light-emitting element LD can improve luminescence purity and efficiency. Adjacent light-emitting units LD1 and LD2 can be connected through a common node NC. The common node NC may be composed of a charge generation layer. (See below for further details.) Figure 5 The structure of the charge generation layer used to form the common node NC and the light-emitting units LD1 and LD2 is described in more detail.

[0083] In one implementation, the common node NC may be connected to a common node reset voltage line VcglL for applying the common node reset voltage Vcg1. The common node reset voltage Vcgl may be, for example, the same as the anode reset voltage VAR, but is not limited thereto.

[0084] When the common node reset voltage Vcgl is the same as the anode reset voltage VAR, the common node reset voltage line VcglL can be electrically connected to the anode reset voltage line VARL. For example, the common node reset voltage line VcglL and the anode reset voltage line VARL can be electrically connected in the display panel 50 (see...). Figure 1 The connection structure between the common node reset voltage line VcglL and the anode reset voltage line VARL will be described in more detail later with reference to the accompanying drawings.

[0085] In the illustrated embodiment, the light-emitting element LD consists of two light-emitting units LD1 and LD2. However, in other embodiments, the light-emitting element LD may include a greater number of light-emitting units, such as... Figure 3 As shown. In this case, the light-emitting units LD1 and LD2 in each adjacent light-emitting element LD can be connected through common nodes NC1 and NC2 respectively. In addition, multiple common nodes NC1 and NC2 can be connected together to the common node reset voltage line VcglL.

[0086] exist Figure 2 and Figure 3In the illustrated embodiment, the pixel PX may include a low-temperature polycrystalline silicon (LTPS) transistor. The LTPS transistor includes a gate, a source, and a drain. The LTPS transistor has an active layer formed of polycrystalline silicon. The LTPS transistor may be configured as a P-type transistor. This LTPS transistor has high electron mobility, thereby providing fast drive characteristics.

[0087] In one embodiment, the driving transistor DT may be composed of an LTPS transistor. Additionally, at least one of the transistors T2 to T6 (e.g., T4, T5, T6, and T7) requiring fast driving characteristics may be composed of LTPS transistors. Specifically, since the fourth transistor T4 and the fifth transistor T5 are composed of LTPS transistors, when the light-emitting signal EM is applied at a conduction level, the fourth transistor T4 and the fifth transistor T5 can quickly conduct, thereby accelerating the light-emitting response of the light-emitting element LD.

[0088] Furthermore, in one embodiment, the pixel PX can be a hybrid type further comprising an oxide semiconductor transistor. The oxide semiconductor transistor includes a gate, a source, and a drain. The oxide semiconductor transistor has an active layer formed of oxide semiconductor. Here, the oxide semiconductor can be configured as an amorphous or crystalline oxide semiconductor. The oxide semiconductor transistor can be configured as an N-type transistor. Compared to LTPS transistors, oxide semiconductor transistors allow for low-temperature processing and have lower charge mobility. Such oxide semiconductor transistors exhibit excellent off-current characteristics.

[0089] exist Figure 2 and Figure 3 In this embodiment, the second transistor T2 and the third transistor T3 are composed of LTPS transistors. However, the embodiment is not limited to this.

[0090] Figure 4 It shows the basis Figure 2 The timing diagram shows the driving method of the implementation of the pixel shown.

[0091] Refer to together Figure 2 and Figure 4 A frame may include a first conduction bias and anode reset period t1, an initialization period t2, a sampling and programming period t3, a second conduction bias and anode reset period t4, and an emission period t5.

[0092] During the first conduction bias and anode reset period t1, the source voltage of the driving transistor DT is biased, and the anode voltage of the light-emitting element LD is reset.

[0093] Specifically, during the first conduction bias and anode reset period t1, a first scan signal SC1 with a conduction level (e.g., high level) is applied, thereby turning on the second transistor T2 and electrically connecting the second node N2 and the third node N3.

[0094] Additionally, during the first conduction bias and anode reset period t1, a third scan signal SC3 with a conduction level (e.g., low level) is applied, and the sixth transistor T6 and the seventh transistor T7 are turned on, applying the anode reset voltage VAR and the conduction bias voltage Vobs to the anode of the light-emitting element LD and the source of the driving transistor DT, respectively. The voltage at the source of the driving transistor DT is set to the conduction bias voltage Vobs, thereby reducing the conduction bias stress of the driving transistor DT.

[0095] In one implementation, the anode reset voltage VAR may be the same or different for each pixel PX. For example, for a pixel PX displaying red (hereinafter referred to as a red pixel), the anode reset voltage VAR may be approximately 0.7V. For a pixel PX displaying green or blue (hereinafter referred to as a green pixel or blue pixel), the anode reset voltage VAR may be approximately 1.8V. However, the implementation is not limited to this.

[0096] During the initialization period t2, the voltage of the master node of pixel PX is initialized.

[0097] Specifically, during the initialization period t2, the third scan signal SC3 switches to the cutoff level (e.g., high level), thereby turning off the sixth transistor T6 and the seventh transistor T7.

[0098] Furthermore, during the initialization period t2, a fourth scan signal SC4 with a conduction level (e.g., high level) is applied, causing the third transistor T3 to conduct and applying the initialization voltage Vini to the gate of the driving transistor DT. The initialization voltage Vini can be further applied to the drain of the driving transistor DT through the second transistor T2, which is in the conduction state. The initialization voltage Vini can be a low-level positive voltage and can correspond to the voltage of black brightness, but is not limited to this.

[0099] The storage capacitor Cst stores the voltage difference between the high-potential drive voltage ELVDD and the initialization voltage Vini (i.e., the voltage of the second node N2).

[0100] During the sampling and programming period t3, the threshold voltage Vth of the driving transistor DT is sampled, and the data voltage Vdata is programmed into the pixel PX.

[0101] Specifically, during the sampling and programming period t3, the fourth scan signal SC4 is switched to the cutoff level (e.g., low level), thereby turning off the third transistor T3.

[0102] Additionally, during the sampling and programming period t3, a second scan signal SC2 with a conduction level (e.g., low level) is applied, causing the first transistor T1 to turn on, and the data voltage Vdata can be applied to the source of the driving transistor DT. The gate and drain of the driving transistor DT are electrically connected through the second transistor T2, which is in the on state, and the drain of the driving transistor DT is floating, resulting in a voltage-variable state (drain follower state).

[0103] During the sampling and programming period t3, the gate-source voltage Vgs of the driving transistor DT, which is the voltage difference between the data voltage Vdata and the initialization voltage Vini, is set below the threshold voltage Vth, i.e., it is in the on condition. Therefore, the driving transistor DT is turned on, and it can provide source-drain current to the drain until the gate-source voltage Vgs reaches the threshold voltage Vth of the driving transistor DT. The voltage at the gate, i.e., the second node N2, increases from the initialization voltage Vini and converges to the sum of the data voltage Vdata and the threshold voltage Vth, i.e., the voltage Vdata + Vth.

[0104] The storage capacitor Cst stores the voltage difference between the high-potential drive voltage ELVDD and the voltage of the second node N2, i.e., ELVDD - (Vdata + Vth). During the sampling and programming period t3, the voltage programmed on the gate of the drive transistor DT is the voltage compensated by the threshold voltage Vth.

[0105] During the second conduction bias and anode reset period t4, the first scan signal SC1 and the second scan signal SC2 are switched to the cutoff level, and the first transistor T1 and the second transistor T2 are turned off.

[0106] Additionally, during the second conduction bias and anode reset period t4, a third scan signal SC3 at a conduction level (e.g., low level) is applied, and the sixth transistor T6 and the seventh transistor T7 are turned on, such that the anode reset voltage VAR and the conduction bias voltage Vobs are applied to the anode of the light-emitting element LD and the source of the driving transistor DT, respectively. The conduction bias voltage Vobs applied during the second conduction bias and anode reset period t4 may be the same as or different from the conduction bias voltage Vobs applied during the first conduction bias and anode reset period t1.

[0107] During the light emission period t5, the conducting light-emitting element LD can emit light with a brightness corresponding to the programmed voltage. Specifically, during the light emission period t5, the third scan signal SC3 switches to the cutoff level, and the light emission signal EM can be applied at a conduction level (e.g., a low level).

[0108] In response to the light-emitting signal EM, when the fourth transistor T4 and the fifth transistor T5 are turned on, the drive current flows from the high-potential drive voltage ELVDD through the drive transistor DT to the light-emitting element LD. Due to the drive current, the drain voltage of the drive transistor DT rises to the operating point voltage of the light-emitting element LD. At this time, the gate voltage is maintained at the voltage programmed by the storage capacitor Cst. The light-emitting element LD emits light in response to the drive current when the drain voltage of the drive transistor DT becomes equal to the operating point voltage. Here, the voltage programmed at the gate of the drive transistor DT is based on the data voltage Vdata compensated by the threshold voltage Vth. Therefore, degradation of the drive transistor DT can be compensated.

[0109] In another embodiment, the common node NC of the light-emitting units LD1 and LD2, which connect the light-emitting elements LD in different pixels PX, can be connected to the common node reset voltage line VcglL. The common node reset voltage line VcglL can be configured to apply the common node reset voltage Vcg1 to the common node NC when the anode reset voltage VAR is applied to the anode of the light-emitting element LD, which is the fourth node N4.

[0110] Specifically, during the first conduction bias and anode reset period t1 and the second conduction bias and anode reset period t4, the sixth transistor T6 can respond to the third scan signal SC3 at the conduction level and apply the anode reset voltage VAR to the anode. The common node reset voltage line VcglL can be configured to apply the common node reset voltage Vcgl to the common node NC when the third scan signal SC3 is applied at the conduction level.

[0111] In one embodiment, the common node reset voltage Vcgl can be the same voltage as the anode reset voltage VAR. In this embodiment, the common node reset voltage line VcglL can be electrically connected to the anode reset voltage line VARL in response to the third scan signal SC3 during the first conduction bias and anode reset period t1 and the second conduction bias and anode reset period t4. Thus, the anode reset voltage VAR can be applied to the common node NC as the common node reset voltage Vcgl.

[0112] Figure 5 This is a diagram showing the structure of a light-emitting element according to an embodiment.

[0113] Reference Figure 5According to one embodiment, the light-emitting element LD may have a series structure, wherein two light-emitting units 220 and 240 are connected in series to emit light. Specifically, the light-emitting element LD includes a first electrode 210 and a second electrode 250 arranged facing each other, a first light-emitting unit 220 and a second light-emitting unit 240 disposed between the first electrode 210 and the second electrode 250, and a charge generation layer 230 disposed between the first light-emitting unit 220 and the second light-emitting unit 240.

[0114] Here, the first electrode 210 can be an anode, and the second electrode 250 can be a cathode. In addition, the first light-emitting unit 220 can be disposed adjacent to the first electrode 210, and the second light-emitting unit 240 can be disposed adjacent to the second electrode 250.

[0115] The first light-emitting unit 220 may include a first hole transport layer 221 and a first light-emitting layer 222 disposed on the first hole transport layer 221. The first electrode 210, the first hole transport layer 221 and the first light-emitting layer 222 may be stacked sequentially.

[0116] The second light-emitting unit 240 may include a second hole transport layer 241 and a second electron transport layer 243 arranged facing each other, and a second light-emitting layer 242 disposed between the second hole transport layer 241 and the second electron transport layer 244. The second hole transport layer 241, the second light-emitting layer 242, the second electron transport layer 243, and the second electrode 250 may be stacked sequentially.

[0117] According to an embodiment, a hole injection layer may be further disposed between the first electrode 210 and the first hole transport layer 221. An electron transport layer may be further disposed between the first light-emitting layer 222 and the charge generation layer 230. In addition, an electron injection layer may be further disposed between the second electron transport layer 243 and the second electrode 250.

[0118] The first light-emitting layer 222 and the second light-emitting layer 242 may include a variety of light-emitting materials that emit light in different colors. For example, each of the first light-emitting layer 222 and the second light-emitting layer 242 may include a blue light-emitting material (B), a red light-emitting material (R), and a green light-emitting material (G). Each light-emitting material (R, G, B) may be formed in a region within the light-emitting layers 222 and 242. A charge-generating layer 230 is disposed between the light-emitting units 220 and 240 to regulate the charge between the light-emitting units 220 and 240, thereby achieving charge balance. The charge-generating layer 230 may include a negative charge-generating layer 231 (n-type charge-generating layer) adjacent to the first light-emitting unit 220 to provide electrons to the first light-emitting unit 220, and a positive charge-generating layer 232 (p-type charge-generating layer) adjacent to the second light-emitting unit 240 to provide holes to the second light-emitting unit 240. The luminous efficiency of the light-emitting element LD can be further improved by the negative charge-generating layer (n-type charge-generating layer) 231 and the positive charge-generating layer (p-type charge-generating layer) 232.

[0119] The charge generation layer 230 can be formed from a metal such as aluminum (Al) or a transparent conductive material such as indium tin oxide (indium tin oxide, ITO). Alternatively, the charge generation layer 230 can be formed by doping n-type and p-type materials into an organic material.

[0120] When a voltage is applied to the first electrode 210 and the second electrode 250 of the light-emitting element LD as described above, electrons are generated in the negative charge generation layer 231 and move to the first light-emitting unit 220, while holes are injected from the first electrode 210 into the first light-emitting unit 220, whereby the holes combine with the electrons of the first light-emitting unit 220. This allows the first light-emitting unit 220 to emit light.

[0121] Similarly, electrons are injected from the second electrode 250 into the second light-emitting unit 240, while holes are generated in the positive charge generation layer 232 and move to the second light-emitting unit 240, where the holes combine with the electrons in the second light-emitting unit 240. This allows the second light-emitting unit 240 to emit light.

[0122] Figure 6 This is a block diagram illustrating the configuration of a display panel according to an embodiment.

[0123] Reference Figure 6 The display panel 50 may include: a display area AA in which an image is displayed; and a non-display area NA surrounding the display area AA, in which no image is displayed.

[0124] The display area AA has pixels PX (see...) Figure 1 An array of ).

[0125] The non-display area NA may include at least a portion of the drive unit that is mounted or connected. For example, the gate driver 20 may be placed in the non-display area NA on one side of the display area AA, or, as shown, in the non-display areas NA on both sides (e.g., the left and right sides). The data driver 30 may be mounted on a flexible film SF and connected to one side of the display panel 50 using a chip-on-film (COF) or chip-on-plastic (COP) method. In one embodiment, the data driver 30 may be connected to the display panel 50 on the side where the gate driver 20 is not located.

[0126] The non-display area NA may include voltage lines that apply driving voltages to pixels PX. These voltage lines may include, for example, a high-potential drive voltage line PL1, a low-potential drive voltage line PL2, a conduction bias voltage line VobsL, an initialization voltage line ViniL, an anode reset voltage line VARL, and a common node reset voltage line VcglL. Figure 1 and Figure 2 As shown. In Figure 6 For ease of explanation, only the low-potential drive voltage line PL2, the anode reset voltage line VARL, and the common node reset voltage line VcglL are shown.

[0127] The low-potential drive voltage line PL2 is disposed at the edge of the non-display area NA and may be disposed outside the gate driver 20. The low-potential drive voltage line PL2 is formed in a closed loop shape along the edge of the display panel 50 and may surround at least three sides of the display area AA. For example, the low-potential drive voltage line PL2 may extend from the internal wiring of the flexible film in which the data driver 30 is mounted on one side of the display panel 50, extending to surround three sides of the display area AA, and may be formed to reconnect with the internal wiring of the flexible film on the same side of the display panel 50.

[0128] The anode reset voltage line VARL and the common node reset voltage line VcglL are disposed in the non-display area NA and may be disposed inside the gate driver 20. That is, the anode reset voltage line VARL and the common node reset voltage line VcglL may be disposed between the gate driver 20 and the display area AA. The anode reset voltage line VARL and the common node reset voltage line VcglL are formed in a closed loop shape along the edge of the display panel 50 and may surround at least three sides of the display area AA.

[0129] For example, the anode reset voltage line VARL can extend from the internal wiring of the flexible film in which the data driver 30 is mounted on one side of the display panel 50, extending to surround the three sides of the display area AA, and can be formed to reconnect with the internal wiring of the flexible film on the same side of the display panel 50.

[0130] For example, the common node reset voltage line VcglL can be formed as a closed loop shape around all four sides of the display area AA.

[0131] The anode reset voltage line VARL and the common node reset voltage line VcglL can be configured to be electrically connected at least in some portions of the non-display area NA. For example, the anode reset voltage line VARL and the common node reset voltage line VcglL can be electrically connected at one or more points by at least one switching element. The switching element can be, for example, a transistor.

[0132] Figure 7 yes Figure 6 An enlarged plan view of region A in the image.

[0133] For reference Figure 6 As described, the anode reset voltage line VARL and the common node reset voltage line VcglL are configured to be electrically connected at at least one point. For example, the anode reset voltage line VARL and the common node reset voltage line VcglL can be connected via one or more connection transistors Tc.

[0134] The first electrode of the connecting transistor Tc is connected to the anode reset voltage line VARL, and the second electrode is connected to the common node reset voltage line VcglL. The gate of the connecting transistor Tc is connected to the third scan line GL3, which can receive the third scan signal SC3. The connecting transistor Tc conducts when the third scan signal SC3, which is at the on level, is applied to the third scan line GL3, thereby electrically connecting the anode reset voltage line VARL and the common node reset voltage line VcglL. When the third scan signal SC3 is applied at the on level during the anode reset period within a frame, the sixth transistor T6 can conduct and apply the anode reset voltage VAR to the anode. The connecting transistor Tc can then conduct and electrically connect the anode reset voltage line VARL and the common node reset voltage line VcglL, which can apply the anode reset voltage VAR to the common node NC.

[0135] The connecting transistor Tc is controlled such that when the seventh transistor T7 is turned on, a bias voltage Vobs is applied to the anode of the light-emitting element LD, and a common node reset voltage Vcgl is applied to the common node NC. In other words, the connecting transistor Tc is configured to conduct together with the seventh transistor T7 when T7 is turned on, thereby connecting the anode reset voltage line VARL and the common node reset voltage line VcglL. Therefore, the connecting transistor Tc can be formed using the same type as the seventh transistor T7, such as a P-type transistor, so that it conducts together with the seventh transistor T7 in response to the third scan signal SC3.

[0136] Figure 8 It is shown Figure 6 A block diagram of the configuration of the gate driver in the diagram.

[0137] Reference Figure 8 The display panel 50 may include a display area AA for displaying images and a non-display area located around the display area AA in which no images are displayed.

[0138] like Figure 1 As shown, an array of pixels PX is arranged in the display area AA. The non-display area may include at least a portion of the driving units that are mounted or connected. For example, gate drivers 20 may be located on one side of the display area AA, or, as shown, on both sides of the non-display area (e.g., left and right). Gate drivers 20 arranged on both sides of the non-display area may be configured symmetrically (in a mirror image). In the following description, the configuration will be based on the gate driver 20 arranged on the left side of the display area AA.

[0139] The gate driver 20 may consist of first to fifth shift registers 21 to 25.

[0140] The first to fourth shift registers 21 to 24 constitute the scan drive circuit 20A (see...). Figure 1 ), and is configured to output scan signals SC1, SC2, SC3 and SC4 (see Figure 2 For example, the first shift register 21 can sequentially output the first scan signal SC1 through the first scan line, the second shift register 22 can sequentially output the second scan signal SC2 through the second scan line, the third shift register 23 can sequentially output the third scan signal SC3 through the third scan line, and the fourth shift register 24 can sequentially output the fourth scan signal SC4 through the fourth scan line.

[0141] The first to fourth shift registers 21 to 24 can each be composed of stage circuits connected in a subordinate manner. Each stage circuit can be connected to the corresponding scan line and can output scan signals SC1, SC2, SC3 and SC4 to the scan line.

[0142] The first scan signal SC1, the second scan signal SC2, the first scan signal SC3, and the fourth scan signal SC4 can be used to drive at least one transistor disposed in pixel PX. For example, the first to fourth scan signals SC1, SC2, SC3, and SC4 can be used to transmit image data DATA (see...) Figure 1 In the programming of pixel PX, initialize the voltage stored in pixel PX, or compensate for the characteristics of the circuit elements.

[0143] The fifth shift register 25 constitutes the light-emitting driver circuit 20B (see...) Figure 1 ), and is configured to output a light emission signal EM (see Figure 2For example, the fifth shift register 25 can output a light-emitting signal EM through a light-emitting line.

[0144] The emission signal EM can be used to drive at least one transistor disposed in pixel PX. For example, the emission signal EM can be used to control the emission of pixel PX.

[0145] Each of the first shift registers 21 to the fifth shift register 25 is driven by receiving a corresponding start signal and a corresponding clock signal via at least one start signal line and multiple clock signal lines. In this case, each clock signal may have a different phase.

[0146] The clock signals applied to the first to fourth shift registers 21 to 24 can be applied via adjacent clock signal lines, and the clock signal applied to the fifth shift register 25 can be applied via adjacent clock signal lines. For example, the first to fourth shift registers 21 to 24 can receive the first and second gate clock signals applied via adjacent clock signal lines, and the fifth shift register 25 can receive the light emission clock signal applied via adjacent clock signal lines. Here, adjacent clock signal lines can be configured as a pair.

[0147] In one embodiment, the second shift register 22 may be arranged adjacent to the display area AA. Here, the first, third, and fourth shift registers 21, 23, and 24 may be arranged sequentially away from the display area AA. In one embodiment, the fifth shift register 25 may be arranged at the outermost position.

[0148] Shift registers 21 to 25 may have the same or different areas. For example, as shown, the first shift register 21 and the second shift register 22 may have relatively large areas (widths), while the third shift register 23, the fourth shift register 24, and the fifth shift register 25 may have relatively small areas (widths). However, the implementation is not limited to this.

[0149] One or more buses may be arranged between the gate driver 20 and the display area AA. The buses may include, for example, a high-level drive voltage line PL1, a conduction bias voltage line VobsL, an initialization voltage line ViniL, and an anode reset voltage line VARL. The anode reset voltage line VARL may include, for example, an anode reset voltage line VARR connected to the red pixel and an anode reset voltage line VARGB connected to the green and blue pixels.

[0150] In one embodiment, the common node reset voltage line VcglL may be further arranged between the gate driver 20 and the display area AA. The common node reset voltage line VcglL may be electrically connected to the anode reset voltage line VARL in the non-display area. For this purpose, a connection area CA may be provided between the common node reset voltage line VcglL and the anode reset voltage line VARL. The connection area CA may include at least one switching element connected to a third scan line GL3 extending from the third shift register 23, and may selectively connect the common node reset voltage line VcglL to the anode reset voltage line VARL according to a third scan signal SC3 output via the third scan line GL3. The switching element may, for example, be a reference... Figure 7 The connection transistors are described, but not limited to them.

[0151] The bus can be connected to pixels PX arranged in the display area AA via connecting lines branching from the bus. In one embodiment, the bus can be arranged symmetrically on both sides of the display area AA. The bus can also be arranged only on one side of the display area AA, either left-right or top-bottom. At least one of the buses can be, for example, as shown in the reference. Figure 6 As explained, it extends in the non-display area to surround at least three sides of the display area AA.

[0152] The arrangement of shift registers 21 to 25 is not limited to the illustrated configuration. The arrangement of shift registers 21 to 25 can be varied within the possible range according to the specifications of display panel 50 to reduce the size of the non-display area and minimize the length and number of wiring.

[0153] Figure 9 This is a cross-sectional view showing the stacked structure of the display device according to an embodiment.

[0154] Reference Figure 9 The display panel 50 may include a display area AA where the pixel PX is located and a non-display area NA surrounding the display area AA where the driving unit is located. Such a display panel 50 may include: a substrate 101; one or more transistors TFT1, TFT2 and light-emitting elements LD disposed on the substrate 101 in the display area AA; and one or more driving units, DAM1, DAM2, DAM3 and crack stopper CS disposed on the substrate 101 in the non-display area NA.

[0155] The substrate 101 supports various components of the display panel 50. The substrate 101 may be formed of a transparent dielectric material such as glass or plastic. When made of plastic, the substrate 101 may be referred to as a plastic film or plastic substrate. For example, the substrate 101 may be in the form of a film and includes one of polyimide-based polymers, polyester-based polymers, silicone-based polymers, acrylic-based polymers, polyolefin-based polymers, and copolymers thereof, but embodiments of the present invention are not limited thereto. Furthermore, when made of plastic, the substrate 101 may be formed as a dual structure. For example, the substrate may be a dual structure with an adhesive layer between a first polyimide layer and a second polyimide layer. The substrate may also include an interlayer insulating layer made of an inorganic insulating material between the first polyimide layer and the second polyimide layer.

[0156] When the substrate 101 is made of glass, it may be referred to as a glass substrate. For example, the glass substrate may include a shielding metal 102 beneath the transistors TFT1 and TFT2 to protect them from external light or signal interference.

[0157] A first buffer layer 105 may be disposed on a substrate 101. The first buffer layer 105 may delay the diffusion of moisture and / or oxygen that can permeate the substrate 101. The first buffer layer 105 may comprise inorganic materials such as oxides and nitrides, organic materials, or inorganic-organic composites, and may be formed as a single layer or a multilayer structure. For example, the first buffer layer 105 may have a three-layer or more structure composed of silicon oxide, silicon nitride, and silicon oxide.

[0158] A shielding metal 102 may be formed between the substrate 101 and the first buffer layer 105. The shielding metal 102 may be configured to overlap with one or more of the transistors TFT1 and TFT2 to protect the transistors from external light or signal interference.

[0159] In the display area AA, transistors TFT1 and TFT2, used to drive the light-emitting element LD, can be disposed on the substrate 101. Transistors TFT1 and TFT2 drive the light-emitting element LD.

[0160] For ease of explanation, it may be included in display device 1 (see...) Figure 1 Of the various transistors in the ), only the driving transistor TFT1 (e.g., the driving transistor DT, see...) is used. Figure 2 ) and a switching transistor TFT2 (e.g., a fourth transistor T4, see Figure 2 )exist Figure 9As shown, transistors TFT1 and TFT2 are not limited to this. Transistor TFT1 can be one of a driving transistor, a compensation transistor, and an anode reset transistor, and transistor TFT2 can be another of a driving transistor, a compensation transistor, and an anode reset transistor. Below, examples of transistors TFT1 and TFT2 having a coplanar structure will be described, but transistors TFT1 and TFT2 can also be implemented in various other structures, such as an interleaved structure.

[0161] The first transistor TFT1 may include a semiconductor layer 111, a gate 112, and a source and drain 113 disposed on the first buffer layer 105.

[0162] Semiconductor layer 111 can be made of polycrystalline silicon (p-Si), and in this case, specific regions may be doped with impurities. Alternatively, semiconductor layer 111 can be made of amorphous silicon (a-Si) or various organic semiconductor materials such as pentacene. Semiconductor layer 111 can also be made of oxide materials. The embodiments are not limited to the materials constituting semiconductor layer 111. Semiconductor layer 111 may be referred to as an active layer.

[0163] Semiconductor layer 111 may form a channel during operation of the first transistor TFT1. Semiconductor layer 111 may include a channel region, a source region, and a drain region. The channel region may be configured to overlap with gate 112 and may be formed between the source region and the drain region. The source region and the drain region may be connected to the source and drain 113 via contact holes.

[0164] The gate 112 may be disposed on top of the semiconductor layer 111, overlapping with the channel region of the semiconductor layer 111. The gate 112 may be formed as a single layer or multiple layers of various conductive materials such as magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au) or their alloys, but is not limited thereto.

[0165] A first insulating layer 110 may be disposed between the semiconductor layer 111 and the gate 112. The first insulating layer 110 may serve as a layer that insulates the semiconductor layer 111 and the gate 112, and may be made of an insulating material. For example, the first insulating layer 110 may be formed as a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0166] The source and drain 113 are electrically connected to the source and drain regions of the semiconductor layer 111, respectively, and are spaced apart. The source and drain 113 may be formed as a single layer or multiple layers of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), or alloys thereof, but are not limited thereto.

[0167] At least one insulating layer may be inserted between the source and drain 113 and the gate 112. For example, a second insulating layer 115, a second buffer layer 120, a third insulating layer 125, and a fourth insulating layer 130 may be inserted between the source and drain 113. Here, the second insulating layer 115 may be formed to cover the gate 112.

[0168] The second transistor TFT2 may include a semiconductor layer 121, a gate 122, and a source and drain 123 disposed on the second buffer layer 120.

[0169] The semiconductor layer 121 may be formed of oxide semiconductor, amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or various organic semiconductors (such as pentacene), but is not limited thereto. The semiconductor layer 121 may be referred to as the active layer.

[0170] Semiconductor layer 121 may form a channel during operation of the second transistor TFT2. Semiconductor layer 121 may include a channel region, a source region, and a drain region. The channel region may be configured to overlap with gate 122 and may be formed between the source region and the drain region. The source region and the drain region may be connected to the source and drain 123 via contact holes.

[0171] The gate 122 may be disposed on top of the semiconductor layer 121 and overlap with the channel region of the semiconductor layer 121. The gate 122 may be formed as a single layer or multiple layers of various conductive materials such as magnesium (Mg), aluminum (Al), nickel (Ni), chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au) or their alloys, but is not limited thereto.

[0172] A third insulating layer 125 may be disposed between the semiconductor layer 121 and the gate 122. The third insulating layer 125 may be a layer for insulating the semiconductor layer 121 from the gate 122, and may be made of an insulating material. For example, the third insulating layer 125 may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0173] The source and drain 123 are electrically connected to the source and drain regions of the semiconductor layer 121, respectively, and are spaced apart. The source and drain 123 may be formed as a single layer or multiple layers of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), or alloys thereof, but are not limited thereto.

[0174] At least one insulating layer may be inserted between the source and drain 123 and the gate 122. For example, a second insulating layer 115, a second buffer layer 120, a third insulating layer 125, and a fourth insulating layer 130 may be inserted between the source and drain 123. The fourth insulating layer 130 may be formed to cover the gate 122.

[0175] The insulating layers 110, 115, 125 and 130 may be composed of silicon oxide SiOx, silicon nitride SiNx or multiple layers thereof.

[0176] A protective film 135 and a planarization layer 140 can be formed on transistors TFT1 and TFT2. The protective film 135 may consist of silicon oxide (SiOx), silicon nitride (SiNx), or multiple layers thereof. The planarization layer 140 may be provided to mitigate steps in the underlying components. The planarization layer 140 may be made of organic materials such as polyimide, benzocyclobutene resins, or acrylates. The planarization layer 140 may be formed as a multilayer, as shown. In the illustrated embodiment, the planarization layer 140 consists of two layers 141 and 142, but in various other embodiments, the planarization layer 140 may consist of three or more layers. One or more conductive layers may be formed between the multiple planarization layers 140.

[0177] For example, a connection electrode 143 may be formed between the first planarization layer 141 and the second planarization layer 142. The connection electrode 143 may be connected to the drain 113 of the transistor TFT1 through connection electrode contact holes passing through the protective film 135 and the first planarization layer 141. The connection electrode 143 may be made of a material having a low resistivity similar to or the same as that of the drain 113, but is not limited thereto. The common node reset voltage line VcglL and the anode reset voltage line VARL may include a first conductive layer disposed on the first planarization layer 141 and a second conductive layer disposed on the fourth insulating layer 130 and connected to the first conductive layer through contact holes.

[0178] In the non-display area NA, driving units may be arranged on substrate 101. For example, shift registers 21 to 25 constituting gate driver 20 may be arranged on substrate 101. Shift registers 21 to 25 may include at least one transistor. The transistors forming the driving units may be of the same type as at least one of transistors TFT1 and TFT2 in display area AA, and may be formed in the same layer with the same structure.

[0179] The bus can also be arranged on the substrate 101. The bus may include a low-level drive voltage line PL2. The low-level drive voltage line PL2 may be formed in a shape surrounding the periphery of the display panel 50. The low-level drive voltage line PL2 may be located outside the gate driver 20, and at least a portion thereof may overlap with the gate driver 20. The low-level drive voltage line PL2 may be electrically connected to the cathode 250 extending to the non-display area NA, and the low-level drive voltage ELVSS (see...) Figure 1 It can be applied to the cathode 250.

[0180] The bus may also include a high-level drive voltage line PL1, a conduction bias voltage line VobsL, an initialization voltage line ViniL, an anode reset voltage line VARL, and a common node reset voltage line VcglL. Some or all of the high-level drive voltage line PL1, the conduction bias voltage line VobsL, the initialization voltage line ViniL, the anode reset voltage line VARL, and the common node reset voltage line VcglL may be formed in a shape surrounding the display area AA and located inside the gate driver 20.

[0181] The anode reset voltage line VARL and the common node reset voltage line VcglL can be electrically connected via a connection transistor Tc. The connection transistor Tc can be of the same type as at least one of the transistors TFT1 and TFT2 in the display area AA, and can be formed in the same layer with the same structure. For example, the connection transistor Tc may include a semiconductor layer 131, a gate 132, and source and drain 133 disposed on the first buffer layer 105. The gate 132 can be electrically connected to the third scan line GL3 extending from the gate driver 20 via a contact hole, or can be formed as a single pattern in the same layer. The source and drain 133 can be electrically connected to the anode reset voltage line VARL and the common node reset voltage line VcglL via contact holes, or can be formed as a single pattern in the same layer. The structure of the connection transistor Tc is not limited to the example shown.

[0182] The bus may have a dual-wiring structure consisting of at least two conductive layers. For example, the bus may include a first conductive layer formed in the same layer as the connection electrode 143 and a second conductive layer formed in the same layer as the source and drain electrodes 113 and 123 of transistors TFT1 and TFT2, wherein these layers may be electrically connected or at least partially stacked. When the bus is configured with dual wiring, the resistance of the bus can be reduced, and the driving voltage can be provided stably.

[0183] The light-emitting element (LD) can be formed on the planarization layer 140 in the display area AA. In one embodiment, the light-emitting element (LD) may have a series structure. In this embodiment, the light-emitting element (LD) has a stacked structure, which includes an anode 210, a first light-emitting unit 220, a charge generation layer 230, a second light-emitting unit 240, and a cathode 250.

[0184] The anode 210 can be connected to the connecting electrode 143 through a contact hole. The anode 210 can be connected to the transistor TFT1 through the connecting electrode 143.

[0185] A dam 150 may be formed on the anode 210. The dam 150 may be arranged to cover a portion of the anode 210 (e.g., an edge), while exposing another portion (e.g., a central region). The dam 150 is formed extensively on the substrate 101 to extend into the non-display area NA. The area of ​​the anode 210 that is not covered by the dam 150 but is exposed may be defined as a light-emitting area.

[0186] The dam 150 may be formed of an opaque material to prevent optical interference between adjacent pixels. For example, the dam 150 may comprise a black-based material, such as a light-shielding material (black dam) composed of at least one of colored pigments (black pigments), black dyes, organic black, or carbon. Optionally, the dam 150 may be composed of organic materials such as benzocyclobutene resin, polyimide resin, acrylic resin, or photosensitive polymer, but is not limited thereto. When the dam 150 is composed of a black-based material, the dam 150 can block external light, thereby further improving the brightness of the display device 1. In this case, the dam 150 can be used to absorb light reflected from its lower part among the external light incident upon it.

[0187] In one embodiment, the embankment 150 may be configured as a multi-layered structure. In this embodiment, some layers of the multi-layered structure (e.g., the lower layer) may contain materials from the black series, while other layers (e.g., the upper layer) may contain materials from the transparent series.

[0188] The first light-emitting unit 220 may be formed on the area of ​​the anode 210 not covered by the embankment 150. The first light-emitting unit 220 may have a structure in which a first hole transport layer, a first light-emitting layer and a first electron transport layer are stacked.

[0189] A charge generation layer 230 may be formed above the first light-emitting unit 220. A second light-emitting unit 240 may be formed above the charge generation layer 230. The second light-emitting unit 240 may have a structure in which a second hole transport layer, a second light-emitting layer, and a second electron transport layer are stacked.

[0190] The cathode 250 may be formed above the second light-emitting unit 240. The cathode 250 may be electrically connected to the low-potential drive voltage line PL2 located at the outermost part of the display panel 50 via an auxiliary electrode 320 formed on the same layer as the anode 210 in the non-display area NA.

[0191] The cathode 250, charge generation layer 230, and light-emitting units 220 and 240 can be formed on the substrate 101 over a wide range. For example, one or more layers constituting the cathode 250, charge generation layer 230, and light-emitting units 220 and 240 can extend from the display area AA to at least a portion of the non-display area NA.

[0192] In the non-display area NA, a common node reset electrode 310 may be formed on the planarization layer 140 and the embankment 150. The common node reset electrode 310 may be formed on the same layer as the anode 210 in the display area AA. The common node reset electrode 310 may be electrically connected to the charge generation layer 230 extending to the non-display area NA through a contact hole through the embankment 150. The common node reset electrode 310 may be connected to the common node reset voltage line VcglL through a contact hole through the planarization layer 140. Since the common node reset voltage line VcglL is connected to the anode reset voltage line VARL via the connecting transistor Tc, the charge generation layer 230 may be electrically connected to the anode reset voltage line VARL via the common node reset electrode 310, the common node reset voltage line VcglL, and the connecting transistor Tc.

[0193] An encapsulation layer 160 may be formed above the light-emitting element (LD). The encapsulation layer 160 can block the penetration of external moisture or oxygen, thereby protecting the light-emitting element (LD) which is susceptible to external moisture or oxygen. For this purpose, the encapsulation layer 160 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer, but is not limited thereto. The structure of the encapsulation layer 160, in which a first encapsulation layer 161, a second encapsulation layer 162, and a third encapsulation layer 163 are stacked sequentially, will be explained below as an example.

[0194] A first encapsulation layer 161 is formed on a substrate 101 on which a cathode 250 is formed. A third encapsulation layer 163 is formed on a substrate 101 on which a second encapsulation layer 162 is formed, and may be configured together with the first encapsulation layer 161 to surround the top, bottom, and side surfaces of the second encapsulation layer 162. The first encapsulation layer 161 and the third encapsulation layer 163 can minimize or prevent the penetration of external moisture or oxygen into the light-emitting element LD. The first encapsulation layer 161 and the third encapsulation layer 163 may be formed of an inorganic insulating material that can be deposited at low temperatures, such as silicon nitride (SiNx), silicon oxide (SiOx), silicon nitride oxide (SiON), or aluminum oxide (Al2O3). Because the first encapsulation layer 161 and the third encapsulation layer 163 are deposited in a low-temperature atmosphere, they can prevent damage to the high-temperature-sensitive light-emitting element LD during the deposition process of the first encapsulation layer 161 and the third encapsulation layer 163.

[0195] The second encapsulation layer 162 can be used as a buffer to reduce the impact of the display device 1 (see...). Figure 1The second encapsulation layer 162 can be formed from non-photosensitive organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene, or silicon carbide (SiOC), or photosensitive organic insulating materials such as optical acrylic, but is not limited thereto. When the second encapsulation layer 162 is formed by inkjet printing, weirs DAM1, DAM2, and DAM3 can be arranged to prevent the liquid form of the second encapsulation layer 162 from spreading to the edge of the substrate 101. Weirs DAM1, DAM2, and DAM3 can be positioned closer to the edge of the substrate 101 than the second encapsulation layer 162. That is, the second encapsulation layer 162 can be formed inside the weirs DAM1, DAM2, and DAM3. Using these weirs DAM1, DAM2, and DAM3, diffusion of the second encapsulation layer 162 into the pad area (where the conductive pads are located at the outermost part of the substrate 101) can be prevented.

[0196] Weirs DAM1, DAM2, and DAM3 are designed to prevent the diffusion of the second encapsulation layer 162. When the second encapsulation layer 162 is formed during the process to exceed the height of weirs DAM1, DAM2, and DAM3, the organic second encapsulation layer 162 can be exposed to the outside, making it easier for moisture or other substances to penetrate into the light-emitting element. Therefore, to prevent this, weirs DAM1, DAM2, and DAM3 can be formed in at least two layers. Weirs DAM1, DAM2, and DAM3 can be disposed in two or more layers. In this case, two or more weirs DAM1, DAM2, and DAM3 can be formed with the same or different structures.

[0197] The first weir DAM1 can be formed using the same process as the planarization layer 140, the dike 150, and the spacer 170. Here, the planarization layer 140 can be a second planarization layer 142, but is not limited to this. The spacer 170 can be formed on the dike 150. The spacer 170 can be formed to prevent mask imprinting during the process and can be made of organic insulating materials such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), and phenolic resin. The first weir DAM1 can have a three-layer structure consisting of the planarization layer 140, the dike 150, and the spacer 170.

[0198] In one embodiment, the auxiliary electrode 320 may extend between the planarization layer 140 and the embankment 150 constituting the first weir DAM1. The lower part of the first weir DAM1 may contact the low-potential drive voltage line PL2.

[0199] The second weir DAM2 can be formed on the outside of the first weir DAM1, and can have the same structure as the first weir DAM1.

[0200] The third weir DAM3 may be formed on the outside of the second weir DAM2 and may be formed using the same process as the planarization layer 140 and the embankment 150. Here, the planarization layer 140 may be the second planarization layer 142, but is not limited thereto. The third weir DAM3 may have a double-layer structure consisting of the planarization layer 140 and the embankment 150. The lower part of the third weir DAM3 may contact at least one area of ​​the low-potential drive voltage line PL2, and the remaining areas may contact the fourth insulating layer 130.

[0201] The first encapsulation layer 161 and the third encapsulation layer 163 may extend beyond the weirs DAM1, DAM2 and DAM3 to extend to the outer edge of the substrate 101.

[0202] A crack stopper CS may be further formed at the outermost edge of the substrate 101. The crack stopper CS prevents cracks that may appear in the substrate 101 from propagating inward due to external forces. The crack stopper CS can prevent the entire substrate 101 from being damaged by cracks that may appear when the substrate 101 is separated from the mother substrate.

[0203] The crack stopper CS can be formed using the same process as that used for planarization layer 140, embankment 150, and spacer 170. Here, planarization layer 140 may be a second planarization layer 142, but is not limited thereto. At the bottom of the crack stopper CS, the first buffer layer 105, first insulating layer 110, second insulating layer 115, second buffer layer 120, third insulating layer 125, and fourth insulating layer 130 may include at least one groove. Planarization layer 140 may be formed as an inner layer filling the groove.

[0204] On the encapsulation layer 160, a touch layer, a color filter layer, and one or more optical functional layers may be further disposed. For example, the touch layer may include touch electrodes or touch sensor electrodes in the display area AA. The touch electrodes or touch sensor electrodes may have a grid shape. For example, the touch layer may include touch wiring or touch routing lines in the non-display area NA. The touch wiring or touch routing lines may be located between the dams DAM1, DAM2, and DAM3 and the display area AA. For example, the touch wiring or touch routing lines may be located in the area overlapping with the gate driver 20.

[0205] Figure 10 This is a cross-sectional view showing the stacked structure of a display device according to another embodiment.

[0206] and Figure 9 Compared to the implementation method, in Figure 10In this embodiment, the common node reset electrode 310 is formed not only in the non-display area NA but also in the display area AA. In this embodiment, the common node reset electrode 310 may include one or more contact areas located in the display area AA that are connected to the charge generation layer 230 and the common node reset voltage line VcglL.

[0207] In the contact area, the common node reset electrode 310 can be connected to the charge generation layer 230 through a contact hole passing through the embankment 150.

[0208] In the contact region, the common node reset voltage line VcglL, patterned below the common node reset electrode 310, can be formed in an overlapping manner. The common node reset voltage line VcglL can be formed in the same layer as the source and drain 133, but is not limited thereto.

[0209] In the contact area, the common node reset electrode 310 can be connected to the node reset voltage line VcglL through a contact hole passing through the planarization layer 140.

[0210] The contact area can be formed as one or more for each pixel PX, or the contact area can be formed as one or more for multiple pixels. For example, the contact area can be formed for each 3×3 pixel unit or 5×5 pixel unit.

[0211] Since the common node reset electrode 310 in the display area AA is connected to the node reset voltage line VcglL through the contact area, the uniformity of the common node reset voltage Vcgl applied to the charge generation layer 230 via the common node reset electrode 310 is improved.

[0212] Figures 11 to 13 It shows the formation Figure 10 A diagram showing the contact area method.

[0213] Reference Figure 10 and Figure 11 A planarization layer 140, including a first planarization layer 141 and a second planarization layer 142, is formed on the substrate 101. A common node reset electrode 310 may be formed together with the anode 210 on the planarization layer 140.

[0214] The dam 150 may be formed on the common node reset electrode 310. The dam 150 may be formed to not cover at least a portion of the common node reset electrode 310 in the contact area.

[0215] A first light-emitting unit 220 may be formed on the common node reset electrode 310, which is not covered by the embankment 150 but exposed at the top. For example, a first hole transport layer, a first light-emitting layer, and a first electron transport layer may be formed sequentially.

[0216] Reference Figure 10and Figure 12 A laser drilling or laser etching process is performed on the first light-emitting unit 220 in the contact area. A hole can be formed in the first light-emitting unit 220 through laser drilling or laser etching. The common node reset electrode 310 formed below the first light-emitting unit 220 will not be laser etched and can be exposed to the upper part through the hole formed in the first light-emitting unit 220.

[0217] Reference Figure 10 and Figure 13 A charge generation layer 230 is formed on the first light-emitting unit 220. The charge generation layer 230 can directly contact the common node reset electrode 310 exposed through the hole in the first light-emitting unit 220.

[0218] The display device according to the embodiment is advantageous in solving the following problem: during the anode reset period within a frame, the common node remains floating, thereby causing voltage fluctuations and resulting in changes in electroluminescence characteristics.

[0219] The display device according to the embodiment is advantageous in preventing voltage fluctuations in the common node by resetting the voltage of the common node during the anode reset period.

[0220] The display device according to the embodiment is advantageous in minimizing current leakage by utilizing oxide semiconductor transistors.

[0221] Although embodiments of the invention have been described above with reference to the accompanying drawings, it will be understood that the technical constructions of the invention described above can be implemented in other specific forms by those skilled in the art without altering the technical concept or essential features of the invention. Therefore, it should be understood that the above embodiments are exemplary in all respects and not restrictive. Furthermore, the scope of the invention is defined by the claims set forth below, and not by the specific description above. Moreover, it should be understood that all modifications or variations derived from the meaning and scope of the claims and their equivalents are included within the scope of the invention.

Claims

1. A display device, comprising: Multiple pixels arranged in the display area; as well as At least one driving unit is arranged in the non-display area surrounding the display area. Each pixel includes: A light-emitting element, comprising multiple light-emitting units connected in series via a common node; A driving transistor, the driving transistor comprising a first electrode connected to a high-potential driving voltage line via a first node, a gate connected to a second node, and a second electrode connected to the anode of the light-emitting element via a third node; A compensation transistor is connected between the second node and the third node and has a gate configured to receive a first scan signal; A switching transistor is connected between the data line and the first node and has a gate configured to receive a second scan signal; An anode reset transistor, connected between the light-emitting element and the anode reset voltage line, and having a gate configured to receive a third scan signal; and The common node reset voltage line is connected to the common node.

2. The display device according to claim 1, wherein the common node reset voltage line is electrically connected to the anode reset voltage line via a connecting transistor.

3. The display device of claim 2, wherein the connection transistor is connected between the anode reset voltage line and the common node reset voltage line, and has a gate configured to receive the third scan signal.

4. The display device according to claim 3, wherein when the third scan signal is applied at an on level during an anode reset period within a frame, the anode reset transistor is turned on and applies an anode reset voltage to the anode, the connection transistor is turned on and electrically connects the anode reset voltage line and the common node reset voltage line, the common node reset voltage line applying the anode reset voltage to the common node.

5. The display device according to claim 3, wherein the connection transistor is disposed in the non-display area.

6. The display device according to claim 5, wherein the anode reset voltage line and the common node reset voltage line are disposed between the at least one driving unit and the display area, and the connection transistor is disposed in a connection area located between the anode reset voltage line and the common node reset voltage line.

7. The display device according to claim 1, wherein the common node reset voltage line is formed in a closed loop shape around the display area, and the anode reset voltage line is formed around at least three sides of the display area.

8. The display device according to claim 1, wherein the light-emitting element comprises: First electrode; A second electrode arranged opposite to the first electrode; A first light-emitting unit and a second light-emitting unit are disposed between the first electrode and the second electrode; as well as A charge generation layer is inserted between the first light-emitting unit and the second light-emitting unit and forms the common node.

9. The display device according to claim 1, wherein each pixel further comprises: An initialization transistor is connected between the initialization voltage line and the second node and has a gate configured to receive a fourth scan signal; A first light-emitting transistor is connected between the high-potential drive voltage line and the first node, and has a gate configured to receive a light-emitting signal. The second light-emitting transistor is connected between the third node and the light-emitting element, and has a gate configured to receive the light-emitting signal; A bias transistor is connected between the first node and the bias voltage line and has a gate configured to receive the third scan signal. as well as A storage capacitor is connected between the high-potential drive voltage line and the second node.

10. The display device according to claim 9, wherein the at least one driving unit comprises: A gate driver configured to output a first scan signal, a second scan signal, a third scan signal, a fourth scan signal, and a light emission signal respectively through corresponding scan lines and light emission lines. The gate driver includes: A first shift register, configured to output the first scan signal; A second shift register, configured to output the second scan signal; A third shift register, configured to output the third scan signal; A fourth shift register, configured to output the fourth scan signal; and A fifth shift register, configured to output the light emission signal. The second shift register is located adjacent to the display area. The first shift register, the third shift register, the fourth shift register, and the fifth shift register are sequentially positioned away from the display area.

11. The display device of claim 1, wherein at least some of the driving transistor, the compensation transistor and the anode reset transistor are low-temperature polysilicon (LTPS) transistors, and the remaining transistors are oxide transistors.

12. The display device according to claim 1, further comprising: substrate; A first buffer layer is disposed on the substrate; The first semiconductor layer of the first transistor disposed on the first buffer layer; A first insulating layer disposed on the first semiconductor layer; The first gate of the first transistor disposed on the first insulating layer; A second insulating layer disposed on the first gate of the first transistor; A second buffer layer disposed on the second insulating layer; The second semiconductor layer of the second transistor disposed on the second buffer layer; A third insulating layer disposed on the second semiconductor layer; The second gate of the second transistor is disposed on the third insulating layer; A fourth insulating layer disposed on the second gate of the second transistor; The source and drain of the first transistor and the second transistor are disposed on the fourth insulating layer; A protective film is disposed on the source and the drain; A planarization layer disposed on the protective film; The anode of the light-emitting element is disposed on the planarization layer; The first light-emitting unit of the light-emitting element disposed on the anode; A charge generation layer of the light-emitting element disposed on the first light-emitting unit, the charge generation layer constituting the common node; The second light-emitting unit of the light-emitting element disposed on the charge generation layer; as well as The cathode of the light-emitting element disposed on the second light-emitting unit, The first transistor is one of the driving transistor, the compensation transistor, and the anode reset transistor, and the second transistor is the other of the driving transistor, the compensation transistor, and the anode reset transistor.

13. The display device of claim 12, further comprising a connection transistor, the connection transistor comprising: A third semiconductor layer disposed on the first buffer layer; A gate disposed on the first insulating layer; as well as The third source and the third drain are disposed on the fourth insulating layer. The third source is connected to the anode reset voltage line, and the third drain is connected to the common node reset voltage line.

14. The display device according to claim 13, further comprising: Common node reset electrode disposed on the planarization layer in the non-display area The common node reset electrode is connected to the charge generation layer and the common node reset voltage line through a contact hole.

15. The display device of claim 14, wherein the common node reset electrode is further disposed in the display area and connected to the charge generation layer and the common node reset voltage line through at least one contact hole in the display area.

16. A display device, comprising: A substrate, the substrate including a display area and a non-display area; A first buffer layer is disposed on the substrate; The first semiconductor layer of the first transistor disposed on the first buffer layer in the display area; A first insulating layer disposed on the first semiconductor layer; The first gate of the first transistor is disposed on the first insulating layer in the display area; A second insulating layer disposed on the first gate of the first transistor; A second buffer layer disposed on the second insulating layer; The second semiconductor layer of the second transistor disposed on the second buffer layer in the display area; A third insulating layer disposed on the second semiconductor layer; The second gate of the second transistor is disposed on the third insulating layer in the display area; A fourth insulating layer disposed on the second gate of the second transistor; The source and drain of the first transistor and the second transistor are disposed on the fourth insulating layer in the display area; A protective film is disposed on the source and the drain; A planarization layer disposed on the protective film; The anode of the light-emitting element disposed on the planarization layer in the display area; The first light-emitting unit of the light-emitting element disposed on the anode; A charge generation layer of the light-emitting element disposed on the first light-emitting unit, the charge generation layer constituting a common node; The second light-emitting unit of the light-emitting element disposed on the charge generation layer; as well as The cathode of the light-emitting element disposed on the second light-emitting unit.

17. The display device of claim 16, further comprising a connection transistor located in the non-display area, the connection transistor comprising: A third semiconductor layer disposed on the first buffer layer; A gate disposed on the first insulating layer; as well as The third source and the third drain are disposed on the fourth insulating layer. The third source is connected to the anode reset voltage line, and the third drain is connected to the common node reset voltage line.

18. The display device according to claim 17, further comprising a common node reset electrode disposed on the planarization layer in the non-display area. The common node reset electrode is connected to the common node reset voltage line through a contact hole, and the charge generation layer extends from the display area to the non-display area and is connected to the common node reset electrode through a contact hole in the non-display area.

19. The display device of claim 18, wherein the common node reset electrode is further disposed in the display area and connected to the charge generation layer and the common node reset voltage line through at least one contact hole in the display area.

20. The display device of claim 17, wherein the planarization layer comprises a first planarization layer and a second planarization layer disposed on the first planarization layer, and the common node reset voltage line and the anode reset voltage line comprise a first conductive layer disposed on the first planarization layer and a second conductive layer disposed on the fourth insulating layer and connected to the first conductive layer through a contact hole.

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