Memory device including a leakage current control circuit

Abstract

A storage device includes a memory cell array and a peripheral circuit region that at least partially overlaps with the memory cell array in a first direction. The peripheral circuit region includes a bias voltage generation circuit and a leakage current control circuit. The bias voltage generation circuit is configured to generate a bias voltage and provide the bias voltage to a separate circuit within the peripheral circuit region. The leakage current control circuit is configured to generate a bias voltage control signal and use the bias voltage control signal to control the amplitude of a leakage current generated in the peripheral circuit region by the bias voltage. The leakage current control circuit includes: a test circuit configured to generate a test voltage based on the bias voltage; a reference circuit configured to generate a reference voltage based on a power supply voltage; and a differential amplifier configured to generate the bias voltage control signal by comparing the test voltage with the reference voltage.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0188739, filed with the Korean Intellectual Property Office on December 17, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure generally relates to a storage device, and more specifically, to a storage device including leakage current control circuitry. Background Technology

[0003] Based on whether the stored data is lost when power to the storage device is interrupted, storage devices can be classified as at least one of volatile storage devices and non-volatile storage devices.

[0004] Volatile memory devices can refer to arrays of memory cells that may include multiple memory blocks, each of which may include transistors and capacitors. Leakage currents can occur in transistors due to reasons such as (but not limited to) memory device degradation. Therefore, the power consumption of the memory device can increase, and / or the reliability of the memory device can decrease.

[0005] Therefore, the inability to optimize the amount of leakage current in memory devices limits improvements in power consumption and / or reliability, thus creating a need for further improvements to memory device technology. This paper presents improvements that can also be applied to other semiconductor technologies. Summary of the Invention

[0006] One or more exemplary embodiments of this disclosure provide a storage device that has improved reliability compared to related storage devices.

[0007] Furthermore, one or more exemplary embodiments of this disclosure provide a storage device including a leakage current control circuit capable of optimizing the amount of leakage current in the storage device.

[0008] This disclosure is not limited to the above embodiments, and those skilled in the art will clearly understand additional embodiments of this disclosure not mentioned herein based on the following description.

[0009] According to one aspect of this disclosure, a memory device includes: a memory cell array including a plurality of memory transistors and a memory capacitor; and a peripheral circuit region at least partially overlapping the memory cell array in a first direction. The peripheral circuit region includes a bias voltage generation circuit and a leakage current control circuit. The bias voltage generation circuit is configured to generate a bias voltage and provide the bias voltage to independent circuitry within the peripheral circuit region. The leakage current control circuit is configured to generate a bias voltage control signal and use the bias voltage control signal to control the amplitude of a leakage current generated in the peripheral circuit region by the bias voltage. The leakage current control circuit includes: a test circuit configured to generate a test voltage based on the bias voltage; a reference circuit configured to generate a reference voltage based on a power supply voltage; and a differential amplifier configured to generate the bias voltage control signal by comparing the test voltage with the reference voltage. The test circuit includes a first transistor having a first threshold voltage and a second transistor having a second threshold voltage different from the first threshold voltage. The reference circuit includes a third transistor having the first threshold voltage and a fourth transistor having the second threshold voltage.

[0010] According to one aspect of this disclosure, a memory device includes: a memory cell array including a plurality of memory transistors and a memory capacitor; and a peripheral circuit region at least partially overlapping the memory cell array in a first direction. The peripheral circuit region includes a bias voltage generation circuit and a leakage current control circuit. The bias voltage generation circuit is configured to generate a bias voltage and provide the bias voltage to independent circuitry within the peripheral circuit region. The leakage current control circuit is configured to generate a bias voltage control signal and use the bias voltage control signal to control the amplitude of a leakage current generated in the peripheral circuit region by the bias voltage. The leakage current control circuit includes: a test circuit configured to generate a test voltage based on the bias voltage; and a reference circuit configured to generate a reference voltage based on a power supply voltage. The leakage current control circuit is further configured to generate a bias voltage control signal that controls the bias voltage generation circuit to generate a bias voltage such that the amplitude of the test voltage is equal to the amplitude of the reference voltage.

[0011] According to one aspect of this disclosure, a memory device includes: a memory cell array including a plurality of memory transistors and a memory capacitor; and a peripheral circuit region at least partially overlapping the memory cell array in a first direction. The peripheral circuit region includes a bias voltage generation circuit and a leakage current control circuit. The bias voltage generation circuit is configured to generate a bias voltage and provide the bias voltage to independent circuitry within the peripheral circuit region. The leakage current control circuit is configured to generate a bias voltage control signal and use the bias voltage control signal to control the amplitude of a leakage current generated in the peripheral circuit region by the bias voltage. The leakage current control circuit includes: a test circuit configured to generate a test voltage based on the bias voltage; a reference circuit configured to generate a reference voltage based on a power supply voltage; and a differential amplifier configured to generate the bias voltage control signal based on the test voltage and the reference voltage. The test circuit includes a first transistor having a first threshold voltage and a second transistor having a second threshold voltage. The reference circuit includes a third transistor having a first threshold voltage and a fourth transistor having a second threshold voltage. The test circuit is further configured to generate a test voltage based on a first resistor and a test leakage current, wherein the test leakage current is generated in the first and second transistors based on a first bias voltage applied to the first substrate of the first transistor and the second substrate of the second transistor. The reference circuit is further configured to generate a reference voltage based on a second resistor and a reference leakage current, wherein the reference leakage current is generated in the third and fourth transistors based on a power supply voltage applied to the third substrate of the third transistor and the fourth substrate of the fourth transistor. The differential amplifier is further configured to generate a bias voltage control signal based on the difference between the test voltage and the reference voltage. The bias voltage generation circuit is further configured to generate a second bias voltage based on the bias voltage control signal. The test circuit is further configured to generate a second test voltage based on a first resistor and a corrected test leakage current, wherein the corrected test leakage current is generated in the first and second transistors based on the second bias voltage applied to the first substrate of the first transistor and the second substrate of the second transistor. The amplitude of the second test voltage is equal to the amplitude of the reference voltage.

[0012] Additional aspects may be set forth in part in the description which follows, and may be apparent in part from the description, and / or may be learned by practice of the presented embodiments. Attached Figure Description

[0013] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, in which:

[0014] Figure 1 This is a block diagram illustrating a memory system according to some embodiments of the present disclosure;

[0015] Figure 2 This illustrates some embodiments according to the present disclosure. Figure 1 A block diagram of the memory chip;

[0016] Figure 3 This illustrates some embodiments according to the present disclosure. Figure 1 A block diagram showing a partial configuration of the memory chip;

[0017] Figure 4 This illustrates some embodiments according to the present disclosure. Figure 3 A diagram of the memory bank array included in the memory chip;

[0018] Figure 5 This is a block diagram illustrating a leakage current control circuit according to some embodiments of the present disclosure;

[0019] Figure 6 This is a circuit diagram showing a leakage current control circuit according to some embodiments of the present disclosure;

[0020] Figure 7 and Figure 8 This illustrates some embodiments according to the present disclosure. Figure 6 The circuit diagram for the operation of the leakage current control circuit;

[0021] Figure 9 This is a circuit diagram showing a leakage current control circuit according to some embodiments of the present disclosure;

[0022] Figure 10 This is a block diagram illustrating a leakage current control circuit according to some embodiments of the present disclosure; and

[0023] Figure 11 This is a schematic block diagram illustrating an electronic device including a storage device according to some embodiments of the present disclosure. Detailed Implementation

[0024] The following description, provided with reference to the accompanying drawings, is intended to aid in a full understanding of the embodiments of this disclosure as defined by the claims and their equivalents. Various specific details are included to aid understanding, but these details are to be considered exemplary only. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Furthermore, for the purposes of clarity and conciseness, descriptions of well-known functions and structures have been omitted.

[0025] Regarding the description of the accompanying drawings, similar reference numerals may be used to refer to similar or related elements. It should be understood that the singular form of a noun corresponding to an item may include one or more things unless the relevant context explicitly indicates otherwise. As used herein, each phrase such as “A or B,” “at least one of A and B,” “at least one of A or B,” “A, B or C,” “at least one of A, B and C,” and “at least one of A, B or C” may include any one or all possible combinations of the items listed together in the corresponding phrases of these phrases. As used herein, terms such as “first” and “second” or “first” and “second” may be used simply to distinguish corresponding components from other components and do not limit the components in any other way (e.g., in terms of importance or order). It should be understood that if the terms “operably” or “communically” are used to refer to an element (e.g., a first element) being “coupled,” “coupled to,” “connected to,” or “attached to” another element (e.g., a second element), it indicates that the element may be coupled directly (e.g., wired), wirelessly, or via a third element to the other element.

[0026] It will be understood that when a component or layer is referred to as being "above," "on top of," "above," "below," "below," "connected to," or "coupled to" another component or layer, it may be directly above, above, above, below, below, or below that other component or layer, or there may be intermediate components or layers. Conversely, when a component is referred to as being "directly above," "above," "above," "below," "below," "below," "directly connected to," or "directly coupled to" another component or layer, there are no intermediate components or layers.

[0027] The terms “upper,” “middle,” “lower,” etc., can be replaced by terms such as “first,” “second,” “third,” etc., to describe the relative positions of elements. The terms “first,” “second,” “third,” etc., can be used to describe various elements, but the elements are not limited by these terms, and a “first element” can be referred to as a “second element.” Alternatively or additionally, the terms “first,” “second,” “third,” etc., can be used to distinguish components from each other and do not limit this disclosure. For example, the terms “first,” “second,” “third,” etc., do not necessarily involve any form of order or numerical meaning.

[0028] As used herein, when an element or layer is referred to as “covering,” “overlapping,” or “surrounding” another element or layer, the element or layer may cover at least a portion of the other element or layer, wherein the portion may include a part of the other element or may include the entirety of the other element. Similarly, when an element or layer is referred to as “penetrating” another element or layer, the element or layer may penetrate at least a portion of the other element or layer, wherein the portion may include a part of the other element or may include the entire dimensions (e.g., length, width, depth) of the other element.

[0029] Throughout this disclosure, references to “an embodiment,” “an embodiment,” “an exemplary embodiment,” or similar language may indicate that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present solution. Therefore, the phrases “in one embodiment,” “in an embodiment,” “in an exemplary embodiment,” and similar language throughout this disclosure may, but not necessarily all, refer to the same embodiment. The embodiments described herein are exemplary embodiments, and therefore, this disclosure is not limited thereto and may be implemented in various other forms.

[0030] The embodiments described herein can be illustrated and described as blocks that perform one or more of the described functions, as shown in the accompanying drawings. These blocks (which may be referred to herein as cells or modules, or named as devices, logic, circuits, controllers, counters, comparators, generators, converters, etc.) can be physically implemented by analog and / or digital circuits including one or more of logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, etc.

[0031] In this disclosure, the article “a” is intended to include one or more items and may be used interchangeably with “one or more.” The term “a” or similar language is used when only one item is intended to be referred to. For example, the term “processor” can refer to a single processor or multiple processors. When a processor is described as performing an operation, and the processor is mentioned as performing additional operations, multiple operations can be performed by a single processor, or any one or a combination of multiple processors.

[0032] Various embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0033] Figure 1 This is a block diagram of a memory system according to some embodiments of the present disclosure.

[0034] refer to Figure 1The memory system 1 may include a memory controller 10 and a memory module 20. Each of the memory controller 10 and the memory module 20 may include an interface for communicating with each other. These interfaces may be connected to each other via a control bus for transmitting commands (CMD), addresses (ADDR), clock signals (CLK), etc., and / or a data bus for transmitting data. Command CMD can be considered to include address ADDR.

[0035] The memory controller 10 can generate commands (CMD) for controlling the memory module 20, and under the control of the memory controller 10, data DATA can be written to and / or read from the memory module 20.

[0036] The memory module 20 may include multiple memory chips 300. Each memory chip 300 may be implemented as an independent chip and packaged in the substrate of the memory module 20. The memory module 20 may transmit data read from the storage cells, status information of the storage devices, etc., to the memory controller 10 via a data bus.

[0037] Figure 2 This illustrates some embodiments according to the present disclosure. Figure 1 A block diagram of a memory chip. Figure 3 This illustrates some embodiments according to the present disclosure. Figure 1 A block diagram showing a partial configuration of the memory chip. Figure 4 This illustrates some embodiments according to the present disclosure. Figure 3 A diagram of the memory bank array included in a memory chip. Figure 5 This is a block diagram illustrating a leakage current control circuit according to some embodiments of the present disclosure.

[0038] refer to Figures 2 to 5 The memory chip 300 may include a memory cell array 310 and a peripheral circuit area 400.

[0039] The memory cell array 310 may include multiple memory bank arrays (e.g., first memory bank arrays 310a to h-th memory bank arrays 310h, where h is a positive integer greater than zero (0)). Each of the multiple memory bank arrays 310a to 310h may include multiple memory cells MC. For example, memory cells MC may be and / or may include dynamic random access memory (DRAM) cells. As another example, the memory interface may perform communication based on one or more memory interface standards (e.g., but not limited to, Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), Graphics Double Data Rate (GDDR), Wide Input / Output (I / O), High Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), etc.).

[0040] The memory cell MC can be arranged at a point where multiple word lines WL (e.g., the first word line WL1, the second word line WL2 to the (2m-1)th word line WL2m-1 and the (2m)th word line BL2m, where m is a positive integer greater than zero (0)) can intersect with multiple bit lines BL (e.g., the first bit line BL1, the second bit line BL2 to the (2n-1)th bit line BL2n-1 and the (2n)th bit line BL2n, where n is a positive integer greater than zero (0)). That is, each memory cell MC can be connected to a single word line WL and a single bit line BL.

[0041] Each memory cell MC may include a switching element and an information storage capacitor. In an embodiment, the switching element may include a transistor, the gate terminal of which may be connected to the word line WL, and the drain / source terminals of the transistor may be connected to the bit line BL and the information storage capacitor, respectively.

[0042] The peripheral circuit area 400 may include logic circuitry 410 and bias voltage (VABB) control circuitry 430.

[0043] In some embodiments, the logic circuit 410 may include memory control logic 390, address register 320, memory bank control logic 330, row selection circuit 340, column decoder 360, sense amplifier unit 350, I / O gating circuit 370, data I / O buffer 380 and refresh controller 395.

[0044] Row selection circuit 340 may include multiple bank row selection circuits (e.g., first bank row selection circuit 340a to h-th bank row selection circuit 340h) connected to multiple bank arrays 310a to 310h. Column decoder 360 may include multiple bank column decoders (e.g., first bank column decoder 360a to h-th bank column decoder 360h) connected to multiple bank arrays 310a to 310h. Readout amplifier unit 350 may include multiple readout amplifiers (e.g., first readout amplifier 350a to h-th readout amplifier 350h) that can be respectively connected to multiple bank arrays 310a to 310h.

[0045] Address register 320 can receive address information from memory controller 10. The address information ADD may include bank address BANK_ADDR, row address ROW_ADDR, and / or column address COL_ADDR. Address register 320 can translate the address information into an internal address for memory module 20. For example, address register 320 can provide bank address BANK_ADDR to memory control logic 330, row address ROW_ADDR to row selection circuit 340, and column address COL_ADDR to column decoder 360.

[0046] The memory bank control logic 330 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. In response to the memory bank control signal, one of the multiple memory bank row selection circuits 340a to 340h that corresponds to the memory bank address BANK_ADDR can be activated, and one of the multiple memory bank column decoders 360a to 360h that corresponds to the memory bank address BANK_ADDR can be activated.

[0047] The row address ROW_ADDR output from address register 320 can be applied to each of the plurality of bank row selection circuits 340a to 340h. Among the bank row selection circuits 340a to 340h, the bank row selection circuit activated by bank control logic 330 can decode the row address ROW_ADDR to activate the word line corresponding to the row address and apply an operating voltage. For example, the activated bank row selection circuit can apply a word line drive voltage to each row corresponding to the row address. In this case, the activation command can be and / or may include commands for data read operations, write operations, and / or erase operations relative to a memory cell. The refresh command can be a command for performing a refresh operation on at least one of a row hammer row or a sacrificial row.

[0048] Column decoder 360 may include a column address latch. The column address latch can receive a column address COL_ADDR from address register 320 and can temporarily store the received column address COL_ADDR. Additionally, the column address latch can progressively increment the received column address COL_ADDR in burst mode. The column address latch can apply the temporarily stored and / or progressively incremented column address COL_ADDR to each of the multiple memory bank column decoders 360a to 360h.

[0049] Among the multiple bank column decoders 360a to 360h, the bank column decoder activated by the bank control logic 330 can activate the sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the I / O gating circuit 370.

[0050] I / O strobe circuit 370 may include input data masking logic, a read data latch for storing data output from multiple memory bank arrays 310a to 310h, a write driver for writing data to the multiple memory bank arrays 310a to 310h, and circuitry for strobe I / O data.

[0051] Data DQ to be read from one of the multiple memory arrays 310a to 310h can be read by one of the multiple sense amplifiers 350a to 350h (which may correspond to one of the multiple memory arrays 310a to 310h) and can be stored in a read data latch. The data DQ stored in the read data latch can be provided to the memory controller via a data I / O buffer 380. Data DQ to be written to one of the multiple memory arrays 310a to 310h can be provided from the memory controller to the data I / O buffer 380. The data DQ provided to the data I / O buffer 380 can be written to one of the multiple memory arrays 310a to 310h via a write driver.

[0052] The refresh controller 395 can control the memory bank row selection circuit 340 of the memory module 20 to perform refresh operations. According to some embodiments, the refresh controller 395 may include a plurality of refresh controllers (e.g., first refresh controller 395a to h-th refresh controller 395h) respectively corresponding to a plurality of memory bank row selection circuits 340a to 340h.

[0053] Memory control logic 390 can control the overall operation of memory chip 300. According to some embodiments, memory control logic 390 can generate a first control signal to perform an activation operation (e.g., a write operation or a read operation) on memory chip 300. According to some embodiments, memory control logic 390 can control refresh controller 395 via a refresh control signal to perform a refresh operation on memory chip 300.

[0054] The VABB control circuit 430 can control the threshold voltage of the metal-oxide-semiconductor (MOS) transistor by generating a bias voltage and applying the bias voltage to the substrate of the MOS transistor included in the peripheral circuitry of the memory chip 300.

[0055] In some embodiments, the VABB control circuit 430 may include a leakage current control circuit 500 and a bias voltage (VABB) generation circuit 510. The leakage current control circuit 500 can periodically (and / or irregularly) measure the leakage current based on the bias voltage provided to the memory chip 300 and can determine an optimal bias voltage. The VABB generation circuit 510 can receive a bias voltage control signal from the leakage current control circuit 500 and can generate the optimal bias voltage. The generated bias voltage can be applied again to the substrate of transistors included in the peripheral circuitry of the memory chip 300. Therefore, a memory device that maintains optimal operating conditions regardless of temperature or process steps can be provided. The configuration and operation of the leakage current control circuit 500 and the VABB generation circuit 510 are described below.

[0056] Figure 6This is a circuit diagram illustrating a leakage current control circuit according to some embodiments of the present disclosure.

[0057] refer to Figure 6 The VABB control circuit 430 may include a leakage current control circuit 500 and a VABB generation circuit 510. The leakage current control circuit 500 may provide a bias voltage control signal LUS to the VABB generation circuit 510.

[0058] In some embodiments, the leakage current control circuit 500 can control the VABB generation circuit 510 to generate an optimal bias voltage by performing a test on the substrate of the transistor in the memory chip 300 to apply a bias voltage to it and generating a bias voltage control signal LUS.

[0059] The leakage current control circuit 500 may include a test circuit 5100, a reference circuit 5200, and a differential amplifier 5000. One end of the test circuit 5100 and one end of the reference circuit 5200 may be electrically connected to the inverting terminal and the non-inverting terminal of the differential amplifier 5000, respectively.

[0060] In some embodiments, the test circuit 5100 may include a first test transistor p1 and a second test transistor p2 that can be connected in parallel to the first node "a". The first test transistor p1 and the second test transistor p2 may be transistors having characteristics similar to those of transistors included in the peripheral circuitry of the memory chip 300. For example, the transistors included in the memory chip 300 may include a transistor having a first threshold voltage and a transistor having a second threshold voltage, the amplitude of which differs from the amplitude of the first threshold voltage. For example, when the transistors having the first threshold voltage and the transistors having the second threshold voltage included in the peripheral circuitry 400 of the memory chip 300 have dimensions of 10 micrometers (µm) and 80 µm, respectively, the first test transistor p1 and the second test transistor p2 included in the test circuit 5100 may have dimensions of 1 µm and 8 µm, respectively. However, embodiments of this disclosure are not limited thereto. That is, the test circuit 5100 may include a plurality of transistors having the same size ratio as the transistors included in the memory chip 300. The first test transistor p1 included in the test circuit 5100 may be a transistor having a first threshold voltage, and the second test transistor p2 may be a transistor having a second threshold voltage.

[0061] In some embodiments, the amplitude ratio of the transistor with a first threshold voltage to the transistor with a second threshold voltage included in the memory chip 300 can be n:m (where n and m are positive integers greater than zero (0)). For example, the amplitude ratio of the first test transistor p1 to the second test transistor p2 can be expressed as n:m. Although the figures show the case where there are two (2) transistors with different threshold voltages in the memory chip 300, the embodiments of this disclosure are not limited thereto. For example, the memory chip 300 may include a transistor with a third threshold voltage. That is, the memory chip 300 may contain three (3) transistors with different threshold voltages. The transistor with the first threshold voltage, the transistor with the second threshold voltage, and the transistor with the third threshold voltage may have a size ratio of n:m:l. In such cases, the test circuit 5100 may include a plurality of transistors with the same size ratio (e.g., n:m:l) as the transistors included in the memory chip 300.

[0062] In some embodiments, a first bias voltage VBP1 may be applied to the substrate of the first test transistor p1 and the second test transistor p2.

[0063] The test circuit 5100 may include a first resistor R1 and test current mirrors (e.g., a first test current mirror n1 and a second test current mirror n2) that can be connected to a first node "a". The first test current mirror n1 and the second test current mirror n2 may each include a third transistor n1 and a fourth transistor n2. The gate and drain terminals of the third transistor n1 and the gate terminal of the fourth transistor n2 may be electrically connected to the first node "a". The drain terminal of the fourth transistor n2 may be electrically connected at a second node "b" to second resistors R2, RO1, RO2, and RON. The second resistors R2, RO1, RO2, and RON may include a first sub-resistor R2 and second sub-resistors RO1, RO2, and RON.

[0064] In some embodiments, the amplitudes of the second sub-resistors RO1, RO2, and RON can vary according to the resistor selection signal RSS. The resistor selection signal RSS will be described below.

[0065] In some embodiments, the reference circuit 5200 may include reference transistors p3 and p4 that can be connected in parallel to the third node "c". Reference transistors p3 and p4 may include a fifth transistor p3 and a sixth transistor p4. The fifth transistor p3 and the sixth transistor p4 may be transistors having characteristics similar to those of transistors included in the peripheral circuitry of the memory chip 300. For example, the transistors included in the memory chip 300 may include a transistor having a first threshold voltage and a transistor having a second threshold voltage, the magnitude of which differs from the magnitude of the first threshold voltage. For example, when the transistors having the first threshold voltage and the transistors having the second threshold voltage included in the peripheral circuitry 400 of the memory chip 300 have dimensions of 10µm and 80µm, respectively, the third transistor p3 and the fourth transistor p4 included in the reference circuit 5200 may have dimensions of 1µm and 8µm, respectively. However, embodiments of this disclosure are not limited to this. That is, the reference circuit 5200 may include a plurality of transistors having the same size ratio as the transistors included in the memory chip 300. The fifth transistor p3 included in the reference circuit 5200 may be a transistor having a first threshold voltage, and the sixth transistor p4 may be a transistor having a second threshold voltage.

[0066] In some embodiments, the amplitude ratio of the transistor with a first threshold voltage to the transistor with a second threshold voltage included in the memory chip 300 can be n:m. That is, the amplitude ratio of the fifth transistor p3 to the sixth transistor p4 can be expressed as n:m. Although the figures show the case where there are two (2) transistors with different threshold voltages in the memory chip 300, the embodiments of this disclosure are not limited thereto. For example, the memory chip 300 may include a transistor with a third threshold voltage. That is, the memory chip 300 may contain three (3) transistors with different threshold voltages. The transistor with the first threshold voltage, the transistor with the second threshold voltage, and the transistor with the third threshold voltage may have a size ratio of n:m:l. In such cases, the test circuit 5100 may include a plurality of transistors with the same size ratio (e.g., n:m:l) as the transistors included in the memory chip 300.

[0067] In some embodiments, a power supply voltage VDD can be applied to the substrates of the fifth transistor p3 and the sixth transistor p4.

[0068] Reference circuit 5200 may include a third resistor R3 that can be connected to the third node "c" and reference current mirrors n3 and n4. Reference current mirrors n3 and n4 may include a seventh transistor n3 and an eighth transistor n4. The gate and drain terminals of the seventh transistor n3 and the gate terminal of the eighth transistor n4 may be electrically connected to the third node "c". The drain terminal of the eighth transistor n4 may be electrically connected to the fourth resistor R4 at the fourth node "d". The amplitudes of the first resistor R1 and the third resistor R3 may be substantially similar and / or the same as each other. The amplitudes of the first sub-resistor R2 and the fourth resistor R4 may be substantially similar and / or the same as each other. That is, test circuit 5100 and reference circuit 5200 may correspond to circuits with bias voltages applied to the base of the transistors and resistors connected to the second node "b" and the fourth node "d" having different amplitudes.

[0069] In some embodiments, the differential amplifier 5000 can receive a test voltage from the test circuit 5100 (e.g., Figure 7 (Vdet) and receive reference voltage from reference circuit 5200 (e.g., Figure 7 The test voltage Vdet can correspond to the voltage measured at the second node "b", and the reference voltage Vref can correspond to the voltage measured at the fourth node "d".

[0070] Differential amplifier 5000 compares the test voltage Vdet with the reference voltage Vref and generates a bias voltage control signal LUS for adjusting the amplitude of the bias voltage. VABB generation circuit 510 receives the bias voltage control signal LUS from leakage current control circuit 500 and generates a corrected bias voltage using regulator 5110 and charge pump 5130.

[0071] The regulator 5110 and charge pump 5130 can convert the input voltage into an output voltage. In some embodiments, the regulator 5110 can be a low dropout voltage regulator.

[0072] The corrected bias voltage can be provided to the transistors in the memory chip 300, and after a predetermined time, the VABB control circuit 430 can perform a test on the corrected bias voltage. As a result, a memory device that maintains optimal operating conditions regardless of temperature or process steps can be provided.

[0073] Figure 7 and Figure 8 This illustrates some embodiments according to the present disclosure. Figure 6 The circuit diagram for the operation of the leakage current control circuit.

[0074] refer to Figure 6 and Figure 7 In the test circuit 5100, a first bias voltage VBP1 can be applied to the substrates of the first test transistor p1 and the second test transistor p2. A first test leakage current i_leak_n can be generated from the first test transistor p1, and a second test leakage current i_leak_0 can be generated from the second test transistor p2. The first test leakage current i_leak_n and the second test leakage current i_leak_0 can be combined at the first node "a" to form a test leakage current i_leak, and the test leakage current i_leak can be combined with a first current i_1 flowing in the first resistor R1 between the power supply voltage VDD and the first node "a" to form a second current i_2. A third current i_3 can be determined based on the second current i_2. For example, when the amplitude ratio of the third transistor n1 and the fourth transistor n2 is 1:m, the ratio of the second current i_2 to the third current i_3 can be 1:m. The test voltage Vdet can be the voltage drop caused by the power supply voltage VDD, the second resistors R2, RO1, RO2 and RON between the second node "b", and the third current i_3.

[0075] In the reference circuit, the power supply voltage VDD can be applied to the substrates of the fifth transistor p3 and the sixth transistor p4. A first reference leakage current i_leak_n_ref can be generated from the fifth transistor p3, and a second reference leakage current i_leak_0_ref can be generated from the sixth transistor p4. The first and second reference leakage currents i_leak_n_ref and i_leak_0_ref can be combined at the third node "c" to form a single reference leakage current i_leak_ref, and this single reference leakage current i_leak_ref can be combined with a first reference current i_1_ref flowing in the third resistor R3 between the power supply voltage VDD and the third node "c" to form a second reference current i_2_ref. A third reference current i_3_ref can be determined based on the second reference current i_2_ref. For example, when the amplitude ratio of the seventh transistor n3 and the eighth transistor n4 is 1:m, the ratio of the second reference current i_2_ref to the third reference current i_3_ref can be 1:m. The reference voltage Vref can be the voltage drop caused by the power supply voltage VDD, the fourth resistor R4 between the fourth node "d", and the third reference current i_3_ref.

[0076] The differential amplifier 5000 can compare the test voltage Vdet with the reference voltage Vref and generate a bias voltage control signal LUS for adjusting the amplitude of the bias voltage.

[0077] For example, when the test voltage Vdet is greater than the reference voltage Vref, the bias voltage control signal LUS can be a signal used to reduce the amplitude of the leakage current generated in the test transistors p1 and p2. In other words, the bias voltage control signal LUS can correspond to a signal used to increase the amplitude of the bias voltage.

[0078] As an example, when the test voltage Vdet is less than the reference voltage Vref, the bias voltage control signal LUS can be a signal used to increase the amplitude of the leakage current generated in the test transistors p1 and p2. In other words, the bias voltage control signal LUS can be a signal used to decrease the amplitude of the bias voltage.

[0079] The VABB generation circuit 510 can receive the bias voltage control signal LUS from the leakage current control circuit 500, and can generate a second bias voltage VBP2 by using the regulator 5110 and the charge pump 5130.

[0080] For example, when the test voltage Vdet is greater than the reference voltage Vref, the second bias voltage VBP2 can be greater than the first bias voltage VBP1.

[0081] As another example, when the test voltage Vdet is less than the reference voltage Vref, the second bias voltage VBP2 can be less than the first bias voltage VBP1.

[0082] refer to Figure 6 and Figure 8 The second bias voltage VBP2 can be applied to the transistor in the memory chip 300, and after a predetermined time, the VABB control circuit 430 can perform a test on the second bias voltage VBP2.

[0083] In the test circuit 5100, a second bias voltage VBP2 can be applied to the substrates of the first test transistor p1 and the second test transistor p2. A third test leakage current i_leak_n' can be generated from the first test transistor p1, and a fourth test leakage current i_leak_0' can be generated from the second test transistor p2. The third test leakage current i_leak_n' and the fourth test leakage current i_leak_0' can be combined at the first node a to form a corrected test leakage current i_leak', and the corrected test leakage current i_leak' can be combined with a first corrected current i_1' flowing in the first resistor R1 between the power supply voltage VDD and the first node a to form a second corrected current i_2'. The third corrected current i_3' can be determined based on the second corrected current i_2'. For example, when the amplitude ratio of the third transistor n1 and the fourth transistor n2 is 1:m, the ratio of the second corrected current i_2' to the third corrected current i_3' can be 1:m. The corrected test voltage Vdet' can be the voltage drop caused by the power supply voltage VDD, the second resistors R2, RO1, RO2 and RON between the second node "b", and the third correction current i_3'.

[0084] In the reference circuit, the power supply voltage VDD can be applied to the substrates of the fifth transistor p3 and the sixth transistor p4. A first reference leakage current i_leak_n_ref can be generated from the fifth transistor p3, and a second reference leakage current i_leak_0_ref can be generated from the sixth transistor p4. The first and second reference leakage currents i_leak_n_ref and i_leak_0_ref can be combined at the third node "c" to form a single reference leakage current i_leak_ref, and this single reference leakage current i_leak_ref can be combined with a first reference current i_1_ref flowing in the third resistor R3 between the power supply voltage VDD and the third node "c" to form a second reference current i_2_ref. A third reference current i_3_ref can be determined based on the second reference current i_2_ref. For example, when the amplitude ratio of the seventh transistor n3 and the eighth transistor n4 is 1:m, the ratio of the second reference current i_2_ref to the third reference current i_3_ref can be 1:m. The reference voltage Vref can be the voltage drop caused by the power supply voltage VDD, the fourth resistor R4 between the fourth node "d", and the third reference current i_3_ref.

[0085] The differential amplifier 5000 can compare the corrected test voltage Vdet' with the reference voltage Vref and generate a bias voltage control signal LUS for adjusting the amplitude of the bias voltage.

[0086] For example, when the amplitude of the corrected test voltage Vdet' equals the amplitude of the reference voltage Vref, the differential amplifier 5000 may not generate a bias voltage control signal LUS. That is, the second bias voltage VBP2 can correspond to the optimal bias voltage for operating the memory chip 300. As a result, a memory device that maintains optimal operating conditions regardless of temperature or process steps can be provided.

[0087] Figure 9 This is a circuit diagram illustrating a leakage current control circuit according to some embodiments of the present disclosure. Figure 9 The leakage current control circuit may include the above reference. Figure 6 The leakage current control circuit described above, and / or may be related to the above reference in many ways. Figure 6 The described leakage current control circuit is similar and may include additional features not mentioned above. Therefore, for the sake of brevity, references to the above can be omitted. Figure 6 The description of the leakage current control circuit is repeated.

[0088] refer to Figure 9 The VABB control circuit 430 may include a leakage current control circuit 500 and a VABB generation circuit 510. The leakage current control circuit 500 may provide a bias voltage control signal LUS to the VABB generation circuit 510.

[0089] The leakage current control circuit 500 can perform tests using the bias voltage applied to the substrate of the transistor in the memory chip 300, generate a bias voltage control signal LUS, and control the VABB generation circuit 510 to generate an optimal bias voltage. The leakage current control circuit 500 may include a test circuit 5100, a reference circuit 5200, and a differential amplifier 5000. One end of the test circuit 5100 and one end of the reference circuit 5200 can be electrically connected to the inverting and non-inverting terminals of the differential amplifier 5000, respectively.

[0090] The test circuit 5100 may include test transistors p1 and p2 that can be connected in parallel to the first node "a", and offset resistors RO1 and Ron. Test transistors p1 and p2 may include a first test transistor p1 and a second test transistor p2. In some embodiments, the magnitudes of the offset resistors RO1 and Ron may vary according to a resistor selection signal RSS. The resistor selection signal RSS is described below.

[0091] In the test circuit 5100, a first bias voltage VBP1 can be applied to the substrates of the first test transistor p1 and the second test transistor p2. A first test leakage current i_leak_n can be generated from the first test transistor p1, and a second test leakage current i_leak_0 can be generated from the second test transistor p2. Based on the resistor selection signal RSS, a first offset current iR1 can occur in the first offset resistor RO1 between the power supply voltage VDD and the first node "a", and a second offset current iRn can occur in the second offset resistor RON between the power supply voltage VDD and the second node "b". The first test leakage current i_leak_n, the second test leakage current i_leak_0, the first offset current iR1, and the second offset current iRn can be combined at the first node "a" to form a test leakage current i_leak, and the test leakage current i_leak can be combined with the first current i_1 flowing in the first resistor R1 between the power supply voltage VDD and the first node "a" to form a second current i_2.

[0092] The test circuit 5100 may include a first resistor R1 that can be connected to a first node "a" and test current mirrors n1 and n2. Test current mirrors n1 and n2 may include a third transistor n1 and a fourth transistor n2. The gate and drain terminals of the third transistor n1 and the gate terminal of the fourth transistor n2 may be electrically connected to the first node "a". The drain terminal of the fourth transistor n2 may be electrically connected to a second resistor R2 at a second node "b".

[0093] The third current i_3 can be determined based on the second current i_2. For example, when the amplitude ratio of the third transistor n1 and the fourth transistor n2 is 1:m, the ratio of the second current i_2 to the third current i_3 can be 1:m. The test voltage Vdet can be the voltage drop caused by the second resistor R2 between the power supply voltage VDD and the second node "b" and the third current i_3.

[0094] In some embodiments, the reference circuit 5200 may include reference transistors p3 and p4 connected in parallel to the third node "c". Reference transistors p3 and p4 may include a fifth transistor p3 and a sixth transistor p4.

[0095] In the reference circuit, the power supply voltage VDD can be applied to the substrates of the fifth transistor p3 and the sixth transistor p4. A first reference leakage current i_leak_n_ref can be generated from the fifth transistor p3, and a second reference leakage current i_leak_0_ref can be generated from the sixth transistor p4. The first reference leakage current i_leak_n_ref and the second reference leakage current i_leak_0_ref can be combined at the third node "c" to form a reference leakage current i_leak_ref, and the reference leakage current i_leak_ref can be combined with the first reference current i_1_ref flowing in the third resistor R3 between the power supply voltage VDD and the third node "c" to form a second reference current i_2_ref.

[0096] Reference circuit 5200 may include a third resistor R3 connected to the third node "c" and reference current mirrors n3 and n4. Reference current mirrors n3 and n4 may include a seventh transistor n3 and an eighth transistor n4. The gate and drain terminals of the seventh transistor n3 and the gate terminal of the eighth transistor n4 may be electrically connected to the third node "c". The drain terminal of the eighth transistor n4 may be electrically connected to the fourth resistor R4 at the fourth node "d". The magnitudes of the first resistor R1 and the third resistor R3 may be substantially the same and / or the same as each other. The magnitudes of the second resistor R2 and the fourth resistor R4 may be substantially the same and / or the same as each other. That is, test circuit 5100 and reference circuit 5200 may correspond to circuits where the bias voltage applied to the transistor substrate and the magnitudes of the resistors connected to the first node "a" and the third node "c" are different from each other.

[0097] The third reference current i_3_ref can be determined based on the second reference current i_2_ref. For example, when the amplitude ratio of the seventh transistor n3 and the eighth transistor n4 is 1:m, the ratio of the second reference current i_2_ref to the third reference current i_3_ref can be 1:m. The reference voltage Vref can be the voltage drop caused by the fourth resistor R4 between the supply voltage VDD and the fourth node "d" and the third reference current i_3_ref.

[0098] In some embodiments, the differential amplifier 5000 may receive a test voltage Vdet from the test circuit 5100 and a reference voltage Vref from the reference circuit 5200. The test voltage Vdet may correspond to the voltage measured at the second node "b", and the reference voltage Vref may correspond to the voltage measured at the fourth node "d".

[0099] The differential amplifier 5000 can compare the test voltage Vdet with the reference voltage Vref and generate a bias voltage control signal LUS for adjusting the amplitude of the bias voltage.

[0100] For example, when the test voltage Vdet is greater than the reference voltage Vref, the bias voltage control signal LUS can be a signal used to reduce the amplitude of the leakage current generated in the test transistors p1 and p2. In other words, the bias voltage control signal LUS can correspond to a signal used to increase the amplitude of the bias voltage.

[0101] As an example, when the test voltage Vdet is less than the reference voltage Vref, the bias voltage control signal LUS can be a signal used to increase the amplitude of the leakage current generated in the test transistors p1 and p2. In other words, the bias voltage control signal LUS can be a signal used to decrease the amplitude of the bias voltage.

[0102] The VABB generation circuit 510 can receive the bias voltage control signal LUS from the leakage current control circuit 500, and can generate a corrected second bias voltage VBP2 by using the regulator 5110 and / or the charge pump 5130.

[0103] The regulator 5110 and charge pump 5130 can convert the input voltage into an output voltage. In some embodiments, the regulator 5110 can be a low dropout voltage regulator (LDO).

[0104] For example, when the test voltage Vdet is greater than the reference voltage Vref, the second bias voltage VBP2 can be greater than the first bias voltage VBP1.

[0105] As another example, when the test voltage Vdet is less than the reference voltage Vref, the second bias voltage VBP2 can be less than the first bias voltage VBP1.

[0106] In one embodiment, a second bias voltage VBP2 can be applied to the transistors in the memory chip 300, and after a predetermined time, the VABB control circuit 430 can perform a test on the second bias voltage VBP2. As a result, a memory device that maintains optimal operating conditions regardless of temperature or process steps can be provided.

[0107] Figure 10 This is a block diagram illustrating a leakage current control circuit according to some embodiments of the present disclosure.

[0108] refer to Figure 10 In some embodiments, the VABB control circuit 430 may include a leakage current control circuit 500, a VABB generation circuit 510, and a mode selection circuit 520.

[0109] The mode selection circuit 520 can generate a resistor selection signal RSS that is provided to the leakage current control circuit 500.

[0110] refer to Figure 6 The second sub-resistors RO1, RO2, and RON may include the first offset resistor RO1, the second offset resistor RO2, and the third offset resistor RON. Each of the first offset resistors RO1 to the third offset resistor RON may be connected to a switch.

[0111] In some embodiments, the second sub-resistors RO1, RO2, and RON can vary according to the resistance selection signal RSS. For example, when the memory chip 300 operates in a first mode (e.g., self-refresh mode), the switch connected to the first offset resistor RO1 can be short-circuited by the resistance selection signal RSS. Alternatively, when the memory chip 300 operates in a second mode (e.g., 2-pin mode), the switch connected to the second offset resistor RO2 can be short-circuited by the resistance selection signal RSS. Therefore, a bias voltage optimized for each mode can be searched and generated. Although three (3) offset resistors are shown in the figure, this is exemplary, and embodiments of this disclosure are not limited thereto.

[0112] refer to Figure 9 The offset resistors RO1 and RON may include a first offset resistor RO1 and a second offset resistor RON. Each of the first offset resistor RO1 and the second offset resistor RON may be connected to a switch.

[0113] In some embodiments, offset resistors RO1 and RON can vary according to a resistance selection signal RSS. For example, when the memory chip 300 operates in a first mode (e.g., self-refresh mode), the switch connected to the first offset resistor RO1 can be short-circuited by the resistance selection signal RSS. Alternatively, when the memory chip 300 operates in a second mode (e.g., 2-pin mode), the switch connected to the second offset resistor RON can be short-circuited by the resistance selection signal RSS. Therefore, a bias voltage optimized for each mode can be searched and generated. Although two (2) offset resistors are shown in the figure, this is exemplary, and embodiments of this disclosure are not limited thereto.

[0114] Return to reference Figure 10The leakage current control circuit 500 periodically measures the leakage current based on the bias voltage supplied to the memory chip 300 and can determine the optimal bias voltage. The VABB generation circuit 510 receives the bias voltage control signal from the leakage current control circuit 500 and can generate the optimal bias voltage. The generated bias voltage can be applied to the substrate of the transistors included in the peripheral circuitry of the memory chip 300. As a result, a memory device that maintains optimal operating conditions regardless of temperature or process steps can be provided. The configuration and operation of the leakage current control circuit 500 and the VABB generation circuit 510 have been described above and can be omitted for brevity.

[0115] Figure 11 This is a schematic block diagram illustrating an electronic device including a storage device according to some embodiments of the present disclosure.

[0116] refer to Figure 11 According to some embodiments, an electronic device 1000 may include a display 1010, a communication unit 1020, a memory 1030, a processor 1040, and an input / output (I / O) unit 1050. Components such as (but not limited to) the display 1010, communication unit 1020, memory 1030, processor 1040, and I / O unit 1050 may communicate with each other via a bus 1060. In addition to the components described above, the electronic device 1000 may also include a power supply, ports, etc.

[0117] Processor 1040 can perform specific calculations, commands, and tasks. Processor 1040 can be and / or may include a central processing unit (CPU), a microprocessor unit (MCU), an application processor (AP), etc., and can communicate with other components (such as, but not limited to, display 1010, communication unit 1020, memory 1030, and I / O unit 1050) via bus 1060.

[0118] Figure 11 The memory 1030 included in the illustrated electronic device 1000 may include memory devices according to various embodiments of the present disclosure. For example, the memory 1030 may be based on references... Figures 1 to 10 The various embodiments described are operational.

[0119] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, those skilled in the art will understand that the present disclosure can be implemented in various forms, and is not limited to the embodiments described above, and can be embodied in other specific forms without departing from the technical spirit and essential characteristics of the present disclosure. Therefore, the above embodiments should be considered illustrative rather than restrictive in all respects.

Claims

1. A memory device comprising: an array of memory cells including a plurality of memory transistors and memory capacitors; and a peripheral circuit region at least partially overlapping the array of memory cells in a first direction, wherein the peripheral circuit region includes: a bias voltage generation circuit configured to generate a bias voltage and to supply the bias voltage to independent circuits of the peripheral circuit region; and a leakage current control circuit configured to generate a bias voltage control signal and to control a magnitude of a leakage current generated in the peripheral circuit region by the bias voltage using the bias voltage control signal, wherein the leakage current control circuit includes: a test circuit configured to generate a test voltage based on the bias voltage; a reference circuit configured to generate a reference voltage based on a supply voltage; and a differential amplifier configured to generate the bias voltage control signal by comparing the test voltage and the reference voltage, wherein the test circuit includes a first transistor having a first threshold voltage and a second transistor having a second threshold voltage different from the first threshold voltage, and wherein the reference circuit includes a third transistor having the first threshold voltage and a fourth transistor having the second threshold voltage.

2. The memory device of claim 1, wherein, the peripheral circuit region further includes a fifth transistor having the first threshold voltage and a sixth transistor having the second threshold voltage.

3. The memory device of claim 2, wherein, a third ratio of a magnitude of the fifth transistor to a magnitude of the sixth transistor is equal to a first ratio of a magnitude of the first transistor to a magnitude of the second transistor, and wherein the third ratio is equal to a second ratio of a magnitude of the third transistor to a magnitude of the fourth transistor.

4. The memory device of claim 2, wherein, the bias voltage generation circuit is further configured to apply a first bias voltage to a first bulk of the first transistor and a second bulk of the second transistor, wherein the reference circuit is further configured to apply the supply voltage to a third bulk of the third transistor and a fourth bulk of the fourth transistor, wherein the test circuit is further configured to generate the test voltage based on a first resistor and a test leakage current generated in the first transistor and the second transistor, and wherein the reference circuit is further configured to generate the reference voltage based on a second resistor and a reference leakage current generated in the third transistor and the fourth transistor.

5. The memory device of claim 4, wherein, the bias voltage generation circuit is further configured to: generate a second bias voltage based on the bias voltage control signal; and apply the second bias voltage to the first bulk of the first transistor and the second bulk of the second transistor.

6. The memory device of claim 5, wherein, the bias voltage generation circuit is further configured to: apply the second bias voltage to a fifth bulk of the fifth transistor and a sixth bulk of the sixth transistor.

7. The memory device of claim 5, wherein, based on the application of the second bias voltage to the first bulk of the first transistor and the second bulk of the second transistor: The test circuit is configured to generate a second test voltage based on the first resistor and the corrected test leakage current generated in the first transistor and the second transistor by the second bias voltage. The reference circuit is configured to generate the reference voltage based on the second resistor and the reference leakage current generated in the third and fourth transistors; and The amplitude of the second test voltage is equal to the amplitude of the reference voltage.

8. The memory device of claim 4, wherein, The test circuit also includes a test current mirror. The test current mirror includes a seventh transistor and an eighth transistor. The first transistor's end, the second transistor's end, the seventh transistor's drain electrode, the seventh transistor's gate electrode, and the eighth transistor's gate electrode are coupled to the first node. The eighth transistor is coupled to the second node at one end. The first resistor is located between the second node and the power supply voltage, and includes a first sub-resistor and a second sub-resistor. The reference circuit further includes a reference current mirror. The reference current mirror includes a ninth transistor and a tenth transistor. The third transistor's end, the fourth transistor's end, the ninth transistor's drain electrode, the ninth transistor's gate electrode, and the tenth transistor's gate electrode are coupled to the third node. The tenth transistor is coupled to the fourth node at one end. Wherein, the second resistor is between the fourth node and the power supply voltage, and The amplitude of the first sub-resistor is equal to the amplitude of the second sub-resistor.

9. The memory device of claim 8, wherein, The peripheral circuit area also includes a mode selection circuit configured to generate a resistor selection signal and use the resistor selection signal to control the amplitude of the second sub-resistor. The second sub-resistor has a first amplitude based on a first resistance selection signal generated by the mode selection circuit, and The second sub-resistor generates a second resistance selection signal that is different from the first resistance selection signal based on the mode selection circuit, and thus has a second amplitude that is different from the first amplitude.

10. The memory device of claim 8, wherein, The test voltage is measured at the second node, and The reference voltage is measured at the fourth node.

11. The memory device of claim 4, wherein, The test circuit also includes a test current mirror. The test current mirror includes a seventh transistor and an eighth transistor. The first transistor's end, the second transistor's end, the seventh transistor's drain electrode, the seventh transistor's gate electrode, and the eighth transistor's gate electrode are coupled to the first node. The eighth transistor is coupled to the second node at one end. The first resistor includes a first sub-resistor and a second sub-resistor. The first sub-resistor is located between the first node and the power supply voltage. The second sub-resistor is located between the second node and the power supply voltage. The reference circuit further includes a reference current mirror. The reference current mirror includes a ninth transistor and a tenth transistor. The third transistor's end, the fourth transistor's end, the ninth transistor's drain electrode, the ninth transistor's gate electrode, and the tenth transistor's gate electrode are coupled to the third node. The tenth transistor is coupled to the fourth node at one end. Wherein, the second resistor is between the fourth node and the power supply voltage, and The amplitude of the second sub-resistor is equal to the amplitude of the second resistor.

12. The memory device of claim 11, wherein, The test circuit also includes a third resistor between the first node and the power supply voltage. The reference circuit further includes a fourth resistor between the third node and the power supply voltage, and The amplitude of the third resistor is equal to the amplitude of the fourth resistor.

13. The memory device of claim 1, wherein, The bias voltage generation circuit includes at least one of a charge pump or a regulator, and The bias voltage generation circuit is configured to generate the bias voltage based on the bias voltage control signal.

14. A storage device comprising: A memory cell array, comprising multiple memory transistors and memory capacitors; as well as The peripheral circuitry region at least partially overlaps with the memory cell array in the first direction. The peripheral circuit area includes: A bias voltage generation circuit is configured to generate a bias voltage and provide the bias voltage to an independent circuit in the peripheral circuit area; and A leakage current control circuit is configured to generate a bias voltage control signal and use the bias voltage control signal to control the amplitude of the leakage current generated by the bias voltage in the peripheral circuit area. The leakage current control circuit includes: The test circuit is configured to generate a test voltage based on the bias voltage; and The reference circuit is configured to generate a reference voltage based on the supply voltage, and The leakage current control circuit is further configured to generate the bias voltage control signal, which controls the bias voltage generation circuit to generate the bias voltage, such that the amplitude of the test voltage is equal to the amplitude of the reference voltage.

15. The memory device of claim 14, wherein, The test circuit includes test transistors and test resistors. The test circuit is configured as follows: A test leakage current is generated in the test transistor by applying the bias voltage to the test substrate of the test transistor; and The test voltage is generated based on the test leakage current and the test resistor. The reference circuit includes a reference transistor and a reference resistor, and The reference circuit is configured as follows: A reference leakage current is generated in the reference transistor by applying the power supply voltage to the reference substrate of the reference transistor; and The reference voltage is generated based on the reference leakage current and the reference resistor.

16. The memory device of claim 15, wherein, The amplitude of the test voltage is greater than the amplitude of the reference voltage.

17. The memory device of claim 16, wherein, The bias voltage generation circuit is further configured to generate a second bias voltage with an amplitude greater than that of the bias voltage based on the bias voltage control signal. The test circuit is further configured as follows: A corrected test leakage current is generated in the test transistor by applying the second bias voltage to the test substrate of the test transistor; and A second test voltage is generated based on the corrected test leakage current and the test resistor, and The amplitude of the second test voltage is equal to the amplitude of the reference voltage.

18. The memory device of claim 15, wherein, The amplitude of the test voltage is less than the amplitude of the reference voltage.

19. The memory device of claim 18, wherein, The bias voltage generation circuit is further configured to generate a second bias voltage with an amplitude smaller than that of the bias voltage based on the bias voltage control signal. The test circuit is further configured as follows: A corrected test leakage current is generated in the test transistor by applying the second bias voltage to the test substrate of the test transistor; and A second test voltage is generated based on the corrected test leakage current and the test resistor, and The amplitude of the second test voltage is equal to the amplitude of the reference voltage.

20. A storage device comprising: A memory cell array, comprising multiple memory transistors and memory capacitors; as well as The peripheral circuitry region at least partially overlaps with the memory cell array in the first direction. The peripheral circuit area includes: A bias voltage generation circuit is configured to generate a bias voltage and provide the bias voltage to an independent circuit in the peripheral circuit area; and A leakage current control circuit is configured to generate a bias voltage control signal and use the bias voltage control signal to control the amplitude of the leakage current generated by the bias voltage in the peripheral circuit area. The leakage current control circuit includes: The test circuit is configured to generate a test voltage based on the bias voltage; The reference circuit is configured to generate a reference voltage based on the supply voltage; and A differential amplifier is configured to generate the bias voltage control signal based on the test voltage and the reference voltage. The test circuit includes a first transistor having a first threshold voltage and a second transistor having a second threshold voltage. The reference circuit includes a third transistor having the first threshold voltage and a fourth transistor having the second threshold voltage. The test circuit is further configured to generate the test voltage based on a first resistor and a test leakage current, wherein the test leakage current is generated in the first transistor and the second transistor based on a first bias voltage applied to the first substrate of the first transistor and the second substrate of the second transistor. The reference circuit is further configured to generate the reference voltage based on a second resistor and a reference leakage current, wherein the reference leakage current is generated in the third and fourth transistors based on the power supply voltage applied to the third base of the third transistor and the fourth base of the fourth transistor. The differential amplifier is further configured to generate the bias voltage control signal based on the difference between the test voltage and the reference voltage. The bias voltage generation circuit is further configured to generate a second bias voltage based on the bias voltage control signal. The test circuit is further configured to generate a second test voltage based on the first resistor and the corrected test leakage current, wherein the corrected test leakage current is generated in the first transistor and the second transistor based on the second bias voltage applied to the first substrate of the first transistor and the second substrate of the second transistor. The amplitude of the second test voltage is equal to the amplitude of the reference voltage.

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